1 /******************************************************************************
3 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
35 * @file xsysmonpsu_hw.h
37 * This header file contains the identifiers and basic driver functions (or
38 * macros) that can be used to access the device. Other driver functions
39 * are defined in xsysmonpsu.h.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ----- -------- -----------------------------------------------
46 * 1.0 kvn 12/15/15 First release
47 * 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
48 * SEQ_CH2 and SEQ_AVG2 offsets and bit masks
52 ******************************************************************************/
54 #ifndef XSYSMONPSU_HW_H__
55 #define XSYSMONPSU_HW_H__
62 /***************************** Include Files ********************************/
64 #include "xil_types.h"
65 #include "xil_assert.h"
67 #include "xparameters.h"
70 * XSysmonPsu Base Address
72 #define XSYSMONPSU_BASEADDR 0xFFA50000U
75 * Register: XSysmonPsuMisc
77 #define XSYSMONPSU_MISC_OFFSET 0x00000000U
78 #define XSYSMONPSU_MISC_RSTVAL 0x00000000U
80 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_SHIFT 1U
81 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_WIDTH 1U
82 #define XSYSMONPSU_MISC_SLVERR_EN_DRP_MASK 0x00000002U
84 #define XSYSMONPSU_MISC_SLVERR_EN_SHIFT 0U
85 #define XSYSMONPSU_MISC_SLVERR_EN_WIDTH 1U
86 #define XSYSMONPSU_MISC_SLVERR_EN_MASK 0x00000001U
89 * Register: XSysmonPsuIsr0
91 #define XSYSMONPSU_ISR_0_OFFSET 0x00000010U
92 #define XSYSMONPSU_ISR_0_MASK 0xffffffffU
93 #define XSYSMONPSU_ISR_0_RSTVAL 0x00000000U
95 #define XSYSMONPSU_ISR_0_PL_ALM_15_SHIFT 31U
96 #define XSYSMONPSU_ISR_0_PL_ALM_15_WIDTH 1U
97 #define XSYSMONPSU_ISR_0_PL_ALM_15_MASK 0x80000000U
99 #define XSYSMONPSU_ISR_0_PL_ALM_14_SHIFT 30U
100 #define XSYSMONPSU_ISR_0_PL_ALM_14_WIDTH 1U
101 #define XSYSMONPSU_ISR_0_PL_ALM_14_MASK 0x40000000U
103 #define XSYSMONPSU_ISR_0_PL_ALM_13_SHIFT 29U
104 #define XSYSMONPSU_ISR_0_PL_ALM_13_WIDTH 1U
105 #define XSYSMONPSU_ISR_0_PL_ALM_13_MASK 0x20000000U
107 #define XSYSMONPSU_ISR_0_PL_ALM_12_SHIFT 28U
108 #define XSYSMONPSU_ISR_0_PL_ALM_12_WIDTH 1U
109 #define XSYSMONPSU_ISR_0_PL_ALM_12_MASK 0x10000000U
111 #define XSYSMONPSU_ISR_0_PL_ALM_11_SHIFT 27U
112 #define XSYSMONPSU_ISR_0_PL_ALM_11_WIDTH 1U
113 #define XSYSMONPSU_ISR_0_PL_ALM_11_MASK 0x08000000U
115 #define XSYSMONPSU_ISR_0_PL_ALM_10_SHIFT 26U
116 #define XSYSMONPSU_ISR_0_PL_ALM_10_WIDTH 1U
117 #define XSYSMONPSU_ISR_0_PL_ALM_10_MASK 0x04000000U
119 #define XSYSMONPSU_ISR_0_PL_ALM_9_SHIFT 25U
120 #define XSYSMONPSU_ISR_0_PL_ALM_9_WIDTH 1U
121 #define XSYSMONPSU_ISR_0_PL_ALM_9_MASK 0x02000000U
123 #define XSYSMONPSU_ISR_0_PL_ALM_8_SHIFT 24U
124 #define XSYSMONPSU_ISR_0_PL_ALM_8_WIDTH 1U
125 #define XSYSMONPSU_ISR_0_PL_ALM_8_MASK 0x01000000U
127 #define XSYSMONPSU_ISR_0_PL_ALM_7_SHIFT 23U
128 #define XSYSMONPSU_ISR_0_PL_ALM_7_WIDTH 1U
129 #define XSYSMONPSU_ISR_0_PL_ALM_7_MASK 0x00800000U
131 #define XSYSMONPSU_ISR_0_PL_ALM_6_SHIFT 22U
132 #define XSYSMONPSU_ISR_0_PL_ALM_6_WIDTH 1U
133 #define XSYSMONPSU_ISR_0_PL_ALM_6_MASK 0x00400000U
135 #define XSYSMONPSU_ISR_0_PL_ALM_5_SHIFT 21U
136 #define XSYSMONPSU_ISR_0_PL_ALM_5_WIDTH 1U
137 #define XSYSMONPSU_ISR_0_PL_ALM_5_MASK 0x00200000U
139 #define XSYSMONPSU_ISR_0_PL_ALM_4_SHIFT 20U
140 #define XSYSMONPSU_ISR_0_PL_ALM_4_WIDTH 1U
141 #define XSYSMONPSU_ISR_0_PL_ALM_4_MASK 0x00100000U
143 #define XSYSMONPSU_ISR_0_PL_ALM_3_SHIFT 19U
144 #define XSYSMONPSU_ISR_0_PL_ALM_3_WIDTH 1U
145 #define XSYSMONPSU_ISR_0_PL_ALM_3_MASK 0x00080000U
147 #define XSYSMONPSU_ISR_0_PL_ALM_2_SHIFT 18U
148 #define XSYSMONPSU_ISR_0_PL_ALM_2_WIDTH 1U
149 #define XSYSMONPSU_ISR_0_PL_ALM_2_MASK 0x00040000U
151 #define XSYSMONPSU_ISR_0_PL_ALM_1_SHIFT 17U
152 #define XSYSMONPSU_ISR_0_PL_ALM_1_WIDTH 1U
153 #define XSYSMONPSU_ISR_0_PL_ALM_1_MASK 0x00020000U
155 #define XSYSMONPSU_ISR_0_PL_ALM_0_SHIFT 16U
156 #define XSYSMONPSU_ISR_0_PL_ALM_0_WIDTH 1U
157 #define XSYSMONPSU_ISR_0_PL_ALM_0_MASK 0x00010000U
159 #define XSYSMONPSU_ISR_0_PS_ALM_15_SHIFT 15U
160 #define XSYSMONPSU_ISR_0_PS_ALM_15_WIDTH 1U
161 #define XSYSMONPSU_ISR_0_PS_ALM_15_MASK 0x00008000U
163 #define XSYSMONPSU_ISR_0_PS_ALM_14_SHIFT 14U
164 #define XSYSMONPSU_ISR_0_PS_ALM_14_WIDTH 1U
165 #define XSYSMONPSU_ISR_0_PS_ALM_14_MASK 0x00004000U
167 #define XSYSMONPSU_ISR_0_PS_ALM_13_SHIFT 13U
168 #define XSYSMONPSU_ISR_0_PS_ALM_13_WIDTH 1U
169 #define XSYSMONPSU_ISR_0_PS_ALM_13_MASK 0x00002000U
171 #define XSYSMONPSU_ISR_0_PS_ALM_12_SHIFT 12U
172 #define XSYSMONPSU_ISR_0_PS_ALM_12_WIDTH 1U
173 #define XSYSMONPSU_ISR_0_PS_ALM_12_MASK 0x00001000U
175 #define XSYSMONPSU_ISR_0_PS_ALM_11_SHIFT 11U
176 #define XSYSMONPSU_ISR_0_PS_ALM_11_WIDTH 1U
177 #define XSYSMONPSU_ISR_0_PS_ALM_11_MASK 0x00000800U
179 #define XSYSMONPSU_ISR_0_PS_ALM_10_SHIFT 10U
180 #define XSYSMONPSU_ISR_0_PS_ALM_10_WIDTH 1U
181 #define XSYSMONPSU_ISR_0_PS_ALM_10_MASK 0x00000400U
183 #define XSYSMONPSU_ISR_0_PS_ALM_9_SHIFT 9U
184 #define XSYSMONPSU_ISR_0_PS_ALM_9_WIDTH 1U
185 #define XSYSMONPSU_ISR_0_PS_ALM_9_MASK 0x00000200U
187 #define XSYSMONPSU_ISR_0_PS_ALM_8_SHIFT 8U
188 #define XSYSMONPSU_ISR_0_PS_ALM_8_WIDTH 1U
189 #define XSYSMONPSU_ISR_0_PS_ALM_8_MASK 0x00000100U
191 #define XSYSMONPSU_ISR_0_PS_ALM_7_SHIFT 7U
192 #define XSYSMONPSU_ISR_0_PS_ALM_7_WIDTH 1U
193 #define XSYSMONPSU_ISR_0_PS_ALM_7_MASK 0x00000080U
195 #define XSYSMONPSU_ISR_0_PS_ALM_6_SHIFT 6U
196 #define XSYSMONPSU_ISR_0_PS_ALM_6_WIDTH 1U
197 #define XSYSMONPSU_ISR_0_PS_ALM_6_MASK 0x00000040U
199 #define XSYSMONPSU_ISR_0_PS_ALM_5_SHIFT 5U
200 #define XSYSMONPSU_ISR_0_PS_ALM_5_WIDTH 1U
201 #define XSYSMONPSU_ISR_0_PS_ALM_5_MASK 0x00000020U
203 #define XSYSMONPSU_ISR_0_PS_ALM_4_SHIFT 4U
204 #define XSYSMONPSU_ISR_0_PS_ALM_4_WIDTH 1U
205 #define XSYSMONPSU_ISR_0_PS_ALM_4_MASK 0x00000010U
207 #define XSYSMONPSU_ISR_0_PS_ALM_3_SHIFT 3U
208 #define XSYSMONPSU_ISR_0_PS_ALM_3_WIDTH 1U
209 #define XSYSMONPSU_ISR_0_PS_ALM_3_MASK 0x00000008U
211 #define XSYSMONPSU_ISR_0_PS_ALM_2_SHIFT 2U
212 #define XSYSMONPSU_ISR_0_PS_ALM_2_WIDTH 1U
213 #define XSYSMONPSU_ISR_0_PS_ALM_2_MASK 0x00000004U
215 #define XSYSMONPSU_ISR_0_PS_ALM_1_SHIFT 1U
216 #define XSYSMONPSU_ISR_0_PS_ALM_1_WIDTH 1U
217 #define XSYSMONPSU_ISR_0_PS_ALM_1_MASK 0x00000002U
219 #define XSYSMONPSU_ISR_0_PS_ALM_0_SHIFT 0U
220 #define XSYSMONPSU_ISR_0_PS_ALM_0_WIDTH 1U
221 #define XSYSMONPSU_ISR_0_PS_ALM_0_MASK 0x00000001U
224 * Register: XSysmonPsuIsr1
226 #define XSYSMONPSU_ISR_1_OFFSET 0x00000014U
227 #define XSYSMONPSU_ISR_1_MASK 0xe000001fU
228 #define XSYSMONPSU_ISR_1_RSTVAL 0x00000000U
230 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_SHIFT 31U
231 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_WIDTH 1U
232 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_MASK 0x80000000U
234 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
235 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
236 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
238 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
239 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
240 #define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
242 #define XSYSMONPSU_ISR_1_EOS_SHIFT 4U
243 #define XSYSMONPSU_ISR_1_EOS_WIDTH 1U
244 #define XSYSMONPSU_ISR_1_EOS_MASK 0x00000010U
246 #define XSYSMONPSU_ISR_1_EOC_SHIFT 3U
247 #define XSYSMONPSU_ISR_1_EOC_WIDTH 1U
248 #define XSYSMONPSU_ISR_1_EOC_MASK 0x00000008U
250 #define XSYSMONPSU_ISR_1_PL_OT_SHIFT 2U
251 #define XSYSMONPSU_ISR_1_PL_OT_WIDTH 1U
252 #define XSYSMONPSU_ISR_1_PL_OT_MASK 0x00000004U
254 #define XSYSMONPSU_ISR_1_PS_LPD_OT_SHIFT 1U
255 #define XSYSMONPSU_ISR_1_PS_LPD_OT_WIDTH 1U
256 #define XSYSMONPSU_ISR_1_PS_LPD_OT_MASK 0x00000002U
258 #define XSYSMONPSU_ISR_1_PS_FPD_OT_SHIFT 0U
259 #define XSYSMONPSU_ISR_1_PS_FPD_OT_WIDTH 1U
260 #define XSYSMONPSU_ISR_1_PS_FPD_OT_MASK 0x00000001U
263 * Register: XSysmonPsuImr0
265 #define XSYSMONPSU_IMR_0_OFFSET 0x00000018U
266 #define XSYSMONPSU_IMR_0_RSTVAL 0xffffffffU
268 #define XSYSMONPSU_IMR_0_PL_ALM_15_SHIFT 31U
269 #define XSYSMONPSU_IMR_0_PL_ALM_15_WIDTH 1U
270 #define XSYSMONPSU_IMR_0_PL_ALM_15_MASK 0x80000000U
272 #define XSYSMONPSU_IMR_0_PL_ALM_14_SHIFT 30U
273 #define XSYSMONPSU_IMR_0_PL_ALM_14_WIDTH 1U
274 #define XSYSMONPSU_IMR_0_PL_ALM_14_MASK 0x40000000U
276 #define XSYSMONPSU_IMR_0_PL_ALM_13_SHIFT 29U
277 #define XSYSMONPSU_IMR_0_PL_ALM_13_WIDTH 1U
278 #define XSYSMONPSU_IMR_0_PL_ALM_13_MASK 0x20000000U
280 #define XSYSMONPSU_IMR_0_PL_ALM_12_SHIFT 28U
281 #define XSYSMONPSU_IMR_0_PL_ALM_12_WIDTH 1U
282 #define XSYSMONPSU_IMR_0_PL_ALM_12_MASK 0x10000000U
284 #define XSYSMONPSU_IMR_0_PL_ALM_11_SHIFT 27U
285 #define XSYSMONPSU_IMR_0_PL_ALM_11_WIDTH 1U
286 #define XSYSMONPSU_IMR_0_PL_ALM_11_MASK 0x08000000U
288 #define XSYSMONPSU_IMR_0_PL_ALM_10_SHIFT 26U
289 #define XSYSMONPSU_IMR_0_PL_ALM_10_WIDTH 1U
290 #define XSYSMONPSU_IMR_0_PL_ALM_10_MASK 0x04000000U
292 #define XSYSMONPSU_IMR_0_PL_ALM_9_SHIFT 25U
293 #define XSYSMONPSU_IMR_0_PL_ALM_9_WIDTH 1U
294 #define XSYSMONPSU_IMR_0_PL_ALM_9_MASK 0x02000000U
296 #define XSYSMONPSU_IMR_0_PL_ALM_8_SHIFT 24U
297 #define XSYSMONPSU_IMR_0_PL_ALM_8_WIDTH 1U
298 #define XSYSMONPSU_IMR_0_PL_ALM_8_MASK 0x01000000U
300 #define XSYSMONPSU_IMR_0_PL_ALM_7_SHIFT 23U
301 #define XSYSMONPSU_IMR_0_PL_ALM_7_WIDTH 1U
302 #define XSYSMONPSU_IMR_0_PL_ALM_7_MASK 0x00800000U
304 #define XSYSMONPSU_IMR_0_PL_ALM_6_SHIFT 22U
305 #define XSYSMONPSU_IMR_0_PL_ALM_6_WIDTH 1U
306 #define XSYSMONPSU_IMR_0_PL_ALM_6_MASK 0x00400000U
308 #define XSYSMONPSU_IMR_0_PL_ALM_5_SHIFT 21U
309 #define XSYSMONPSU_IMR_0_PL_ALM_5_WIDTH 1U
310 #define XSYSMONPSU_IMR_0_PL_ALM_5_MASK 0x00200000U
312 #define XSYSMONPSU_IMR_0_PL_ALM_4_SHIFT 20U
313 #define XSYSMONPSU_IMR_0_PL_ALM_4_WIDTH 1U
314 #define XSYSMONPSU_IMR_0_PL_ALM_4_MASK 0x00100000U
316 #define XSYSMONPSU_IMR_0_PL_ALM_3_SHIFT 19U
317 #define XSYSMONPSU_IMR_0_PL_ALM_3_WIDTH 1U
318 #define XSYSMONPSU_IMR_0_PL_ALM_3_MASK 0x00080000U
320 #define XSYSMONPSU_IMR_0_PL_ALM_2_SHIFT 18U
321 #define XSYSMONPSU_IMR_0_PL_ALM_2_WIDTH 1U
322 #define XSYSMONPSU_IMR_0_PL_ALM_2_MASK 0x00040000U
324 #define XSYSMONPSU_IMR_0_PL_ALM_1_SHIFT 17U
325 #define XSYSMONPSU_IMR_0_PL_ALM_1_WIDTH 1U
326 #define XSYSMONPSU_IMR_0_PL_ALM_1_MASK 0x00020000U
328 #define XSYSMONPSU_IMR_0_PL_ALM_0_SHIFT 16U
329 #define XSYSMONPSU_IMR_0_PL_ALM_0_WIDTH 1U
330 #define XSYSMONPSU_IMR_0_PL_ALM_0_MASK 0x00010000U
332 #define XSYSMONPSU_IMR_0_PS_ALM_15_SHIFT 15U
333 #define XSYSMONPSU_IMR_0_PS_ALM_15_WIDTH 1U
334 #define XSYSMONPSU_IMR_0_PS_ALM_15_MASK 0x00008000U
336 #define XSYSMONPSU_IMR_0_PS_ALM_14_SHIFT 14U
337 #define XSYSMONPSU_IMR_0_PS_ALM_14_WIDTH 1U
338 #define XSYSMONPSU_IMR_0_PS_ALM_14_MASK 0x00004000U
340 #define XSYSMONPSU_IMR_0_PS_ALM_13_SHIFT 13U
341 #define XSYSMONPSU_IMR_0_PS_ALM_13_WIDTH 1U
342 #define XSYSMONPSU_IMR_0_PS_ALM_13_MASK 0x00002000U
344 #define XSYSMONPSU_IMR_0_PS_ALM_12_SHIFT 12U
345 #define XSYSMONPSU_IMR_0_PS_ALM_12_WIDTH 1U
346 #define XSYSMONPSU_IMR_0_PS_ALM_12_MASK 0x00001000U
348 #define XSYSMONPSU_IMR_0_PS_ALM_11_SHIFT 11U
349 #define XSYSMONPSU_IMR_0_PS_ALM_11_WIDTH 1U
350 #define XSYSMONPSU_IMR_0_PS_ALM_11_MASK 0x00000800U
352 #define XSYSMONPSU_IMR_0_PS_ALM_10_SHIFT 10U
353 #define XSYSMONPSU_IMR_0_PS_ALM_10_WIDTH 1U
354 #define XSYSMONPSU_IMR_0_PS_ALM_10_MASK 0x00000400U
356 #define XSYSMONPSU_IMR_0_PS_ALM_9_SHIFT 9U
357 #define XSYSMONPSU_IMR_0_PS_ALM_9_WIDTH 1U
358 #define XSYSMONPSU_IMR_0_PS_ALM_9_MASK 0x00000200U
360 #define XSYSMONPSU_IMR_0_PS_ALM_8_SHIFT 8U
361 #define XSYSMONPSU_IMR_0_PS_ALM_8_WIDTH 1U
362 #define XSYSMONPSU_IMR_0_PS_ALM_8_MASK 0x00000100U
364 #define XSYSMONPSU_IMR_0_PS_ALM_7_SHIFT 7U
365 #define XSYSMONPSU_IMR_0_PS_ALM_7_WIDTH 1U
366 #define XSYSMONPSU_IMR_0_PS_ALM_7_MASK 0x00000080U
368 #define XSYSMONPSU_IMR_0_PS_ALM_6_SHIFT 6U
369 #define XSYSMONPSU_IMR_0_PS_ALM_6_WIDTH 1U
370 #define XSYSMONPSU_IMR_0_PS_ALM_6_MASK 0x00000040U
372 #define XSYSMONPSU_IMR_0_PS_ALM_5_SHIFT 5U
373 #define XSYSMONPSU_IMR_0_PS_ALM_5_WIDTH 1U
374 #define XSYSMONPSU_IMR_0_PS_ALM_5_MASK 0x00000020U
376 #define XSYSMONPSU_IMR_0_PS_ALM_4_SHIFT 4U
377 #define XSYSMONPSU_IMR_0_PS_ALM_4_WIDTH 1U
378 #define XSYSMONPSU_IMR_0_PS_ALM_4_MASK 0x00000010U
380 #define XSYSMONPSU_IMR_0_PS_ALM_3_SHIFT 3U
381 #define XSYSMONPSU_IMR_0_PS_ALM_3_WIDTH 1U
382 #define XSYSMONPSU_IMR_0_PS_ALM_3_MASK 0x00000008U
384 #define XSYSMONPSU_IMR_0_PS_ALM_2_SHIFT 2U
385 #define XSYSMONPSU_IMR_0_PS_ALM_2_WIDTH 1U
386 #define XSYSMONPSU_IMR_0_PS_ALM_2_MASK 0x00000004U
388 #define XSYSMONPSU_IMR_0_PS_ALM_1_SHIFT 1U
389 #define XSYSMONPSU_IMR_0_PS_ALM_1_WIDTH 1U
390 #define XSYSMONPSU_IMR_0_PS_ALM_1_MASK 0x00000002U
392 #define XSYSMONPSU_IMR_0_PS_ALM_0_SHIFT 0U
393 #define XSYSMONPSU_IMR_0_PS_ALM_0_WIDTH 1U
394 #define XSYSMONPSU_IMR_0_PS_ALM_0_MASK 0x00000001U
397 * Register: XSysmonPsuImr1
399 #define XSYSMONPSU_IMR_1_OFFSET 0x0000001CU
400 #define XSYSMONPSU_IMR_1_RSTVAL 0xe000001fU
402 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_SHIFT 31U
403 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_WIDTH 1U
404 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_MASK 0x80000000U
406 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
407 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
408 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
410 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
411 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
412 #define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
414 #define XSYSMONPSU_IMR_1_EOS_SHIFT 4U
415 #define XSYSMONPSU_IMR_1_EOS_WIDTH 1U
416 #define XSYSMONPSU_IMR_1_EOS_MASK 0x00000010U
418 #define XSYSMONPSU_IMR_1_EOC_SHIFT 3U
419 #define XSYSMONPSU_IMR_1_EOC_WIDTH 1U
420 #define XSYSMONPSU_IMR_1_EOC_MASK 0x00000008U
422 #define XSYSMONPSU_IMR_1_PL_OT_SHIFT 2U
423 #define XSYSMONPSU_IMR_1_PL_OT_WIDTH 1U
424 #define XSYSMONPSU_IMR_1_PL_OT_MASK 0x00000004U
426 #define XSYSMONPSU_IMR_1_PS_LPD_OT_SHIFT 1U
427 #define XSYSMONPSU_IMR_1_PS_LPD_OT_WIDTH 1U
428 #define XSYSMONPSU_IMR_1_PS_LPD_OT_MASK 0x00000002U
430 #define XSYSMONPSU_IMR_1_PS_FPD_OT_SHIFT 0U
431 #define XSYSMONPSU_IMR_1_PS_FPD_OT_WIDTH 1U
432 #define XSYSMONPSU_IMR_1_PS_FPD_OT_MASK 0x00000001U
435 * Register: XSysmonPsuIer0
437 #define XSYSMONPSU_IER_0_OFFSET 0x00000020U
438 #define XSYSMONPSU_IXR_0_MASK 0xFFFFFFFFU
439 #define XSYSMONPSU_IER_0_RSTVAL 0x00000000U
441 #define XSYSMONPSU_IER_0_PL_ALM_15_SHIFT 31U
442 #define XSYSMONPSU_IER_0_PL_ALM_15_WIDTH 1U
443 #define XSYSMONPSU_IER_0_PL_ALM_15_MASK 0x80000000U
445 #define XSYSMONPSU_IER_0_PL_ALM_14_SHIFT 30U
446 #define XSYSMONPSU_IER_0_PL_ALM_14_WIDTH 1U
447 #define XSYSMONPSU_IER_0_PL_ALM_14_MASK 0x40000000U
449 #define XSYSMONPSU_IER_0_PL_ALM_13_SHIFT 29U
450 #define XSYSMONPSU_IER_0_PL_ALM_13_WIDTH 1U
451 #define XSYSMONPSU_IER_0_PL_ALM_13_MASK 0x20000000U
453 #define XSYSMONPSU_IER_0_PL_ALM_12_SHIFT 28U
454 #define XSYSMONPSU_IER_0_PL_ALM_12_WIDTH 1U
455 #define XSYSMONPSU_IER_0_PL_ALM_12_MASK 0x10000000U
457 #define XSYSMONPSU_IER_0_PL_ALM_11_SHIFT 27U
458 #define XSYSMONPSU_IER_0_PL_ALM_11_WIDTH 1U
459 #define XSYSMONPSU_IER_0_PL_ALM_11_MASK 0x08000000U
461 #define XSYSMONPSU_IER_0_PL_ALM_10_SHIFT 26U
462 #define XSYSMONPSU_IER_0_PL_ALM_10_WIDTH 1U
463 #define XSYSMONPSU_IER_0_PL_ALM_10_MASK 0x04000000U
465 #define XSYSMONPSU_IER_0_PL_ALM_9_SHIFT 25U
466 #define XSYSMONPSU_IER_0_PL_ALM_9_WIDTH 1U
467 #define XSYSMONPSU_IER_0_PL_ALM_9_MASK 0x02000000U
469 #define XSYSMONPSU_IER_0_PL_ALM_8_SHIFT 24U
470 #define XSYSMONPSU_IER_0_PL_ALM_8_WIDTH 1U
471 #define XSYSMONPSU_IER_0_PL_ALM_8_MASK 0x01000000U
473 #define XSYSMONPSU_IER_0_PL_ALM_7_SHIFT 23U
474 #define XSYSMONPSU_IER_0_PL_ALM_7_WIDTH 1U
475 #define XSYSMONPSU_IER_0_PL_ALM_7_MASK 0x00800000U
477 #define XSYSMONPSU_IER_0_PL_ALM_6_SHIFT 22U
478 #define XSYSMONPSU_IER_0_PL_ALM_6_WIDTH 1U
479 #define XSYSMONPSU_IER_0_PL_ALM_6_MASK 0x00400000U
481 #define XSYSMONPSU_IER_0_PL_ALM_5_SHIFT 21U
482 #define XSYSMONPSU_IER_0_PL_ALM_5_WIDTH 1U
483 #define XSYSMONPSU_IER_0_PL_ALM_5_MASK 0x00200000U
485 #define XSYSMONPSU_IER_0_PL_ALM_4_SHIFT 20U
486 #define XSYSMONPSU_IER_0_PL_ALM_4_WIDTH 1U
487 #define XSYSMONPSU_IER_0_PL_ALM_4_MASK 0x00100000U
489 #define XSYSMONPSU_IER_0_PL_ALM_3_SHIFT 19U
490 #define XSYSMONPSU_IER_0_PL_ALM_3_WIDTH 1U
491 #define XSYSMONPSU_IER_0_PL_ALM_3_MASK 0x00080000U
493 #define XSYSMONPSU_IER_0_PL_ALM_2_SHIFT 18U
494 #define XSYSMONPSU_IER_0_PL_ALM_2_WIDTH 1U
495 #define XSYSMONPSU_IER_0_PL_ALM_2_MASK 0x00040000U
497 #define XSYSMONPSU_IER_0_PL_ALM_1_SHIFT 17U
498 #define XSYSMONPSU_IER_0_PL_ALM_1_WIDTH 1U
499 #define XSYSMONPSU_IER_0_PL_ALM_1_MASK 0x00020000U
501 #define XSYSMONPSU_IER_0_PL_ALM_0_SHIFT 16U
502 #define XSYSMONPSU_IER_0_PL_ALM_0_WIDTH 1U
503 #define XSYSMONPSU_IER_0_PL_ALM_0_MASK 0x00010000U
505 #define XSYSMONPSU_IER_0_PS_ALM_15_SHIFT 15U
506 #define XSYSMONPSU_IER_0_PS_ALM_15_WIDTH 1U
507 #define XSYSMONPSU_IER_0_PS_ALM_15_MASK 0x00008000U
509 #define XSYSMONPSU_IER_0_PS_ALM_14_SHIFT 14U
510 #define XSYSMONPSU_IER_0_PS_ALM_14_WIDTH 1U
511 #define XSYSMONPSU_IER_0_PS_ALM_14_MASK 0x00004000U
513 #define XSYSMONPSU_IER_0_PS_ALM_13_SHIFT 13U
514 #define XSYSMONPSU_IER_0_PS_ALM_13_WIDTH 1U
515 #define XSYSMONPSU_IER_0_PS_ALM_13_MASK 0x00002000U
517 #define XSYSMONPSU_IER_0_PS_ALM_12_SHIFT 12U
518 #define XSYSMONPSU_IER_0_PS_ALM_12_WIDTH 1U
519 #define XSYSMONPSU_IER_0_PS_ALM_12_MASK 0x00001000U
521 #define XSYSMONPSU_IER_0_PS_ALM_11_SHIFT 11U
522 #define XSYSMONPSU_IER_0_PS_ALM_11_WIDTH 1U
523 #define XSYSMONPSU_IER_0_PS_ALM_11_MASK 0x00000800U
525 #define XSYSMONPSU_IER_0_PS_ALM_10_SHIFT 10U
526 #define XSYSMONPSU_IER_0_PS_ALM_10_WIDTH 1U
527 #define XSYSMONPSU_IER_0_PS_ALM_10_MASK 0x00000400U
529 #define XSYSMONPSU_IER_0_PS_ALM_9_SHIFT 9U
530 #define XSYSMONPSU_IER_0_PS_ALM_9_WIDTH 1U
531 #define XSYSMONPSU_IER_0_PS_ALM_9_MASK 0x00000200U
533 #define XSYSMONPSU_IER_0_PS_ALM_8_SHIFT 8U
534 #define XSYSMONPSU_IER_0_PS_ALM_8_WIDTH 1U
535 #define XSYSMONPSU_IER_0_PS_ALM_8_MASK 0x00000100U
537 #define XSYSMONPSU_IER_0_PS_ALM_7_SHIFT 7U
538 #define XSYSMONPSU_IER_0_PS_ALM_7_WIDTH 1U
539 #define XSYSMONPSU_IER_0_PS_ALM_7_MASK 0x00000080U
541 #define XSYSMONPSU_IER_0_PS_ALM_6_SHIFT 6U
542 #define XSYSMONPSU_IER_0_PS_ALM_6_WIDTH 1U
543 #define XSYSMONPSU_IER_0_PS_ALM_6_MASK 0x00000040U
545 #define XSYSMONPSU_IER_0_PS_ALM_5_SHIFT 5U
546 #define XSYSMONPSU_IER_0_PS_ALM_5_WIDTH 1U
547 #define XSYSMONPSU_IER_0_PS_ALM_5_MASK 0x00000020U
549 #define XSYSMONPSU_IER_0_PS_ALM_4_SHIFT 4U
550 #define XSYSMONPSU_IER_0_PS_ALM_4_WIDTH 1U
551 #define XSYSMONPSU_IER_0_PS_ALM_4_MASK 0x00000010U
553 #define XSYSMONPSU_IER_0_PS_ALM_3_SHIFT 3U
554 #define XSYSMONPSU_IER_0_PS_ALM_3_WIDTH 1U
555 #define XSYSMONPSU_IER_0_PS_ALM_3_MASK 0x00000008U
557 #define XSYSMONPSU_IER_0_PS_ALM_2_SHIFT 2U
558 #define XSYSMONPSU_IER_0_PS_ALM_2_WIDTH 1U
559 #define XSYSMONPSU_IER_0_PS_ALM_2_MASK 0x00000004U
561 #define XSYSMONPSU_IER_0_PS_ALM_1_SHIFT 1U
562 #define XSYSMONPSU_IER_0_PS_ALM_1_WIDTH 1U
563 #define XSYSMONPSU_IER_0_PS_ALM_1_MASK 0x00000002U
565 #define XSYSMONPSU_IER_0_PS_ALM_0_SHIFT 0U
566 #define XSYSMONPSU_IER_0_PS_ALM_0_WIDTH 1U
567 #define XSYSMONPSU_IER_0_PS_ALM_0_MASK 0x00000001U
570 * Register: XSysmonPsuIer1
572 #define XSYSMONPSU_IER_1_OFFSET 0x00000024U
573 #define XSYSMONPSU_IXR_1_MASK 0xE000001FU
574 #define XSYSMONPSU_IER_1_RSTVAL 0x00000000U
576 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_SHIFT 31U
577 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_WIDTH 1U
578 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_MASK 0x80000000U
580 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
581 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
582 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
584 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
585 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
586 #define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
588 #define XSYSMONPSU_IER_1_EOS_SHIFT 4U
589 #define XSYSMONPSU_IER_1_EOS_WIDTH 1U
590 #define XSYSMONPSU_IER_1_EOS_MASK 0x00000010U
592 #define XSYSMONPSU_IER_1_EOC_SHIFT 3U
593 #define XSYSMONPSU_IER_1_EOC_WIDTH 1U
594 #define XSYSMONPSU_IER_1_EOC_MASK 0x00000008U
596 #define XSYSMONPSU_IER_1_PL_OT_SHIFT 2U
597 #define XSYSMONPSU_IER_1_PL_OT_WIDTH 1U
598 #define XSYSMONPSU_IER_1_PL_OT_MASK 0x00000004U
600 #define XSYSMONPSU_IER_1_PS_LPD_OT_SHIFT 1U
601 #define XSYSMONPSU_IER_1_PS_LPD_OT_WIDTH 1U
602 #define XSYSMONPSU_IER_1_PS_LPD_OT_MASK 0x00000002U
604 #define XSYSMONPSU_IER_1_PS_FPD_OT_SHIFT 0U
605 #define XSYSMONPSU_IER_1_PS_FPD_OT_WIDTH 1U
606 #define XSYSMONPSU_IER_1_PS_FPD_OT_MASK 0x00000001U
608 #define XSYSMONPSU_IXR_1_SHIFT 32U
611 * Register: XSysmonPsuIdr0
613 #define XSYSMONPSU_IDR_0_OFFSET 0x00000028U
614 #define XSYSMONPSU_IDR_0_RSTVAL 0x00000000U
616 #define XSYSMONPSU_IDR_0_PL_ALM_15_SHIFT 31U
617 #define XSYSMONPSU_IDR_0_PL_ALM_15_WIDTH 1U
618 #define XSYSMONPSU_IDR_0_PL_ALM_15_MASK 0x80000000U
620 #define XSYSMONPSU_IDR_0_PL_ALM_14_SHIFT 30U
621 #define XSYSMONPSU_IDR_0_PL_ALM_14_WIDTH 1U
622 #define XSYSMONPSU_IDR_0_PL_ALM_14_MASK 0x40000000U
624 #define XSYSMONPSU_IDR_0_PL_ALM_13_SHIFT 29U
625 #define XSYSMONPSU_IDR_0_PL_ALM_13_WIDTH 1U
626 #define XSYSMONPSU_IDR_0_PL_ALM_13_MASK 0x20000000U
628 #define XSYSMONPSU_IDR_0_PL_ALM_12_SHIFT 28U
629 #define XSYSMONPSU_IDR_0_PL_ALM_12_WIDTH 1U
630 #define XSYSMONPSU_IDR_0_PL_ALM_12_MASK 0x10000000U
632 #define XSYSMONPSU_IDR_0_PL_ALM_11_SHIFT 27U
633 #define XSYSMONPSU_IDR_0_PL_ALM_11_WIDTH 1U
634 #define XSYSMONPSU_IDR_0_PL_ALM_11_MASK 0x08000000U
636 #define XSYSMONPSU_IDR_0_PL_ALM_10_SHIFT 26U
637 #define XSYSMONPSU_IDR_0_PL_ALM_10_WIDTH 1U
638 #define XSYSMONPSU_IDR_0_PL_ALM_10_MASK 0x04000000U
640 #define XSYSMONPSU_IDR_0_PL_ALM_9_SHIFT 25U
641 #define XSYSMONPSU_IDR_0_PL_ALM_9_WIDTH 1U
642 #define XSYSMONPSU_IDR_0_PL_ALM_9_MASK 0x02000000U
644 #define XSYSMONPSU_IDR_0_PL_ALM_8_SHIFT 24U
645 #define XSYSMONPSU_IDR_0_PL_ALM_8_WIDTH 1U
646 #define XSYSMONPSU_IDR_0_PL_ALM_8_MASK 0x01000000U
648 #define XSYSMONPSU_IDR_0_PL_ALM_7_SHIFT 23U
649 #define XSYSMONPSU_IDR_0_PL_ALM_7_WIDTH 1U
650 #define XSYSMONPSU_IDR_0_PL_ALM_7_MASK 0x00800000U
652 #define XSYSMONPSU_IDR_0_PL_ALM_6_SHIFT 22U
653 #define XSYSMONPSU_IDR_0_PL_ALM_6_WIDTH 1U
654 #define XSYSMONPSU_IDR_0_PL_ALM_6_MASK 0x00400000U
656 #define XSYSMONPSU_IDR_0_PL_ALM_5_SHIFT 21U
657 #define XSYSMONPSU_IDR_0_PL_ALM_5_WIDTH 1U
658 #define XSYSMONPSU_IDR_0_PL_ALM_5_MASK 0x00200000U
660 #define XSYSMONPSU_IDR_0_PL_ALM_4_SHIFT 20U
661 #define XSYSMONPSU_IDR_0_PL_ALM_4_WIDTH 1U
662 #define XSYSMONPSU_IDR_0_PL_ALM_4_MASK 0x00100000U
664 #define XSYSMONPSU_IDR_0_PL_ALM_3_SHIFT 19U
665 #define XSYSMONPSU_IDR_0_PL_ALM_3_WIDTH 1U
666 #define XSYSMONPSU_IDR_0_PL_ALM_3_MASK 0x00080000U
668 #define XSYSMONPSU_IDR_0_PL_ALM_2_SHIFT 18U
669 #define XSYSMONPSU_IDR_0_PL_ALM_2_WIDTH 1U
670 #define XSYSMONPSU_IDR_0_PL_ALM_2_MASK 0x00040000U
672 #define XSYSMONPSU_IDR_0_PL_ALM_1_SHIFT 17U
673 #define XSYSMONPSU_IDR_0_PL_ALM_1_WIDTH 1U
674 #define XSYSMONPSU_IDR_0_PL_ALM_1_MASK 0x00020000U
676 #define XSYSMONPSU_IDR_0_PL_ALM_0_SHIFT 16U
677 #define XSYSMONPSU_IDR_0_PL_ALM_0_WIDTH 1U
678 #define XSYSMONPSU_IDR_0_PL_ALM_0_MASK 0x00010000U
680 #define XSYSMONPSU_IDR_0_PS_ALM_15_SHIFT 15U
681 #define XSYSMONPSU_IDR_0_PS_ALM_15_WIDTH 1U
682 #define XSYSMONPSU_IDR_0_PS_ALM_15_MASK 0x00008000U
684 #define XSYSMONPSU_IDR_0_PS_ALM_14_SHIFT 14U
685 #define XSYSMONPSU_IDR_0_PS_ALM_14_WIDTH 1U
686 #define XSYSMONPSU_IDR_0_PS_ALM_14_MASK 0x00004000U
688 #define XSYSMONPSU_IDR_0_PS_ALM_13_SHIFT 13U
689 #define XSYSMONPSU_IDR_0_PS_ALM_13_WIDTH 1U
690 #define XSYSMONPSU_IDR_0_PS_ALM_13_MASK 0x00002000U
692 #define XSYSMONPSU_IDR_0_PS_ALM_12_SHIFT 12U
693 #define XSYSMONPSU_IDR_0_PS_ALM_12_WIDTH 1U
694 #define XSYSMONPSU_IDR_0_PS_ALM_12_MASK 0x00001000U
696 #define XSYSMONPSU_IDR_0_PS_ALM_11_SHIFT 11U
697 #define XSYSMONPSU_IDR_0_PS_ALM_11_WIDTH 1U
698 #define XSYSMONPSU_IDR_0_PS_ALM_11_MASK 0x00000800U
700 #define XSYSMONPSU_IDR_0_PS_ALM_10_SHIFT 10U
701 #define XSYSMONPSU_IDR_0_PS_ALM_10_WIDTH 1U
702 #define XSYSMONPSU_IDR_0_PS_ALM_10_MASK 0x00000400U
704 #define XSYSMONPSU_IDR_0_PS_ALM_9_SHIFT 9U
705 #define XSYSMONPSU_IDR_0_PS_ALM_9_WIDTH 1U
706 #define XSYSMONPSU_IDR_0_PS_ALM_9_MASK 0x00000200U
708 #define XSYSMONPSU_IDR_0_PS_ALM_8_SHIFT 8U
709 #define XSYSMONPSU_IDR_0_PS_ALM_8_WIDTH 1U
710 #define XSYSMONPSU_IDR_0_PS_ALM_8_MASK 0x00000100U
712 #define XSYSMONPSU_IDR_0_PS_ALM_7_SHIFT 7U
713 #define XSYSMONPSU_IDR_0_PS_ALM_7_WIDTH 1U
714 #define XSYSMONPSU_IDR_0_PS_ALM_7_MASK 0x00000080U
716 #define XSYSMONPSU_IDR_0_PS_ALM_6_SHIFT 6U
717 #define XSYSMONPSU_IDR_0_PS_ALM_6_WIDTH 1U
718 #define XSYSMONPSU_IDR_0_PS_ALM_6_MASK 0x00000040U
720 #define XSYSMONPSU_IDR_0_PS_ALM_5_SHIFT 5U
721 #define XSYSMONPSU_IDR_0_PS_ALM_5_WIDTH 1U
722 #define XSYSMONPSU_IDR_0_PS_ALM_5_MASK 0x00000020U
724 #define XSYSMONPSU_IDR_0_PS_ALM_4_SHIFT 4U
725 #define XSYSMONPSU_IDR_0_PS_ALM_4_WIDTH 1U
726 #define XSYSMONPSU_IDR_0_PS_ALM_4_MASK 0x00000010U
728 #define XSYSMONPSU_IDR_0_PS_ALM_3_SHIFT 3U
729 #define XSYSMONPSU_IDR_0_PS_ALM_3_WIDTH 1U
730 #define XSYSMONPSU_IDR_0_PS_ALM_3_MASK 0x00000008U
732 #define XSYSMONPSU_IDR_0_PS_ALM_2_SHIFT 2U
733 #define XSYSMONPSU_IDR_0_PS_ALM_2_WIDTH 1U
734 #define XSYSMONPSU_IDR_0_PS_ALM_2_MASK 0x00000004U
736 #define XSYSMONPSU_IDR_0_PS_ALM_1_SHIFT 1U
737 #define XSYSMONPSU_IDR_0_PS_ALM_1_WIDTH 1U
738 #define XSYSMONPSU_IDR_0_PS_ALM_1_MASK 0x00000002U
740 #define XSYSMONPSU_IDR_0_PS_ALM_0_SHIFT 0U
741 #define XSYSMONPSU_IDR_0_PS_ALM_0_WIDTH 1U
742 #define XSYSMONPSU_IDR_0_PS_ALM_0_MASK 0x00000001U
745 * Register: XSysmonPsuIdr1
747 #define XSYSMONPSU_IDR_1_OFFSET 0x0000002CU
748 #define XSYSMONPSU_IDR_1_RSTVAL 0x00000000U
750 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_SHIFT 31U
751 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_WIDTH 1U
752 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_MASK 0x80000000U
754 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT 30U
755 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH 1U
756 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_MASK 0x40000000U
758 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT 29U
759 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH 1U
760 #define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_MASK 0x20000000U
762 #define XSYSMONPSU_IDR_1_EOS_SHIFT 4U
763 #define XSYSMONPSU_IDR_1_EOS_WIDTH 1U
764 #define XSYSMONPSU_IDR_1_EOS_MASK 0x00000010U
766 #define XSYSMONPSU_IDR_1_EOC_SHIFT 3U
767 #define XSYSMONPSU_IDR_1_EOC_WIDTH 1U
768 #define XSYSMONPSU_IDR_1_EOC_MASK 0x00000008U
770 #define XSYSMONPSU_IDR_1_PL_OT_SHIFT 2U
771 #define XSYSMONPSU_IDR_1_PL_OT_WIDTH 1U
772 #define XSYSMONPSU_IDR_1_PL_OT_MASK 0x00000004U
774 #define XSYSMONPSU_IDR_1_PS_LPD_OT_SHIFT 1U
775 #define XSYSMONPSU_IDR_1_PS_LPD_OT_WIDTH 1U
776 #define XSYSMONPSU_IDR_1_PS_LPD_OT_MASK 0x00000002U
778 #define XSYSMONPSU_IDR_1_PS_FPD_OT_SHIFT 0U
779 #define XSYSMONPSU_IDR_1_PS_FPD_OT_WIDTH 1U
780 #define XSYSMONPSU_IDR_1_PS_FPD_OT_MASK 0x00000001U
783 * Register: XSysmonPsuPsSysmonSts
785 #define XSYSMONPSU_PS_SYSMON_CSTS_OFFSET 0x00000040U
786 #define XSYSMONPSU_PS_SYSMON_CSTS_RSTVAL 0x00000000U
788 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_SHIFT 24U
789 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_WIDTH 4U
790 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_MASK 0x0f000000U
792 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_SHIFT 16U
793 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_WIDTH 1U
794 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_MASK 0x00010000U
796 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_SHIFT 3U
797 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_WIDTH 1U
798 #define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK 0x00000008U
800 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_SHIFT 2U
801 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_WIDTH 1U
802 #define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK 0x00000004U
804 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_SHIFT 1U
805 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_WIDTH 1U
806 #define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_MASK 0x00000002U
808 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_SHIFT 0U
809 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_WIDTH 1U
810 #define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_MASK 0x00000001U
812 #define XSYSMONPSU_PS_SYSMON_READY 0x08010000U
815 * Register: XSysmonPsuPlSysmonSts
817 #define XSYSMONPSU_PL_SYSMON_CSTS_OFFSET 0x00000044U
818 #define XSYSMONPSU_PL_SYSMON_CSTS_RSTVAL 0x00000000U
820 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_SHIFT 0U
821 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_WIDTH 1U
822 #define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK 0x00000001U
825 * Register: XSysmonPsuMonSts
827 #define XSYSMONPSU_MON_STS_OFFSET 0x00000050U
828 #define XSYSMONPSU_MON_STS_RSTVAL 0x00000000U
830 #define XSYSMONPSU_MON_STS_JTAG_LCKD_SHIFT 23U
831 #define XSYSMONPSU_MON_STS_JTAG_LCKD_WIDTH 1U
832 #define XSYSMONPSU_MON_STS_JTAG_LCKD_MASK 0x00800000U
834 #define XSYSMONPSU_MON_STS_BSY_SHIFT 22U
835 #define XSYSMONPSU_MON_STS_BSY_WIDTH 1U
836 #define XSYSMONPSU_MON_STS_BSY_MASK 0x00400000U
838 #define XSYSMONPSU_MON_STS_CH_SHIFT 16U
839 #define XSYSMONPSU_MON_STS_CH_WIDTH 6U
840 #define XSYSMONPSU_MON_STS_CH_MASK 0x003f0000U
842 #define XSYSMONPSU_MON_STS_DATA_SHIFT 0U
843 #define XSYSMONPSU_MON_STS_DATA_WIDTH 16U
844 #define XSYSMONPSU_MON_STS_DATA_MASK 0x0000ffffU
847 * Register: XSysmonPsuVccPspll0
849 #define XSYSMONPSU_VCC_PSPLL0_OFFSET 0x00000060U
850 #define XSYSMONPSU_VCC_PSPLL0_RSTVAL 0x00000000U
852 #define XSYSMONPSU_VCC_PSPLL0_VAL_SHIFT 0U
853 #define XSYSMONPSU_VCC_PSPLL0_VAL_WIDTH 16U
854 #define XSYSMONPSU_VCC_PSPLL0_VAL_MASK 0x0000ffffU
857 * Register: XSysmonPsuVccPspll1
859 #define XSYSMONPSU_VCC_PSPLL1_OFFSET 0x00000064U
860 #define XSYSMONPSU_VCC_PSPLL1_RSTVAL 0x00000000U
862 #define XSYSMONPSU_VCC_PSPLL1_VAL_SHIFT 0U
863 #define XSYSMONPSU_VCC_PSPLL1_VAL_WIDTH 16U
864 #define XSYSMONPSU_VCC_PSPLL1_VAL_MASK 0x0000ffffU
867 * Register: XSysmonPsuVccPspll2
869 #define XSYSMONPSU_VCC_PSPLL2_OFFSET 0x00000068U
870 #define XSYSMONPSU_VCC_PSPLL2_RSTVAL 0x00000000U
872 #define XSYSMONPSU_VCC_PSPLL2_VAL_SHIFT 0U
873 #define XSYSMONPSU_VCC_PSPLL2_VAL_WIDTH 16U
874 #define XSYSMONPSU_VCC_PSPLL2_VAL_MASK 0x0000ffffU
877 * Register: XSysmonPsuVccPspll3
879 #define XSYSMONPSU_VCC_PSPLL3_OFFSET 0x0000006CU
880 #define XSYSMONPSU_VCC_PSPLL3_RSTVAL 0x00000000U
882 #define XSYSMONPSU_VCC_PSPLL3_VAL_SHIFT 0U
883 #define XSYSMONPSU_VCC_PSPLL3_VAL_WIDTH 16U
884 #define XSYSMONPSU_VCC_PSPLL3_VAL_MASK 0x0000ffffU
887 * Register: XSysmonPsuVccPspll4
889 #define XSYSMONPSU_VCC_PSPLL4_OFFSET 0x00000070U
890 #define XSYSMONPSU_VCC_PSPLL4_RSTVAL 0x00000000U
892 #define XSYSMONPSU_VCC_PSPLL4_VAL_SHIFT 0U
893 #define XSYSMONPSU_VCC_PSPLL4_VAL_WIDTH 16U
894 #define XSYSMONPSU_VCC_PSPLL4_VAL_MASK 0x0000ffffU
897 * Register: XSysmonPsuVccPsbatt
899 #define XSYSMONPSU_VCC_PSBATT_OFFSET 0x00000074U
900 #define XSYSMONPSU_VCC_PSBATT_RSTVAL 0x00000000U
902 #define XSYSMONPSU_VCC_PSBATT_VAL_SHIFT 0U
903 #define XSYSMONPSU_VCC_PSBATT_VAL_WIDTH 16U
904 #define XSYSMONPSU_VCC_PSBATT_VAL_MASK 0x0000ffffU
907 * Register: XSysmonPsuVccint
909 #define XSYSMONPSU_VCCINT_OFFSET 0x00000078U
910 #define XSYSMONPSU_VCCINT_RSTVAL 0x00000000U
912 #define XSYSMONPSU_VCCINT_VAL_SHIFT 0U
913 #define XSYSMONPSU_VCCINT_VAL_WIDTH 16U
914 #define XSYSMONPSU_VCCINT_VAL_MASK 0x0000ffffU
917 * Register: XSysmonPsuVccbram
919 #define XSYSMONPSU_VCCBRAM_OFFSET 0x0000007CU
920 #define XSYSMONPSU_VCCBRAM_RSTVAL 0x00000000U
922 #define XSYSMONPSU_VCCBRAM_VAL_SHIFT 0U
923 #define XSYSMONPSU_VCCBRAM_VAL_WIDTH 16U
924 #define XSYSMONPSU_VCCBRAM_VAL_MASK 0x0000ffffU
927 * Register: XSysmonPsuVccaux
929 #define XSYSMONPSU_VCCAUX_OFFSET 0x00000080U
930 #define XSYSMONPSU_VCCAUX_RSTVAL 0x00000000U
932 #define XSYSMONPSU_VCCAUX_VAL_SHIFT 0U
933 #define XSYSMONPSU_VCCAUX_VAL_WIDTH 16U
934 #define XSYSMONPSU_VCCAUX_VAL_MASK 0x0000ffffU
937 * Register: XSysmonPsuVccPsddrpll
939 #define XSYSMONPSU_VCC_PSDDRPLL_OFFSET 0x00000084U
940 #define XSYSMONPSU_VCC_PSDDRPLL_RSTVAL 0x00000000U
942 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_SHIFT 0U
943 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_WIDTH 16U
944 #define XSYSMONPSU_VCC_PSDDRPLL_VAL_MASK 0x0000ffffU
947 * Register: XSysmonPsuDdrphyVref
949 #define XSYSMONPSU_DDRPHY_VREF_OFFSET 0x00000088U
950 #define XSYSMONPSU_DDRPHY_VREF_RSTVAL 0x00000000U
952 #define XSYSMONPSU_DDRPHY_VREF_VAL_SHIFT 0U
953 #define XSYSMONPSU_DDRPHY_VREF_VAL_WIDTH 16U
954 #define XSYSMONPSU_DDRPHY_VREF_VAL_MASK 0x0000ffffU
957 * Register: XSysmonPsuDdrphyAto
959 #define XSYSMONPSU_DDRPHY_ATO_OFFSET 0x0000008CU
960 #define XSYSMONPSU_DDRPHY_ATO_RSTVAL 0x00000000U
962 #define XSYSMONPSU_DDRPHY_ATO_VAL_SHIFT 0U
963 #define XSYSMONPSU_DDRPHY_ATO_VAL_WIDTH 16U
964 #define XSYSMONPSU_DDRPHY_ATO_VAL_MASK 0x0000ffffU
967 * Register: XSysmonPsuPsgtAt0
969 #define XSYSMONPSU_PSGT_AT0_OFFSET 0x00000090U
970 #define XSYSMONPSU_PSGT_AT0_RSTVAL 0x00000000U
972 #define XSYSMONPSU_PSGT_AT0_VAL_SHIFT 0U
973 #define XSYSMONPSU_PSGT_AT0_VAL_WIDTH 16U
974 #define XSYSMONPSU_PSGT_AT0_VAL_MASK 0x0000ffffU
977 * Register: XSysmonPsuPsgtAt1
979 #define XSYSMONPSU_PSGT_AT1_OFFSET 0x00000094U
980 #define XSYSMONPSU_PSGT_AT1_RSTVAL 0x00000000U
982 #define XSYSMONPSU_PSGT_AT1_VAL_SHIFT 0U
983 #define XSYSMONPSU_PSGT_AT1_VAL_WIDTH 16U
984 #define XSYSMONPSU_PSGT_AT1_VAL_MASK 0x0000ffffU
987 * Register: XSysmonPsuReserve0
989 #define XSYSMONPSU_RESERVE0_OFFSET 0x00000098U
990 #define XSYSMONPSU_RESERVE0_RSTVAL 0x00000000U
992 #define XSYSMONPSU_RESERVE0_VAL_SHIFT 0U
993 #define XSYSMONPSU_RESERVE0_VAL_WIDTH 16U
994 #define XSYSMONPSU_RESERVE0_VAL_MASK 0x0000ffffU
997 * Register: XSysmonPsuReserve1
999 #define XSYSMONPSU_RESERVE1_OFFSET 0x0000009CU
1000 #define XSYSMONPSU_RESERVE1_RSTVAL 0x00000000U
1002 #define XSYSMONPSU_RESERVE1_VAL_SHIFT 0U
1003 #define XSYSMONPSU_RESERVE1_VAL_WIDTH 16U
1004 #define XSYSMONPSU_RESERVE1_VAL_MASK 0x0000ffffU
1007 * Register: XSysmonPsuTemp
1009 #define XSYSMONPSU_TEMP_OFFSET 0x00000000U
1010 #define XSYSMONPSU_TEMP_RSTVAL 0x00000000U
1012 #define XSYSMONPSU_TEMP_SHIFT 0U
1013 #define XSYSMONPSU_TEMP_WIDTH 16U
1014 #define XSYSMONPSU_TEMP_MASK 0x0000ffffU
1017 * Register: XSysmonPsuSup1
1019 #define XSYSMONPSU_SUP1_OFFSET 0x00000004U
1020 #define XSYSMONPSU_SUP1_RSTVAL 0x00000000U
1022 #define XSYSMONPSU_SUP1_SUP_VAL_SHIFT 0U
1023 #define XSYSMONPSU_SUP1_SUP_VAL_WIDTH 16U
1024 #define XSYSMONPSU_SUP1_SUP_VAL_MASK 0x0000ffffU
1027 * Register: XSysmonPsuSup2
1029 #define XSYSMONPSU_SUP2_OFFSET 0x00000008U
1030 #define XSYSMONPSU_SUP2_RSTVAL 0x00000000U
1032 #define XSYSMONPSU_SUP2_SUP_VAL_SHIFT 0U
1033 #define XSYSMONPSU_SUP2_SUP_VAL_WIDTH 16U
1034 #define XSYSMONPSU_SUP2_SUP_VAL_MASK 0x0000ffffU
1037 * Register: XSysmonPsuVpVn
1039 #define XSYSMONPSU_VP_VN_OFFSET 0x0000000CU
1040 #define XSYSMONPSU_VP_VN_RSTVAL 0x00000000U
1042 #define XSYSMONPSU_VP_VN_SHIFT 0U
1043 #define XSYSMONPSU_VP_VN_WIDTH 16U
1044 #define XSYSMONPSU_VP_VN_MASK 0x0000ffffU
1047 * Register: XSysmonPsuVrefp
1049 #define XSYSMONPSU_VREFP_OFFSET 0x00000010U
1050 #define XSYSMONPSU_VREFP_RSTVAL 0x00000000U
1052 #define XSYSMONPSU_VREFP_SUP_VAL_SHIFT 0U
1053 #define XSYSMONPSU_VREFP_SUP_VAL_WIDTH 16U
1054 #define XSYSMONPSU_VREFP_SUP_VAL_MASK 0x0000ffffU
1057 * Register: XSysmonPsuVrefn
1059 #define XSYSMONPSU_VREFN_OFFSET 0x00000014U
1060 #define XSYSMONPSU_VREFN_RSTVAL 0x00000000U
1062 #define XSYSMONPSU_VREFN_SUP_VAL_SHIFT 0U
1063 #define XSYSMONPSU_VREFN_SUP_VAL_WIDTH 16U
1064 #define XSYSMONPSU_VREFN_SUP_VAL_MASK 0x0000ffffU
1067 * Register: XSysmonPsuSup3
1069 #define XSYSMONPSU_SUP3_OFFSET 0x00000018U
1070 #define XSYSMONPSU_SUP3_RSTVAL 0x00000000U
1072 #define XSYSMONPSU_SUP3_SUP_VAL_SHIFT 0U
1073 #define XSYSMONPSU_SUP3_SUP_VAL_WIDTH 16U
1074 #define XSYSMONPSU_SUP3_SUP_VAL_MASK 0x0000ffffU
1077 * Register: XSysmonPsuCalSupOff
1079 #define XSYSMONPSU_CAL_SUP_OFF_OFFSET 0x00000020U
1080 #define XSYSMONPSU_CAL_SUP_OFF_RSTVAL 0x00000000U
1082 #define XSYSMONPSU_CAL_SUP_OFF_VAL_SHIFT 0U
1083 #define XSYSMONPSU_CAL_SUP_OFF_VAL_WIDTH 16U
1084 #define XSYSMONPSU_CAL_SUP_OFF_VAL_MASK 0x0000ffffU
1087 * Register: XSysmonPsuCalAdcBiplrOff
1089 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_OFFSET 0x00000024U
1090 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_RSTVAL 0x00000000U
1092 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_SHIFT 0U
1093 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_WIDTH 16U
1094 #define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_MASK 0x0000ffffU
1097 * Register: XSysmonPsuCalGainErr
1099 #define XSYSMONPSU_CAL_GAIN_ERR_OFFSET 0x00000028U
1100 #define XSYSMONPSU_CAL_GAIN_ERR_RSTVAL 0x00000000U
1102 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_SHIFT 0U
1103 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_WIDTH 16U
1104 #define XSYSMONPSU_CAL_GAIN_ERR_VAL_MASK 0x0000ffffU
1107 * Register: XSysmonPsuSup4
1109 #define XSYSMONPSU_SUP4_OFFSET 0x00000034U
1110 #define XSYSMONPSU_SUP4_RSTVAL 0x00000000U
1112 #define XSYSMONPSU_SUP4_SUP_VAL_SHIFT 0U
1113 #define XSYSMONPSU_SUP4_SUP_VAL_WIDTH 16U
1114 #define XSYSMONPSU_SUP4_SUP_VAL_MASK 0x0000ffffU
1117 * Register: XSysmonPsuSup5
1119 #define XSYSMONPSU_SUP5_OFFSET 0x00000038U
1120 #define XSYSMONPSU_SUP5_RSTVAL 0x00000000U
1122 #define XSYSMONPSU_SUP5_SUP_VAL_SHIFT 0U
1123 #define XSYSMONPSU_SUP5_SUP_VAL_WIDTH 16U
1124 #define XSYSMONPSU_SUP5_SUP_VAL_MASK 0x0000ffffU
1127 * Register: XSysmonPsuSup6
1129 #define XSYSMONPSU_SUP6_OFFSET 0x0000003CU
1130 #define XSYSMONPSU_SUP6_RSTVAL 0x00000000U
1132 #define XSYSMONPSU_SUP6_SUP_VAL_SHIFT 0U
1133 #define XSYSMONPSU_SUP6_SUP_VAL_WIDTH 16U
1134 #define XSYSMONPSU_SUP6_SUP_VAL_MASK 0x0000ffffU
1137 * Register: XSysmonPsuVaux00
1139 #define XSYSMONPSU_VAUX00_OFFSET 0x00000040U
1140 #define XSYSMONPSU_VAUX00_RSTVAL 0x00000000U
1142 #define XSYSMONPSU_VAUX00_VAUX_VAL_SHIFT 0U
1143 #define XSYSMONPSU_VAUX00_VAUX_VAL_WIDTH 16U
1144 #define XSYSMONPSU_VAUX00_VAUX_VAL_MASK 0x0000ffffU
1147 * Register: XSysmonPsuVaux01
1149 #define XSYSMONPSU_VAUX01_OFFSET 0x00000044U
1150 #define XSYSMONPSU_VAUX01_RSTVAL 0x00000000U
1152 #define XSYSMONPSU_VAUX01_VAUX_VAL_SHIFT 0U
1153 #define XSYSMONPSU_VAUX01_VAUX_VAL_WIDTH 16U
1154 #define XSYSMONPSU_VAUX01_VAUX_VAL_MASK 0x0000ffffU
1157 * Register: XSysmonPsuVaux02
1159 #define XSYSMONPSU_VAUX02_OFFSET 0x00000048U
1160 #define XSYSMONPSU_VAUX02_RSTVAL 0x00000000U
1162 #define XSYSMONPSU_VAUX02_VAUX_VAL_SHIFT 0U
1163 #define XSYSMONPSU_VAUX02_VAUX_VAL_WIDTH 16U
1164 #define XSYSMONPSU_VAUX02_VAUX_VAL_MASK 0x0000ffffU
1167 * Register: XSysmonPsuVaux03
1169 #define XSYSMONPSU_VAUX03_OFFSET 0x0000004CU
1170 #define XSYSMONPSU_VAUX03_RSTVAL 0x00000000U
1172 #define XSYSMONPSU_VAUX03_VAUX_VAL_SHIFT 0U
1173 #define XSYSMONPSU_VAUX03_VAUX_VAL_WIDTH 16U
1174 #define XSYSMONPSU_VAUX03_VAUX_VAL_MASK 0x0000ffffU
1177 * Register: XSysmonPsuVaux04
1179 #define XSYSMONPSU_VAUX04_OFFSET 0x00000050U
1180 #define XSYSMONPSU_VAUX04_RSTVAL 0x00000000U
1182 #define XSYSMONPSU_VAUX04_VAUX_VAL_SHIFT 0U
1183 #define XSYSMONPSU_VAUX04_VAUX_VAL_WIDTH 16U
1184 #define XSYSMONPSU_VAUX04_VAUX_VAL_MASK 0x0000ffffU
1187 * Register: XSysmonPsuVaux05
1189 #define XSYSMONPSU_VAUX05_OFFSET 0x00000054U
1190 #define XSYSMONPSU_VAUX05_RSTVAL 0x00000000U
1192 #define XSYSMONPSU_VAUX05_VAUX_VAL_SHIFT 0U
1193 #define XSYSMONPSU_VAUX05_VAUX_VAL_WIDTH 16U
1194 #define XSYSMONPSU_VAUX05_VAUX_VAL_MASK 0x0000ffffU
1197 * Register: XSysmonPsuVaux06
1199 #define XSYSMONPSU_VAUX06_OFFSET 0x00000058U
1200 #define XSYSMONPSU_VAUX06_RSTVAL 0x00000000U
1202 #define XSYSMONPSU_VAUX06_VAUX_VAL_SHIFT 0U
1203 #define XSYSMONPSU_VAUX06_VAUX_VAL_WIDTH 16U
1204 #define XSYSMONPSU_VAUX06_VAUX_VAL_MASK 0x0000ffffU
1207 * Register: XSysmonPsuVaux07
1209 #define XSYSMONPSU_VAUX07_OFFSET 0x0000005CU
1210 #define XSYSMONPSU_VAUX07_RSTVAL 0x00000000U
1212 #define XSYSMONPSU_VAUX07_VAUX_VAL_SHIFT 0U
1213 #define XSYSMONPSU_VAUX07_VAUX_VAL_WIDTH 16U
1214 #define XSYSMONPSU_VAUX07_VAUX_VAL_MASK 0x0000ffffU
1217 * Register: XSysmonPsuVaux08
1219 #define XSYSMONPSU_VAUX08_OFFSET 0x00000060U
1220 #define XSYSMONPSU_VAUX08_RSTVAL 0x00000000U
1222 #define XSYSMONPSU_VAUX08_VAUX_VAL_SHIFT 0U
1223 #define XSYSMONPSU_VAUX08_VAUX_VAL_WIDTH 16U
1224 #define XSYSMONPSU_VAUX08_VAUX_VAL_MASK 0x0000ffffU
1227 * Register: XSysmonPsuVaux09
1229 #define XSYSMONPSU_VAUX09_OFFSET 0x00000064U
1230 #define XSYSMONPSU_VAUX09_RSTVAL 0x00000000U
1232 #define XSYSMONPSU_VAUX09_VAUX_VAL_SHIFT 0U
1233 #define XSYSMONPSU_VAUX09_VAUX_VAL_WIDTH 16U
1234 #define XSYSMONPSU_VAUX09_VAUX_VAL_MASK 0x0000ffffU
1237 * Register: XSysmonPsuVaux0a
1239 #define XSYSMONPSU_VAUX0A_OFFSET 0x00000068U
1240 #define XSYSMONPSU_VAUX0A_RSTVAL 0x00000000U
1242 #define XSYSMONPSU_VAUX0A_VAUX_VAL_SHIFT 0U
1243 #define XSYSMONPSU_VAUX0A_VAUX_VAL_WIDTH 16U
1244 #define XSYSMONPSU_VAUX0A_VAUX_VAL_MASK 0x0000ffffU
1247 * Register: XSysmonPsuVaux0b
1249 #define XSYSMONPSU_VAUX0B_OFFSET 0x0000006CU
1250 #define XSYSMONPSU_VAUX0B_RSTVAL 0x00000000U
1252 #define XSYSMONPSU_VAUX0B_VAUX_VAL_SHIFT 0U
1253 #define XSYSMONPSU_VAUX0B_VAUX_VAL_WIDTH 16U
1254 #define XSYSMONPSU_VAUX0B_VAUX_VAL_MASK 0x0000ffffU
1257 * Register: XSysmonPsuVaux0c
1259 #define XSYSMONPSU_VAUX0C_OFFSET 0x00000070U
1260 #define XSYSMONPSU_VAUX0C_RSTVAL 0x00000000U
1262 #define XSYSMONPSU_VAUX0C_VAUX_VAL_SHIFT 0U
1263 #define XSYSMONPSU_VAUX0C_VAUX_VAL_WIDTH 16U
1264 #define XSYSMONPSU_VAUX0C_VAUX_VAL_MASK 0x0000ffffU
1267 * Register: XSysmonPsuVaux0d
1269 #define XSYSMONPSU_VAUX0D_OFFSET 0x00000074U
1270 #define XSYSMONPSU_VAUX0D_RSTVAL 0x00000000U
1272 #define XSYSMONPSU_VAUX0D_VAUX_VAL_SHIFT 0U
1273 #define XSYSMONPSU_VAUX0D_VAUX_VAL_WIDTH 16U
1274 #define XSYSMONPSU_VAUX0D_VAUX_VAL_MASK 0x0000ffffU
1277 * Register: XSysmonPsuVaux0e
1279 #define XSYSMONPSU_VAUX0E_OFFSET 0x00000078U
1280 #define XSYSMONPSU_VAUX0E_RSTVAL 0x00000000U
1282 #define XSYSMONPSU_VAUX0E_VAUX_VAL_SHIFT 0U
1283 #define XSYSMONPSU_VAUX0E_VAUX_VAL_WIDTH 16U
1284 #define XSYSMONPSU_VAUX0E_VAUX_VAL_MASK 0x0000ffffU
1287 * Register: XSysmonPsuVaux0f
1289 #define XSYSMONPSU_VAUX0F_OFFSET 0x0000007CU
1290 #define XSYSMONPSU_VAUX0F_RSTVAL 0x00000000U
1292 #define XSYSMONPSU_VAUX0F_VAUX_VAL_SHIFT 0U
1293 #define XSYSMONPSU_VAUX0F_VAUX_VAL_WIDTH 16U
1294 #define XSYSMONPSU_VAUX0F_VAUX_VAL_MASK 0x0000ffffU
1297 * Register: XSysmonPsuMaxTemp
1299 #define XSYSMONPSU_MAX_TEMP_OFFSET 0x00000080U
1300 #define XSYSMONPSU_MAX_TEMP_RSTVAL 0x00000000U
1302 #define XSYSMONPSU_MAX_TEMP_SHIFT 0U
1303 #define XSYSMONPSU_MAX_TEMP_WIDTH 16U
1304 #define XSYSMONPSU_MAX_TEMP_MASK 0x0000ffffU
1307 * Register: XSysmonPsuMaxSup1
1309 #define XSYSMONPSU_MAX_SUP1_OFFSET 0x00000084U
1310 #define XSYSMONPSU_MAX_SUP1_RSTVAL 0x00000000U
1312 #define XSYSMONPSU_MAX_SUP1_VAL_SHIFT 0U
1313 #define XSYSMONPSU_MAX_SUP1_VAL_WIDTH 16U
1314 #define XSYSMONPSU_MAX_SUP1_VAL_MASK 0x0000ffffU
1317 * Register: XSysmonPsuMaxSup2
1319 #define XSYSMONPSU_MAX_SUP2_OFFSET 0x00000088U
1320 #define XSYSMONPSU_MAX_SUP2_RSTVAL 0x00000000U
1322 #define XSYSMONPSU_MAX_SUP2_VAL_SHIFT 0U
1323 #define XSYSMONPSU_MAX_SUP2_VAL_WIDTH 16U
1324 #define XSYSMONPSU_MAX_SUP2_VAL_MASK 0x0000ffffU
1327 * Register: XSysmonPsuMaxSup3
1329 #define XSYSMONPSU_MAX_SUP3_OFFSET 0x0000008CU
1330 #define XSYSMONPSU_MAX_SUP3_RSTVAL 0x00000000U
1332 #define XSYSMONPSU_MAX_SUP3_VAL_SHIFT 0U
1333 #define XSYSMONPSU_MAX_SUP3_VAL_WIDTH 16U
1334 #define XSYSMONPSU_MAX_SUP3_VAL_MASK 0x0000ffffU
1337 * Register: XSysmonPsuMinTemp
1339 #define XSYSMONPSU_MIN_TEMP_OFFSET 0x00000090U
1340 #define XSYSMONPSU_MIN_TEMP_RSTVAL 0x0000ffffU
1342 #define XSYSMONPSU_MIN_TEMP_SHIFT 0U
1343 #define XSYSMONPSU_MIN_TEMP_WIDTH 16U
1344 #define XSYSMONPSU_MIN_TEMP_MASK 0x0000ffffU
1347 * Register: XSysmonPsuMinSup1
1349 #define XSYSMONPSU_MIN_SUP1_OFFSET 0x00000094U
1350 #define XSYSMONPSU_MIN_SUP1_RSTVAL 0x0000ffffU
1352 #define XSYSMONPSU_MIN_SUP1_VAL_SHIFT 0U
1353 #define XSYSMONPSU_MIN_SUP1_VAL_WIDTH 16U
1354 #define XSYSMONPSU_MIN_SUP1_VAL_MASK 0x0000ffffU
1357 * Register: XSysmonPsuMinSup2
1359 #define XSYSMONPSU_MIN_SUP2_OFFSET 0x00000098U
1360 #define XSYSMONPSU_MIN_SUP2_RSTVAL 0x0000ffffU
1362 #define XSYSMONPSU_MIN_SUP2_VAL_SHIFT 0U
1363 #define XSYSMONPSU_MIN_SUP2_VAL_WIDTH 16U
1364 #define XSYSMONPSU_MIN_SUP2_VAL_MASK 0x0000ffffU
1367 * Register: XSysmonPsuMinSup3
1369 #define XSYSMONPSU_MIN_SUP3_OFFSET 0x0000009CU
1370 #define XSYSMONPSU_MIN_SUP3_RSTVAL 0x0000ffffU
1372 #define XSYSMONPSU_MIN_SUP3_VAL_SHIFT 0U
1373 #define XSYSMONPSU_MIN_SUP3_VAL_WIDTH 16U
1374 #define XSYSMONPSU_MIN_SUP3_VAL_MASK 0x0000ffffU
1377 * Register: XSysmonPsuMaxSup4
1379 #define XSYSMONPSU_MAX_SUP4_OFFSET 0x000000A0U
1380 #define XSYSMONPSU_MAX_SUP4_RSTVAL 0x00000000U
1382 #define XSYSMONPSU_MAX_SUP4_VAL_SHIFT 0U
1383 #define XSYSMONPSU_MAX_SUP4_VAL_WIDTH 16U
1384 #define XSYSMONPSU_MAX_SUP4_VAL_MASK 0x0000ffffU
1387 * Register: XSysmonPsuMaxSup5
1389 #define XSYSMONPSU_MAX_SUP5_OFFSET 0x000000A4U
1390 #define XSYSMONPSU_MAX_SUP5_RSTVAL 0x00000000U
1392 #define XSYSMONPSU_MAX_SUP5_VAL_SHIFT 0U
1393 #define XSYSMONPSU_MAX_SUP5_VAL_WIDTH 16U
1394 #define XSYSMONPSU_MAX_SUP5_VAL_MASK 0x0000ffffU
1397 * Register: XSysmonPsuMaxSup6
1399 #define XSYSMONPSU_MAX_SUP6_OFFSET 0x000000A8U
1400 #define XSYSMONPSU_MAX_SUP6_RSTVAL 0x00000000U
1402 #define XSYSMONPSU_MAX_SUP6_VAL_SHIFT 0U
1403 #define XSYSMONPSU_MAX_SUP6_VAL_WIDTH 16U
1404 #define XSYSMONPSU_MAX_SUP6_VAL_MASK 0x0000ffffU
1407 * Register: XSysmonPsuMinSup4
1409 #define XSYSMONPSU_MIN_SUP4_OFFSET 0x000000B0U
1410 #define XSYSMONPSU_MIN_SUP4_RSTVAL 0x0000ffffU
1412 #define XSYSMONPSU_MIN_SUP4_VAL_SHIFT 0U
1413 #define XSYSMONPSU_MIN_SUP4_VAL_WIDTH 16U
1414 #define XSYSMONPSU_MIN_SUP4_VAL_MASK 0x0000ffffU
1417 * Register: XSysmonPsuMinSup5
1419 #define XSYSMONPSU_MIN_SUP5_OFFSET 0x000000B4U
1420 #define XSYSMONPSU_MIN_SUP5_RSTVAL 0x0000ffffU
1422 #define XSYSMONPSU_MIN_SUP5_VAL_SHIFT 0U
1423 #define XSYSMONPSU_MIN_SUP5_VAL_WIDTH 16U
1424 #define XSYSMONPSU_MIN_SUP5_VAL_MASK 0x0000ffffU
1427 * Register: XSysmonPsuMinSup6
1429 #define XSYSMONPSU_MIN_SUP6_OFFSET 0x000000B8U
1430 #define XSYSMONPSU_MIN_SUP6_RSTVAL 0x0000ffffU
1432 #define XSYSMONPSU_MIN_SUP6_VAL_SHIFT 0U
1433 #define XSYSMONPSU_MIN_SUP6_VAL_WIDTH 16U
1434 #define XSYSMONPSU_MIN_SUP6_VAL_MASK 0x0000ffffU
1437 * Register: XSysmonPsuStsFlag
1439 #define XSYSMONPSU_STS_FLAG_OFFSET 0x000000FCU
1440 #define XSYSMONPSU_STS_FLAG_RSTVAL 0x00000000U
1442 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_SHIFT 15U
1443 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_WIDTH 1U
1444 #define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_MASK 0x00008000U
1446 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_SHIFT 14U
1447 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_WIDTH 1U
1448 #define XSYSMONPSU_STS_FLAG_BLK_IN_RST_MASK 0x00004000U
1450 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_SHIFT 11U
1451 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_WIDTH 1U
1452 #define XSYSMONPSU_STS_FLAG_JTAG_DISD_MASK 0x00000800U
1454 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_SHIFT 10U
1455 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_WIDTH 1U
1456 #define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_MASK 0x00000400U
1458 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_SHIFT 9U
1459 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_WIDTH 1U
1460 #define XSYSMONPSU_STS_FLAG_INTRNL_REF_MASK 0x00000200U
1462 #define XSYSMONPSU_STS_FLAG_DISD_SHIFT 8U
1463 #define XSYSMONPSU_STS_FLAG_DISD_WIDTH 1U
1464 #define XSYSMONPSU_STS_FLAG_DISD_MASK 0x00000100U
1466 #define XSYSMONPSU_STS_FLAG_ALM_6_3_SHIFT 4U
1467 #define XSYSMONPSU_STS_FLAG_ALM_6_3_WIDTH 4U
1468 #define XSYSMONPSU_STS_FLAG_ALM_6_3_MASK 0x000000f0U
1470 #define XSYSMONPSU_STS_FLAG_OT_SHIFT 3U
1471 #define XSYSMONPSU_STS_FLAG_OT_WIDTH 1U
1472 #define XSYSMONPSU_STS_FLAG_OT_MASK 0x00000008U
1474 #define XSYSMONPSU_STS_FLAG_ALM_2_0_SHIFT 0U
1475 #define XSYSMONPSU_STS_FLAG_ALM_2_0_WIDTH 3U
1476 #define XSYSMONPSU_STS_FLAG_ALM_2_0_MASK 0x00000007U
1479 * Register: XSysmonPsuCfgReg0
1481 #define XSYSMONPSU_CFG_REG0_OFFSET 0x00000100U
1482 #define XSYSMONPSU_CFG_REG0_RSTVAL 0x00000000U
1484 #define XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT 12U
1485 #define XSYSMONPSU_CFG_REG0_AVRGNG_WIDTH 2U
1486 #define XSYSMONPSU_CFG_REG0_AVRGNG_MASK 0x00003000U
1488 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_SHIFT 11U
1489 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_WIDTH 1U
1490 #define XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK 0x00000800U
1492 #define XSYSMONPSU_CFG_REG0_BU_SHIFT 10U
1493 #define XSYSMONPSU_CFG_REG0_BU_WIDTH 1U
1494 #define XSYSMONPSU_CFG_REG0_BU_MASK 0x00000400U
1496 #define XSYSMONPSU_CFG_REG0_EC_SHIFT 9U
1497 #define XSYSMONPSU_CFG_REG0_EC_WIDTH 1U
1498 #define XSYSMONPSU_CFG_REG0_EC_MASK 0x00000200U
1500 #define XSYSMONPSU_EVENT_MODE 1
1501 #define XSYSMONPSU_CONTINUOUS_MODE 2
1503 #define XSYSMONPSU_CFG_REG0_ACQ_SHIFT 8U
1504 #define XSYSMONPSU_CFG_REG0_ACQ_WIDTH 1U
1505 #define XSYSMONPSU_CFG_REG0_ACQ_MASK 0x00000100U
1507 #define XSYSMONPSU_CFG_REG0_MUX_CH_SHIFT 0U
1508 #define XSYSMONPSU_CFG_REG0_MUX_CH_WIDTH 6U
1509 #define XSYSMONPSU_CFG_REG0_MUX_CH_MASK 0x0000003fU
1512 * Register: XSysmonPsuCfgReg1
1514 #define XSYSMONPSU_CFG_REG1_OFFSET 0x00000104U
1515 #define XSYSMONPSU_CFG_REG1_RSTVAL 0x00000000U
1517 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT 12U
1518 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_WIDTH 4U
1519 #define XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK 0x0000f000U
1521 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_SHIFT 8U
1522 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_WIDTH 4U
1523 #define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_MASK 0x00000f00U
1525 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_SHIFT 1U
1526 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_WIDTH 3U
1527 #define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_MASK 0x0000000eU
1529 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_SHIFT 0U
1530 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_WIDTH 1U
1531 #define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_MASK 0x00000001U
1533 #define XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK 0x00000f0fU
1534 #define XSYSMONPSU_CFR_REG1_ALRM_SUP6_MASK 0x0800U
1535 #define XSYSMONPSU_CFR_REG1_ALRM_SUP5_MASK 0x0400U
1536 #define XSYSMONPSU_CFR_REG1_ALRM_SUP4_MASK 0x0200U
1537 #define XSYSMONPSU_CFR_REG1_ALRM_SUP3_MASK 0x0100U
1538 #define XSYSMONPSU_CFR_REG1_ALRM_SUP2_MASK 0x0008U
1539 #define XSYSMONPSU_CFR_REG1_ALRM_SUP1_MASK 0x0004U
1540 #define XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK 0x0002U
1541 #define XSYSMONPSU_CFR_REG1_ALRM_OT_MASK 0x0001U
1544 * Register: XSysmonPsuCfgReg2
1546 #define XSYSMONPSU_CFG_REG2_OFFSET 0x00000108U
1547 #define XSYSMONPSU_CFG_REG2_RSTVAL 0x00000000U
1549 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT 8U
1550 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_WIDTH 8U
1551 #define XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK 0x0000ff00U
1553 #define XSYSMONPSU_CLK_DVDR_MIN_VAL 0U
1554 #define XSYSMONPSU_CLK_DVDR_MAX_VAL 255U
1556 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT 4U
1557 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_WIDTH 4U
1558 #define XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK 0x000000f0U
1560 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_SHIFT 2U
1561 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_WIDTH 1U
1562 #define XSYSMONPSU_CFG_REG2_TST_CH_EN_MASK 0x00000004U
1564 #define XSYSMONPSU_CFG_REG2_TST_MDE_SHIFT 0U
1565 #define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH 2U
1566 #define XSYSMONPSU_CFG_REG2_TST_MDE_MASK 0x00000003U
1568 /* Register: XSysmonPsuCfgReg3 */
1569 #define XSYSMONPSU_CFG_REG3_OFFSET 0x0000010CU
1570 #define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK 0x0000003FU
1572 #define XSM_CFG_ALARM_SHIFT 16U
1574 /* Register: XSysmonPsuSeqCh2 */
1575 #define XSYSMONPSU_SEQ_CH2_OFFSET 0x00000118U
1577 #define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT 5U
1578 #define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK 0x00000020U
1580 #define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT 4U
1581 #define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK 0x00000010U
1583 #define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT 3U
1584 #define XSYSMONPSU_SEQ_CH2_SUP10_MASK 0x00000008U
1586 #define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT 2U
1587 #define XSYSMONPSU_SEQ_CH2_SUP9_MASK 0x00000004U
1589 #define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT 1U
1590 #define XSYSMONPSU_SEQ_CH2_SUP8_MASK 0x00000002U
1592 #define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT 0U
1593 #define XSYSMONPSU_SEQ_CH2_SUP7_MASK 0x00000001U
1595 #define XSYSMONPSU_SEQ_CH2_VALID_MASK 0x0000003FU
1597 /* Register: XSysmonPsuSeqAverage0 */
1598 #define XSYSMONPSU_SEQ_AVERAGE2_OFFSET 0x0000011CU
1599 #define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
1600 #define XSYSMONPSU_SEQ_AVERAGE2_MASK 0x0000003FU
1603 * Register: XSysmonPsuSeqCh0
1605 #define XSYSMONPSU_SEQ_CH0_OFFSET 0x00000120U
1606 #define XSYSMONPSU_SEQ_CH0_RSTVAL 0x00000000U
1608 #define XSYSMONPSU_SEQ_CH0_CUR_MON_SHIFT 15U
1609 #define XSYSMONPSU_SEQ_CH0_CUR_MON_WIDTH 1U
1610 #define XSYSMONPSU_SEQ_CH0_CUR_MON_MASK 0x00008000U
1612 #define XSYSMONPSU_SEQ_CH0_SUP3_SHIFT 14U
1613 #define XSYSMONPSU_SEQ_CH0_SUP3_WIDTH 1U
1614 #define XSYSMONPSU_SEQ_CH0_SUP3_MASK 0x00004000U
1616 #define XSYSMONPSU_SEQ_CH0_VREFN_SHIFT 13U
1617 #define XSYSMONPSU_SEQ_CH0_VREFN_WIDTH 1U
1618 #define XSYSMONPSU_SEQ_CH0_VREFN_MASK 0x00002000U
1620 #define XSYSMONPSU_SEQ_CH0_VREFP_SHIFT 12U
1621 #define XSYSMONPSU_SEQ_CH0_VREFP_WIDTH 1U
1622 #define XSYSMONPSU_SEQ_CH0_VREFP_MASK 0x00001000U
1624 #define XSYSMONPSU_SEQ_CH0_VP_VN_SHIFT 11U
1625 #define XSYSMONPSU_SEQ_CH0_VP_VN_WIDTH 1U
1626 #define XSYSMONPSU_SEQ_CH0_VP_VN_MASK 0x00000800U
1628 #define XSYSMONPSU_SEQ_CH0_SUP2_SHIFT 10U
1629 #define XSYSMONPSU_SEQ_CH0_SUP2_WIDTH 1U
1630 #define XSYSMONPSU_SEQ_CH0_SUP2_MASK 0x00000400U
1632 #define XSYSMONPSU_SEQ_CH0_SUP1_SHIFT 9U
1633 #define XSYSMONPSU_SEQ_CH0_SUP1_WIDTH 1U
1634 #define XSYSMONPSU_SEQ_CH0_SUP1_MASK 0x00000200U
1636 #define XSYSMONPSU_SEQ_CH0_TEMP_SHIFT 8U
1637 #define XSYSMONPSU_SEQ_CH0_TEMP_WIDTH 1U
1638 #define XSYSMONPSU_SEQ_CH0_TEMP_MASK 0x00000100U
1640 #define XSYSMONPSU_SEQ_CH0_SUP6_SHIFT 7U
1641 #define XSYSMONPSU_SEQ_CH0_SUP6_WIDTH 1U
1642 #define XSYSMONPSU_SEQ_CH0_SUP6_MASK 0x00000080U
1644 #define XSYSMONPSU_SEQ_CH0_SUP5_SHIFT 6U
1645 #define XSYSMONPSU_SEQ_CH0_SUP5_WIDTH 1U
1646 #define XSYSMONPSU_SEQ_CH0_SUP5_MASK 0x00000040U
1648 #define XSYSMONPSU_SEQ_CH0_SUP4_SHIFT 5U
1649 #define XSYSMONPSU_SEQ_CH0_SUP4_WIDTH 1U
1650 #define XSYSMONPSU_SEQ_CH0_SUP4_MASK 0x00000020U
1652 #define XSYSMONPSU_SEQ_CH0_TST_CH_SHIFT 3U
1653 #define XSYSMONPSU_SEQ_CH0_TST_CH_WIDTH 1U
1654 #define XSYSMONPSU_SEQ_CH0_TST_CH_MASK 0x00000008U
1656 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_SHIFT 0U
1657 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_WIDTH 1U
1658 #define XSYSMONPSU_SEQ_CH0_CALIBRTN_MASK 0x00000001U
1660 #define XSYSMONPSU_SEQ_CH0_VALID_MASK 0x0000FFE9U
1663 * Register: XSysmonPsuSeqCh1
1665 #define XSYSMONPSU_SEQ_CH1_OFFSET 0x00000124U
1666 #define XSYSMONPSU_SEQ_CH1_VALID_MASK 0x0000FFFFU
1667 #define XSYSMONPSU_SEQ_CH1_RSTVAL 0x00000000U
1669 #define XSYSMONPSU_SEQ_CH1_VAUX0F_SHIFT 15U
1670 #define XSYSMONPSU_SEQ_CH1_VAUX0F_WIDTH 1U
1671 #define XSYSMONPSU_SEQ_CH1_VAUX0F_MASK 0x00008000U
1673 #define XSYSMONPSU_SEQ_CH1_VAUX0E_SHIFT 14U
1674 #define XSYSMONPSU_SEQ_CH1_VAUX0E_WIDTH 1U
1675 #define XSYSMONPSU_SEQ_CH1_VAUX0E_MASK 0x00004000U
1677 #define XSYSMONPSU_SEQ_CH1_VAUX0D_SHIFT 13U
1678 #define XSYSMONPSU_SEQ_CH1_VAUX0D_WIDTH 1U
1679 #define XSYSMONPSU_SEQ_CH1_VAUX0D_MASK 0x00002000U
1681 #define XSYSMONPSU_SEQ_CH1_VAUX0C_SHIFT 12U
1682 #define XSYSMONPSU_SEQ_CH1_VAUX0C_WIDTH 1U
1683 #define XSYSMONPSU_SEQ_CH1_VAUX0C_MASK 0x00001000U
1685 #define XSYSMONPSU_SEQ_CH1_VAUX0B_SHIFT 11U
1686 #define XSYSMONPSU_SEQ_CH1_VAUX0B_WIDTH 1U
1687 #define XSYSMONPSU_SEQ_CH1_VAUX0B_MASK 0x00000800U
1689 #define XSYSMONPSU_SEQ_CH1_VAUX0A_SHIFT 10U
1690 #define XSYSMONPSU_SEQ_CH1_VAUX0A_WIDTH 1U
1691 #define XSYSMONPSU_SEQ_CH1_VAUX0A_MASK 0x00000400U
1693 #define XSYSMONPSU_SEQ_CH1_VAUX09_SHIFT 9U
1694 #define XSYSMONPSU_SEQ_CH1_VAUX09_WIDTH 1U
1695 #define XSYSMONPSU_SEQ_CH1_VAUX09_MASK 0x00000200U
1697 #define XSYSMONPSU_SEQ_CH1_VAUX08_SHIFT 8U
1698 #define XSYSMONPSU_SEQ_CH1_VAUX08_WIDTH 1U
1699 #define XSYSMONPSU_SEQ_CH1_VAUX08_MASK 0x00000100U
1701 #define XSYSMONPSU_SEQ_CH1_VAUX07_SHIFT 7U
1702 #define XSYSMONPSU_SEQ_CH1_VAUX07_WIDTH 1U
1703 #define XSYSMONPSU_SEQ_CH1_VAUX07_MASK 0x00000080U
1705 #define XSYSMONPSU_SEQ_CH1_VAUX06_SHIFT 6U
1706 #define XSYSMONPSU_SEQ_CH1_VAUX06_WIDTH 1U
1707 #define XSYSMONPSU_SEQ_CH1_VAUX06_MASK 0x00000040U
1709 #define XSYSMONPSU_SEQ_CH1_VAUX05_SHIFT 5U
1710 #define XSYSMONPSU_SEQ_CH1_VAUX05_WIDTH 1U
1711 #define XSYSMONPSU_SEQ_CH1_VAUX05_MASK 0x00000020U
1713 #define XSYSMONPSU_SEQ_CH1_VAUX04_SHIFT 4U
1714 #define XSYSMONPSU_SEQ_CH1_VAUX04_WIDTH 1U
1715 #define XSYSMONPSU_SEQ_CH1_VAUX04_MASK 0x00000010U
1717 #define XSYSMONPSU_SEQ_CH1_VAUX03_SHIFT 3U
1718 #define XSYSMONPSU_SEQ_CH1_VAUX03_WIDTH 1U
1719 #define XSYSMONPSU_SEQ_CH1_VAUX03_MASK 0x00000008U
1721 #define XSYSMONPSU_SEQ_CH1_VAUX02_SHIFT 2U
1722 #define XSYSMONPSU_SEQ_CH1_VAUX02_WIDTH 1U
1723 #define XSYSMONPSU_SEQ_CH1_VAUX02_MASK 0x00000004U
1725 #define XSYSMONPSU_SEQ_CH1_VAUX01_SHIFT 1U
1726 #define XSYSMONPSU_SEQ_CH1_VAUX01_WIDTH 1U
1727 #define XSYSMONPSU_SEQ_CH1_VAUX01_MASK 0x00000002U
1729 #define XSYSMONPSU_SEQ_CH1_VAUX00_SHIFT 0U
1730 #define XSYSMONPSU_SEQ_CH1_VAUX00_WIDTH 1U
1731 #define XSYSMONPSU_SEQ_CH1_VAUX00_MASK 0x00000001U
1733 #define XSM_SEQ_CH_SHIFT 16U
1734 #define XSM_SEQ_CH2_SHIFT 32U
1737 * Register: XSysmonPsuSeqAverage0
1739 #define XSYSMONPSU_SEQ_AVERAGE0_OFFSET 0x00000128U
1740 #define XSYSMONPSU_SEQ_AVERAGE0_RSTVAL 0x00000000U
1742 #define XSYSMONPSU_SEQ_AVERAGE0_SHIFT 0U
1743 #define XSYSMONPSU_SEQ_AVERAGE0_WIDTH 16U
1744 #define XSYSMONPSU_SEQ_AVERAGE0_MASK 0x0000ffffU
1747 * Register: XSysmonPsuSeqAverage1
1749 #define XSYSMONPSU_SEQ_AVERAGE1_OFFSET 0x0000012CU
1750 #define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL 0x00000000U
1752 #define XSYSMONPSU_SEQ_AVERAGE1_SHIFT 0U
1753 #define XSYSMONPSU_SEQ_AVERAGE1_WIDTH 16U
1754 #define XSYSMONPSU_SEQ_AVERAGE1_MASK 0x0000ffffU
1757 * Register: XSysmonPsuSeqInputMde0
1759 #define XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET 0x00000130U
1760 #define XSYSMONPSU_SEQ_INPUT_MDE0_RSTVAL 0x00000000U
1762 #define XSYSMONPSU_SEQ_INPUT_MDE0_SHIFT 0U
1763 #define XSYSMONPSU_SEQ_INPUT_MDE0_WIDTH 16U
1764 #define XSYSMONPSU_SEQ_INPUT_MDE0_MASK 0x0000ffffU
1767 * Register: XSysmonPsuSeqInputMde1
1769 #define XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET 0x00000134U
1770 #define XSYSMONPSU_SEQ_INPUT_MDE1_RSTVAL 0x00000000U
1772 #define XSYSMONPSU_SEQ_INPUT_MDE1_SHIFT 0U
1773 #define XSYSMONPSU_SEQ_INPUT_MDE1_WIDTH 16U
1774 #define XSYSMONPSU_SEQ_INPUT_MDE1_MASK 0x0000ffffU
1777 * Register: XSysmonPsuSeqAcq0
1779 #define XSYSMONPSU_SEQ_ACQ0_OFFSET 0x00000138U
1780 #define XSYSMONPSU_SEQ_ACQ0_RSTVAL 0x00000000U
1782 #define XSYSMONPSU_SEQ_ACQ0_SHIFT 0U
1783 #define XSYSMONPSU_SEQ_ACQ0_WIDTH 16U
1784 #define XSYSMONPSU_SEQ_ACQ0_MASK 0x0000ffffU
1787 * Register: XSysmonPsuSeqAcq1
1789 #define XSYSMONPSU_SEQ_ACQ1_OFFSET 0x0000013CU
1790 #define XSYSMONPSU_SEQ_ACQ1_RSTVAL 0x00000000U
1792 #define XSYSMONPSU_SEQ_ACQ1_SHIFT 0U
1793 #define XSYSMONPSU_SEQ_ACQ1_WIDTH 16U
1794 #define XSYSMONPSU_SEQ_ACQ1_MASK 0x0000ffffU
1797 * Register: XSysmonPsuAlrmTempUpr
1799 #define XSYSMONPSU_ALRM_TEMP_UPR_OFFSET 0x00000140U
1800 #define XSYSMONPSU_ALRM_TEMP_UPR_RSTVAL 0x00000000U
1802 #define XSYSMONPSU_ALRM_TEMP_UPR_SHIFT 0U
1803 #define XSYSMONPSU_ALRM_TEMP_UPR_WIDTH 16U
1804 #define XSYSMONPSU_ALRM_TEMP_UPR_MASK 0x0000ffffU
1807 * Register: XSysmonPsuAlrmSup1Upr
1809 #define XSYSMONPSU_ALRM_SUP1_UPR_OFFSET 0x00000144U
1810 #define XSYSMONPSU_ALRM_SUP1_UPR_RSTVAL 0x00000000U
1812 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_SHIFT 0U
1813 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_WIDTH 16U
1814 #define XSYSMONPSU_ALRM_SUP1_UPR_SUP_MASK 0x0000ffffU
1817 * Register: XSysmonPsuAlrmSup2Upr
1819 #define XSYSMONPSU_ALRM_SUP2_UPR_OFFSET 0x00000148U
1820 #define XSYSMONPSU_ALRM_SUP2_UPR_RSTVAL 0x00000000U
1822 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_SHIFT 0U
1823 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_WIDTH 16U
1824 #define XSYSMONPSU_ALRM_SUP2_UPR_SUP_MASK 0x0000ffffU
1827 * Register: XSysmonPsuAlrmOtUpr
1829 #define XSYSMONPSU_ALRM_OT_UPR_OFFSET 0x0000014CU
1830 #define XSYSMONPSU_ALRM_OT_UPR_RSTVAL 0x00000000U
1832 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_SHIFT 0U
1833 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_WIDTH 16U
1834 #define XSYSMONPSU_ALRM_OT_UPR_TEMP_MASK 0x0000ffffU
1837 * Register: XSysmonPsuAlrmTempLwr
1839 #define XSYSMONPSU_ALRM_TEMP_LWR_OFFSET 0x00000150U
1840 #define XSYSMONPSU_ALRM_TEMP_LWR_RSTVAL 0x00000000U
1842 #define XSYSMONPSU_ALRM_TEMP_LWR_SHIFT 1U
1843 #define XSYSMONPSU_ALRM_TEMP_LWR_WIDTH 15U
1844 #define XSYSMONPSU_ALRM_TEMP_LWR_MASK 0x0000fffeU
1846 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_SHIFT 0U
1847 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_WIDTH 1U
1848 #define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_MASK 0x00000001U
1851 * Register: XSysmonPsuAlrmSup1Lwr
1853 #define XSYSMONPSU_ALRM_SUP1_LWR_OFFSET 0x00000154U
1854 #define XSYSMONPSU_ALRM_SUP1_LWR_RSTVAL 0x00000000U
1856 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_SHIFT 0U
1857 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_WIDTH 16U
1858 #define XSYSMONPSU_ALRM_SUP1_LWR_SUP_MASK 0x0000ffffU
1861 * Register: XSysmonPsuAlrmSup2Lwr
1863 #define XSYSMONPSU_ALRM_SUP2_LWR_OFFSET 0x00000158U
1864 #define XSYSMONPSU_ALRM_SUP2_LWR_RSTVAL 0x00000000U
1866 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_SHIFT 0U
1867 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_WIDTH 16U
1868 #define XSYSMONPSU_ALRM_SUP2_LWR_SUP_MASK 0x0000ffffU
1871 * Register: XSysmonPsuAlrmOtLwr
1873 #define XSYSMONPSU_ALRM_OT_LWR_OFFSET 0x0000015CU
1874 #define XSYSMONPSU_ALRM_OT_LWR_RSTVAL 0x00000000U
1876 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_SHIFT 1U
1877 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_WIDTH 15U
1878 #define XSYSMONPSU_ALRM_OT_LWR_TEMP_MASK 0x0000fffeU
1880 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_SHIFT 0U
1881 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_WIDTH 1U
1882 #define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_MASK 0x00000001U
1885 * Register: XSysmonPsuAlrmSup3Upr
1887 #define XSYSMONPSU_ALRM_SUP3_UPR_OFFSET 0x00000160U
1888 #define XSYSMONPSU_ALRM_SUP3_UPR_RSTVAL 0x00000000U
1890 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_SHIFT 0U
1891 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_WIDTH 16U
1892 #define XSYSMONPSU_ALRM_SUP3_UPR_SUP_MASK 0x0000ffffU
1895 * Register: XSysmonPsuAlrmSup4Upr
1897 #define XSYSMONPSU_ALRM_SUP4_UPR_OFFSET 0x00000164U
1898 #define XSYSMONPSU_ALRM_SUP4_UPR_RSTVAL 0x00000000U
1900 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_SHIFT 0U
1901 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_WIDTH 16U
1902 #define XSYSMONPSU_ALRM_SUP4_UPR_SUP_MASK 0x0000ffffU
1905 * Register: XSysmonPsuAlrmSup5Upr
1907 #define XSYSMONPSU_ALRM_SUP5_UPR_OFFSET 0x00000168U
1908 #define XSYSMONPSU_ALRM_SUP5_UPR_RSTVAL 0x00000000U
1910 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_SHIFT 0U
1911 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_WIDTH 16U
1912 #define XSYSMONPSU_ALRM_SUP5_UPR_SUP_MASK 0x0000ffffU
1915 * Register: XSysmonPsuAlrmSup6Upr
1917 #define XSYSMONPSU_ALRM_SUP6_UPR_OFFSET 0x0000016CU
1918 #define XSYSMONPSU_ALRM_SUP6_UPR_RSTVAL 0x00000000U
1920 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_SHIFT 0U
1921 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_WIDTH 16U
1922 #define XSYSMONPSU_ALRM_SUP6_UPR_SUP_MASK 0x0000ffffU
1925 * Register: XSysmonPsuAlrmSup3Lwr
1927 #define XSYSMONPSU_ALRM_SUP3_LWR_OFFSET 0x00000170U
1928 #define XSYSMONPSU_ALRM_SUP3_LWR_RSTVAL 0x00000000U
1930 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_SHIFT 0U
1931 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_WIDTH 16U
1932 #define XSYSMONPSU_ALRM_SUP3_LWR_SUP_MASK 0x0000ffffU
1935 * Register: XSysmonPsuAlrmSup4Lwr
1937 #define XSYSMONPSU_ALRM_SUP4_LWR_OFFSET 0x00000174U
1938 #define XSYSMONPSU_ALRM_SUP4_LWR_RSTVAL 0x00000000U
1940 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_SHIFT 0U
1941 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_WIDTH 16U
1942 #define XSYSMONPSU_ALRM_SUP4_LWR_SUP_MASK 0x0000ffffU
1945 * Register: XSysmonPsuAlrmSup5Lwr
1947 #define XSYSMONPSU_ALRM_SUP5_LWR_OFFSET 0x00000178U
1948 #define XSYSMONPSU_ALRM_SUP5_LWR_RSTVAL 0x00000000U
1950 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_SHIFT 0U
1951 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_WIDTH 16U
1952 #define XSYSMONPSU_ALRM_SUP5_LWR_SUP_MASK 0x0000ffffU
1955 * Register: XSysmonPsuAlrmSup6Lwr
1957 #define XSYSMONPSU_ALRM_SUP6_LWR_OFFSET 0x0000017CU
1958 #define XSYSMONPSU_ALRM_SUP6_LWR_RSTVAL 0x00000000U
1960 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_SHIFT 0U
1961 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_WIDTH 16U
1962 #define XSYSMONPSU_ALRM_SUP6_LWR_SUP_MASK 0x0000ffffU
1965 * Register: XSysmonPsuAlrmSup7Upr
1967 #define XSYSMONPSU_ALRM_SUP7_UPR_OFFSET 0x00000180U
1968 #define XSYSMONPSU_ALRM_SUP7_UPR_RSTVAL 0x00000000U
1970 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_SHIFT 0U
1971 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_WIDTH 16U
1972 #define XSYSMONPSU_ALRM_SUP7_UPR_SUP_MASK 0x0000ffffU
1975 * Register: XSysmonPsuAlrmSup8Upr
1977 #define XSYSMONPSU_ALRM_SUP8_UPR_OFFSET 0x00000184U
1978 #define XSYSMONPSU_ALRM_SUP8_UPR_RSTVAL 0x00000000U
1980 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_SHIFT 0U
1981 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_WIDTH 16U
1982 #define XSYSMONPSU_ALRM_SUP8_UPR_SUP_MASK 0x0000ffffU
1985 * Register: XSysmonPsuAlrmSup9Upr
1987 #define XSYSMONPSU_ALRM_SUP9_UPR_OFFSET 0x00000188U
1988 #define XSYSMONPSU_ALRM_SUP9_UPR_RSTVAL 0x00000000U
1990 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_SHIFT 0U
1991 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_WIDTH 16U
1992 #define XSYSMONPSU_ALRM_SUP9_UPR_SUP_MASK 0x0000ffffU
1995 * Register: XSysmonPsuAlrmSup10Upr
1997 #define XSYSMONPSU_ALRM_SUP10_UPR_OFFSET 0x0000018CU
1998 #define XSYSMONPSU_ALRM_SUP10_UPR_RSTVAL 0x00000000U
2000 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_SHIFT 0U
2001 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_WIDTH 16U
2002 #define XSYSMONPSU_ALRM_SUP10_UPR_SUP_MASK 0x0000ffffU
2005 * Register: XSysmonPsuAlrmVccamsUpr
2007 #define XSYSMONPSU_ALRM_VCCAMS_UPR_OFFSET 0x00000190U
2008 #define XSYSMONPSU_ALRM_VCCAMS_UPR_RSTVAL 0x00000000U
2010 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_SHIFT 0U
2011 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_WIDTH 16U
2012 #define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_MASK 0x0000ffffU
2015 * Register: XSysmonPsuAlrmTremoteUpr
2017 #define XSYSMONPSU_ALRM_TREMOTE_UPR_OFFSET 0x00000194U
2018 #define XSYSMONPSU_ALRM_TREMOTE_UPR_RSTVAL 0x00000000U
2020 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_SHIFT 0U
2021 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_WIDTH 16U
2022 #define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_MASK 0x0000ffffU
2025 * Register: XSysmonPsuAlrmSup7Lwr
2027 #define XSYSMONPSU_ALRM_SUP7_LWR_OFFSET 0x000001A0U
2028 #define XSYSMONPSU_ALRM_SUP7_LWR_RSTVAL 0x00000000U
2030 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_SHIFT 0U
2031 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_WIDTH 16U
2032 #define XSYSMONPSU_ALRM_SUP7_LWR_SUP_MASK 0x0000ffffU
2035 * Register: XSysmonPsuAlrmSup8Lwr
2037 #define XSYSMONPSU_ALRM_SUP8_LWR_OFFSET 0x000001A4U
2038 #define XSYSMONPSU_ALRM_SUP8_LWR_RSTVAL 0x00000000U
2040 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_SHIFT 0U
2041 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_WIDTH 16U
2042 #define XSYSMONPSU_ALRM_SUP8_LWR_SUP_MASK 0x0000ffffU
2045 * Register: XSysmonPsuAlrmSup9Lwr
2047 #define XSYSMONPSU_ALRM_SUP9_LWR_OFFSET 0x000001A8U
2048 #define XSYSMONPSU_ALRM_SUP9_LWR_RSTVAL 0x00000000U
2050 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_SHIFT 0U
2051 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_WIDTH 16U
2052 #define XSYSMONPSU_ALRM_SUP9_LWR_SUP_MASK 0x0000ffffU
2055 * Register: XSysmonPsuAlrmSup10Lwr
2057 #define XSYSMONPSU_ALRM_SUP10_LWR_OFFSET 0x000001ACU
2058 #define XSYSMONPSU_ALRM_SUP10_LWR_RSTVAL 0x00000000U
2060 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_SHIFT 0U
2061 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_WIDTH 16U
2062 #define XSYSMONPSU_ALRM_SUP10_LWR_SUP_MASK 0x0000ffffU
2065 * Register: XSysmonPsuAlrmVccamsLwr
2067 #define XSYSMONPSU_ALRM_VCCAMS_LWR_OFFSET 0x000001B0U
2068 #define XSYSMONPSU_ALRM_VCCAMS_LWR_RSTVAL 0x00000000U
2070 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_SHIFT 0U
2071 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_WIDTH 16U
2072 #define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_MASK 0x0000ffffU
2075 * Register: XSysmonPsuAlrmTremoteLwr
2077 #define XSYSMONPSU_ALRM_TREMOTE_LWR_OFFSET 0x000001B4U
2078 #define XSYSMONPSU_ALRM_TREMOTE_LWR_RSTVAL 0x00000000U
2080 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_SHIFT 1U
2081 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_WIDTH 15U
2082 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_MASK 0x0000fffeU
2084 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_SHIFT 0U
2085 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH 1U
2086 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK 0x00000001U
2088 /* Register: XSysmonPsuSeqInputMde2 */
2089 #define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET 0x000001E0U
2090 #define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL 0x00000000U
2092 #define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT 0U
2093 #define XSYSMONPSU_SEQ_INPUT_MDE2_MASK 0x0000003FU
2096 * Register: XSysmonPsuSeqAcq2
2098 #define XSYSMONPSU_SEQ_ACQ2_OFFSET 0x000001E4U
2099 #define XSYSMONPSU_SEQ_ACQ2_RSTVAL 0x00000000U
2101 #define XSYSMONPSU_SEQ_ACQ2_SHIFT 0U
2102 #define XSYSMONPSU_SEQ_ACQ2_MASK 0x0000003FU
2105 * Register: XSysmonPsuSup7
2107 #define XSYSMONPSU_SUP7_OFFSET 0x00000200U
2108 #define XSYSMONPSU_SUP7_RSTVAL 0x00000000U
2110 #define XSYSMONPSU_SUP7_SUP_VAL_SHIFT 0U
2111 #define XSYSMONPSU_SUP7_SUP_VAL_WIDTH 16U
2112 #define XSYSMONPSU_SUP7_SUP_VAL_MASK 0x0000ffffU
2115 * Register: XSysmonPsuSup8
2117 #define XSYSMONPSU_SUP8_OFFSET 0x00000204U
2118 #define XSYSMONPSU_SUP8_RSTVAL 0x00000000U
2120 #define XSYSMONPSU_SUP8_SUP_VAL_SHIFT 0U
2121 #define XSYSMONPSU_SUP8_SUP_VAL_WIDTH 16U
2122 #define XSYSMONPSU_SUP8_SUP_VAL_MASK 0x0000ffffU
2125 * Register: XSysmonPsuSup9
2127 #define XSYSMONPSU_SUP9_OFFSET 0x00000208U
2128 #define XSYSMONPSU_SUP9_RSTVAL 0x00000000U
2130 #define XSYSMONPSU_SUP9_SUP_VAL_SHIFT 0U
2131 #define XSYSMONPSU_SUP9_SUP_VAL_WIDTH 16U
2132 #define XSYSMONPSU_SUP9_SUP_VAL_MASK 0x0000ffffU
2135 * Register: XSysmonPsuSup10
2137 #define XSYSMONPSU_SUP10_OFFSET 0x0000020CU
2138 #define XSYSMONPSU_SUP10_RSTVAL 0x00000000U
2140 #define XSYSMONPSU_SUP10_SUP_VAL_SHIFT 0U
2141 #define XSYSMONPSU_SUP10_SUP_VAL_WIDTH 16U
2142 #define XSYSMONPSU_SUP10_SUP_VAL_MASK 0x0000ffffU
2145 * Register: XSysmonPsuVccams
2147 #define XSYSMONPSU_VCCAMS_OFFSET 0x00000210U
2148 #define XSYSMONPSU_VCCAMS_RSTVAL 0x00000000U
2150 #define XSYSMONPSU_VCCAMS_SUP_VAL_SHIFT 0U
2151 #define XSYSMONPSU_VCCAMS_SUP_VAL_WIDTH 16U
2152 #define XSYSMONPSU_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2155 * Register: XSysmonPsuTempRemte
2157 #define XSYSMONPSU_TEMP_REMTE_OFFSET 0x00000214U
2158 #define XSYSMONPSU_TEMP_REMTE_RSTVAL 0x00000000U
2160 #define XSYSMONPSU_TEMP_REMTE_SHIFT 0U
2161 #define XSYSMONPSU_TEMP_REMTE_WIDTH 16U
2162 #define XSYSMONPSU_TEMP_REMTE_MASK 0x0000ffffU
2165 * Register: XSysmonPsuMaxSup7
2167 #define XSYSMONPSU_MAX_SUP7_OFFSET 0x00000280U
2168 #define XSYSMONPSU_MAX_SUP7_RSTVAL 0x00000000U
2170 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_SHIFT 0U
2171 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_WIDTH 16U
2172 #define XSYSMONPSU_MAX_SUP7_SUP_VAL_MASK 0x0000ffffU
2175 * Register: XSysmonPsuMaxSup8
2177 #define XSYSMONPSU_MAX_SUP8_OFFSET 0x00000284U
2178 #define XSYSMONPSU_MAX_SUP8_RSTVAL 0x00000000U
2180 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_SHIFT 0U
2181 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_WIDTH 16U
2182 #define XSYSMONPSU_MAX_SUP8_SUP_VAL_MASK 0x0000ffffU
2185 * Register: XSysmonPsuMaxSup9
2187 #define XSYSMONPSU_MAX_SUP9_OFFSET 0x00000288U
2188 #define XSYSMONPSU_MAX_SUP9_RSTVAL 0x00000000U
2190 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_SHIFT 0U
2191 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_WIDTH 16U
2192 #define XSYSMONPSU_MAX_SUP9_SUP_VAL_MASK 0x0000ffffU
2195 * Register: XSysmonPsuMaxSup10
2197 #define XSYSMONPSU_MAX_SUP10_OFFSET 0x0000028CU
2198 #define XSYSMONPSU_MAX_SUP10_RSTVAL 0x00000000U
2200 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_SHIFT 0U
2201 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_WIDTH 16U
2202 #define XSYSMONPSU_MAX_SUP10_SUP_VAL_MASK 0x0000ffffU
2205 * Register: XSysmonPsuMaxVccams
2207 #define XSYSMONPSU_MAX_VCCAMS_OFFSET 0x00000290U
2208 #define XSYSMONPSU_MAX_VCCAMS_RSTVAL 0x00000000U
2210 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_SHIFT 0U
2211 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_WIDTH 16U
2212 #define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2215 * Register: XSysmonPsuMaxTempRemte
2217 #define XSYSMONPSU_MAX_TEMP_REMTE_OFFSET 0x00000294U
2218 #define XSYSMONPSU_MAX_TEMP_REMTE_RSTVAL 0x00000000U
2220 #define XSYSMONPSU_MAX_TEMP_REMTE_SHIFT 0U
2221 #define XSYSMONPSU_MAX_TEMP_REMTE_WIDTH 16U
2222 #define XSYSMONPSU_MAX_TEMP_REMTE_MASK 0x0000ffffU
2225 * Register: XSysmonPsuMinSup7
2227 #define XSYSMONPSU_MIN_SUP7_OFFSET 0x000002A0U
2228 #define XSYSMONPSU_MIN_SUP7_RSTVAL 0x0000ffffU
2230 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_SHIFT 0U
2231 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_WIDTH 16U
2232 #define XSYSMONPSU_MIN_SUP7_SUP_VAL_MASK 0x0000ffffU
2235 * Register: XSysmonPsuMinSup8
2237 #define XSYSMONPSU_MIN_SUP8_OFFSET 0x000002A4U
2238 #define XSYSMONPSU_MIN_SUP8_RSTVAL 0x0000ffffU
2240 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_SHIFT 0U
2241 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_WIDTH 16U
2242 #define XSYSMONPSU_MIN_SUP8_SUP_VAL_MASK 0x0000ffffU
2245 * Register: XSysmonPsuMinSup9
2247 #define XSYSMONPSU_MIN_SUP9_OFFSET 0x000002A8U
2248 #define XSYSMONPSU_MIN_SUP9_RSTVAL 0x0000ffffU
2250 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_SHIFT 0U
2251 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_WIDTH 16U
2252 #define XSYSMONPSU_MIN_SUP9_SUP_VAL_MASK 0x0000ffffU
2255 * Register: XSysmonPsuMinSup10
2257 #define XSYSMONPSU_MIN_SUP10_OFFSET 0x000002ACU
2258 #define XSYSMONPSU_MIN_SUP10_RSTVAL 0x0000ffffU
2260 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_SHIFT 0U
2261 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_WIDTH 16U
2262 #define XSYSMONPSU_MIN_SUP10_SUP_VAL_MASK 0x0000ffffU
2265 * Register: XSysmonPsuMinVccams
2267 #define XSYSMONPSU_MIN_VCCAMS_OFFSET 0x000002B0U
2268 #define XSYSMONPSU_MIN_VCCAMS_RSTVAL 0x0000ffffU
2270 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_SHIFT 0U
2271 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_WIDTH 16U
2272 #define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_MASK 0x0000ffffU
2275 * Register: XSysmonPsuMinTempRemte
2277 #define XSYSMONPSU_MIN_TEMP_REMTE_OFFSET 0x000002B4U
2278 #define XSYSMONPSU_MIN_TEMP_REMTE_RSTVAL 0x0000ffffU
2280 #define XSYSMONPSU_MIN_TEMP_REMTE_SHIFT 0U
2281 #define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH 16U
2282 #define XSYSMONPSU_MIN_TEMP_REMTE_MASK 0x0000ffffU
2284 /***************** Macros (Inline Functions) Definitions *********************/
2286 /****************************************************************************/
2289 * This macro reads the given register.
2291 * @param RegisterAddr is the register address in the address
2292 * space of the SYSMONPSU device.
2294 * @return The 32-bit value of the register
2298 *****************************************************************************/
2299 #define XSysmonPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
2301 /****************************************************************************/
2304 * This macro writes the given register.
2306 * @param RegisterAddr is the register address in the address
2307 * space of the SYSMONPSU device.
2308 * @param Data is the 32-bit value to write to the register.
2314 *****************************************************************************/
2315 #define XSysmonPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
2321 #endif /* XSYSMONPSU_HW_H__ */