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32 /*****************************************************************************/
36 * @addtogroup ttcps_v3_0
40 * This is the driver for one 16-bit timer counter in the Triple Timer Counter
41 * (TTC) module in the Ps block.
43 * The TTC module provides three independent timer/counter modules that can each
44 * be clocked using either the system clock (pclk) or an externally driven
45 * clock (ext_clk). In addition, each counter can independently prescale its
46 * selected clock input (divided by 2 to 65536). Counters can be set to
47 * decrement or increment.
49 * Each of the counters can be programmed to generate interrupt pulses:
50 * . At a regular, predefined period, that is on a timed interval
51 * . When the counter registers overflow
52 * . When the count matches any one of the three 'match' registers
54 * Therefore, up to six different events can trigger a timer interrupt: three
55 * match interrupts, an overflow interrupt, an interval interrupt and an event
56 * timer interrupt. Note that the overflow interrupt and the interval interrupt
57 * are mutually exclusive.
59 * <b>Initialization & Configuration</b>
61 * An XTtcPs_Config structure is used to configure a driver instance.
62 * Information in the XTtcPs_Config structure is the hardware properties
65 * A driver instance is initialized through
66 * XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
67 * is a pointer to the XTtcPs_Config structure, it can be looked up statically
68 * through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
69 * EffectiveAddr can be the static base address of the device or virtual
70 * mapped address if address translation is supported.
74 * Interrupt handler is not provided by the driver, as handling of interrupt
75 * is application specific.
78 * The default setting for a timer/counter is:
80 * - Internal clock (pclk) selected
82 * - All Interrupts disabled
83 * - Output waveforms disabled
86 * MODIFICATION HISTORY:
88 * Ver Who Date Changes
89 * ----- ------ -------- -----------------------------------------------------
90 * 1.00a drg/jz 01/20/10 First release..
91 * 2.0 adk 12/10/13 Updated as per the New Tcl API's
92 * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
93 * modified for MISRA-C:2012 compliance.
94 * 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
95 * macros to return 32 bit values for zynq ultrascale+mpsoc
98 ******************************************************************************/
100 #ifndef XTTCPS_H /* prevent circular inclusions */
101 #define XTTCPS_H /* by using protection macros */
107 /***************************** Include Files *********************************/
109 #include "xttcps_hw.h"
112 /************************** Constant Definitions *****************************/
114 * Flag for a9 processor
116 #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
121 * Maximum Value for interval counter
124 #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
126 #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
129 /** @name Configuration options
131 * Options for the device. Each of the options is bit field, so more than one
132 * options can be specified.
136 #define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
137 #define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
139 #define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
140 #define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
141 #define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
142 #define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
143 #define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
145 /**************************** Type Definitions *******************************/
148 * This typedef contains configuration information for the device.
151 u16 DeviceId; /**< Unique ID for device */
152 u32 BaseAddress; /**< Base address for device */
153 u32 InputClockHz; /**< Input clock frequency */
157 * The XTtcPs driver instance data. The user is required to allocate a
158 * variable of this type for each PS timer/counter device in the system. A
159 * pointer to a variable of this type is then passed to various driver API
163 XTtcPs_Config Config; /**< Configuration structure */
164 u32 IsReady; /**< Device is initialized and ready */
168 * This typedef contains interval count
171 typedef u16 XInterval;
173 typedef u32 XInterval;
175 /***************** Macros (Inline Functions) Definitions *********************/
178 * Internal helper macros
180 #define InstReadReg(InstancePtr, RegOffset) \
181 (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
183 #define InstWriteReg(InstancePtr, RegOffset, Data) \
184 (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
186 /*****************************************************************************/
189 * This function starts the counter/timer without resetting the counter value.
191 * @param InstancePtr is a pointer to the XTtcPs instance.
195 * @note C-style signature:
196 * void XTtcPs_Start(XTtcPs *InstancePtr)
198 ****************************************************************************/
199 #define XTtcPs_Start(InstancePtr) \
200 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
201 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
202 ~XTTCPS_CNT_CNTRL_DIS_MASK))
204 /*****************************************************************************/
207 * This function stops the counter/timer. This macro may be called at any time
208 * to stop the counter. The counter holds the last value until it is reset,
209 * restarted or enabled.
211 * @param InstancePtr is a pointer to the XTtcPs instance.
215 * @note C-style signature:
216 * void XTtcPs_Stop(XTtcPs *InstancePtr)
218 ****************************************************************************/
219 #define XTtcPs_Stop(InstancePtr) \
220 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
221 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
222 XTTCPS_CNT_CNTRL_DIS_MASK))
224 /*****************************************************************************/
227 * This function checks whether the timer counter has already started.
229 * @param InstancePtr is a pointer to the XTtcPs instance
231 * @return Non-zero if the device has started, '0' otherwise.
233 * @note C-style signature:
234 * int XTtcPs_IsStarted(XTtcPs *InstancePtr)
236 ****************************************************************************/
237 #define XTtcPs_IsStarted(InstancePtr) \
238 ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
239 XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
241 /*****************************************************************************/
244 * This function returns the current 16-bit counter value. It may be called at
247 * @param InstancePtr is a pointer to the XTtcPs instance.
249 * @return zynq:16 bit counter value.
250 * zynq ultrascale+mpsoc:32 bit counter value.
252 * @note C-style signature:
253 * zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
254 * zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
256 ****************************************************************************/
259 * ttc supports 16 bit counter for zynq
261 #define XTtcPs_GetCounterValue(InstancePtr) \
262 (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
265 * ttc supports 32 bit counter for zynq ultrascale+mpsoc
267 #define XTtcPs_GetCounterValue(InstancePtr) \
268 InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
271 /*****************************************************************************/
274 * This function sets the interval value to be used in interval mode.
276 * @param InstancePtr is a pointer to the XTtcPs instance.
277 * @param Value is the 16-bit value to be set in the interval register.
281 * @note C-style signature:
282 * void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
284 ****************************************************************************/
285 #define XTtcPs_SetInterval(InstancePtr, Value) \
286 InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
288 /*****************************************************************************/
291 * This function gets the interval value from the interval register.
293 * @param InstancePtr is a pointer to the XTtcPs instance.
295 * @return zynq:16 bit interval value.
296 * zynq ultrascale+mpsoc:32 bit interval value.
298 * @note C-style signature:
299 * zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
300 * zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
302 ****************************************************************************/
305 * ttc supports 16 bit interval counter for zynq
307 #define XTtcPs_GetInterval(InstancePtr) \
308 (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
311 * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
313 #define XTtcPs_GetInterval(InstancePtr) \
314 InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
316 /*****************************************************************************/
319 * This macro resets the count register. It may be called at any time. The
320 * counter is reset to either 0 or 0xFFFF, or the interval value, depending on
321 * the increment/decrement mode. The state of the counter, as started or
322 * stopped, is not affected by calling reset.
324 * @param InstancePtr is a pointer to the XTtcPs instance.
328 * @note C-style signature:
329 * void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
331 ****************************************************************************/
332 #define XTtcPs_ResetCounterValue(InstancePtr) \
333 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
334 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
335 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
337 /*****************************************************************************/
340 * This function enables the interrupts.
342 * @param InstancePtr is a pointer to the XTtcPs instance.
343 * @param InterruptMask defines which interrupt should be enabled.
344 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
345 * This is a bit mask, all set bits will be enabled, cleared bits
346 * will not be disabled.
352 * void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
354 ******************************************************************************/
355 #define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
356 InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
357 (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
360 /*****************************************************************************/
363 * This function disables the interrupts.
365 * @param InstancePtr is a pointer to the XTtcPs instance.
366 * @param InterruptMask defines which interrupt should be disabled.
367 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
368 * This is a bit mask, all set bits will be disabled, cleared bits
369 * will not be disabled.
375 * void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
377 ******************************************************************************/
378 #define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
379 InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
380 (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
383 /*****************************************************************************/
386 * This function reads the interrupt status.
388 * @param InstancePtr is a pointer to the XTtcPs instance.
392 * @note C-style signature:
393 * u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
395 ******************************************************************************/
396 #define XTtcPs_GetInterruptStatus(InstancePtr) \
397 InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
399 /*****************************************************************************/
402 * This function clears the interrupt status.
404 * @param InstancePtr is a pointer to the XTtcPs instance.
405 * @param InterruptMask defines which interrupt should be cleared.
406 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
407 * This is a bit mask, all set bits will be cleared, cleared bits
408 * will not be cleared.
414 * void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
416 ******************************************************************************/
417 #define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
418 InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
422 /************************** Function Prototypes ******************************/
425 * Initialization functions in xttcps_sinit.c
427 XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
430 * Required functions, in xttcps.c
432 s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
433 XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
435 void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
436 u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
438 void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
439 u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
441 void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
442 XInterval *Interval, u8 *Prescaler);
445 * Functions for options, in file xttcps_options.c
447 s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
448 u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
451 * Function for self-test, in file xttcps_selftest.c
453 s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
459 #endif /* end of protection macro */