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32 /*****************************************************************************/
36 * @addtogroup ttcps_v3_5
40 * This is the driver for one 16-bit timer counter in the Triple Timer Counter
41 * (TTC) module in the Ps block.
43 * The TTC module provides three independent timer/counter modules that can each
44 * be clocked using either the system clock (pclk) or an externally driven
45 * clock (ext_clk). In addition, each counter can independently prescale its
46 * selected clock input (divided by 2 to 65536). Counters can be set to
47 * decrement or increment.
49 * Each of the counters can be programmed to generate interrupt pulses:
50 * . At a regular, predefined period, that is on a timed interval
51 * . When the counter registers overflow
52 * . When the count matches any one of the three 'match' registers
54 * Therefore, up to six different events can trigger a timer interrupt: three
55 * match interrupts, an overflow interrupt, an interval interrupt and an event
56 * timer interrupt. Note that the overflow interrupt and the interval interrupt
57 * are mutually exclusive.
59 * <b>Initialization & Configuration</b>
61 * An XTtcPs_Config structure is used to configure a driver instance.
62 * Information in the XTtcPs_Config structure is the hardware properties
65 * A driver instance is initialized through
66 * XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
67 * is a pointer to the XTtcPs_Config structure, it can be looked up statically
68 * through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
69 * EffectiveAddr can be the static base address of the device or virtual
70 * mapped address if address translation is supported.
74 * Interrupt handler is not provided by the driver, as handling of interrupt
75 * is application specific.
78 * The default setting for a timer/counter is:
80 * - Internal clock (pclk) selected
82 * - All Interrupts disabled
83 * - Output waveforms disabled
86 * MODIFICATION HISTORY:
88 * Ver Who Date Changes
89 * ----- ------ -------- -----------------------------------------------------
90 * 1.00a drg/jz 01/20/10 First release..
91 * 2.0 adk 12/10/13 Updated as per the New Tcl API's
92 * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
93 * modified for MISRA-C:2012 compliance.
94 * 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
95 * macros to return 32 bit values for zynq ultrascale+mpsoc
96 * ms 01/23/17 Modified xil_printf statement in main function for all
97 * examples to ensure that "Successfully ran" and "Failed"
98 * strings are available in all examples. This is a fix
100 * ms 03/17/17 Added readme.txt file in examples folder for doxygen
102 * 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros
103 * definitions of ttcps in xparameters.h
104 * 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width
108 ******************************************************************************/
110 #ifndef XTTCPS_H /* prevent circular inclusions */
111 #define XTTCPS_H /* by using protection macros */
117 /***************************** Include Files *********************************/
119 #include "xttcps_hw.h"
122 /************************** Constant Definitions *****************************/
126 * Maximum Value for interval counter
129 #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
131 #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
134 /** @name Configuration options
136 * Options for the device. Each of the options is bit field, so more than one
137 * options can be specified.
141 #define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
142 #define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
144 #define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
145 #define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
146 #define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
147 #define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
148 #define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
150 /**************************** Type Definitions *******************************/
153 * This typedef contains configuration information for the device.
156 u16 DeviceId; /**< Unique ID for device */
157 u32 BaseAddress; /**< Base address for device */
158 u32 InputClockHz; /**< Input clock frequency */
162 * The XTtcPs driver instance data. The user is required to allocate a
163 * variable of this type for each PS timer/counter device in the system. A
164 * pointer to a variable of this type is then passed to various driver API
168 XTtcPs_Config Config; /**< Configuration structure */
169 u32 IsReady; /**< Device is initialized and ready */
173 * This typedef contains interval count and Match register value
176 typedef u16 XInterval;
177 typedef u16 XMatchRegValue;
179 typedef u32 XInterval;
180 typedef u32 XMatchRegValue;
182 /***************** Macros (Inline Functions) Definitions *********************/
185 * Internal helper macros
187 #define InstReadReg(InstancePtr, RegOffset) \
188 (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
190 #define InstWriteReg(InstancePtr, RegOffset, Data) \
191 (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
193 /*****************************************************************************/
196 * This function starts the counter/timer without resetting the counter value.
198 * @param InstancePtr is a pointer to the XTtcPs instance.
202 * @note C-style signature:
203 * void XTtcPs_Start(XTtcPs *InstancePtr)
205 ****************************************************************************/
206 #define XTtcPs_Start(InstancePtr) \
207 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
208 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
209 ~XTTCPS_CNT_CNTRL_DIS_MASK))
211 /*****************************************************************************/
214 * This function stops the counter/timer. This macro may be called at any time
215 * to stop the counter. The counter holds the last value until it is reset,
216 * restarted or enabled.
218 * @param InstancePtr is a pointer to the XTtcPs instance.
222 * @note C-style signature:
223 * void XTtcPs_Stop(XTtcPs *InstancePtr)
225 ****************************************************************************/
226 #define XTtcPs_Stop(InstancePtr) \
227 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
228 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
229 XTTCPS_CNT_CNTRL_DIS_MASK))
231 /*****************************************************************************/
234 * This function checks whether the timer counter has already started.
236 * @param InstancePtr is a pointer to the XTtcPs instance
238 * @return Non-zero if the device has started, '0' otherwise.
240 * @note C-style signature:
241 * int XTtcPs_IsStarted(XTtcPs *InstancePtr)
243 ****************************************************************************/
244 #define XTtcPs_IsStarted(InstancePtr) \
245 ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
246 XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
248 /*****************************************************************************/
251 * This function returns the current 16-bit counter value. It may be called at
254 * @param InstancePtr is a pointer to the XTtcPs instance.
256 * @return zynq:16 bit counter value.
257 * zynq ultrascale+mpsoc:32 bit counter value.
259 * @note C-style signature:
260 * zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
261 * zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
263 ****************************************************************************/
266 * ttc supports 16 bit counter for zynq
268 #define XTtcPs_GetCounterValue(InstancePtr) \
269 (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
272 * ttc supports 32 bit counter for zynq ultrascale+mpsoc
274 #define XTtcPs_GetCounterValue(InstancePtr) \
275 InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
278 /*****************************************************************************/
281 * This function sets the interval value to be used in interval mode.
283 * @param InstancePtr is a pointer to the XTtcPs instance.
284 * @param Value is the 16-bit value to be set in the interval register.
288 * @note C-style signature:
289 * void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
291 ****************************************************************************/
292 #define XTtcPs_SetInterval(InstancePtr, Value) \
293 InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
295 /*****************************************************************************/
298 * This function gets the interval value from the interval register.
300 * @param InstancePtr is a pointer to the XTtcPs instance.
302 * @return zynq:16 bit interval value.
303 * zynq ultrascale+mpsoc:32 bit interval value.
305 * @note C-style signature:
306 * zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
307 * zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
309 ****************************************************************************/
312 * ttc supports 16 bit interval counter for zynq
314 #define XTtcPs_GetInterval(InstancePtr) \
315 (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
318 * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
320 #define XTtcPs_GetInterval(InstancePtr) \
321 InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
323 /*****************************************************************************/
326 * This macro resets the count register. It may be called at any time. The
327 * counter is reset to either 0 or 0xFFFF, or the interval value, depending on
328 * the increment/decrement mode. The state of the counter, as started or
329 * stopped, is not affected by calling reset.
331 * @param InstancePtr is a pointer to the XTtcPs instance.
335 * @note C-style signature:
336 * void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
338 ****************************************************************************/
339 #define XTtcPs_ResetCounterValue(InstancePtr) \
340 InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
341 (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
342 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
344 /*****************************************************************************/
347 * This function enables the interrupts.
349 * @param InstancePtr is a pointer to the XTtcPs instance.
350 * @param InterruptMask defines which interrupt should be enabled.
351 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
352 * This is a bit mask, all set bits will be enabled, cleared bits
353 * will not be disabled.
359 * void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
361 ******************************************************************************/
362 #define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
363 InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
364 (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
367 /*****************************************************************************/
370 * This function disables the interrupts.
372 * @param InstancePtr is a pointer to the XTtcPs instance.
373 * @param InterruptMask defines which interrupt should be disabled.
374 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
375 * This is a bit mask, all set bits will be disabled, cleared bits
376 * will not be disabled.
382 * void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
384 ******************************************************************************/
385 #define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
386 InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
387 (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
390 /*****************************************************************************/
393 * This function reads the interrupt status.
395 * @param InstancePtr is a pointer to the XTtcPs instance.
399 * @note C-style signature:
400 * u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
402 ******************************************************************************/
403 #define XTtcPs_GetInterruptStatus(InstancePtr) \
404 InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
406 /*****************************************************************************/
409 * This function clears the interrupt status.
411 * @param InstancePtr is a pointer to the XTtcPs instance.
412 * @param InterruptMask defines which interrupt should be cleared.
413 * Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
414 * This is a bit mask, all set bits will be cleared, cleared bits
415 * will not be cleared.
421 * void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
423 ******************************************************************************/
424 #define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
425 InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
429 /************************** Function Prototypes ******************************/
432 * Initialization functions in xttcps_sinit.c
434 XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
437 * Required functions, in xttcps.c
439 s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
440 XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
442 void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
443 XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
445 void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
446 u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
448 void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
449 XInterval *Interval, u8 *Prescaler);
452 * Functions for options, in file xttcps_options.c
454 s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
455 u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
458 * Function for self-test, in file xttcps_selftest.c
460 s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
466 #endif /* end of protection macro */