1 /******************************************************************************
3 * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
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9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
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29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup usbpsu_v1_3
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- ----- -------- -----------------------------------------------------
45 * 1.0 sg 06/06/16 First release
46 * 1.4 myk 12/01/18 Added support of hibernation
50 *****************************************************************************/
52 #ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
53 #define XUSBPSU_HW_H /* by using protection macros */
59 /***************************** Include Files ********************************/
61 /************************** Constant Definitions ****************************/
63 /**@name Register offsets
65 * The following constants provide access to each of the registers of the
71 #define XUSBPSU_PORTSC_30 0x430
72 #define XUSBPSU_PORTMSC_30 0x434
74 /* XUSBPSU registers memory space boundries */
75 #define XUSBPSU_GLOBALS_REGS_START 0xc100
76 #define XUSBPSU_GLOBALS_REGS_END 0xc6ff
77 #define XUSBPSU_DEVICE_REGS_START 0xc700
78 #define XUSBPSU_DEVICE_REGS_END 0xcbff
79 #define XUSBPSU_OTG_REGS_START 0xcc00
80 #define XUSBPSU_OTG_REGS_END 0xccff
82 /* Global Registers */
83 #define XUSBPSU_GSBUSCFG0 0xc100
84 #define XUSBPSU_GSBUSCFG1 0xc104
85 #define XUSBPSU_GTXTHRCFG 0xc108
86 #define XUSBPSU_GRXTHRCFG 0xc10c
87 #define XUSBPSU_GCTL 0xc110
88 #define XUSBPSU_GEVTEN 0xc114
89 #define XUSBPSU_GSTS 0xc118
90 #define XUSBPSU_GSNPSID 0xc120
91 #define XUSBPSU_GGPIO 0xc124
92 #define XUSBPSU_GUID 0xc128
93 #define XUSBPSU_GUCTL 0xc12c
94 #define XUSBPSU_GBUSERRADDR0 0xc130
95 #define XUSBPSU_GBUSERRADDR1 0xc134
96 #define XUSBPSU_GPRTBIMAP0 0xc138
97 #define XUSBPSU_GPRTBIMAP1 0xc13c
98 #define XUSBPSU_GHWPARAMS0_OFFSET 0xc140U
99 #define XUSBPSU_GHWPARAMS1_OFFSET 0xc144U
100 #define XUSBPSU_GHWPARAMS2_OFFSET 0xc148U
101 #define XUSBPSU_GHWPARAMS3_OFFSET 0xc14cU
102 #define XUSBPSU_GHWPARAMS4_OFFSET 0xc150U
103 #define XUSBPSU_GHWPARAMS5_OFFSET 0xc154U
104 #define XUSBPSU_GHWPARAMS6_OFFSET 0xc158U
105 #define XUSBPSU_GHWPARAMS7_OFFSET 0xc15cU
106 #define XUSBPSU_GDBGFIFOSPACE 0xc160
107 #define XUSBPSU_GDBGLTSSM 0xc164
108 #define XUSBPSU_GPRTBIMAP_HS0 0xc180
109 #define XUSBPSU_GPRTBIMAP_HS1 0xc184
110 #define XUSBPSU_GPRTBIMAP_FS0 0xc188
111 #define XUSBPSU_GPRTBIMAP_FS1 0xc18c
113 #define XUSBPSU_GUSB2PHYCFG(n) ((u32)0xc200 + ((u32)(n) * (u32)0x04))
114 #define XUSBPSU_GUSB2I2CCTL(n) ((u32)0xc240 + ((u32)(n) * (u32)0x04))
116 #define XUSBPSU_GUSB2PHYACC(n) ((u32)0xc280 + ((u32)(n) * (u32)0x04))
118 #define XUSBPSU_GUSB3PIPECTL(n) ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
120 #define XUSBPSU_GTXFIFOSIZ(n) ((u32)0xc300 + ((u32)(n) * (u32)0x04))
121 #define XUSBPSU_GRXFIFOSIZ(n) ((u32)0xc380 + ((u32)(n) * (u32)0x04))
123 #define XUSBPSU_GEVNTADRLO(n) ((u32)0xc400 + ((u32)(n) * (u32)0x10))
124 #define XUSBPSU_GEVNTADRHI(n) ((u32)0xc404 + ((u32)(n) * (u32)0x10))
125 #define XUSBPSU_GEVNTSIZ(n) ((u32)0xc408 + ((u32)(n) * (u32)0x10))
126 #define XUSBPSU_GEVNTCOUNT(n) ((u32)0xc40c + ((u32)(n) * (u32)0x10))
128 #define XUSBPSU_GHWPARAMS8 0x0000c600U
130 /* Device Registers */
131 #define XUSBPSU_DCFG 0x0000c700U
132 #define XUSBPSU_DCTL 0x0000c704U
133 #define XUSBPSU_DEVTEN 0x0000c708U
134 #define XUSBPSU_DSTS 0x0000c70cU
135 #define XUSBPSU_DGCMDPAR 0x0000c710U
136 #define XUSBPSU_DGCMD 0x0000c714U
137 #define XUSBPSU_DALEPENA 0x0000c720U
138 #define XUSBPSU_DEPCMDPAR2(n) ((u32)0xc800 + ((u32)n * (u32)0x10))
139 #define XUSBPSU_DEPCMDPAR1(n) ((u32)0xc804 + ((u32)n * (u32)0x10))
140 #define XUSBPSU_DEPCMDPAR0(n) ((u32)0xc808 + ((u32)n * (u32)0x10))
141 #define XUSBPSU_DEPCMD(n) ((u32)0xc80c + ((u32)n * (u32)0x10))
144 #define XUSBPSU_OCFG 0x0000cc00U
145 #define XUSBPSU_OCTL 0x0000cc04U
146 #define XUSBPSU_OEVT 0xcc08U
147 #define XUSBPSU_OEVTEN 0xcc0CU
148 #define XUSBPSU_OSTS 0xcc10U
152 /* Global Configuration Register */
153 #define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
154 #define XUSBPSU_GCTL_U2RSTECN (1 << 16)
155 #define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
156 #define XUSBPSU_GCTL_CLK_BUS (0U)
157 #define XUSBPSU_GCTL_CLK_PIPE (1U)
158 #define XUSBPSU_GCTL_CLK_PIPEHALF (2U)
159 #define XUSBPSU_GCTL_CLK_MASK (3U)
161 #define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
162 #define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
163 #define XUSBPSU_GCTL_PRTCAP_HOST 1U
164 #define XUSBPSU_GCTL_PRTCAP_DEVICE 2U
165 #define XUSBPSU_GCTL_PRTCAP_OTG 3U
167 #define XUSBPSU_GCTL_CORESOFTRESET (0x00000001U << 11)
168 #define XUSBPSU_GCTL_SOFITPSYNC (0x00000001U << 10)
169 #define XUSBPSU_GCTL_SCALEDOWN(n) ((u32)(n) << 4)
170 #define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
171 #define XUSBPSU_GCTL_DISSCRAMBLE (0x00000001U << 3)
172 #define XUSBPSU_GCTL_U2EXIT_LFPS (0x00000001U << 2)
173 #define XUSBPSU_GCTL_GBLHIBERNATIONEN (0x00000001U << 1)
174 #define XUSBPSU_GCTL_DSBLCLKGTNG (0x00000001U << 0)
176 /* Global Status Register Device Interrupt Mask */
177 #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
178 #define XUSBPSU_GSTS_CUR_MODE (0x00000001U << 0)
180 /* Global USB2 PHY Configuration Register */
181 #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31)
182 #define XUSBPSU_GUSB2PHYCFG_SUSPHY (0x00000001U << 6)
184 /* Global USB3 PIPE Control Register */
185 #define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (0x00000001U << 31)
186 #define XUSBPSU_GUSB3PIPECTL_SUSPHY (0x00000001U << 17)
188 /* Global TX Fifo Size Register */
189 #define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((u32)(n) & (u32)0xffffU)
190 #define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((u32)(n) & 0xffff0000U)
192 /* Global Event Size Registers */
193 #define XUSBPSU_GEVNTSIZ_INTMASK ((u32)0x00000001U << 31U)
194 #define XUSBPSU_GEVNTSIZ_SIZE(n) ((u32)(n) & (u32)0xffffU)
196 /* Global HWPARAMS1 Register */
197 #define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((u32)(n) & ((u32)3 << 24)) >> 24)
198 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0U
199 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1U
200 #define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2U
201 #define XUSBPSU_GHWPARAMS1_PWROPT(n) ((u32)(n) << 24)
202 #define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
204 /* Global HWPARAMS4 Register */
205 #define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
206 #define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15U
208 /* Device Configuration Register */
209 #define XUSBPSU_DCFG_DEVADDR(addr) ((u32)(addr) << 3)
210 #define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
212 #define XUSBPSU_DCFG_SPEED_MASK 7U
213 #define XUSBPSU_DCFG_SUPERSPEED 4U
214 #define XUSBPSU_DCFG_HIGHSPEED 0U
215 #define XUSBPSU_DCFG_FULLSPEED2 1U
216 #define XUSBPSU_DCFG_LOWSPEED 2U
217 #define XUSBPSU_DCFG_FULLSPEED1 3U
219 #define XUSBPSU_DCFG_LPM_CAP (0x00000001U << 22U)
221 /* Device Control Register */
222 #define XUSBPSU_DCTL_RUN_STOP (0x00000001U << 31U)
223 #define XUSBPSU_DCTL_CSFTRST ((u32)0x00000001U << 30U)
224 #define XUSBPSU_DCTL_LSFTRST (0x00000001U << 29U)
226 #define XUSBPSU_DCTL_HIRD_THRES_MASK (0x0000001fU << 24U)
227 #define XUSBPSU_DCTL_HIRD_THRES(n) ((u32)(n) << 24)
229 #define XUSBPSU_DCTL_APPL1RES (0x00000001U << 23)
231 /* These apply for core versions 1.87a and earlier */
232 #define XUSBPSU_DCTL_TRGTULST_MASK (0x0000000fU << 17)
233 #define XUSBPSU_DCTL_TRGTULST(n) ((u32)(n) << 17)
234 #define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
235 #define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
236 #define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
237 #define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
238 #define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
240 /* These apply for core versions 1.94a and later */
241 #define XUSBPSU_DCTL_KEEP_CONNECT (0x00000001U << 19)
242 #define XUSBPSU_DCTL_L1_HIBER_EN (0x00000001U << 18)
243 #define XUSBPSU_DCTL_CRS (0x00000001U << 17)
244 #define XUSBPSU_DCTL_CSS (0x00000001U << 16)
246 #define XUSBPSU_DCTL_INITU2ENA (0x00000001U << 12)
247 #define XUSBPSU_DCTL_ACCEPTU2ENA (0x00000001U << 11)
248 #define XUSBPSU_DCTL_INITU1ENA (0x00000001U << 10)
249 #define XUSBPSU_DCTL_ACCEPTU1ENA (0x00000001U << 9)
250 #define XUSBPSU_DCTL_TSTCTRL_MASK (0x0000000fU << 1)
252 #define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0000000fU << 5)
253 #define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
255 #define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
256 #define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
257 #define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
258 #define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
259 #define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
260 #define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
261 #define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
263 /* Device Event Enable Register */
264 #define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN ((u32)0x00000001 << 12)
265 #define XUSBPSU_DEVTEN_EVNTOVERFLOWEN ((u32)0x00000001 << 11)
266 #define XUSBPSU_DEVTEN_CMDCMPLTEN ((u32)0x00000001 << 10)
267 #define XUSBPSU_DEVTEN_ERRTICERREN ((u32)0x00000001 << 9)
268 #define XUSBPSU_DEVTEN_SOFEN ((u32)0x00000001 << 7)
269 #define XUSBPSU_DEVTEN_EOPFEN ((u32)0x00000001 << 6)
270 #define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN ((u32)0x00000001 << 5)
271 #define XUSBPSU_DEVTEN_WKUPEVTEN ((u32)0x00000001 << 4)
272 #define XUSBPSU_DEVTEN_ULSTCNGEN ((u32)0x00000001 << 3)
273 #define XUSBPSU_DEVTEN_CONNECTDONEEN ((u32)0x00000001 << 2)
274 #define XUSBPSU_DEVTEN_USBRSTEN ((u32)0x00000001 << 1)
275 #define XUSBPSU_DEVTEN_DISCONNEVTEN ((u32)0x00000001 << 0)
277 /* Device Status Register */
278 #define XUSBPSU_DSTS_DCNRD (0x00000001U << 29)
280 /* This applies for core versions 1.87a and earlier */
281 #define XUSBPSU_DSTS_PWRUPREQ (0x00000001U << 24)
283 /* These apply for core versions 1.94a and later */
284 #define XUSBPSU_DSTS_RSS (0x00000001U << 25)
285 #define XUSBPSU_DSTS_SSS (0x00000001U << 24)
287 #define XUSBPSU_DSTS_COREIDLE (0x00000001U << 23)
288 #define XUSBPSU_DSTS_DEVCTRLHLT (0x00000001U << 22)
290 #define XUSBPSU_DSTS_USBLNKST_MASK (0x0000000fU << 18)
291 #define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
293 #define XUSBPSU_DSTS_RXFIFOEMPTY (0x00000001U << 17)
295 #define XUSBPSU_DSTS_SOFFN_MASK (0x00003fffU << 3)
296 #define XUSBPSU_DSTS_SOFFN(n) (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
298 #define XUSBPSU_DSTS_CONNECTSPD (0x00000007U << 0)
300 #define XUSBPSU_DSTS_SUPERSPEED (4U << 0)
301 #define XUSBPSU_DSTS_HIGHSPEED (0U << 0)
302 #define XUSBPSU_DSTS_FULLSPEED2 (1U << 0)
303 #define XUSBPSU_DSTS_LOWSPEED (2U << 0)
304 #define XUSBPSU_DSTS_FULLSPEED1 (3U << 0)
306 /*Portpmsc 3.0 bit field*/
307 #define XUSBPSU_PORTMSC_30_FLA_MASK (1U << 16)
308 #define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK (0xffU << 8)
309 #define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT (8U)
310 #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0)
311 #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U)
313 /* Register for LPD block */
314 #define RST_LPD_TOP 0x23C
315 #define USB0_CORE_RST (1 << 6)
316 #define USB1_CORE_RST (1 << 7)
318 /* Vendor registers for Xilinx */
319 #define XIL_CUR_PWR_STATE 0x00
320 #define XIL_PME_ENABLE 0x34
321 #define XIL_REQ_PWR_STATE 0x3c
322 #define XIL_PWR_CONFIG_USB3 0x48
324 #define XIL_REQ_PWR_STATE_D0 0
325 #define XIL_REQ_PWR_STATE_D3 3
326 #define XIL_PME_ENABLE_SIG_GEN 1
327 #define XIL_CUR_PWR_STATE_D0 0
328 #define XIL_CUR_PWR_STATE_D3 3
329 #define XIL_CUR_PWR_STATE_BITMASK 0x03
331 #define VENDOR_BASE_ADDRESS 0xFF9D0000
332 #define LPD_BASE_ADDRESS 0xFF5E0000
336 /**************************** Type Definitions *******************************/
338 /***************** Macros (Inline Functions) Definitions *********************/
340 /*****************************************************************************/
343 * Read a register of the USBPS8 device. This macro provides register
344 * access to all registers using the register offsets defined above.
346 * @param InstancePtr is a pointer to the XUsbPsu instance.
347 * @param Offset is the offset of the register to read.
349 * @return The contents of the register.
351 * @note C-style Signature:
352 * u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
354 ******************************************************************************/
355 #define XUsbPsu_ReadReg(InstancePtr, Offset) \
356 Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
358 /*****************************************************************************/
361 * Write a register of the USBPS8 device. This macro provides
362 * register access to all registers using the register offsets defined above.
364 * @param InstancePtr is a pointer to the XUsbPsu instance.
365 * @param RegOffset is the offset of the register to write.
366 * @param Data is the value to write to the register.
370 * @note C-style Signature:
371 * void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
372 * u32 Offset,u32 Data)
374 ******************************************************************************/
375 #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
376 Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
378 /*****************************************************************************/
381 * Read a vendor register of the USBPS8 device.
383 * @param Offset is the offset of the register to read.
385 * @return The contents of the register.
387 * @note C-style Signature:
388 * u32 XUsbPsu_ReadVendorReg(struct XUsbPsu *InstancePtr, u32 Offset);
390 ******************************************************************************/
391 #define XUsbPsu_ReadVendorReg(Offset) \
392 Xil_In32(VENDOR_BASE_ADDRESS + (u32)(Offset))
394 /*****************************************************************************/
397 * Write a Vendor register of the USBPS8 device.
399 * @param RegOffset is the offset of the register to write.
400 * @param Data is the value to write to the register.
404 * @note C-style Signature:
405 * void XUsbPsu_WriteVendorReg(struct XUsbPsu *InstancePtr,
406 * u32 Offset,u32 Data)
408 ******************************************************************************/
409 #define XUsbPsu_WriteVendorReg(Offset, Data) \
410 Xil_Out32(VENDOR_BASE_ADDRESS + (u32)(Offset), (u32)(Data))
412 /*****************************************************************************/
415 * Read a LPD register of the USBPS8 device.
417 * @param InstancePtr is a pointer to the XUsbPsu instance.
418 * @param Offset is the offset of the register to read.
420 * @return The contents of the register.
422 * @note C-style Signature:
423 * u32 XUsbPsu_ReadLpdReg(struct XUsbPsu *InstancePtr, u32 Offset);
425 ******************************************************************************/
426 #define XUsbPsu_ReadLpdReg(Offset) \
427 Xil_In32(LPD_BASE_ADDRESS + (u32)(Offset))
429 /*****************************************************************************/
432 * Write a LPD register of the USBPS8 device.
434 * @param InstancePtr is a pointer to the XUsbPsu instance.
435 * @param RegOffset is the offset of the register to write.
436 * @param Data is the value to write to the register.
440 * @note C-style Signature:
441 * void XUsbPsu_WriteLpdReg(struct XUsbPsu *InstancePtr,
442 * u32 Offset,u32 Data)
444 ******************************************************************************/
445 #define XUsbPsu_WriteLpdReg(Offset, Data) \
446 Xil_Out32(LPD_BASE_ADDRESS + (u32)(Offset), (u32)(Data))
448 /************************** Function Prototypes ******************************/
454 #endif /* End of protection macro. */