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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup zdma_v1_5
40 * ZDMA is a general purpose DMA designed to support memory to memory and memory
41 * to IO buffer transfers. ZynqMP has two instance of general purpose ZDMA.
42 * One is located in FPD (full power domain) which is GDMA and other is located
43 * in LPD (low power domain) which is ADMA.
45 * GMDA & ADMA are configured each with 8 DMA channels and and each channel can
46 * be programmed secure or non-secure.
47 * Each channel is divided into two functional sides, Source (Read) and
48 * Destination (Write). Each DMA channel can be independently programmed
49 * in one of following DMA modes.
51 * - Normal data transfer from source to destination.
54 * - Scatter Gather DMA
55 * - Only Normal mode it can't support other two modes.
56 * In Scatter gather descriptor can be of 3 types
57 * - Linear descriptor.
58 * - Linked list descriptor
59 * - Hybrid descriptor (Combination of both Linear and Linked list)
60 * Our driver will not support Hybrid type of descriptor.
62 * <b>Initialization & Configuration</b>
64 * The device driver enables higher layer software (e.g., an application) to
65 * communicate to the ZDMA core.
67 * XZDma_CfgInitialize() API is used to initialize the ZDMA core.
68 * The user needs to first call the XZDma_LookupConfig() API which returns
69 * the Configuration structure pointer which is passed as a parameter to the
70 * XZDma_CfgInitialize() API.
73 * The driver provides an interrupt handler XZDma_IntrHandler for handling
74 * the interrupt from the ZDMA core. The users of this driver have to
75 * register this handler with the interrupt system and provide the callback
76 * functions by using XZDma_SetCallBack API. In this version Descriptor done
79 * <b> Virtual Memory </b>
81 * This driver supports Virtual Memory. The RTOS is responsible for calculating
82 * the correct device base address in Virtual Memory space.
86 * This driver is not thread safe. Any needs for threads or thread mutual
87 * exclusion must be satisfied by the layer above this driver.
91 * Asserts are used within all Xilinx drivers to enforce constraints on argument
92 * values. Asserts can be turned off on a system-wide basis by defining, at
93 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
94 * is recommended that users leave asserts on during development.
96 * <b> Building the driver </b>
98 * The XZDma driver is composed of several source files. This allows the user
99 * to build and link only those parts of the driver that are necessary.
101 * This header file contains identifiers and register-level driver functions (or
102 * macros), range macros, structure typedefs that can be used to access the
103 * Xilinx ZDMA core instance.
106 * MODIFICATION HISTORY:
108 * Ver Who Date Changes
109 * ----- ------ -------- ------------------------------------------------------
110 * 1.0 vns 2/27/15 First release
111 * 1.1 vns 15/02/16 Corrected Destination descriptor addresss calculation
112 * in XZDma_CreateBDList API
113 * Modified XZDma_SetMode to return XST_FAILURE on
114 * selecting DMA mode other than normal mode in
115 * scatter gather mode data transfer and corrected
116 * XZDma_SetChDataConfig API to set over fetch and
117 * src issue parameters correctly.
118 * ms 03/17/17 Added readme.txt file in examples folder for doxygen
120 * ms 04/05/17 Modified comment lines notation in functions of zdma
121 * examples to avoid unnecessary description to get
122 * displayed while generating doxygen and also changed
123 * filename tag to include the readonly mode example file
125 * 1.3 mus 08/14/17 Update cache coherency information of the interface in
126 * its config structure.
127 * 1.4 adk 11/02/17 Updated examples to fix compilation errors for IAR
129 * 1.5 adk 11/22/17 Added peripheral test app support for ZDMA driver.
130 * 12/11/17 Fixed peripheral test app generation issues when dma
131 * buffers are configured on OCM memory(CR#990806).
134 ******************************************************************************/
142 /***************************** Include Files *********************************/
144 #include "xzdma_hw.h"
145 #include "xil_assert.h"
147 #include "xil_cache.h"
148 #include "bspconfig.h"
150 /************************** Constant Definitions *****************************/
153 /**************************** Type Definitions *******************************/
155 /** @name ZDMA Handler Types
159 XZDMA_HANDLER_DONE, /**< For Done Handler */
160 XZDMA_HANDLER_ERROR, /**< For Error Handler */
164 /** @name ZDMA Descriptors Types
168 XZDMA_LINEAR, /**< Linear descriptor */
169 XZDMA_LINKEDLIST, /**< Linked list descriptor */
173 /** @name ZDMA Operation modes
177 XZDMA_NORMAL_MODE, /**< Normal transfer from source to
179 XZDMA_WRONLY_MODE, /**< Write only mode */
180 XZDMA_RDONLY_MODE /**< Read only mode */
188 XZDMA_IDLE, /**< ZDMA is in Idle state */
189 XZDMA_PAUSE, /**< Paused state */
190 XZDMA_BUSY, /**< Busy state */
194 /** @name ZDMA AXI Burst type
198 XZDMA_FIXED_BURST = 0, /**< Fixed burst type */
199 XZDMA_INCR_BURST /**< Increment burst type */
203 /******************************************************************************/
205 * This typedef contains scatter gather descriptor fields for ZDMA core.
208 void *SrcDscrPtr; /**< Source Descriptor pointer */
209 void *DstDscrPtr; /**< Destination Descriptor pointer */
210 u32 DscrCount; /**< Count of descriptors available */
211 XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
212 * Linked list type */
215 /******************************************************************************/
217 * This typedef contains scatter gather descriptor fields for ZDMA core.
219 #if defined (__ICCARM__)
220 #pragma pack(push, 1)
223 u64 Address; /**< Address */
224 u32 Size; /**< Word2, Size of data */
225 u32 Cntl; /**< Word3 Control data */
226 u64 NextDscr; /**< Address of next descriptor */
227 u64 Reserved; /**< Reserved address */
228 #if defined (__ICCARM__)
232 } __attribute__ ((packed)) XZDma_LlDscr;
234 /******************************************************************************/
236 * This typedef contains Linear descriptor fields for ZDMA core.
238 #if defined (__ICCARM__)
239 #pragma pack(push, 1)
242 u64 Address; /**< Address */
243 u32 Size; /**< Word3, Size of data */
244 u32 Cntl; /**< Word4, control data */
245 #if defined (__ICCARM__)
249 } __attribute__ ((packed)) XZDma_LiDscr;
251 /******************************************************************************/
254 * This typedef contains the data configurations of ZDMA core
257 u8 OverFetch; /**< Enable Over fetch */
258 u8 SrcIssue; /**< Outstanding transactions for Source */
259 XZDma_BurstType SrcBurstType;
260 /**< Burst type for SRC */
261 u8 SrcBurstLen; /**< AXI length for data read */
262 XZDma_BurstType DstBurstType;
263 /**< Burst type for DST */
264 u8 DstBurstLen; /**< AXI length for data write */
265 u8 SrcCache; /**< AXI cache bits for data read */
266 u8 SrcQos; /**< AXI QOS bits for data read */
267 u8 DstCache; /**< AXI cache bits for data write */
268 u8 DstQos; /**< AXI QOS bits for data write */
271 /******************************************************************************/
274 * This typedef contains the descriptor configurations of ZDMA core
277 u8 AxCoherent; /**< AXI transactions are coherent or non-coherent */
278 u8 AXCache; /**< AXI cache for DSCR fetch */
279 u8 AXQos; /**< Qos bit for DSCR fetch */
282 /******************************************************************************/
284 * Callback type for Completion of all data transfers.
286 * @param CallBackRef is a callback reference passed in by the upper layer
287 * when setting the callback functions, and passed back to the
288 * upper layer when the callback is invoked.
289 *******************************************************************************/
290 typedef void (*XZDma_DoneHandler) (void *CallBackRef);
292 /******************************************************************************/
294 * Callback type for all error interrupts.
296 * @param CallBackRef is a callback reference passed in by the upper layer
297 * when setting the callback functions, and passed back to the
298 * upper layer when the callback is invoked.
299 * @param ErrorMask is a bit mask indicating the cause of the error. Its
300 * value equals 'OR'ing one or more XZDMA_IXR_* values defined in
302 ****************************************************************************/
303 typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
306 * This typedef contains configuration information for a ZDMA core
307 * Each ZDMA core should have a configuration structure associated.
310 u16 DeviceId; /**< Device Id of ZDMA */
311 u32 BaseAddress; /**< BaseAddress of ZDMA */
312 u8 DmaType; /**< Type of DMA */
313 u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not;
314 * Applicable only to A53 in EL1 NS mode */
317 /******************************************************************************/
320 * The XZDma driver instance data structure. A pointer to an instance data
321 * structure is passed around by functions to refer to a specific driver
325 XZDma_Config Config; /**< Hardware configuration */
326 u32 IsReady; /**< Device and the driver instance
328 u32 IntrMask; /**< Mask for enabling interrupts */
330 XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */
331 u8 IsSgDma; /**< Is ZDMA core is in scatter gather or
332 * not will be specified */
333 u32 Slcr_adma; /**< Used to hold SLCR ADMA register
335 XZDma_Descriptor Descriptor; /**< It contains information about
338 XZDma_DoneHandler DoneHandler; /**< Call back for transfer
340 void *DoneRef; /**< To be passed to the done
341 * interrupt callback */
343 XZDma_ErrorHandler ErrorHandler;/**< Call back for error
345 void *ErrorRef; /**< To be passed to the error
346 * interrupt callback */
347 XZDma_DataConfig DataConfig; /**< Current configurations */
348 XZDma_DscrConfig DscrConfig; /**< Current configurations */
349 XZDmaState ChannelState; /**< ZDMA channel is busy */
353 /******************************************************************************/
356 * This typedef contains the fields for transfer of data.
359 UINTPTR SrcAddr; /**< Source address */
360 UINTPTR DstAddr; /**< Destination Address */
361 u32 Size; /**< Size of the data to be transferred */
362 u8 SrcCoherent; /**< Source coherent */
363 u8 DstCoherent; /**< Destination coherent */
364 u8 Pause; /**< Will pause data transmission after
365 * this transfer only for SG mode */
368 /***************** Macros (Inline Functions) Definitions *********************/
370 /*****************************************************************************/
373 * This function returns interrupt status read from Interrupt Status Register.
374 * Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
377 * @param InstancePtr is a pointer to the XZDma instance.
379 * @return The pending interrupts of the ZDMA core.
380 * Use the masks specified in xzdma_hw.h to interpret
381 * the returned value.
384 * void XZDma_IntrGetStatus(XZDma *InstancePtr)
386 ******************************************************************************/
387 #define XZDma_IntrGetStatus(InstancePtr) \
388 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)
390 /*****************************************************************************/
393 * This function clears interrupt(s). Every bit set in Interrupt Status
394 * Register indicates that a specific type of interrupt is occurring, and this
395 * function clears one or more interrupts by writing a bit mask to Interrupt
398 * @param InstancePtr is a pointer to the XZDma instance.
399 * @param Mask is the type of the interrupts to enable. Use OR'ing of
400 * XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
401 * this parameter value.
407 * void XZDma_IntrClear(XZDma *InstancePtr)
409 ******************************************************************************/
410 #define XZDma_IntrClear(InstancePtr, Mask) \
411 XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
412 XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))
414 /*****************************************************************************/
417 * This function returns interrupt mask to know which interrupts are
418 * enabled and which of them were disabled.
420 * @param InstancePtr is a pointer to the XZDma instance.
422 * @return The current interrupt mask. The mask indicates which interrupts
423 * are enabled/disabled.
424 * 0 bit represents .....corresponding interrupt is enabled.
425 * 1 bit represents .....Corresponding interrupt is disabled.
429 * void XZDma_GetIntrMask(XZDma *InstancePtr)
431 ******************************************************************************/
432 #define XZDma_GetIntrMask(InstancePtr) \
433 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
434 (u32)(XZDMA_CH_IMR_OFFSET))
436 /*****************************************************************************/
439 * This function enables individual interrupts of the ZDMA core by updating
440 * the Interrupt Enable register.
442 * @param InstancePtr is a pointer to the XZDma instance.
443 * @param Mask is the type of the interrupts to enable. Use OR'ing of
444 * XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
445 * this parameter value.
449 * @note The existing enabled interrupt(s) will remain enabled.
451 * void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
453 ******************************************************************************/
454 #define XZDma_EnableIntr(InstancePtr, Mask) \
455 (InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))
457 /*****************************************************************************/
460 * This function disables individual interrupts of the ZDMA core by updating
461 * the Interrupt Disable register.
463 * @param InstancePtr is a pointer to the XZDma instance.
464 * @param Mask is the type of the interrupts to disable. Use OR'ing of
465 * XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
466 * this parameter value.
470 * @note The existing disabled interrupt(s) will remain disabled.
472 * void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
474 ******************************************************************************/
475 #define XZDma_DisableIntr(InstancePtr, Mask) \
476 XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
477 XZDMA_CH_IDS_OFFSET, \
478 ((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
479 XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))
481 /*****************************************************************************/
484 * This function returns source current payload address under process
487 * @param InstancePtr is a pointer to the XZDma instance.
491 * @note This address may not be precise due to ZDMA pipeline structure
493 * u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
495 ******************************************************************************/
496 #define XZDma_SrcCurPyld(InstancePtr) \
497 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
498 XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
499 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
500 XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
502 /*****************************************************************************/
505 * This function returns destination current payload address under process
508 * @param InstancePtr is a pointer to the XZDma instance.
512 * @note This address may not be precise due to ZDMA pipeline structure
514 * u64 XZDma_DstCurPyld(XZDma *InstancePtr)
516 ******************************************************************************/
517 #define XZDma_DstCurPyld(InstancePtr) \
518 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
519 XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
520 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
521 XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
523 /*****************************************************************************/
526 * This function returns source descriptor current payload address under
527 * process of ZDMA core.
529 * @param InstancePtr is a pointer to the XZDma instance.
533 * @note This address may not be precise due to ZDMA pipeline structure
535 * u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
537 ******************************************************************************/
538 #define XZDma_SrcDscrCurPyld(InstancePtr) \
539 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
540 XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
541 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
542 XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
545 /*****************************************************************************/
548 * This function returns destination descriptor current payload address under
549 * process of ZDMA core.
551 * @param InstancePtr is a pointer to the XZDma instance.
555 * @note This address may not be precise due to ZDMA pipeline structure
557 * u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
559 ******************************************************************************/
560 #define XZDma_DstDscrCurPyld(InstancePtr) \
561 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
562 XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
563 ((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
564 XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
566 /*****************************************************************************/
569 * This function gets the count of total bytes transferred through core
570 * since last clear in ZDMA core.
572 * @param InstancePtr is a pointer to the XZDma instance.
578 * void XZDma_GetTotalByte(XZDma *InstancePtr)
580 ******************************************************************************/
581 #define XZDma_GetTotalByte(InstancePtr) \
582 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
583 XZDMA_CH_TOTAL_BYTE_OFFSET)
585 /*****************************************************************************/
588 * This function clears the count of total bytes transferred in ZDMA core.
590 * @param InstancePtr is a pointer to the XZDma instance.
596 * void XZDma_TotalByteClear(XZDma *InstancePtr)
598 ******************************************************************************/
599 #define XZDma_TotalByteClear(InstancePtr) \
600 XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
601 XZDMA_CH_TOTAL_BYTE_OFFSET, \
602 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
603 XZDMA_CH_TOTAL_BYTE_OFFSET))
605 /*****************************************************************************/
608 * This function gets the total number of Interrupt count for source after last
611 * @param InstancePtr is a pointer to the XZDma instance.
615 * @note Once this API is called then count will become zero.
617 * void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
619 ******************************************************************************/
620 #define XZDma_GetSrcIntrCnt(InstancePtr) \
621 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
622 XZDMA_CH_IRQ_SRC_ACCT_OFFSET)
624 /*****************************************************************************/
627 * This function gets the total number of Interrupt count for destination
628 * after last call of this API.
630 * @param InstancePtr is a pointer to the XZDma instance.
634 * @note Once this API is called then count will become zero.
636 * void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
638 ******************************************************************************/
639 #define XZDma_GetDstIntrCnt(InstancePtr) \
640 XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
641 XZDMA_CH_IRQ_DST_ACCT_OFFSET)
643 /*****************************************************************************/
646 * This function Enable's the ZDMA core for initiating the data transfer once the
647 * data transfer completes it will be automatically disabled.
649 * @param InstancePtr is a pointer to the XZDma instance.
655 * void XZDma_EnableCh(XZDma *InstancePtr)
657 ******************************************************************************/
658 #define XZDma_EnableCh(InstancePtr) \
659 XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
660 (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))
662 /*****************************************************************************/
665 * This function Disable's the ZDMA core.
667 * @param InstancePtr is a pointer to the XZDma instance.
673 * void XZDma_DisableCh(XZDma *InstancePtr)
675 ******************************************************************************/
676 #define XZDma_DisableCh(InstancePtr) \
677 XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
678 (XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))
680 /************************ Prototypes of functions **************************/
682 XZDma_Config *XZDma_LookupConfig(u16 DeviceId);
684 s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
686 s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
687 u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
688 UINTPTR Dscr_MemPtr, u32 NoOfBytes);
689 s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
690 void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
691 s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
692 void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
693 s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
694 void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
695 void XZDma_Resume(XZDma *InstancePtr);
696 void XZDma_Reset(XZDma *InstancePtr);
697 XZDmaState XZDma_ChannelState(XZDma *InstancePtr);
699 s32 XZDma_SelfTest(XZDma *InstancePtr);
701 void XZDma_IntrHandler(void *Instance);
702 s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
703 void *CallBackFunc, void *CallBackRef);
712 #endif /* XZDMA_H_ */