1 #****************************************************************************
6 # This file is automatically generated
8 #****************************************************************************
9 set psu_pll_init_data {
11 # Register : RPLL_CFG @ 0XFF5E0034</p>
13 # PLL loop filter resistor control
14 # PSU_CRL_APB_RPLL_CFG_RES 0xc
16 # PLL charge pump control
17 # PSU_CRL_APB_RPLL_CFG_CP 0x3
19 # PLL loop filter high frequency capacitor control
20 # PSU_CRL_APB_RPLL_CFG_LFHF 0x3
22 # Lock circuit counter setting
23 # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339
25 # Lock circuit configuration settings for lock windowsize
26 # PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
28 # Helper data. Values are to be looked up in a table from Data Sheet
29 #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) */
30 mask_write 0XFF5E0034 0xFE7FEDEF 0x7E672C6C
32 # Register : RPLL_CTRL @ 0XFF5E0030</p>
34 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
35 # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
36 # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
37 # PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
39 # The integer portion of the feedback divider to the PLL
40 # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d
42 # This turns on the divide by 2 that is inside of the PLL. This does not c
43 # hange the VCO frequency, just the output frequency
44 # PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
47 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) */
48 mask_write 0XFF5E0030 0x00717F00 0x00012D00
50 # Register : RPLL_CTRL @ 0XFF5E0030</p>
52 # Bypasses the PLL clock. The usable clock will be determined from the POS
53 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
54 # clock and 4 cycles of the new clock. This is not usually an issue, but d
55 # esigners must be aware.)
56 # PSU_CRL_APB_RPLL_CTRL_BYPASS 1
59 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) */
60 mask_write 0XFF5E0030 0x00000008 0x00000008
62 # Register : RPLL_CTRL @ 0XFF5E0030</p>
64 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
66 # PSU_CRL_APB_RPLL_CTRL_RESET 1
69 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) */
70 mask_write 0XFF5E0030 0x00000001 0x00000001
72 # Register : RPLL_CTRL @ 0XFF5E0030</p>
74 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
76 # PSU_CRL_APB_RPLL_CTRL_RESET 0
79 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) */
80 mask_write 0XFF5E0030 0x00000001 0x00000000
82 # Register : PLL_STATUS @ 0XFF5E0040</p>
85 # PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
86 mask_poll 0XFF5E0040 0x00000002
87 # : REMOVE PLL BY PASS
88 # Register : RPLL_CTRL @ 0XFF5E0030</p>
90 # Bypasses the PLL clock. The usable clock will be determined from the POS
91 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
92 # clock and 4 cycles of the new clock. This is not usually an issue, but d
93 # esigners must be aware.)
94 # PSU_CRL_APB_RPLL_CTRL_BYPASS 0
97 #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) */
98 mask_write 0XFF5E0030 0x00000008 0x00000000
99 # Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
101 # Divisor value for this clock.
102 # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
104 # Control for a clock that will be generated in the LPD, but used in the F
105 # PD as a clock source for the peripheral clock muxes.
106 #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) */
107 mask_write 0XFF5E0048 0x00003F00 0x00000200
110 # Register : IOPLL_CFG @ 0XFF5E0024</p>
112 # PLL loop filter resistor control
113 # PSU_CRL_APB_IOPLL_CFG_RES 0x2
115 # PLL charge pump control
116 # PSU_CRL_APB_IOPLL_CFG_CP 0x4
118 # PLL loop filter high frequency capacitor control
119 # PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
121 # Lock circuit counter setting
122 # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258
124 # Lock circuit configuration settings for lock windowsize
125 # PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
127 # Helper data. Values are to be looked up in a table from Data Sheet
128 #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) */
129 mask_write 0XFF5E0024 0xFE7FEDEF 0x7E4B0C82
131 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
133 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
134 # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
135 # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
136 # PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
138 # The integer portion of the feedback divider to the PLL
139 # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a
141 # This turns on the divide by 2 that is inside of the PLL. This does not c
142 # hange the VCO frequency, just the output frequency
143 # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1
146 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) */
147 mask_write 0XFF5E0020 0x00717F00 0x00015A00
149 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
151 # Bypasses the PLL clock. The usable clock will be determined from the POS
152 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
153 # clock and 4 cycles of the new clock. This is not usually an issue, but d
154 # esigners must be aware.)
155 # PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
158 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) */
159 mask_write 0XFF5E0020 0x00000008 0x00000008
161 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
163 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
165 # PSU_CRL_APB_IOPLL_CTRL_RESET 1
168 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) */
169 mask_write 0XFF5E0020 0x00000001 0x00000001
171 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
173 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
175 # PSU_CRL_APB_IOPLL_CTRL_RESET 0
178 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) */
179 mask_write 0XFF5E0020 0x00000001 0x00000000
181 # Register : PLL_STATUS @ 0XFF5E0040</p>
184 # PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
185 mask_poll 0XFF5E0040 0x00000001
186 # : REMOVE PLL BY PASS
187 # Register : IOPLL_CTRL @ 0XFF5E0020</p>
189 # Bypasses the PLL clock. The usable clock will be determined from the POS
190 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
191 # clock and 4 cycles of the new clock. This is not usually an issue, but d
192 # esigners must be aware.)
193 # PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
196 #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) */
197 mask_write 0XFF5E0020 0x00000008 0x00000000
198 # Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
200 # Divisor value for this clock.
201 # PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
203 # Control for a clock that will be generated in the LPD, but used in the F
204 # PD as a clock source for the peripheral clock muxes.
205 #(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */
206 mask_write 0XFF5E0044 0x00003F00 0x00000300
209 # Register : APLL_CFG @ 0XFD1A0024</p>
211 # PLL loop filter resistor control
212 # PSU_CRF_APB_APLL_CFG_RES 0x2
214 # PLL charge pump control
215 # PSU_CRF_APB_APLL_CFG_CP 0x3
217 # PLL loop filter high frequency capacitor control
218 # PSU_CRF_APB_APLL_CFG_LFHF 0x3
220 # Lock circuit counter setting
221 # PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
223 # Lock circuit configuration settings for lock windowsize
224 # PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
226 # Helper data. Values are to be looked up in a table from Data Sheet
227 #(OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) */
228 mask_write 0XFD1A0024 0xFE7FEDEF 0x7E4B0C62
230 # Register : APLL_CTRL @ 0XFD1A0020</p>
232 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
233 # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
234 # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
235 # PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
237 # The integer portion of the feedback divider to the PLL
238 # PSU_CRF_APB_APLL_CTRL_FBDIV 0x48
240 # This turns on the divide by 2 that is inside of the PLL. This does not c
241 # hange the VCO frequency, just the output frequency
242 # PSU_CRF_APB_APLL_CTRL_DIV2 0x1
245 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) */
246 mask_write 0XFD1A0020 0x00717F00 0x00014800
248 # Register : APLL_CTRL @ 0XFD1A0020</p>
250 # Bypasses the PLL clock. The usable clock will be determined from the POS
251 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
252 # clock and 4 cycles of the new clock. This is not usually an issue, but d
253 # esigners must be aware.)
254 # PSU_CRF_APB_APLL_CTRL_BYPASS 1
257 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) */
258 mask_write 0XFD1A0020 0x00000008 0x00000008
260 # Register : APLL_CTRL @ 0XFD1A0020</p>
262 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
264 # PSU_CRF_APB_APLL_CTRL_RESET 1
267 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) */
268 mask_write 0XFD1A0020 0x00000001 0x00000001
270 # Register : APLL_CTRL @ 0XFD1A0020</p>
272 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
274 # PSU_CRF_APB_APLL_CTRL_RESET 0
277 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) */
278 mask_write 0XFD1A0020 0x00000001 0x00000000
280 # Register : PLL_STATUS @ 0XFD1A0044</p>
283 # PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
284 mask_poll 0XFD1A0044 0x00000001
285 # : REMOVE PLL BY PASS
286 # Register : APLL_CTRL @ 0XFD1A0020</p>
288 # Bypasses the PLL clock. The usable clock will be determined from the POS
289 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
290 # clock and 4 cycles of the new clock. This is not usually an issue, but d
291 # esigners must be aware.)
292 # PSU_CRF_APB_APLL_CTRL_BYPASS 0
295 #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) */
296 mask_write 0XFD1A0020 0x00000008 0x00000000
297 # Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
299 # Divisor value for this clock.
300 # PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
302 # Control for a clock that will be generated in the FPD, but used in the L
303 # PD as a clock source for the peripheral clock muxes.
304 #(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */
305 mask_write 0XFD1A0048 0x00003F00 0x00000300
308 # Register : DPLL_CFG @ 0XFD1A0030</p>
310 # PLL loop filter resistor control
311 # PSU_CRF_APB_DPLL_CFG_RES 0x2
313 # PLL charge pump control
314 # PSU_CRF_APB_DPLL_CFG_CP 0x3
316 # PLL loop filter high frequency capacitor control
317 # PSU_CRF_APB_DPLL_CFG_LFHF 0x3
319 # Lock circuit counter setting
320 # PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
322 # Lock circuit configuration settings for lock windowsize
323 # PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
325 # Helper data. Values are to be looked up in a table from Data Sheet
326 #(OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) */
327 mask_write 0XFD1A0030 0xFE7FEDEF 0x7E4B0C62
329 # Register : DPLL_CTRL @ 0XFD1A002C</p>
331 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
332 # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
333 # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
334 # PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
336 # The integer portion of the feedback divider to the PLL
337 # PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
339 # This turns on the divide by 2 that is inside of the PLL. This does not c
340 # hange the VCO frequency, just the output frequency
341 # PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
344 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) */
345 mask_write 0XFD1A002C 0x00717F00 0x00014000
347 # Register : DPLL_CTRL @ 0XFD1A002C</p>
349 # Bypasses the PLL clock. The usable clock will be determined from the POS
350 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
351 # clock and 4 cycles of the new clock. This is not usually an issue, but d
352 # esigners must be aware.)
353 # PSU_CRF_APB_DPLL_CTRL_BYPASS 1
356 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) */
357 mask_write 0XFD1A002C 0x00000008 0x00000008
359 # Register : DPLL_CTRL @ 0XFD1A002C</p>
361 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
363 # PSU_CRF_APB_DPLL_CTRL_RESET 1
366 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) */
367 mask_write 0XFD1A002C 0x00000001 0x00000001
369 # Register : DPLL_CTRL @ 0XFD1A002C</p>
371 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
373 # PSU_CRF_APB_DPLL_CTRL_RESET 0
376 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) */
377 mask_write 0XFD1A002C 0x00000001 0x00000000
379 # Register : PLL_STATUS @ 0XFD1A0044</p>
382 # PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
383 mask_poll 0XFD1A0044 0x00000002
384 # : REMOVE PLL BY PASS
385 # Register : DPLL_CTRL @ 0XFD1A002C</p>
387 # Bypasses the PLL clock. The usable clock will be determined from the POS
388 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
389 # clock and 4 cycles of the new clock. This is not usually an issue, but d
390 # esigners must be aware.)
391 # PSU_CRF_APB_DPLL_CTRL_BYPASS 0
394 #(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) */
395 mask_write 0XFD1A002C 0x00000008 0x00000000
396 # Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
398 # Divisor value for this clock.
399 # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2
401 # Control for a clock that will be generated in the FPD, but used in the L
402 # PD as a clock source for the peripheral clock muxes.
403 #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) */
404 mask_write 0XFD1A004C 0x00003F00 0x00000200
407 # Register : VPLL_CFG @ 0XFD1A003C</p>
409 # PLL loop filter resistor control
410 # PSU_CRF_APB_VPLL_CFG_RES 0x2
412 # PLL charge pump control
413 # PSU_CRF_APB_VPLL_CFG_CP 0x4
415 # PLL loop filter high frequency capacitor control
416 # PSU_CRF_APB_VPLL_CFG_LFHF 0x3
418 # Lock circuit counter setting
419 # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258
421 # Lock circuit configuration settings for lock windowsize
422 # PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
424 # Helper data. Values are to be looked up in a table from Data Sheet
425 #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) */
426 mask_write 0XFD1A003C 0xFE7FEDEF 0x7E4B0C82
428 # Register : VPLL_CTRL @ 0XFD1A0038</p>
430 # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
431 # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
432 # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
433 # PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
435 # The integer portion of the feedback divider to the PLL
436 # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a
438 # This turns on the divide by 2 that is inside of the PLL. This does not c
439 # hange the VCO frequency, just the output frequency
440 # PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
443 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) */
444 mask_write 0XFD1A0038 0x00717F00 0x00015A00
446 # Register : VPLL_CTRL @ 0XFD1A0038</p>
448 # Bypasses the PLL clock. The usable clock will be determined from the POS
449 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
450 # clock and 4 cycles of the new clock. This is not usually an issue, but d
451 # esigners must be aware.)
452 # PSU_CRF_APB_VPLL_CTRL_BYPASS 1
455 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) */
456 mask_write 0XFD1A0038 0x00000008 0x00000008
458 # Register : VPLL_CTRL @ 0XFD1A0038</p>
460 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
462 # PSU_CRF_APB_VPLL_CTRL_RESET 1
465 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) */
466 mask_write 0XFD1A0038 0x00000001 0x00000001
468 # Register : VPLL_CTRL @ 0XFD1A0038</p>
470 # Asserts Reset to the PLL. When asserting reset, the PLL must already be
472 # PSU_CRF_APB_VPLL_CTRL_RESET 0
475 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) */
476 mask_write 0XFD1A0038 0x00000001 0x00000000
478 # Register : PLL_STATUS @ 0XFD1A0044</p>
481 # PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
482 mask_poll 0XFD1A0044 0x00000004
483 # : REMOVE PLL BY PASS
484 # Register : VPLL_CTRL @ 0XFD1A0038</p>
486 # Bypasses the PLL clock. The usable clock will be determined from the POS
487 # T_SRC field. (This signal may only be toggled after 4 cycles of the old
488 # clock and 4 cycles of the new clock. This is not usually an issue, but d
489 # esigners must be aware.)
490 # PSU_CRF_APB_VPLL_CTRL_BYPASS 0
493 #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) */
494 mask_write 0XFD1A0038 0x00000008 0x00000000
495 # Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
497 # Divisor value for this clock.
498 # PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
500 # Control for a clock that will be generated in the FPD, but used in the L
501 # PD as a clock source for the peripheral clock muxes.
502 #(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */
503 mask_write 0XFD1A0050 0x00003F00 0x00000300
507 set psu_clock_init_data {
508 # : CLOCK CONTROL SLCR REGISTER
509 # Register : GEM3_REF_CTRL @ 0XFF5E005C</p>
511 # Clock active for the RX channel
512 # PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1
514 # Clock active signal. Switch to 0 to disable the clock
515 # PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1
518 # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
521 # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
523 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
524 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
525 # usually an issue, but designers must be aware.)
526 # PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
528 # This register controls this reference clock
529 #(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */
530 mask_write 0XFF5E005C 0x063F3F07 0x06010C00
531 # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100</p>
534 # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
536 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
537 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
538 # usually an issue, but designers must be aware.)
539 # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0
542 # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
544 # Clock active signal. Switch to 0 to disable the clock
545 # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
547 # This register controls this reference clock
548 #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) */
549 mask_write 0XFF5E0100 0x013F3F07 0x01010600
550 # Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
552 # Clock active signal. Switch to 0 to disable the clock
553 # PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
556 # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
559 # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
561 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
562 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
563 # usually an issue, but designers must be aware.)
564 # PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
566 # This register controls this reference clock
567 #(OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) */
568 mask_write 0XFF5E0060 0x023F3F07 0x02010600
569 # Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
571 # Clock active signal. Switch to 0 to disable the clock
572 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
575 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3
578 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19
580 # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
581 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
582 # usually an issue, but designers must be aware.)
583 # PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
585 # This register controls this reference clock
586 #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) */
587 mask_write 0XFF5E004C 0x023F3F07 0x02031900
588 # Register : QSPI_REF_CTRL @ 0XFF5E0068</p>
590 # Clock active signal. Switch to 0 to disable the clock
591 # PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1
594 # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
597 # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
599 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
600 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
601 # usually an issue, but designers must be aware.)
602 # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
604 # This register controls this reference clock
605 #(OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) */
606 mask_write 0XFF5E0068 0x013F3F07 0x01010C00
607 # Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
609 # Clock active signal. Switch to 0 to disable the clock
610 # PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
613 # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
616 # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
618 # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
619 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
620 # usually an issue, but designers must be aware.)
621 # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
623 # This register controls this reference clock
624 #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) */
625 mask_write 0XFF5E0070 0x013F3F07 0x01010800
626 # Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
628 # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
630 # PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
632 # SoC Debug Clock Control
633 #(OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) */
634 mask_write 0XFF18030C 0x00020000 0x00000000
635 # Register : UART0_REF_CTRL @ 0XFF5E0074</p>
637 # Clock active signal. Switch to 0 to disable the clock
638 # PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
641 # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
644 # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
646 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
647 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
648 # usually an issue, but designers must be aware.)
649 # PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
651 # This register controls this reference clock
652 #(OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) */
653 mask_write 0XFF5E0074 0x013F3F07 0x01010F00
654 # Register : UART1_REF_CTRL @ 0XFF5E0078</p>
656 # Clock active signal. Switch to 0 to disable the clock
657 # PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
660 # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
663 # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
665 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
666 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
667 # usually an issue, but designers must be aware.)
668 # PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
670 # This register controls this reference clock
671 #(OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) */
672 mask_write 0XFF5E0078 0x013F3F07 0x01010F00
673 # Register : I2C0_REF_CTRL @ 0XFF5E0120</p>
675 # Clock active signal. Switch to 0 to disable the clock
676 # PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1
679 # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
682 # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
684 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
685 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
686 # usually an issue, but designers must be aware.)
687 # PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
689 # This register controls this reference clock
690 #(OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) */
691 mask_write 0XFF5E0120 0x013F3F07 0x01010F00
692 # Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
694 # Clock active signal. Switch to 0 to disable the clock
695 # PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
698 # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
701 # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
703 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
704 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
705 # usually an issue, but designers must be aware.)
706 # PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
708 # This register controls this reference clock
709 #(OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) */
710 mask_write 0XFF5E0124 0x013F3F07 0x01010F00
711 # Register : CAN1_REF_CTRL @ 0XFF5E0088</p>
713 # Clock active signal. Switch to 0 to disable the clock
714 # PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
717 # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
720 # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
722 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
723 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
724 # usually an issue, but designers must be aware.)
725 # PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
727 # This register controls this reference clock
728 #(OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) */
729 mask_write 0XFF5E0088 0x013F3F07 0x01010F00
730 # Register : CPU_R5_CTRL @ 0XFF5E0090</p>
732 # Turing this off will shut down the OCM, some parts of the APM, and preve
733 # nt transactions going from the FPD to the LPD and could lead to system h
735 # PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
738 # PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
740 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
741 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
742 # usually an issue, but designers must be aware.)
743 # PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
745 # This register controls this reference clock
746 #(OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) */
747 mask_write 0XFF5E0090 0x01003F07 0x01000302
748 # Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
750 # Clock active signal. Switch to 0 to disable the clock
751 # PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
754 # PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
756 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
757 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
758 # usually an issue, but designers must be aware.)
759 # PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
761 # This register controls this reference clock
762 #(OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) */
763 mask_write 0XFF5E009C 0x01003F07 0x01000602
764 # Register : PCAP_CTRL @ 0XFF5E00A4</p>
766 # Clock active signal. Switch to 0 to disable the clock
767 # PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
770 # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
772 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
773 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
774 # usually an issue, but designers must be aware.)
775 # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
777 # This register controls this reference clock
778 #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) */
779 mask_write 0XFF5E00A4 0x01003F07 0x01000800
780 # Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
782 # Clock active signal. Switch to 0 to disable the clock
783 # PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
786 # PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
788 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
789 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
790 # usually an issue, but designers must be aware.)
791 # PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
793 # This register controls this reference clock
794 #(OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) */
795 mask_write 0XFF5E00A8 0x01003F07 0x01000302
796 # Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
798 # Clock active signal. Switch to 0 to disable the clock
799 # PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
802 # PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
804 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
805 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
806 # usually an issue, but designers must be aware.)
807 # PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
809 # This register controls this reference clock
810 #(OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) */
811 mask_write 0XFF5E00AC 0x01003F07 0x01000F02
812 # Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
814 # Clock active signal. Switch to 0 to disable the clock
815 # PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
818 # PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
820 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
821 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
822 # usually an issue, but designers must be aware.)
823 # PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
825 # This register controls this reference clock
826 #(OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) */
827 mask_write 0XFF5E00B0 0x01003F07 0x01000602
828 # Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
830 # Clock active signal. Switch to 0 to disable the clock
831 # PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
834 # PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
836 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
837 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
838 # usually an issue, but designers must be aware.)
839 # PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
841 # This register controls this reference clock
842 #(OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) */
843 mask_write 0XFF5E00B8 0x01003F07 0x01000302
844 # Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
846 # Clock active signal. Switch to 0 to disable the clock
847 # PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
850 # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
853 # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
855 # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
856 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
857 # usually an issue, but designers must be aware.)
858 # PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
860 # This register controls this reference clock
861 #(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) */
862 mask_write 0XFF5E00C0 0x013F3F07 0x01010F00
863 # Register : AMS_REF_CTRL @ 0XFF5E0108</p>
866 # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
869 # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e
871 # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
872 # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
873 # usually an issue, but designers must be aware.)
874 # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
876 # Clock active signal. Switch to 0 to disable the clock
877 # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
879 # This register controls this reference clock
880 #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) */
881 mask_write 0XFF5E0108 0x013F3F07 0x01011E02
882 # Register : DLL_REF_CTRL @ 0XFF5E0104</p>
884 # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
885 # of the old clock and 4 cycles of the new clock. This is not usually an
886 # issue, but designers must be aware.)
887 # PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
889 # This register controls this reference clock
890 #(OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) */
891 mask_write 0XFF5E0104 0x00000007 0x00000000
892 # Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
895 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
897 # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
898 # only be toggled after 4 cycles of the old clock and 4 cycles of the new
899 # clock. This is not usually an issue, but designers must be aware.)
900 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
902 # Clock active signal. Switch to 0 to disable the clock
903 # PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
905 # This register controls this reference clock
906 #(OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) */
907 mask_write 0XFF5E0128 0x01003F07 0x01000F00
908 # Register : SATA_REF_CTRL @ 0XFD1A00A0</p>
910 # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
911 # gled after 4 cycles of the old clock and 4 cycles of the new clock. This
912 # is not usually an issue, but designers must be aware.)
913 # PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0
915 # Clock active signal. Switch to 0 to disable the clock
916 # PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1
919 # PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2
921 # This register controls this reference clock
922 #(OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) */
923 mask_write 0XFD1A00A0 0x01003F07 0x01000200
924 # Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>
926 # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
927 # be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
928 # k. This is not usually an issue, but designers must be aware.)
929 # PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
931 # Clock active signal. Switch to 0 to disable the clock
932 # PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
935 # PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
937 # This register controls this reference clock
938 #(OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) */
939 mask_write 0XFD1A00B4 0x01003F07 0x01000200
940 # Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
943 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
946 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5
948 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
949 # his signal may only be toggled after 4 cycles of the old clock and 4 cyc
950 # les of the new clock. This is not usually an issue, but designers must b
952 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0
954 # Clock active signal. Switch to 0 to disable the clock
955 # PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
957 # This register controls this reference clock
958 #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) */
959 mask_write 0XFD1A0070 0x013F3F07 0x01010500
960 # Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
963 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
966 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf
968 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
969 # his signal may only be toggled after 4 cycles of the old clock and 4 cyc
970 # les of the new clock. This is not usually an issue, but designers must b
972 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3
974 # Clock active signal. Switch to 0 to disable the clock
975 # PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1
977 # This register controls this reference clock
978 #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) */
979 mask_write 0XFD1A0074 0x013F3F07 0x01010F03
980 # Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>
983 # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1
986 # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe
988 # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
989 # led after 4 cycles of the old clock and 4 cycles of the new clock. This
990 # is not usually an issue, but designers must be aware.)
991 # PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3
993 # Clock active signal. Switch to 0 to disable the clock
994 # PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1
996 # This register controls this reference clock
997 #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) */
998 mask_write 0XFD1A007C 0x013F3F07 0x01010E03
999 # Register : ACPU_CTRL @ 0XFD1A0060</p>
1002 # PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1
1004 # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
1005 # er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1006 # usually an issue, but designers must be aware.)
1007 # PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0
1009 # Clock active signal. Switch to 0 to disable the clock. For the half spee
1011 # PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1
1013 # Clock active signal. Switch to 0 to disable the clock. For the full spee
1014 # d ACPUX Clock. This will shut off the high speed clock to the entire APU
1015 # PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1
1017 # This register controls this reference clock
1018 #(OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) */
1019 mask_write 0XFD1A0060 0x03003F07 0x03000100
1020 # Register : DBG_FPD_CTRL @ 0XFD1A0068</p>
1023 # PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2
1025 # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1026 # gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1027 # is not usually an issue, but designers must be aware.)
1028 # PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0
1030 # Clock active signal. Switch to 0 to disable the clock
1031 # PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1
1033 # This register controls this reference clock
1034 #(OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) */
1035 mask_write 0XFD1A0068 0x01003F07 0x01000200
1036 # Register : DDR_CTRL @ 0XFD1A0080</p>
1039 # PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2
1041 # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
1042 # of the old clock and 4 cycles of the new clock. This is not usually an i
1043 # ssue, but designers must be aware.)
1044 # PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0
1046 # This register controls this reference clock
1047 #(OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) */
1048 mask_write 0XFD1A0080 0x00003F07 0x00000200
1049 # Register : GPU_REF_CTRL @ 0XFD1A0084</p>
1052 # PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1
1054 # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
1055 # gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1056 # is not usually an issue, but designers must be aware.)
1057 # PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0
1059 # Clock active signal. Switch to 0 to disable the clock, which will stop c
1060 # lock for GPU (and both Pixel Processors).
1061 # PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1
1063 # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1064 # k only to this Pixel Processor
1065 # PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1
1067 # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
1068 # k only to this Pixel Processor
1069 # PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1
1071 # This register controls this reference clock
1072 #(OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) */
1073 mask_write 0XFD1A0084 0x07003F07 0x07000100
1074 # Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>
1077 # PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2
1079 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1080 # er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1081 # usually an issue, but designers must be aware.)
1082 # PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0
1084 # Clock active signal. Switch to 0 to disable the clock
1085 # PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1
1087 # This register controls this reference clock
1088 #(OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) */
1089 mask_write 0XFD1A00B8 0x01003F07 0x01000200
1090 # Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>
1093 # PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2
1095 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1096 # er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1097 # usually an issue, but designers must be aware.)
1098 # PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0
1100 # Clock active signal. Switch to 0 to disable the clock
1101 # PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1
1103 # This register controls this reference clock
1104 #(OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) */
1105 mask_write 0XFD1A00BC 0x01003F07 0x01000200
1106 # Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>
1109 # PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2
1111 # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
1112 # er 4 cycles of the old clock and 4 cycles of the new clock. This is not
1113 # usually an issue, but designers must be aware.)
1114 # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3
1116 # Clock active signal. Switch to 0 to disable the clock
1117 # PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1
1119 # This register controls this reference clock
1120 #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) */
1121 mask_write 0XFD1A00C0 0x01003F07 0x01000203
1122 # Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>
1125 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5
1127 # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
1128 # gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1129 # is not usually an issue, but designers must be aware.)
1130 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2
1132 # Clock active signal. Switch to 0 to disable the clock
1133 # PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1
1135 # This register controls this reference clock
1136 #(OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) */
1137 mask_write 0XFD1A00C4 0x01003F07 0x01000502
1138 # Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>
1141 # PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2
1143 # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
1144 # gled after 4 cycles of the old clock and 4 cycles of the new clock. This
1145 # is not usually an issue, but designers must be aware.)
1146 # PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0
1148 # This register controls this reference clock
1149 #(OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) */
1150 mask_write 0XFD1A00F8 0x00003F07 0x00000200
1151 # Register : IOU_TTC_APB_CLK @ 0XFF180380</p>
1153 # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
1154 # lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
1155 # clock for the APB interface of TTC0
1156 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0
1158 # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
1159 # lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
1160 # clock for the APB interface of TTC1
1161 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0
1163 # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
1164 # lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
1165 # clock for the APB interface of TTC2
1166 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0
1168 # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
1169 # lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
1170 # clock for the APB interface of TTC3
1171 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0
1173 # TTC APB clock select
1174 #(OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) */
1175 mask_write 0XFF180380 0x000000FF 0x00000000
1176 # Register : WDT_CLK_SEL @ 0XFD610100</p>
1178 # System watchdog timer clock source selection: 0: Internal APB clock 1: E
1179 # xternal (PL clock via EMIO or Pinout clock via MIO)
1180 # PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0
1182 # SWDT clock source select
1183 #(OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) */
1184 mask_write 0XFD610100 0x00000001 0x00000000
1185 # Register : WDT_CLK_SEL @ 0XFF180300</p>
1187 # System watchdog timer clock source selection: 0: internal clock APB cloc
1188 # k 1: external clock from PL via EMIO, or from pinout via MIO
1189 # PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0
1191 # SWDT clock source select
1192 #(OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) */
1193 mask_write 0XFF180300 0x00000001 0x00000000
1194 # Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050</p>
1196 # System watchdog timer clock source selection: 0: internal clock APB cloc
1197 # k 1: external clock pss_ref_clk
1198 # PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0
1200 # SWDT clock source select
1201 #(OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) */
1202 mask_write 0XFF410050 0x00000001 0x00000000
1205 set psu_ddr_init_data {
1206 # : DDR INITIALIZATION
1207 # : DDR CONTROLLER RESET
1208 # Register : RST_DDR_SS @ 0XFD1A0108</p>
1210 # DDR block level reset inside of the DDR Sub System
1211 # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1
1213 # DDR sub system block level reset
1214 #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) */
1215 mask_write 0XFD1A0108 0x00000008 0x00000008
1216 # Register : MSTR @ 0XFD070000</p>
1218 # Indicates the configuration of the device used in the system. - 00 - x4
1219 # device - 01 - x8 device - 10 - x16 device - 11 - x32 device
1220 # PSU_DDRC_MSTR_DEVICE_CONFIG 0x1
1222 # Choose which registers are used. - 0 - Original registers - 1 - Shadow r
1224 # PSU_DDRC_MSTR_FREQUENCY_MODE 0x0
1226 # Only present for multi-rank configurations. Each bit represents one rank
1227 # . For two-rank configurations, only bits[25:24] are present. - 1 - popul
1228 # ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
1229 # ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
1230 # Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
1231 # k - 0011 - Two ranks - 1111 - Four ranks
1232 # PSU_DDRC_MSTR_ACTIVE_RANKS 0x1
1234 # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
1235 # mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
1236 # st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
1237 # values are reserved. This controls the burst size used to access the SDR
1238 # AM. This must match the burst length mode register setting in the SDRAM.
1239 # (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
1240 # Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
1241 # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
1242 # PSU_DDRC_MSTR_BURST_RDWR 0x4
1244 # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
1245 # frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
1246 # normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
1247 # TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
1248 # s bit must be set to '0'.
1249 # PSU_DDRC_MSTR_DLL_OFF_MODE 0x0
1251 # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
1252 # DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
1253 # DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
1254 # only supported when the SDRAM bus width is a multiple of 16, and quarter
1255 # bus width mode is only supported when the SDRAM bus width is a multiple
1256 # of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
1257 # th refers to DQ bus width (excluding any ECC width).
1258 # PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0
1260 # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
1261 # RAM in normal mode (1N). This register can be changed, only when the Con
1262 # troller is in self-refresh mode. This signal must be set the same value
1263 # as MR3 bit A3. Note: Geardown mode is not supported if the configuration
1264 # parameter MEMC_CMD_RTN2IDLE is set
1265 # PSU_DDRC_MSTR_GEARDOWN_MODE 0x0
1267 # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
1268 # g, all command signals (except chip select) are held for 2 clocks on the
1269 # SDRAM bus. Chip select is asserted on the second cycle of the command N
1270 # ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
1271 # ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
1272 # s set Note: 2T timing is not supported in DDR4 geardown mode.
1273 # PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0
1275 # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
1276 # sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
1277 # bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
1278 # cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
1279 # disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
1280 # ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
1281 # , and this bit must be set to '0'
1282 # PSU_DDRC_MSTR_BURSTCHOP 0x0
1284 # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
1285 # evice in use Present only in designs configured to support LPDDR4.
1286 # PSU_DDRC_MSTR_LPDDR4 0x0
1288 # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
1289 # in use Present only in designs configured to support DDR4.
1290 # PSU_DDRC_MSTR_DDR4 0x1
1292 # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
1293 # evice in use Present only in designs configured to support LPDDR3.
1294 # PSU_DDRC_MSTR_LPDDR3 0x0
1296 # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
1297 # evice in use Present only in designs configured to support LPDDR2.
1298 # PSU_DDRC_MSTR_LPDDR2 0x0
1300 # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
1301 # vice in use Only present in designs that support DDR3.
1302 # PSU_DDRC_MSTR_DDR3 0x0
1305 #(OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) */
1306 mask_write 0XFD070000 0xE30FBE3D 0x41040010
1307 # Register : MRCTRL0 @ 0XFD070010</p>
1309 # Setting this register bit to 1 triggers a mode register read or write op
1310 # eration. When the MR operation is complete, the uMCTL2 automatically cle
1311 # ars this bit. The other register fields of this register must be written
1312 # in a separate APB transaction, before setting this mr_wr bit. It is rec
1313 # ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
1315 # PSU_DDRC_MRCTRL0_MR_WR 0x0
1317 # Address of the mode register that is to be written to. - 0000 - MR0 - 00
1318 # 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
1319 # 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
1320 # for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
1321 # o used for writing to control words of RDIMMs. In that case, it correspo
1322 # nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
1323 # 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
1324 # s the bit[2:0] must be set to an appropriate value which is considered b
1325 # oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
1327 # PSU_DDRC_MRCTRL0_MR_ADDR 0x0
1329 # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
1330 # d to access all ranks, so all bits should be set to 1. However, for mult
1331 # i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
1332 # ary to access ranks individually. Examples (assume uMCTL2 is configured
1333 # for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
1334 # 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
1336 # PSU_DDRC_MRCTRL0_MR_RANK 0x3
1338 # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
1339 # efore automatic SDRAM initialization routine or not. For DDR4, this bit
1340 # can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
1341 # ialization. For LPDDR4, this bit can be used to program additional mode
1342 # registers before automatic SDRAM initialization if necessary. Note: This
1343 # must be cleared to 0 after completing Software operation. Otherwise, SD
1344 # RAM initialization routine will not re-start. - 0 - Software interventio
1345 # n is not allowed - 1 - Software intervention is allowed
1346 # PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0
1348 # Indicates whether the mode register operation is MRS in PDA mode or not
1349 # - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
1350 # PSU_DDRC_MRCTRL0_PDA_EN 0x0
1352 # Indicates whether the mode register operation is MRS or WR/RD for MPR (o
1353 # nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
1354 # PSU_DDRC_MRCTRL0_MPR_EN 0x0
1356 # Indicates whether the mode register operation is read or write. Only use
1357 # d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
1358 # PSU_DDRC_MRCTRL0_MR_TYPE 0x0
1360 # Mode Register Read/Write Control Register 0. Note: Do not enable more th
1361 # an one of the following fields simultaneously: - sw_init_int - pda_en -
1363 #(OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) */
1364 mask_write 0XFD070010 0x8000F03F 0x00000030
1365 # Register : DERATEEN @ 0XFD070020</p>
1367 # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
1368 # es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
1369 # esigns configured to support LPDDR4. The required number of cycles for d
1370 # erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
1371 # eriod, and rounding up the next integer.
1372 # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2
1374 # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
1375 # LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
1376 # ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
1377 # PSU_DDRC_DERATEEN_DERATE_BYTE 0x0
1379 # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
1380 # y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
1381 # LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
1382 # ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
1383 # 75 ns is less than a core_ddrc_core_clk period or not.
1384 # PSU_DDRC_DERATEEN_DERATE_VALUE 0x0
1386 # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
1387 # g parameter derating is enabled using MR4 read value. Present only in de
1388 # signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
1389 # to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
1390 # PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0
1392 # Temperature Derate Enable Register
1393 #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) */
1394 mask_write 0XFD070020 0x000003F3 0x00000200
1395 # Register : DERATEINT @ 0XFD070024</p>
1397 # Interval between two MR4 reads, used to derate the timing parameters. Pr
1398 # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
1399 # egister must not be set to zero
1400 # PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000
1402 # Temperature Derate Interval Register
1403 #(OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) */
1404 mask_write 0XFD070024 0xFFFFFFFF 0x00800000
1405 # Register : PWRCTL @ 0XFD070030</p>
1407 # Self refresh state is an intermediate state to enter to Self refresh pow
1408 # er down state or exit Self refresh power down state for LPDDR4. This reg
1409 # ister controls transition from the Self refresh state. - 1 - Prohibit tr
1410 # ansition from Self refresh state - 0 - Allow transition from Self refres
1412 # PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0
1414 # A value of 1 to this register causes system to move to Self Refresh stat
1415 # e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
1416 # This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
1417 # re Entry to Self Refresh - 0 - Software Exit from Self Refresh
1418 # PSU_DDRC_PWRCTL_SELFREF_SW 0x0
1420 # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
1421 # when the transaction store is empty. This register must be reset to '0'
1422 # to bring uMCTL2 out of maximum power saving mode. Present only in desig
1423 # ns configured to support DDR4. For non-DDR4, this register should not be
1424 # set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
1425 # the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
1426 # equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
1427 # PSU_DDRC_PWRCTL_MPSM_EN 0x0
1429 # Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
1430 # uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
1431 # Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
1432 # be asserted in Self Refresh. In DDR4, can be asserted in following: - i
1433 # n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
1434 # n be asserted in following: - in Self Refresh - in Power Down - in Deep
1435 # Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
1436 # rted in following: - in Self Refresh Power Down - in Power Down - during
1437 # Normal operation (Clock Stop)
1438 # PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0
1440 # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
1441 # transaction store is empty. This register must be reset to '0' to bring
1442 # uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
1443 # initialization on deep power-down exit. Present only in designs configu
1444 # red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
1445 # DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
1446 # PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0
1448 # If true then the uMCTL2 goes into power-down after a programmable number
1449 # of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
1450 # x32). This register bit may be re-programmed during the course of normal
1452 # PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0
1454 # If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
1455 # mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
1456 # selfref_to_x32)'. This register bit may be re-programmed during the cour
1457 # se of normal operation.
1458 # PSU_DDRC_PWRCTL_SELFREF_EN 0x0
1460 # Low Power Control Register
1461 #(OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) */
1462 mask_write 0XFD070030 0x0000007F 0x00000000
1463 # Register : PWRTMG @ 0XFD070034</p>
1465 # After this many clocks of NOP or deselect the uMCTL2 automatically puts
1466 # the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
1467 # en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
1468 # PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40
1470 # Minimum deep power-down time. For mDDR, value from the JEDEC specificati
1471 # on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
1472 # .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
1473 # C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
1474 # n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
1476 # PSU_DDRC_PWRTMG_T_DPD_X4096 0x84
1478 # After this many clocks of NOP or deselect the uMCTL2 automatically puts
1479 # the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
1480 # en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
1481 # PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10
1483 # Low Power Timing Register
1484 #(OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) */
1485 mask_write 0XFD070034 0x00FFFF1F 0x00408410
1486 # Register : RFSHCTL0 @ 0XFD070050</p>
1488 # Threshold value in number of clock cycles before the critical refresh or
1489 # page timer expires. A critical refresh is to be issued before this thre
1490 # shold is reached. It is recommended that this not be changed from the de
1491 # fault value, currently shown as 0x2. It must always be less than interna
1492 # lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
1493 # sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
1494 # s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
1495 # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
1497 # PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2
1499 # If the refresh timer (tRFCnom, also known as tREFI) has expired at least
1500 # once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
1501 # a speculative refresh may be performed. A speculative refresh is a refr
1502 # esh performed at a time when refresh would be useful, but before it is a
1503 # bsolutely required. When the SDRAM bus is idle for a period of time dete
1504 # rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
1505 # at least once since the last refresh, then a speculative refresh is per
1506 # formed. Speculative refreshes continues successively until there are no
1507 # refreshes pending or until new reads or writes are issued to the uMCTL2.
1508 # FOR PERFORMANCE ONLY.
1509 # PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10
1511 # The programmed value + 1 is the number of refresh timeouts that is allow
1512 # ed to accumulate before traffic is blocked and the refreshes are forced
1513 # to execute. Closing pages to perform a refresh is a one-time penalty tha
1514 # t must be paid for each group of refreshes. Therefore, performing refres
1515 # hes in a burst reduces the per-refresh penalty of these page closings. H
1516 # igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
1517 # lower numbers decreases the worst-case latency associated with refreshes
1518 # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
1519 # For information on burst refresh feature refer to section 3.9 of DDR2 J
1520 # EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
1521 # r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
1522 # I cycles using the burst refresh feature. In DDR4 mode, according to Fin
1523 # e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
1524 # shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
1525 # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
1526 # ure that tRFCmax is not violated due to a PHY-initiated update occurring
1527 # shortly before a refresh burst was due. In this situation, the refresh
1528 # burst will be delayed until the PHY-initiated update is complete.
1529 # PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0
1531 # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
1532 # traffic to flow to other banks. Per bank refresh is not supported by all
1533 # LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
1534 # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
1535 # PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0
1537 # Refresh Control Register 0
1538 #(OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) */
1539 mask_write 0XFD070050 0x00F1F1F4 0x00210000
1540 # Register : RFSHCTL1 @ 0XFD070054</p>
1542 # Refresh timer start for rank 1 (only present in multi-rank configuration
1543 # s). This is useful in staggering the refreshes to multiple ranks to help
1544 # traffic to proceed. This is explained in Refresh Controls section of ar
1545 # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
1546 # PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0
1548 # Refresh timer start for rank 0 (only present in multi-rank configuration
1549 # s). This is useful in staggering the refreshes to multiple ranks to help
1550 # traffic to proceed. This is explained in Refresh Controls section of ar
1551 # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
1552 # PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0
1554 # Refresh Control Register 1
1555 #(OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) */
1556 mask_write 0XFD070054 0x0FFF0FFF 0x00000000
1557 # Register : RFSHCTL3 @ 0XFD070060</p>
1559 # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
1560 # ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
1561 # 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
1562 # te: The on-the-fly modes is not supported in this version of the uMCTL2.
1563 # Note: This must be set up while the Controller is in reset or while the
1564 # Controller is in self-refresh mode. Changing this during normal operati
1565 # on is not allowed. Making this a dynamic register will be supported in f
1566 # uture version of the uMCTL2.
1567 # PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0
1569 # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
1570 # the refresh register(s) have been updated. The value is automatically up
1571 # dated when exiting reset, so it does not need to be toggled initially.
1572 # PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0
1574 # When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
1575 # h is disabled, the SoC core must generate refreshes using the registers
1576 # reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
1577 # nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
1578 # , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
1579 # CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
1580 # isable auto-refresh is not supported, and this bit must be set to '0'. T
1581 # his register field is changeable on the fly.
1582 # PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1
1584 # Refresh Control Register 3
1585 #(OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) */
1586 mask_write 0XFD070060 0x00000073 0x00000001
1587 # Register : RFSHTMG @ 0XFD070064</p>
1589 # tREFI: Average time interval between refreshes per rank (Specification:
1590 # 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
1591 # LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
1592 # shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
1593 # FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
1594 # register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
1595 # IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
1596 # ue is different depending on the refresh mode. The user should program t
1597 # he appropriate value from the spec based on the value programmed in the
1598 # refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
1599 # ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
1600 # an 0x1. Unit: Multiples of 32 clocks.
1601 # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81
1603 # Used only when LPDDR3 memory type is connected. Should only be changed w
1604 # hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
1605 # equired by some LPDDR3 devices which comply with earlier versions of the
1606 # LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
1607 # - tREFBW parameter used
1608 # PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1
1610 # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
1611 # REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
1612 # CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
1613 # undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
1614 # all-bank refreshes, the tRFCmin value in the above equations is equal to
1615 # tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
1616 # uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
1617 # equations is different depending on the refresh mode (fixed 1X,2X,4X) an
1618 # d the device density. The user should program the appropriate value from
1619 # the spec based on the 'refresh_mode' and the device density that is use
1621 # PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b
1623 # Refresh Timing Register
1624 #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) */
1625 mask_write 0XFD070064 0x0FFF83FF 0x0081808B
1626 # Register : ECCCFG0 @ 0XFD070070</p>
1628 # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
1630 # PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1
1632 # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
1633 # er 1 beat - all other settings are reserved for future use
1634 # PSU_DDRC_ECCCFG0_ECC_MODE 0x0
1636 # ECC Configuration Register 0
1637 #(OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) */
1638 mask_write 0XFD070070 0x00000017 0x00000010
1639 # Register : ECCCFG1 @ 0XFD070074</p>
1641 # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
1642 # ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
1644 # PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0
1646 # Enable ECC data poisoning - introduces ECC errors on writes to address s
1647 # pecified by the ECCPOISONADDR0/1 registers
1648 # PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0
1650 # ECC Configuration Register 1
1651 #(OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) */
1652 mask_write 0XFD070074 0x00000003 0x00000000
1653 # Register : CRCPARCTL1 @ 0XFD0700C4</p>
1655 # The maximum number of DFI PHY clock cycles allowed from the assertion of
1656 # the dfi_rddata_en signal to the assertion of each of the corresponding
1657 # bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
1658 # parameter tphy_rdlat. Refer to PHY specification for correct value. This
1659 # value it only used for detecting read data timeout when DDR4 retry is e
1660 # nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
1661 # - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
1662 # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
1663 # : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
1664 # fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
1665 # rdlat < 'd114 Unit: DFI Clocks
1666 # PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10
1668 # After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
1669 # re has an option to read the mode registers in the DRAM before the hardw
1670 # are begins the retry process - 1: Wait for software to read/write the mo
1671 # de registers before hardware begins the retry. After software is done wi
1672 # th its operations, it will clear the alert interrupt register bit - 0: H
1673 # ardware can begin the retry right away after the dfi_alert_n pulse goes
1674 # away. The value on this register is valid only when retry is enabled (PA
1675 # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
1676 # he software doesn't clear the interrupt register after handling the pari
1677 # ty/CRC error, then the hardware will not begin the retry process and the
1678 # system will hang. In the case of Parity/CRC error, there are two possib
1679 # ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
1680 # t parity' mode register bit is NOT set: the commands sent during retry a
1681 # nd normal operation are executed without parity checking. The value in t
1682 # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
1683 # parity' mode register bit is SET: Parity checking is done for commands s
1684 # ent during retry and normal operation. If multiple errors occur before M
1685 # R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
1687 # PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1
1689 # - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
1690 # 0: Disable command retry mechanism when C/A Parity or CRC features are
1691 # enabled. Note that retry functionality is not supported if burst chop is
1692 # enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
1693 # SHCTL3.dis_auto_refresh = 1)
1694 # PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0
1696 # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
1697 # t includes DM signal Present only in designs configured to support DDR4.
1698 # PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0
1700 # CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
1701 # n of CRC The setting of this register should match the CRC mode register
1702 # setting in the DRAM.
1703 # PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0
1705 # C/A Parity enable register - 1: Enable generation of C/A parity and dete
1706 # ction of C/A parity error - 0: Disable generation of C/A parity and disa
1707 # ble detection of C/A parity error If RCD's parity error detection or SDR
1708 # AM's parity detection is enabled, this register should be 1.
1709 # PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0
1711 # CRC Parity Control Register1
1712 #(OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) */
1713 mask_write 0XFD0700C4 0x3F000391 0x10000200
1714 # Register : CRCPARCTL2 @ 0XFD0700C8</p>
1716 # Value from the DRAM spec indicating the maximum width of the dfi_alert_n
1717 # pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
1718 # AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
1719 # _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
1720 # llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
1721 # PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40
1723 # Value from the DRAM spec indicating the maximum width of the dfi_alert_n
1724 # pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
1725 # For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
1726 # .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
1727 # gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
1728 # PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5
1730 # Indicates the maximum duration in number of DRAM clock cycles for which
1731 # a command should be held in the Command Retry FIFO before it is popped o
1732 # ut. Every location in the Command Retry FIFO has an associated down coun
1733 # ting timer that will use this register as the start value. The down coun
1734 # ting starts when a command is loaded into the FIFO. The timer counts dow
1735 # n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
1736 # d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
1737 # or occurs before the counter reaches zero. The counter is reset to 0, af
1738 # ter all the commands in the FIFO are retried. Recommended(minimum) value
1739 # s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
1740 # + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
1741 # cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
1742 # d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
1743 # DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
1744 # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
1745 # in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
1746 # ) should be considered. Note 3: Use the worst case(longer) value for PHY
1747 # Latencies/Board delay Note 4: The Recommended values are minimum value
1748 # to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
1749 # value can be set to this register is defined below: - MEMC_BURST_LENGTH
1750 # == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
1751 # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
1752 # us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
1753 # e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
1754 # RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
1755 # ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
1756 # Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
1757 # bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
1758 # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
1759 # =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
1760 # ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
1761 # x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
1763 # PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f
1765 # CRC Parity Control Register2
1766 #(OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) */
1767 mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F
1768 # Register : INIT0 @ 0XFD0700D0</p>
1770 # If lower bit is enabled the SDRAM initialization routine is skipped. The
1771 # upper bit decides what state the controller starts up in when reset is
1772 # removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
1773 # SDRAM Intialization routine is skipped after power-up. Controller starts
1774 # up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
1775 # ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
1776 # ation routine is run after power-up. Note: The only 2'b00 is supported f
1777 # or LPDDR4 in this version of the uMCTL2.
1778 # PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0
1780 # Cycles to wait after driving CKE high to start the SDRAM initialization
1781 # sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
1782 # uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
1783 # R3 typically requires this to be programmed for a delay of 200 us. LPDDR
1784 # 4 typically requires this to be programmed for a delay of 2 us. For conf
1785 # igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
1786 # ded by 2, and round it up to next integer value.
1787 # PSU_DDRC_INIT0_POST_CKE_X1024 0x2
1789 # Cycles to wait after reset before driving CKE high to start the SDRAM in
1790 # itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
1791 # cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
1792 # DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
1793 # ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
1794 # 2, and round it up to next integer value.
1795 # PSU_DDRC_INIT0_PRE_CKE_X1024 0x106
1797 # SDRAM Initialization Register 0
1798 #(OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) */
1799 mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106
1800 # Register : INIT1 @ 0XFD0700D4</p>
1802 # Number of cycles to assert SDRAM reset signal during init sequence. This
1803 # is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
1804 # r use with a DDR PHY, this should be set to a minimum of 1
1805 # PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2
1807 # Cycles to wait after completing the SDRAM initialization sequence before
1808 # starting the dynamic scheduler. Unit: Counts of a global timer that pul
1809 # ses every 32 clock cycles. There is no known specific requirement for th
1810 # is; it may be set to zero.
1811 # PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0
1813 # Wait period before driving the OCD complete command to SDRAM. Unit: Coun
1814 # ts of a global timer that pulses every 32 clock cycles. There is no know
1815 # n specific requirement for this; it may be set to zero.
1816 # PSU_DDRC_INIT1_PRE_OCD_X32 0x0
1818 # SDRAM Initialization Register 1
1819 #(OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) */
1820 mask_write 0XFD0700D4 0x01FF7F0F 0x00020000
1821 # Register : INIT2 @ 0XFD0700D8</p>
1823 # Idle time after the reset command, tINIT4. Present only in designs confi
1824 # gured to support LPDDR2. Unit: 32 clock cycles.
1825 # PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23
1827 # Time to wait after the first CKE high, tINIT2. Present only in designs c
1828 # onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
1829 # ypically requires 5 x tCK delay.
1830 # PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5
1832 # SDRAM Initialization Register 2
1833 #(OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) */
1834 mask_write 0XFD0700D8 0x0000FF0F 0x00002305
1835 # Register : INIT3 @ 0XFD0700DC</p>
1837 # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
1838 # re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
1839 # loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
1840 # DDR3/LPDDR4 - Value to write to MR1 register
1841 # PSU_DDRC_INIT3_MR 0x730
1843 # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
1844 # ng in this register is ignored. The uMCTL2 sets those bits appropriately
1845 # . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
1846 # ation mode training is enabled, this bit is set appropriately by the uMC
1847 # TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
1848 # LPDDR3/LPDDR4 - Value to write to MR2 register
1849 # PSU_DDRC_INIT3_EMR 0x301
1851 # SDRAM Initialization Register 3
1852 #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) */
1853 mask_write 0XFD0700DC 0xFFFFFFFF 0x07300301
1854 # Register : INIT4 @ 0XFD0700E0</p>
1856 # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
1857 # register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
1859 # PSU_DDRC_INIT4_EMR2 0x20
1861 # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
1862 # register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
1864 # PSU_DDRC_INIT4_EMR3 0x200
1866 # SDRAM Initialization Register 4
1867 #(OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) */
1868 mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200
1869 # Register : INIT5 @ 0XFD0700E4</p>
1871 # ZQ initial calibration, tZQINIT. Present only in designs configured to s
1872 # upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
1873 # lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
1875 # PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21
1877 # Maximum duration of the auto initialization, tINIT5. Present only in des
1878 # igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
1880 # PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4
1882 # SDRAM Initialization Register 5
1883 #(OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) */
1884 mask_write 0XFD0700E4 0x00FF03FF 0x00210004
1885 # Register : INIT6 @ 0XFD0700E8</p>
1887 # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
1889 # PSU_DDRC_INIT6_MR4 0x0
1891 # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
1893 # PSU_DDRC_INIT6_MR5 0x6c0
1895 # SDRAM Initialization Register 6
1896 #(OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) */
1897 mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0
1898 # Register : INIT7 @ 0XFD0700EC</p>
1900 # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
1902 # PSU_DDRC_INIT7_MR6 0x819
1904 # SDRAM Initialization Register 7
1905 #(OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) */
1906 mask_write 0XFD0700EC 0xFFFF0000 0x08190000
1907 # Register : DIMMCTL @ 0XFD0700F0</p>
1909 # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
1910 # BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
1911 # equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
1912 # ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
1913 # PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0
1915 # Enable for BG1 bit of MRS command. BG1 bit of the mode register address
1916 # is specified as RFU (Reserved for Future Use) and must be programmed to
1917 # 0 during MRS. In case where DRAMs which do not have BG1 are attached and
1918 # both the CA parity and the Output Inversion are enabled, this must be s
1919 # et to 0, so that the calculation of CA parity will not include BG1 bit.
1920 # Note: This has no effect on the address of any other memory accesses, or
1921 # of software-driven mode register accesses. If address mirroring is enab
1922 # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
1923 # abled - 0 - Disabled
1924 # PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1
1926 # Enable for A17 bit of MRS command. A17 bit of the mode register address
1927 # is specified as RFU (Reserved for Future Use) and must be programmed to
1928 # 0 during MRS. In case where DRAMs which do not have A17 are attached and
1929 # the Output Inversion are enabled, this must be set to 0, so that the ca
1930 # lculation of CA parity will not include A17 bit. Note: This has no effec
1931 # t on the address of any other memory accesses, or of software-driven mod
1932 # e register accesses. - 1 - Enabled - 0 - Disabled
1933 # PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0
1935 # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
1936 # M implements the Output Inversion feature by default, which means that t
1937 # he following address, bank address and bank group bits of B-side DRAMs a
1938 # re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
1939 # sures that, for mode register accesses generated by the uMCTL2 during th
1940 # e automatic initialization routine and enabling of a particular DDR4 fea
1941 # ture, separate A-side and B-side mode register accesses are generated. F
1942 # or B-side mode register accesses, these bits are inverted within the uMC
1943 # TL2 to compensate for this RDIMM inversion. Note: This has no effect on
1944 # the address of any other memory accesses, or of software-driven mode reg
1945 # ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
1946 # Do not implement output inversion for B-side DRAMs.
1947 # PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0
1949 # Address Mirroring Enable (for multi-rank UDIMM implementations and multi
1950 # -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
1951 # address mirroring for odd ranks, which means that the following address
1952 # , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
1953 # A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
1954 # his bit ensures that, for mode register accesses during the automatic in
1955 # itialization routine, these bits are swapped within the uMCTL2 to compen
1956 # sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
1957 # ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
1958 # e automatic MRS access to enable/disable of a particular DDR4 feature. N
1959 # ote: This has no effect on the address of any other memory accesses, or
1960 # of software-driven mode register accesses. This is not supported for mDD
1961 # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
1962 # output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
1963 # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
1964 # ks, implement address mirroring for MRS commands to during initializatio
1965 # n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
1966 # lements address mirroring) - 0 - Do not implement address mirroring
1967 # PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0
1969 # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
1970 # M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
1971 # or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
1972 # software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
1973 # sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
1974 # nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
1975 # nds to even and odd ranks seperately - 0 - Do not stagger accesses
1976 # PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0
1978 # DIMM Control Register
1979 #(OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) */
1980 mask_write 0XFD0700F0 0x0000003F 0x00000010
1981 # Register : RANKCTL @ 0XFD0700F4</p>
1983 # Only present for multi-rank configurations. Indicates the number of cloc
1984 # ks of gap in data responses when performing consecutive writes to differ
1985 # ent ranks. This is used to switch the delays in the PHY to match the ran
1986 # k requirements. This value should consider both PHY requirement and ODT
1987 # requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
1988 # alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
1989 # 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
1990 # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
1991 # reased by 1. - ODT requirement: The value programmed in this register ta
1992 # kes care of the ODT switch off timing requirement when switching ranks d
1993 # uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
1994 # For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
1995 # f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
1996 # RATIO=2, program this to the larger value divided by two and round it up
1997 # to the next integer.
1998 # PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6
2000 # Only present for multi-rank configurations. Indicates the number of cloc
2001 # ks of gap in data responses when performing consecutive reads to differe
2002 # nt ranks. This is used to switch the delays in the PHY to match the rank
2003 # requirements. This value should consider both PHY requirement and ODT r
2004 # equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
2005 # lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
2006 # should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
2007 # ), should be increased by 1. - ODT requirement: The value programmed in
2008 # this register takes care of the ODT switch off timing requirement when s
2009 # witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
2010 # program this to the larger of PHY requirement or ODT requirement. For co
2011 # nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
2012 # vided by two and round it up to the next integer.
2013 # PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6
2015 # Only present for multi-rank configurations. Background: Reads to the sam
2016 # e rank can be performed back-to-back. Reads to different ranks require a
2017 # dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
2018 # to avoid possible data bus contention as well as to give PHY enough tim
2019 # e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
2020 # access on a cycle-by-cycle basis; therefore after a read is scheduled,
2021 # there are few clock cycles (determined by the value on RANKCTL.diff_rank
2022 # _rd_gap register) in which only reads from the same rank are eligible to
2023 # be scheduled. This prevents reads from other ranks from having fair acc
2024 # ess to the data bus. This parameter represents the maximum number of rea
2025 # ds that can be scheduled consecutively to the same rank. After this numb
2026 # er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
2027 # the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
2028 # her numbers increase bandwidth utilization, lower numbers increase fairn
2029 # ess. This feature can be DISABLED by setting this register to 0. When se
2030 # t to 0, the Controller will stay on the same rank as long as commands ar
2031 # e available for it. Minimum programmable value is 0 (feature disabled) a
2032 # nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
2033 # PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf
2035 # Rank Control Register
2036 #(OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) */
2037 mask_write 0XFD0700F4 0x00000FFF 0x0000066F
2038 # Register : DRAMTMG0 @ 0XFD070100</p>
2040 # Minimum time between write and precharge to same bank. Unit: Clocks Spec
2041 # ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
2042 # @400MHz and less for lower frequencies where: - WL = write latency - BL
2043 # = burst length. This must match the value programmed in the BL bit of t
2044 # he mode register to the SDRAM. BST (burst terminate) is not supported at
2045 # present. - tWR = Write recovery time. This comes directly from the SDRA
2046 # M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
2047 # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
2048 # above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
2049 # IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
2050 # p to the next integer value.
2051 # PSU_DDRC_DRAMTMG0_WR2PRE 0x11
2053 # tFAW Valid only when 8 or more banks(or banks x bank groups) are present
2054 # . In 8-bank design, at most 4 banks must be activated in a rolling windo
2055 # w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
2056 # s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
2057 # t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
2059 # PSU_DDRC_DRAMTMG0_T_FAW 0x10
2061 # tRAS(max): Maximum time between activate and precharge to same bank. Thi
2062 # s is the maximum time that a page can be kept open Minimum value of this
2063 # register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
2064 # =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
2066 # PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24
2068 # tRAS(min): Minimum time between activate and precharge to the same bank.
2069 # For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
2070 # S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
2071 # mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
2072 # e next integer value. Unit: Clocks
2073 # PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
2075 # SDRAM Timing Register 0
2076 #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) */
2077 mask_write 0XFD070100 0x7F3F7F3F 0x11102412
2078 # Register : DRAMTMG1 @ 0XFD070104</p>
2080 # tXP: Minimum time after power-down exit to any operation. For DDR3, this
2081 # should be programmed to tXPDLL if slow powerdown exit is selected in MR
2082 # 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
2083 # igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
2084 # up to the next integer value. Units: Clocks
2085 # PSU_DDRC_DRAMTMG1_T_XP 0x4
2087 # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
2088 # /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
2089 # ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
2090 # - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
2091 # RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
2092 # - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
2093 # RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
2094 # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
2095 # ve value by 2 and round it up to the next integer value. Unit: Clocks.
2096 # PSU_DDRC_DRAMTMG1_RD2PRE 0x4
2098 # tRC: Minimum time between activates to same bank. For configurations wit
2099 # h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
2100 # r value. Unit: Clocks.
2101 # PSU_DDRC_DRAMTMG1_T_RC 0x1a
2103 # SDRAM Timing Register 1
2104 #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) */
2105 mask_write 0XFD070104 0x001F1F7F 0x0004041A
2106 # Register : DRAMTMG2 @ 0XFD070108</p>
2108 # Set to WL Time from write command to write data on SDRAM interface. This
2109 # must be set to WL. For mDDR, it should normally be set to 1. Note that,
2110 # depending on the PHY, if using RDIMM, it may be necessary to use a valu
2111 # e of WL + 1 to compensate for the extra cycle of latency through the RDI
2112 # MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
2113 # d using the above equation by 2, and round it up to next integer. This r
2114 # egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
2115 # is set), as the DFI read and write latencies defined in DFITMG0 and DFI
2116 # TMG1 are sufficient for those protocols Unit: clocks
2117 # PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7
2119 # Set to RL Time from read command to read data on SDRAM interface. This m
2120 # ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
2121 # t be necessary to use a value of RL + 1 to compensate for the extra cycl
2122 # e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
2123 # , divide the value calculated using the above equation by 2, and round i
2124 # t up to next integer. This register field is not required for DDR2 and D
2125 # DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
2126 # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
2128 # PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8
2130 # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
2131 # PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
2132 # sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
2133 # LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
2134 # E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
2135 # command. Include time for bus turnaround and all per-bank, per-rank, an
2136 # d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
2137 # urst length. This must match the value programmed in the BL bit of the m
2138 # ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
2139 # E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
2140 # read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
2141 # erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
2142 # be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
2143 # culated using the above equation by 2, and round it up to next integer.
2144 # PSU_DDRC_DRAMTMG2_RD2WR 0x6
2146 # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
2147 # m time from write command to read command for same bank group. In others
2148 # , minimum time from write command to read command. Includes time for bus
2149 # turnaround, recovery times, and all per-bank, per-rank, and global cons
2150 # traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
2151 # tency - BL = burst length. This must match the value programmed in the B
2152 # L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
2153 # d command delay for same bank group. This comes directly from the SDRAM
2154 # specification. - tWTR = internal write to read command delay. This comes
2155 # directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
2156 # PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
2157 # e the value calculated using the above equation by 2, and round it up to
2159 # PSU_DDRC_DRAMTMG2_WR2RD 0xd
2161 # SDRAM Timing Register 2
2162 #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) */
2163 mask_write 0XFD070108 0x3F3F3F3F 0x0708060D
2164 # Register : DRAMTMG3 @ 0XFD07010C</p>
2166 # Time to wait after a mode register write or read (MRW or MRR). Present o
2167 # nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
2168 # pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
2169 # R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
2170 # er is used for the time from a MRW/MRR to all other commands. For LDPDR3
2171 # , this register is used for the time from a MRW/MRR to a MRW/MRR.
2172 # PSU_DDRC_DRAMTMG3_T_MRW 0x5
2174 # tMRD: Cycles to wait after a mode register write or read. Depending on t
2175 # he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
2176 # mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
2177 # e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
2178 # program this to (tMRD/2) and round it up to the next integer value. If
2179 # C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
2180 # PSU_DDRC_DRAMTMG3_T_MRD 0x4
2182 # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
2183 # mand and following non-load mode command. If C/A parity for DDR4 is used
2184 # , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
2185 # tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
2186 # using RDIMM, depending on the PHY, it may be necessary to use a value of
2187 # tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
2188 # pplied to mode register writes by the RDIMM chip.
2189 # PSU_DDRC_DRAMTMG3_T_MOD 0xc
2191 # SDRAM Timing Register 3
2192 #(OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) */
2193 mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C
2194 # Register : DRAMTMG4 @ 0XFD070110</p>
2196 # tRCD - tAL: Minimum time from activate to read or write command to same
2197 # bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
2198 # - tAL)/2) and round it up to the next integer value. Minimum value allow
2199 # ed for this register is 1, which implies minimum (tRCD - tAL) value to b
2200 # e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
2201 # PSU_DDRC_DRAMTMG4_T_RCD 0x8
2203 # DDR4: tCCD_L: This is the minimum time between two reads or two writes f
2204 # or same bank group. Others: tCCD: This is the minimum time between two r
2205 # eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
2206 # his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
2208 # PSU_DDRC_DRAMTMG4_T_CCD 0x3
2210 # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
2211 # or same bank group. Others: tRRD: Minimum time between activates from ba
2212 # nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
2213 # s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
2215 # PSU_DDRC_DRAMTMG4_T_RRD 0x3
2217 # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
2218 # _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
2219 # C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
2220 # RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
2221 # uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
2222 # PSU_DDRC_DRAMTMG4_T_RP 0x9
2224 # SDRAM Timing Register 4
2225 #(OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) */
2226 mask_write 0XFD070110 0x1F0F0F1F 0x08030309
2227 # Register : DRAMTMG5 @ 0XFD070114</p>
2229 # This is the time before Self Refresh Exit that CK is maintained as a val
2230 # id clock before issuing SRX. Specifies the clock stable time before SRX.
2231 # Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
2232 # EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
2233 # FREQ_RATIO=2, program this to recommended value divided by two and round
2234 # it up to next integer.
2235 # PSU_DDRC_DRAMTMG5_T_CKSRX 0x6
2237 # This is the time after Self Refresh Down Entry that CK is maintained as
2238 # a valid clock. Specifies the clock disable delay after SRE. Recommended
2239 # settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
2240 # - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
2241 # with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
2242 # o and round it up to next integer.
2243 # PSU_DDRC_DRAMTMG5_T_CKSRE 0x6
2245 # Minimum CKE low width for Self refresh or Self refresh power down entry
2246 # to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
2247 # C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
2248 # tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
2249 # _RATIO=2, program this to recommended value divided by two and round it
2250 # up to next integer.
2251 # PSU_DDRC_DRAMTMG5_T_CKESR 0x4
2253 # Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
2254 # esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
2255 # DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
2256 # non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
2257 # s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
2258 # round it up to the next integer value. Unit: Clocks.
2259 # PSU_DDRC_DRAMTMG5_T_CKE 0x3
2261 # SDRAM Timing Register 5
2262 #(OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) */
2263 mask_write 0XFD070114 0x0F0F3F1F 0x06060403
2264 # Register : DRAMTMG6 @ 0XFD070118</p>
2266 # This is the time after Deep Power Down Entry that CK is maintained as a
2267 # valid clock. Specifies the clock disable delay after DPDE. Recommended s
2268 # ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
2269 # FREQ_RATIO=2, program this to recommended value divided by two and round
2270 # it up to next integer. This is only present for designs supporting mDDR
2271 # or LPDDR2/LPDDR3 devices.
2272 # PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1
2274 # This is the time before Deep Power Down Exit that CK is maintained as a
2275 # valid clock before issuing DPDX. Specifies the clock stable time before
2276 # DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
2277 # urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
2278 # ed by two and round it up to next integer. This is only present for desi
2279 # gns supporting mDDR or LPDDR2 devices.
2280 # PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1
2282 # This is the time before Clock Stop Exit that CK is maintained as a valid
2283 # clock before issuing Clock Stop Exit. Specifies the clock stable time b
2284 # efore next command after Clock Stop Exit. Recommended settings: - mDDR:
2285 # 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
2286 # ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
2287 # two and round it up to next integer. This is only present for designs su
2288 # pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2289 # PSU_DDRC_DRAMTMG6_T_CKCSX 0x4
2291 # SDRAM Timing Register 6
2292 #(OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) */
2293 mask_write 0XFD070118 0x0F0F000F 0x01010004
2294 # Register : DRAMTMG7 @ 0XFD07011C</p>
2296 # This is the time after Power Down Entry that CK is maintained as a valid
2297 # clock. Specifies the clock disable delay after PDE. Recommended setting
2298 # s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
2299 # s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
2300 # wo and round it up to next integer. This is only present for designs sup
2301 # porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2302 # PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
2304 # This is the time before Power Down Exit that CK is maintained as a valid
2305 # clock before issuing PDX. Specifies the clock stable time before PDX. R
2306 # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
2307 # onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
2308 # divided by two and round it up to next integer. This is only present for
2309 # designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
2310 # PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
2312 # SDRAM Timing Register 7
2313 #(OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) */
2314 mask_write 0XFD07011C 0x00000F0F 0x00000606
2315 # Register : DRAMTMG8 @ 0XFD070120</p>
2317 # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
2318 # Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
2319 # to the above value divided by 2 and round up to next integer value. Unit
2320 # : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
2321 # mands. Note: Ensure this is less than or equal to t_xs_x32.
2322 # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3
2324 # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
2325 # elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
2326 # is to the above value divided by 2 and round up to next integer value. U
2327 # nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
2329 # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3
2331 # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
2332 # urations with MEMC_FREQ_RATIO=2, program this to the above value divided
2333 # by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
2334 # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
2335 # PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd
2337 # tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
2338 # gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
2339 # d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
2340 # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
2341 # PSU_DDRC_DRAMTMG8_T_XS_X32 0x6
2343 # SDRAM Timing Register 8
2344 #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) */
2345 mask_write 0XFD070120 0x7F7F7F7F 0x03030D06
2346 # Register : DRAMTMG9 @ 0XFD070124</p>
2348 # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
2349 # nly with MEMC_FREQ_RATIO=2
2350 # PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0
2352 # tCCD_S: This is the minimum time between two reads or two writes for dif
2353 # ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
2354 # inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
2355 # , program this to (tCCD_S/2) and round it up to the next integer value.
2356 # Present only in designs configured to support DDR4. Unit: clocks.
2357 # PSU_DDRC_DRAMTMG9_T_CCD_S 0x2
2359 # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
2360 # ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
2361 # is to (tRRD_S/2) and round it up to the next integer value. Present only
2362 # in designs configured to support DDR4. Unit: Clocks.
2363 # PSU_DDRC_DRAMTMG9_T_RRD_S 0x2
2365 # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
2366 # for different bank group. Includes time for bus turnaround, recovery ti
2367 # mes, and all per-bank, per-rank, and global constraints. Present only in
2368 # designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
2369 # ite latency - PL = Parity latency - BL = burst length. This must match t
2370 # he value programmed in the BL bit of the mode register to the SDRAM - tW
2371 # TR_S = internal write to read command delay for different bank group. Th
2372 # is comes directly from the SDRAM specification. For configurations with
2373 # MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
2374 # by 2, and round it up to next integer.
2375 # PSU_DDRC_DRAMTMG9_WR2RD_S 0xb
2377 # SDRAM Timing Register 9
2378 #(OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) */
2379 mask_write 0XFD070124 0x40070F3F 0x0002020B
2380 # Register : DRAMTMG11 @ 0XFD07012C</p>
2382 # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
2383 # L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
2384 # ) and round it up to the next integer value. Present only in designs con
2385 # figured to support DDR4. Unit: Multiples of 32 clocks.
2386 # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70
2388 # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
2389 # configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
2390 # )+1. Present only in designs configured to support DDR4. Unit: clocks.
2391 # PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7
2393 # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
2394 # FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
2395 # eger value. Present only in designs configured to support DDR4. Unit: Cl
2397 # PSU_DDRC_DRAMTMG11_T_MPX_S 0x1
2399 # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
2400 # n designs configured to support DDR4. Unit: Clocks. For configurations w
2401 # ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
2402 # ion by 2, and round it up to next integer.
2403 # PSU_DDRC_DRAMTMG11_T_CKMPE 0xe
2405 # SDRAM Timing Register 11
2406 #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) */
2407 mask_write 0XFD07012C 0x7F1F031F 0x7007010E
2408 # Register : DRAMTMG12 @ 0XFD070130</p>
2410 # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
2411 # er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
2412 # am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
2414 # PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2
2416 # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
2417 # ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
2418 # p to next integer value.
2419 # PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6
2421 # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
2422 # For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
2423 # and round it up to next integer value.
2424 # PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8
2426 # SDRAM Timing Register 12
2427 #(OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) */
2428 mask_write 0XFD070130 0x00030F1F 0x00020608
2429 # Register : ZQCTL0 @ 0XFD070180</p>
2431 # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
2432 # ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
2433 # request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
2434 # on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
2435 # sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2436 # PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1
2438 # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
2439 # h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
2440 # or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
2441 # n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
2442 # n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
2443 # for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2444 # PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0
2446 # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
2447 # L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
2448 # tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
2449 # mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
2450 # d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
2452 # PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0
2454 # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
2455 # Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
2456 # mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
2457 # mode. This is only present for designs supporting DDR4 devices.
2458 # PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0
2460 # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
2461 # r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
2462 # art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
2463 # =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
2464 # eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
2465 # e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
2466 # o the next integer value. Unit: Clock cycles. This is only present for d
2467 # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
2468 # PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100
2470 # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
2471 # NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
2472 # is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
2473 # his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
2474 # cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
2475 # DDR3/LPDDR4 devices.
2476 # PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40
2478 # ZQ Control Register 0
2479 #(OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) */
2480 mask_write 0XFD070180 0xF7FF03FF 0x81000040
2481 # Register : ZQCTL1 @ 0XFD070184</p>
2483 # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
2484 # on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
2485 # RATIO=2, program this to tZQReset/2 and round it up to the next integer
2486 # value. Unit: Clock cycles. This is only present for designs supporting L
2487 # PDDR2/LPDDR3/LPDDR4 devices.
2488 # PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20
2490 # Average interval to wait between automatically issuing ZQCS (ZQ calibrat
2491 # ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
2492 # 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
2493 # . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
2495 # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc
2497 # ZQ Control Register 1
2498 #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) */
2499 mask_write 0XFD070184 0x3FFFFFFF 0x020196DC
2500 # Register : DFITMG0 @ 0XFD070190</p>
2502 # Specifies the number of DFI clock cycles after an assertion or de-assert
2503 # ion of the DFI control signals that the control signals at the PHY-DRAM
2504 # interface reflect the assertion or de-assertion. If the DFI clock and th
2505 # e memory clock are not phase-aligned, this timing parameter should be ro
2506 # unded up to the next integer value. Note that if using RDIMM, it is nece
2507 # ssary to increment this parameter by RDIMM's extra cycle of latency in t
2508 # erms of DFI clock.
2509 # PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4
2511 # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
2512 # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
2513 # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
2514 # - 1 in terms of SDR clock cycles Refer to PHY specification for correct
2516 # PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1
2518 # Time from the assertion of a read command on the DFI interface to the as
2519 # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
2520 # ect value. This corresponds to the DFI parameter trddata_en. Note that,
2521 # depending on the PHY, if using RDIMM, it may be necessary to use the val
2522 # ue (CL + 1) in the calculation of trddata_en. This is to compensate for
2523 # the extra cycle of latency through the RDIMM. Unit: Clocks
2524 # PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb
2526 # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
2527 # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
2528 # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
2529 # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
2530 # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
2531 # n for correct value.
2532 # PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1
2534 # Specifies the number of clock cycles between when dfi_wrdata_en is asser
2535 # ted to when the associated write data is driven on the dfi_wrdata signal
2536 # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
2537 # specification for correct value. Note, max supported value is 8. Unit:
2539 # PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2
2541 # Write latency Number of clocks from the write command to write data enab
2542 # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
2543 # lat. Refer to PHY specification for correct value.Note that, depending o
2544 # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
2545 # in the calculation of tphy_wrlat. This is to compensate for the extra c
2546 # ycle of latency through the RDIMM.
2547 # PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb
2549 # DFI Timing Register 0
2550 #(OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) */
2551 mask_write 0XFD070190 0x1FBFBF3F 0x048B820B
2552 # Register : DFITMG1 @ 0XFD070194</p>
2554 # Specifies the number of DFI PHY clocks between when the dfi_cs signal is
2555 # asserted and when the associated command is driven. This field is used
2556 # for CAL mode, should be set to '0' or the value which matches the CAL mo
2557 # de register setting in the DRAM. If the PHY can add the latency for CAL
2558 # mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
2559 # PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0
2561 # Specifies the number of DFI PHY clocks between when the dfi_cs signal is
2562 # asserted and when the associated dfi_parity_in signal is driven.
2563 # PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0
2565 # Specifies the number of DFI clocks between when the dfi_wrdata_en signal
2566 # is asserted and when the corresponding write data transfer is completed
2567 # on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
2568 # elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
2569 # to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
2570 # 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
2571 # lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
2572 # RATIO=2, divide PHY's value by 2 and round up to next integer. If using
2573 # DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
2574 # PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3
2576 # Specifies the number of DFI clock cycles from the assertion of the dfi_d
2577 # ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
2578 # ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
2579 # and the memory clock are not phase aligned, this timing parameter should
2580 # be rounded up to the next integer value.
2581 # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3
2583 # Specifies the number of DFI clock cycles from the de-assertion of the df
2584 # i_dram_clk_disable signal on the DFI until the first valid rising edge o
2585 # f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
2586 # DFI clock and the memory clock are not phase aligned, this timing param
2587 # eter should be rounded up to the next integer value.
2588 # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4
2590 # DFI Timing Register 1
2591 #(OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) */
2592 mask_write 0XFD070194 0xF31F0F0F 0x00030304
2593 # Register : DFILPCFG0 @ 0XFD070198</p>
2595 # Setting for DFI's tlp_resp time. Same value is used for both Power Down,
2596 # Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
2597 # pecification onwards, recommends using a fixed value of 7 always.
2598 # PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7
2600 # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
2601 # red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
2602 # cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
2603 # 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
2604 # 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
2605 # 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
2606 # his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
2608 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0
2610 # Enables DFI Low Power interface handshaking during Deep Power Down Entry
2611 # /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
2612 # porting mDDR or LPDDR2/LPDDR3 devices.
2613 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0
2615 # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
2616 # . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
2617 # les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
2618 # cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
2619 # - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
2620 # ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
2621 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0
2623 # Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
2624 # it. - 0 - Disabled - 1 - Enabled
2625 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1
2627 # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
2628 # Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
2629 # s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
2630 # cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
2631 # 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
2632 # les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
2633 # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
2635 # Enables DFI Low Power interface handshaking during Power Down Entry/Exit
2636 # . - 0 - Disabled - 1 - Enabled
2637 # PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
2639 # DFI Low Power Configuration Register 0
2640 #(OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) */
2641 mask_write 0XFD070198 0x0FF1F1F1 0x07000101
2642 # Register : DFILPCFG1 @ 0XFD07019C</p>
2644 # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
2645 # entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
2646 # - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
2647 # 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
2648 # es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
2649 # 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
2650 # ted This is only present for designs supporting DDR4 devices.
2651 # PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2
2653 # Enables DFI Low Power interface handshaking during Maximum Power Saving
2654 # Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
2655 # esigns supporting DDR4 devices.
2656 # PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1
2658 # DFI Low Power Configuration Register 1
2659 #(OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) */
2660 mask_write 0XFD07019C 0x000000F1 0x00000021
2661 # Register : DFIUPD0 @ 0XFD0701A0</p>
2663 # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
2664 # . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
2665 # _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
2666 # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0
2668 # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
2669 # following a self-refresh exit. The core must issue the dfi_ctrlupd_req
2670 # signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
2671 # rlupd_req after exiting self-refresh.
2672 # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0
2674 # Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
2675 # gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
2677 # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40
2679 # Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
2680 # gnal must be asserted. The uMCTL2 expects the PHY to respond within this
2681 # time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
2682 # d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
2683 # variable is 0x3. Unit: Clocks
2684 # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3
2686 # DFI Update Register 0
2687 #(OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) */
2688 mask_write 0XFD0701A0 0xC3FF03FF 0x00400003
2689 # Register : DFIUPD1 @ 0XFD0701A4</p>
2691 # This is the minimum amount of time between uMCTL2 initiated DFI update r
2692 # equests (which is executed whenever the uMCTL2 is idle). Set this number
2693 # higher to reduce the frequency of update requests, which can have a sma
2694 # ll impact on the latency of the first read request when the uMCTL2 is id
2695 # le. Unit: 1024 clocks
2696 # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41
2698 # This is the maximum amount of time between uMCTL2 initiated DFI update r
2699 # equests. This timer resets with each update request; when the timer expi
2700 # res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
2701 # _ackx is received. PHY can use this idle time to recalibrate the delay l
2702 # ines to the DLLs. The DFI controller update is also used to reset PHY FI
2703 # FO pointers in case of data capture errors. Updates are required to main
2704 # tain calibration over PVT, but frequent updates may impact performance.
2705 # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
2706 # be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
2708 # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1
2710 # DFI Update Register 1
2711 #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) */
2712 mask_write 0XFD0701A4 0x00FF00FF 0x004100E1
2713 # Register : DFIMISC @ 0XFD0701B0</p>
2715 # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
2716 # s are active low - 1: Signals are active high
2717 # PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0
2719 # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
2720 # - 1 - PHY implements DBI functionality. Present only in designs configu
2721 # red to support DDR4 and LPDDR4.
2722 # PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0
2724 # PHY initialization complete enable signal. When asserted the dfi_init_co
2725 # mplete signal can be used to trigger SDRAM initialisation
2726 # PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0
2728 # DFI Miscellaneous Control Register
2729 #(OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) */
2730 mask_write 0XFD0701B0 0x00000007 0x00000000
2731 # Register : DFITMG2 @ 0XFD0701B4</p>
2733 # >Number of clocks between when a read command is sent on the DFI control
2734 # interface and when the associated dfi_rddata_cs signal is asserted. Thi
2735 # s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
2736 # cification for correct value.
2737 # PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9
2739 # Number of clocks between when a write command is sent on the DFI control
2740 # interface and when the associated dfi_wrdata_cs signal is asserted. Thi
2741 # s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
2742 # cification for correct value.
2743 # PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6
2745 # DFI Timing Register 2
2746 #(OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) */
2747 mask_write 0XFD0701B4 0x00003F3F 0x00000906
2748 # Register : DBICTL @ 0XFD0701C0</p>
2750 # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
2751 # BI is enabled. This signal must be set the same value as DRAM's mode reg
2752 # ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
2753 # e set to 0. - LPDDR4: MR3[6]
2754 # PSU_DDRC_DBICTL_RD_DBI_EN 0x0
2756 # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
2757 # e DBI is enabled. This signal must be set the same value as DRAM's mode
2758 # register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
2759 # t be set to 0. - LPDDR4: MR3[7]
2760 # PSU_DDRC_DBICTL_WR_DBI_EN 0x0
2762 # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
2763 # s signal must be set the same logical value as DRAM's mode register. - D
2764 # DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
2765 # is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
2766 # [5] which is opposite polarity from this signal
2767 # PSU_DDRC_DBICTL_DM_EN 0x1
2769 # DM/DBI Control Register
2770 #(OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) */
2771 mask_write 0XFD0701C0 0x00000007 0x00000001
2772 # Register : ADDRMAP0 @ 0XFD070200</p>
2774 # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
2775 # o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
2776 # by adding the internal base to the value of this field. If set to 31, r
2777 # ank address bit 0 is set to 0.
2778 # PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f
2780 # Address Map Register 0
2781 #(OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) */
2782 mask_write 0XFD070200 0x0000001F 0x0000001F
2783 # Register : ADDRMAP1 @ 0XFD070204</p>
2785 # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
2786 # o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
2787 # by adding the internal base to the value of this field. If set to 31, ba
2788 # nk address bit 2 is set to 0.
2789 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f
2791 # Selects the HIF address bits used as bank address bit 1. Valid Range: 0
2792 # to 30 Internal Base: 3 The selected HIF address bit for each of the bank
2793 # address bits is determined by adding the internal base to the value of
2795 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa
2797 # Selects the HIF address bits used as bank address bit 0. Valid Range: 0
2798 # to 30 Internal Base: 2 The selected HIF address bit for each of the bank
2799 # address bits is determined by adding the internal base to the value of
2801 # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa
2803 # Address Map Register 1
2804 #(OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) */
2805 mask_write 0XFD070204 0x001F1F1F 0x001F0A0A
2806 # Register : ADDRMAP2 @ 0XFD070208</p>
2808 # - Full bus width mode: Selects the HIF address bit used as column addres
2809 # s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
2810 # mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
2811 # used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
2812 # : 5 The selected HIF address bit is determined by adding the internal ba
2813 # se to the value of this field. If set to 15, this column address bit is
2815 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
2817 # - Full bus width mode: Selects the HIF address bit used as column addres
2818 # s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
2819 # mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
2820 # used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
2821 # 4 The selected HIF address bit is determined by adding the internal bas
2822 # e to the value of this field. If set to 15, this column address bit is s
2824 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
2826 # - Full bus width mode: Selects the HIF address bit used as column addres
2827 # s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
2828 # mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
2829 # used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
2830 # elected HIF address bit is determined by adding the internal base to the
2831 # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
2832 # 6, it is required to program this to 0, hence register does not exist in
2834 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
2836 # - Full bus width mode: Selects the HIF address bit used as column addres
2837 # s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
2838 # mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
2839 # used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
2840 # elected HIF address bit is determined by adding the internal base to the
2841 # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
2842 # or 16, it is required to program this to 0.
2843 # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
2845 # Address Map Register 2
2846 #(OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) */
2847 mask_write 0XFD070208 0x0F0F0F0F 0x00000000
2848 # Register : ADDRMAP3 @ 0XFD07020C</p>
2850 # - Full bus width mode: Selects the HIF address bit used as column addres
2851 # s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
2852 # mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
2853 # Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
2854 # LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
2855 # HIF address bit is determined by adding the internal base to the value o
2856 # f this field. If set to 15, this column address bit is set to 0. Note: P
2857 # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
2858 # r indicating auto-precharge, and hence no source address bit can be mapp
2859 # ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
2860 # for auto-precharge in the CA bus and hence column bit 10 is used.
2861 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0
2863 # - Full bus width mode: Selects the HIF address bit used as column addres
2864 # s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
2865 # mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
2866 # used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
2867 # to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
2868 # d by adding the internal base to the value of this field. If set to 15,
2869 # this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
2870 # cation, column address bit 10 is reserved for indicating auto-precharge,
2871 # and hence no source address bit can be mapped to column address bit 10.
2872 # In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
2873 # bus and hence column bit 10 is used.
2874 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0
2876 # - Full bus width mode: Selects the HIF address bit used as column addres
2877 # s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
2878 # mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
2879 # used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
2880 # 7 The selected HIF address bit is determined by adding the internal bas
2881 # e to the value of this field. If set to 15, this column address bit is s
2883 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0
2885 # - Full bus width mode: Selects the HIF address bit used as column addres
2886 # s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
2887 # mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
2888 # used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
2889 # 6 The selected HIF address bit is determined by adding the internal bas
2890 # e to the value of this field. If set to 15, this column address bit is s
2892 # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0
2894 # Address Map Register 3
2895 #(OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) */
2896 mask_write 0XFD07020C 0x0F0F0F0F 0x00000000
2897 # Register : ADDRMAP4 @ 0XFD070210</p>
2899 # - Full bus width mode: Selects the HIF address bit used as column addres
2900 # s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
2901 # ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
2902 # used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
2903 # and 15 Internal Base: 11 The selected HIF address bit is determined by
2904 # adding the internal base to the value of this field. If set to 15, this
2905 # column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
2906 # n, column address bit 10 is reserved for indicating auto-precharge, and
2907 # hence no source address bit can be mapped to column address bit 10. In L
2908 # PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
2909 # and hence column bit 10 is used.
2910 # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf
2912 # - Full bus width mode: Selects the HIF address bit used as column addres
2913 # s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
2914 # HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
2915 # . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
2916 # to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
2917 # address bit is determined by adding the internal base to the value of t
2918 # his field. If set to 15, this column address bit is set to 0. Note: Per
2919 # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
2920 # ndicating auto-precharge, and hence no source address bit can be mapped
2921 # to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
2922 # auto-precharge in the CA bus and hence column bit 10 is used.
2923 # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf
2925 # Address Map Register 4
2926 #(OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) */
2927 mask_write 0XFD070210 0x00000F0F 0x00000F0F
2928 # Register : ADDRMAP5 @ 0XFD070214</p>
2930 # Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
2931 # o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
2932 # d by adding the internal base to the value of this field. If set to 15,
2933 # row address bit 11 is set to 0.
2934 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8
2936 # Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
2937 # ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
2938 # address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
2939 # w address bit 10) The selected HIF address bit for each of the row addre
2940 # ss bits is determined by adding the internal base to the value of this f
2941 # ield. When value 15 is used the values of row address bits 2 to 10 are d
2942 # efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
2943 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf
2945 # Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
2946 # o 11 Internal Base: 7 The selected HIF address bit for each of the row a
2947 # ddress bits is determined by adding the internal base to the value of th
2949 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8
2951 # Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
2952 # o 11 Internal Base: 6 The selected HIF address bit for each of the row a
2953 # ddress bits is determined by adding the internal base to the value of th
2955 # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8
2957 # Address Map Register 5
2958 #(OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) */
2959 mask_write 0XFD070214 0x0F0F0F0F 0x080F0808
2960 # Register : ADDRMAP6 @ 0XFD070218</p>
2962 # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
2963 # - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
2964 # =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
2965 # All addresses are valid Present only in designs configured to support L
2967 # PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0
2969 # Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
2970 # o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
2971 # d by adding the internal base to the value of this field. If set to 15,
2972 # row address bit 15 is set to 0.
2973 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf
2975 # Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
2976 # o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
2977 # d by adding the internal base to the value of this field. If set to 15,
2978 # row address bit 14 is set to 0.
2979 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8
2981 # Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
2982 # o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
2983 # d by adding the internal base to the value of this field. If set to 15,
2984 # row address bit 13 is set to 0.
2985 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8
2987 # Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
2988 # o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
2989 # d by adding the internal base to the value of this field. If set to 15,
2990 # row address bit 12 is set to 0.
2991 # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8
2993 # Address Map Register 6
2994 #(OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) */
2995 mask_write 0XFD070218 0x8F0F0F0F 0x0F080808
2996 # Register : ADDRMAP7 @ 0XFD07021C</p>
2998 # Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
2999 # o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
3000 # d by adding the internal base to the value of this field. If set to 15,
3001 # row address bit 17 is set to 0.
3002 # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf
3004 # Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
3005 # o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
3006 # d by adding the internal base to the value of this field. If set to 15,
3007 # row address bit 16 is set to 0.
3008 # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf
3010 # Address Map Register 7
3011 #(OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) */
3012 mask_write 0XFD07021C 0x00000F0F 0x00000F0F
3013 # Register : ADDRMAP8 @ 0XFD070220</p>
3015 # Selects the HIF address bits used as bank group address bit 1. Valid Ran
3016 # ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
3017 # ch of the bank group address bits is determined by adding the internal b
3018 # ase to the value of this field. If set to 31, bank group address bit 1 i
3020 # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8
3022 # Selects the HIF address bits used as bank group address bit 0. Valid Ran
3023 # ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
3024 # e bank group address bits is determined by adding the internal base to t
3025 # he value of this field.
3026 # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8
3028 # Address Map Register 8
3029 #(OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) */
3030 mask_write 0XFD070220 0x00001F1F 0x00000808
3031 # Register : ADDRMAP9 @ 0XFD070224</p>
3033 # Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
3034 # o 11 Internal Base: 11 The selected HIF address bit for each of the row
3035 # address bits is determined by adding the internal base to the value of t
3036 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3037 # _10 is set to value 15.
3038 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8
3040 # Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
3041 # o 11 Internal Base: 10 The selected HIF address bit for each of the row
3042 # address bits is determined by adding the internal base to the value of t
3043 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3044 # _10 is set to value 15.
3045 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8
3047 # Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
3048 # o 11 Internal Base: 9 The selected HIF address bit for each of the row a
3049 # ddress bits is determined by adding the internal base to the value of th
3050 # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3051 # 10 is set to value 15.
3052 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8
3054 # Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
3055 # o 11 Internal Base: 8 The selected HIF address bit for each of the row a
3056 # ddress bits is determined by adding the internal base to the value of th
3057 # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
3058 # 10 is set to value 15.
3059 # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8
3061 # Address Map Register 9
3062 #(OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) */
3063 mask_write 0XFD070224 0x0F0F0F0F 0x08080808
3064 # Register : ADDRMAP10 @ 0XFD070228</p>
3066 # Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
3067 # o 11 Internal Base: 15 The selected HIF address bit for each of the row
3068 # address bits is determined by adding the internal base to the value of t
3069 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3070 # _10 is set to value 15.
3071 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8
3073 # Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
3074 # o 11 Internal Base: 14 The selected HIF address bit for each of the row
3075 # address bits is determined by adding the internal base to the value of t
3076 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3077 # _10 is set to value 15.
3078 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8
3080 # Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
3081 # o 11 Internal Base: 13 The selected HIF address bit for each of the row
3082 # address bits is determined by adding the internal base to the value of t
3083 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3084 # _10 is set to value 15.
3085 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8
3087 # Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
3088 # o 11 Internal Base: 12 The selected HIF address bit for each of the row
3089 # address bits is determined by adding the internal base to the value of t
3090 # his field. This register field is used only when ADDRMAP5.addrmap_row_b2
3091 # _10 is set to value 15.
3092 # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8
3094 # Address Map Register 10
3095 #(OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) */
3096 mask_write 0XFD070228 0x0F0F0F0F 0x08080808
3097 # Register : ADDRMAP11 @ 0XFD07022C</p>
3099 # Selects the HIF address bits used as row address bit 10. Valid Range: 0
3100 # to 11 Internal Base: 16 The selected HIF address bit for each of the row
3101 # address bits is determined by adding the internal base to the value of
3102 # this field. This register field is used only when ADDRMAP5.addrmap_row_b
3103 # 2_10 is set to value 15.
3104 # PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8
3106 # Address Map Register 11
3107 #(OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) */
3108 mask_write 0XFD07022C 0x0000000F 0x00000008
3109 # Register : ODTCFG @ 0XFD070240</p>
3111 # Cycles to hold ODT for a write command. The minimum supported value is 2
3112 # . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
3113 # ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
3114 # DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
3115 # EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
3116 # not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
3117 # PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6
3119 # The delay, in clock cycles, from issuing a write command to setting ODT
3120 # values associated with that command. ODT setting must remain constant fo
3121 # r the entire time that DQS is driven by the uMCTL2. Recommended values:
3122 # DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
3123 # AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
3124 # r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
3125 # for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
3126 # PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0
3128 # Cycles to hold ODT for a read command. The minimum supported value is 2.
3129 # Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
3130 # BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
3131 # : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
3132 # reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
3133 # RU(tODTon(max)/tCK)
3134 # PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6
3136 # The delay, in clock cycles, from issuing a read command to setting ODT v
3137 # alues associated with that command. ODT setting must remain constant for
3138 # the entire time that DQS is driven by the uMCTL2. Recommended values: D
3139 # DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
3140 # - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
3141 # WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
3142 # (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
3143 # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
3144 # amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
3145 # pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
3146 # U(tODTon(max)/tCK)
3147 # PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0
3149 # ODT Configuration Register
3150 #(OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) */
3151 mask_write 0XFD070240 0x0F1F0F7C 0x06000600
3152 # Register : ODTMAP @ 0XFD070244</p>
3154 # Indicates which remote ODTs must be turned on during a read from rank 1.
3155 # Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3156 # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3157 # s controlled by bit next to the LSB, etc. For each rank, set its bit to
3158 # 1 to enable its ODT. Present only in configurations that have 2 or more
3160 # PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0
3162 # Indicates which remote ODTs must be turned on during a write to rank 1.
3163 # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3164 # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3165 # controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3166 # to enable its ODT. Present only in configurations that have 2 or more r
3168 # PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0
3170 # Indicates which remote ODTs must be turned on during a read from rank 0.
3171 # Each rank has a remote ODT (in the SDRAM) which can be turned on by set
3172 # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
3173 # s controlled by bit next to the LSB, etc. For each rank, set its bit to
3174 # 1 to enable its ODT.
3175 # PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0
3177 # Indicates which remote ODTs must be turned on during a write to rank 0.
3178 # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
3179 # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
3180 # controlled by bit next to the LSB, etc. For each rank, set its bit to 1
3181 # to enable its ODT.
3182 # PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1
3184 # ODT/Rank Map Register
3185 #(OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) */
3186 mask_write 0XFD070244 0x00003333 0x00000001
3187 # Register : SCHED @ 0XFD070250</p>
3189 # When the preferred transaction store is empty for these many clock cycle
3190 # s, switch to the alternate transaction store if it is non-empty. The rea
3191 # d transaction store (both high and low priority) is the default preferre
3192 # d transaction store and the write transaction store is the alternative s
3193 # tore. When prefer write over read is set this is reversed. 0x0 is a lega
3194 # l value for this register. When set to 0x0, the transaction store switch
3195 # ing will happen immediately when the switching conditions become true. F
3196 # OR PERFORMANCE ONLY
3197 # PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1
3200 # PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0
3202 # Number of entries in the low priority transaction store is this value +
3203 # 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
3204 # ries available for the high priority transaction store. Setting this to
3205 # maximum value allocates all entries to low priority transaction store. S
3206 # etting this to 0 allocates 1 entry to low priority transaction store and
3207 # the rest to high priority transaction store. Note: In ECC configuration
3208 # s, the numbers of write and low priority read credits issued is one less
3209 # than in the non-ECC case. One entry each is reserved in the write and l
3210 # ow-priority read CAMs for storing the RMW requests arising out of single
3211 # bit error correction RMW operation.
3212 # PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20
3214 # If true, bank is kept open only while there are page hit transactions av
3215 # ailable in the CAM to that bank. The last read or write command in the C
3216 # AM with a bank and page hit will be executed with auto-precharge if SCHE
3217 # D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
3218 # e_timer is set to 0, explicit precharge (and not auto-precharge) may be
3219 # issued in some cases where there is a mode switch between Write and Read
3220 # or between LPR and HPR. The Read and Write commands that are executed a
3221 # s part of the ECC scrub requests are also executed without auto-precharg
3222 # e. If false, the bank remains open until there is a need to close it (to
3223 # open a different page, or for page timeout or refresh timeout) - also k
3224 # nown as open page policy. The open page policy can be overridden by sett
3225 # ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
3226 # The pageclose feature provids a midway between Open and Close page polic
3227 # ies. FOR PERFORMANCE ONLY.
3228 # PSU_DDRC_SCHED_PAGECLOSE 0x0
3230 # If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
3231 # PSU_DDRC_SCHED_PREFER_WRITE 0x0
3233 # Active low signal. When asserted ('0'), all incoming transactions are fo
3234 # rced to low priority. This implies that all High Priority Read (HPR) and
3235 # Variable Priority Read commands (VPR) will be treated as Low Priority R
3236 # ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
3237 # commands will be treated as Normal Priority Write (NPW) commands. Forci
3238 # ng the incoming transactions to low priority implicitly turns off Bypass
3239 # path for read commands. FOR PERFORMANCE ONLY.
3240 # PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1
3242 # Scheduler Control Register
3243 #(OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) */
3244 mask_write 0XFD070250 0x7FFF3F07 0x01002001
3245 # Register : PERFLPR1 @ 0XFD070264</p>
3247 # Number of transactions that are serviced once the LPR queue goes critica
3248 # l is the smaller of: - (a) This number - (b) Number of transactions avai
3249 # lable. Unit: Transaction. FOR PERFORMANCE ONLY.
3250 # PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8
3252 # Number of clocks that the LPR queue can be starved before it goes critic
3253 # al. The minimum valid functional value for this register is 0x1. Program
3254 # ming it to 0x0 will disable the starvation functionality; during normal
3255 # operation, this function should not be disabled as it will cause excessi
3256 # ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3257 # PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40
3259 # Low Priority Read CAM Register 1
3260 #(OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) */
3261 mask_write 0XFD070264 0xFF00FFFF 0x08000040
3262 # Register : PERFWR1 @ 0XFD07026C</p>
3264 # Number of transactions that are serviced once the WR queue goes critical
3265 # is the smaller of: - (a) This number - (b) Number of transactions avail
3266 # able. Unit: Transaction. FOR PERFORMANCE ONLY.
3267 # PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8
3269 # Number of clocks that the WR queue can be starved before it goes critica
3270 # l. The minimum valid functional value for this register is 0x1. Programm
3271 # ing it to 0x0 will disable the starvation functionality; during normal o
3272 # peration, this function should not be disabled as it will cause excessiv
3273 # e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
3274 # PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40
3276 # Write CAM Register 1
3277 #(OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) */
3278 mask_write 0XFD07026C 0xFF00FFFF 0x08000040
3279 # Register : DQMAP0 @ 0XFD070280</p>
3281 # DQ nibble map for DQ bits [12-15] Present only in designs configured to
3283 # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0
3285 # DQ nibble map for DQ bits [8-11] Present only in designs configured to s
3287 # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0
3289 # DQ nibble map for DQ bits [4-7] Present only in designs configured to su
3291 # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0
3293 # DQ nibble map for DQ bits [0-3] Present only in designs configured to su
3295 # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0
3298 #(OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) */
3299 mask_write 0XFD070280 0xFFFFFFFF 0x00000000
3300 # Register : DQMAP1 @ 0XFD070284</p>
3302 # DQ nibble map for DQ bits [28-31] Present only in designs configured to
3304 # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0
3306 # DQ nibble map for DQ bits [24-27] Present only in designs configured to
3308 # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0
3310 # DQ nibble map for DQ bits [20-23] Present only in designs configured to
3312 # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0
3314 # DQ nibble map for DQ bits [16-19] Present only in designs configured to
3316 # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0
3319 #(OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) */
3320 mask_write 0XFD070284 0xFFFFFFFF 0x00000000
3321 # Register : DQMAP2 @ 0XFD070288</p>
3323 # DQ nibble map for DQ bits [44-47] Present only in designs configured to
3325 # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0
3327 # DQ nibble map for DQ bits [40-43] Present only in designs configured to
3329 # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0
3331 # DQ nibble map for DQ bits [36-39] Present only in designs configured to
3333 # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0
3335 # DQ nibble map for DQ bits [32-35] Present only in designs configured to
3337 # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0
3340 #(OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) */
3341 mask_write 0XFD070288 0xFFFFFFFF 0x00000000
3342 # Register : DQMAP3 @ 0XFD07028C</p>
3344 # DQ nibble map for DQ bits [60-63] Present only in designs configured to
3346 # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0
3348 # DQ nibble map for DQ bits [56-59] Present only in designs configured to
3350 # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0
3352 # DQ nibble map for DQ bits [52-55] Present only in designs configured to
3354 # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0
3356 # DQ nibble map for DQ bits [48-51] Present only in designs configured to
3358 # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0
3361 #(OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) */
3362 mask_write 0XFD07028C 0xFFFFFFFF 0x00000000
3363 # Register : DQMAP4 @ 0XFD070290</p>
3365 # DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
3366 # igured to support DDR4.
3367 # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0
3369 # DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
3370 # igured to support DDR4.
3371 # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0
3374 #(OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) */
3375 mask_write 0XFD070290 0x0000FFFF 0x00000000
3376 # Register : DQMAP5 @ 0XFD070294</p>
3378 # All even ranks have the same DQ mapping controled by DQMAP0-4 register a
3379 # s rank 0. This register provides DQ swap function for all odd ranks to s
3380 # upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
3381 # it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
3382 # sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
3383 # configured to support DDR4.
3384 # PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1
3387 #(OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) */
3388 mask_write 0XFD070294 0x00000001 0x00000001
3389 # Register : DBG0 @ 0XFD070300</p>
3391 # When this is set to '0', auto-precharge is disabled for the flushed comm
3392 # and in a collision case. Collision cases are write followed by read to s
3393 # ame address, read followed by write to same address, or write followed b
3394 # y write to same address with DBG0.dis_wc bit = 1 (where same address com
3395 # parisons exclude the two address bits representing critical word). FOR D
3397 # PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0
3399 # When 1, disable write combine. FOR DEBUG ONLY
3400 # PSU_DDRC_DBG0_DIS_WC 0x0
3403 #(OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) */
3404 mask_write 0XFD070300 0x00000011 0x00000000
3405 # Register : DBGCMD @ 0XFD07030C</p>
3407 # Setting this register bit to 1 allows refresh and ZQCS commands to be tr
3408 # iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
3409 # zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
3410 # d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
3411 # ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
3412 # t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
3413 # function, and are ignored by the uMCTL2 logic. This register is static,
3414 # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
3416 # PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0
3418 # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
3419 # rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
3420 # is automatically cleared. This operation must only be performed when DF
3421 # IUPD0.dis_auto_ctrlupd=1.
3422 # PSU_DDRC_DBGCMD_CTRLUPD 0x0
3424 # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
3425 # ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
3426 # s request is stored in the uMCTL2, the bit is automatically cleared. Thi
3427 # s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
3428 # mended NOT to set this register bit if in Init operating mode. This regi
3429 # ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
3430 # (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
3432 # PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0
3434 # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
3435 # h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
3436 # set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
3437 # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
3438 # auto_refresh=1. It is recommended NOT to set this register bit if in Ini
3439 # t or Deep power-down operating modes or Maximum Power Saving Mode.
3440 # PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0
3442 # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
3443 # h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
3444 # set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
3445 # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
3446 # auto_refresh=1. It is recommended NOT to set this register bit if in Ini
3447 # t or Deep power-down operating modes or Maximum Power Saving Mode.
3448 # PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0
3450 # Command Debug Register
3451 #(OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) */
3452 mask_write 0XFD07030C 0x80000033 0x00000000
3453 # Register : SWCTL @ 0XFD070320</p>
3455 # Enable quasi-dynamic register programming outside reset. Program registe
3456 # r to 0 to enable quasi-dynamic programming. Set back register to 1 once
3457 # programming is done.
3458 # PSU_DDRC_SWCTL_SW_DONE 0x0
3460 # Software register programming control enable
3461 #(OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) */
3462 mask_write 0XFD070320 0x00000001 0x00000000
3463 # Register : PCCFG @ 0XFD070400</p>
3465 # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
3466 # s every AXI burst into multiple HIF commands, using the memory burst len
3467 # gth as a unit. If set to 1, then XPI will use half of the memory burst l
3468 # ength as a unit. This applies to both reads and writes. When MSTR.data_b
3469 # us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
3470 # n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
3471 # is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
3472 # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
3473 # ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
3474 # L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
3475 # d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
3476 # R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
3477 # t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
3478 # CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
3480 # PSU_DDRC_PCCFG_BL_EXP_MODE 0x0
3482 # Page match four limit. If set to 1, limits the number of consecutive sam
3483 # e page DDRC transactions that can be granted by the Port Arbiter to four
3484 # when Page Match feature is enabled. If set to 0, there is no limit impo
3485 # sed on number of consecutive same page DDRC transactions.
3486 # PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0
3488 # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
3489 # pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
3490 # urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
3491 # go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
3492 # t DDRC are driven to 1b'0.
3493 # PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1
3495 # Port Common Configuration Register
3496 #(OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) */
3497 mask_write 0XFD070400 0x00000111 0x00000001
3498 # Register : PCFGR_0 @ 0XFD070404</p>
3500 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3501 # ng port is granted, the port is continued to be granted if the following
3502 # immediate commands are to the same memory page (same bank and same row)
3503 # . See also related PCCFG.pagematch_limit register.
3504 # PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0
3506 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
3507 # bled and arurgent is asserted by the master, that port becomes the highe
3508 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
3509 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
3510 # urgent signal can be asserted anytime and as long as required which is i
3511 # ndependent of address handshaking (it is not associated with any particu
3513 # PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1
3515 # If set to 1, enables aging function for the read channel of the port.
3516 # PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0
3518 # Determines the initial load value of read aging counters. These counters
3519 # will be parallel loaded after reset, or after each grant to the corresp
3520 # onding port. The aging counters down-count every clock cycle where the p
3521 # ort is requesting but not granted. The higher significant 5-bits of the
3522 # read aging counter sets the priority of the read channel of a given port
3523 # . Port's priority will increase as the higher significant 5-bits of the
3524 # counter starts to decrease. When the aging counter becomes 0, the corres
3525 # ponding port channel will have the highest priority level (timeout condi
3526 # tion - Priority0). For multi-port configurations, the aging counters can
3527 # not be used to set port priorities when external dynamic priority inputs
3528 # (arqos) are enabled (timeout is still applicable). For single port conf
3529 # igurations, the aging counters are only used when they timeout (become 0
3530 # ) to force read-write direction switching. In this case, external dynami
3531 # c priority input, arqos (for reads only) can still be used to set the DD
3532 # RC read priority (2 priority levels: low priority read - LPR, high prior
3533 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
3534 # s register field are tied internally to 2'b00.
3535 # PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf
3537 # Port n Configuration Read Register
3538 #(OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) */
3539 mask_write 0XFD070404 0x000073FF 0x0000200F
3540 # Register : PCFGW_0 @ 0XFD070408</p>
3542 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3543 # ng port is granted, the port is continued to be granted if the following
3544 # immediate commands are to the same memory page (same bank and same row)
3545 # . See also related PCCFG.pagematch_limit register.
3546 # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0
3548 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
3549 # bled and awurgent is asserted by the master, that port becomes the highe
3550 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
3551 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
3552 # serted anytime and as long as required which is independent of address h
3553 # andshaking (it is not associated with any particular command).
3554 # PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1
3556 # If set to 1, enables aging function for the write channel of the port.
3557 # PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0
3559 # Determines the initial load value of write aging counters. These counter
3560 # s will be parallel loaded after reset, or after each grant to the corres
3561 # ponding port. The aging counters down-count every clock cycle where the
3562 # port is requesting but not granted. The higher significant 5-bits of the
3563 # write aging counter sets the initial priority of the write channel of a
3564 # given port. Port's priority will increase as the higher significant 5-b
3565 # its of the counter starts to decrease. When the aging counter becomes 0,
3566 # the corresponding port channel will have the highest priority level. Fo
3567 # r multi-port configurations, the aging counters cannot be used to set po
3568 # rt priorities when external dynamic priority inputs (awqos) are enabled
3569 # (timeout is still applicable). For single port configurations, the aging
3570 # counters are only used when they timeout (become 0) to force read-write
3571 # direction switching. Note: The two LSBs of this register field are tied
3572 # internally to 2'b00.
3573 # PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf
3575 # Port n Configuration Write Register
3576 #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) */
3577 mask_write 0XFD070408 0x000073FF 0x0000200F
3578 # Register : PCTRL_0 @ 0XFD070490</p>
3581 # PSU_DDRC_PCTRL_0_PORT_EN 0x1
3583 # Port n Control Register
3584 #(OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) */
3585 mask_write 0XFD070490 0x00000001 0x00000001
3586 # Register : PCFGQOS0_0 @ 0XFD070494</p>
3588 # This bitfield indicates the traffic class of region 1. Valid values are:
3589 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
3590 # maps to the blue address queue. In this case, valid values are 0: LPR a
3591 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
3592 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
3594 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2
3596 # This bitfield indicates the traffic class of region 0. Valid values are:
3597 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
3598 # maps to the blue address queue. In this case, valid values are: 0: LPR
3599 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
3600 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
3602 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0
3604 # Separation level1 indicating the end of region0 mapping; start of region
3605 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
3606 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
3607 # lues are used directly as port priorities, where the higher the value co
3608 # rresponds to higher port priority. All of the map_level* registers must
3609 # be set to distinct values.
3610 # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb
3612 # Port n Read QoS Configuration Register 0
3613 #(OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) */
3614 mask_write 0XFD070494 0x0033000F 0x0020000B
3615 # Register : PCFGQOS1_0 @ 0XFD070498</p>
3617 # Specifies the timeout value for transactions mapped to the red address q
3619 # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0
3621 # Specifies the timeout value for transactions mapped to the blue address
3623 # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0
3625 # Port n Read QoS Configuration Register 1
3626 #(OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) */
3627 mask_write 0XFD070498 0x07FF07FF 0x00000000
3628 # Register : PCFGR_1 @ 0XFD0704B4</p>
3630 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3631 # ng port is granted, the port is continued to be granted if the following
3632 # immediate commands are to the same memory page (same bank and same row)
3633 # . See also related PCCFG.pagematch_limit register.
3634 # PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0
3636 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
3637 # bled and arurgent is asserted by the master, that port becomes the highe
3638 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
3639 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
3640 # urgent signal can be asserted anytime and as long as required which is i
3641 # ndependent of address handshaking (it is not associated with any particu
3643 # PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1
3645 # If set to 1, enables aging function for the read channel of the port.
3646 # PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0
3648 # Determines the initial load value of read aging counters. These counters
3649 # will be parallel loaded after reset, or after each grant to the corresp
3650 # onding port. The aging counters down-count every clock cycle where the p
3651 # ort is requesting but not granted. The higher significant 5-bits of the
3652 # read aging counter sets the priority of the read channel of a given port
3653 # . Port's priority will increase as the higher significant 5-bits of the
3654 # counter starts to decrease. When the aging counter becomes 0, the corres
3655 # ponding port channel will have the highest priority level (timeout condi
3656 # tion - Priority0). For multi-port configurations, the aging counters can
3657 # not be used to set port priorities when external dynamic priority inputs
3658 # (arqos) are enabled (timeout is still applicable). For single port conf
3659 # igurations, the aging counters are only used when they timeout (become 0
3660 # ) to force read-write direction switching. In this case, external dynami
3661 # c priority input, arqos (for reads only) can still be used to set the DD
3662 # RC read priority (2 priority levels: low priority read - LPR, high prior
3663 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
3664 # s register field are tied internally to 2'b00.
3665 # PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf
3667 # Port n Configuration Read Register
3668 #(OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) */
3669 mask_write 0XFD0704B4 0x000073FF 0x0000200F
3670 # Register : PCFGW_1 @ 0XFD0704B8</p>
3672 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3673 # ng port is granted, the port is continued to be granted if the following
3674 # immediate commands are to the same memory page (same bank and same row)
3675 # . See also related PCCFG.pagematch_limit register.
3676 # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0
3678 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
3679 # bled and awurgent is asserted by the master, that port becomes the highe
3680 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
3681 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
3682 # serted anytime and as long as required which is independent of address h
3683 # andshaking (it is not associated with any particular command).
3684 # PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1
3686 # If set to 1, enables aging function for the write channel of the port.
3687 # PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0
3689 # Determines the initial load value of write aging counters. These counter
3690 # s will be parallel loaded after reset, or after each grant to the corres
3691 # ponding port. The aging counters down-count every clock cycle where the
3692 # port is requesting but not granted. The higher significant 5-bits of the
3693 # write aging counter sets the initial priority of the write channel of a
3694 # given port. Port's priority will increase as the higher significant 5-b
3695 # its of the counter starts to decrease. When the aging counter becomes 0,
3696 # the corresponding port channel will have the highest priority level. Fo
3697 # r multi-port configurations, the aging counters cannot be used to set po
3698 # rt priorities when external dynamic priority inputs (awqos) are enabled
3699 # (timeout is still applicable). For single port configurations, the aging
3700 # counters are only used when they timeout (become 0) to force read-write
3701 # direction switching. Note: The two LSBs of this register field are tied
3702 # internally to 2'b00.
3703 # PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf
3705 # Port n Configuration Write Register
3706 #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) */
3707 mask_write 0XFD0704B8 0x000073FF 0x0000200F
3708 # Register : PCTRL_1 @ 0XFD070540</p>
3711 # PSU_DDRC_PCTRL_1_PORT_EN 0x1
3713 # Port n Control Register
3714 #(OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) */
3715 mask_write 0XFD070540 0x00000001 0x00000001
3716 # Register : PCFGQOS0_1 @ 0XFD070544</p>
3718 # This bitfield indicates the traffic class of region2. For dual address q
3719 # ueue configurations, region2 maps to the red address queue. Valid values
3720 # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
3721 # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
3722 # ased to LPR traffic.
3723 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2
3725 # This bitfield indicates the traffic class of region 1. Valid values are:
3726 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
3727 # maps to the blue address queue. In this case, valid values are 0: LPR a
3728 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
3729 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
3731 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0
3733 # This bitfield indicates the traffic class of region 0. Valid values are:
3734 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
3735 # maps to the blue address queue. In this case, valid values are: 0: LPR
3736 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
3737 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
3739 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0
3741 # Separation level2 indicating the end of region1 mapping; start of region
3742 # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
3743 # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
3744 # that for PA, arqos values are used directly as port priorities, where t
3745 # he higher the value corresponds to higher port priority. All of the map_
3746 # level* registers must be set to distinct values.
3747 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb
3749 # Separation level1 indicating the end of region0 mapping; start of region
3750 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
3751 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
3752 # lues are used directly as port priorities, where the higher the value co
3753 # rresponds to higher port priority. All of the map_level* registers must
3754 # be set to distinct values.
3755 # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3
3757 # Port n Read QoS Configuration Register 0
3758 #(OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) */
3759 mask_write 0XFD070544 0x03330F0F 0x02000B03
3760 # Register : PCFGQOS1_1 @ 0XFD070548</p>
3762 # Specifies the timeout value for transactions mapped to the red address q
3764 # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0
3766 # Specifies the timeout value for transactions mapped to the blue address
3768 # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0
3770 # Port n Read QoS Configuration Register 1
3771 #(OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) */
3772 mask_write 0XFD070548 0x07FF07FF 0x00000000
3773 # Register : PCFGR_2 @ 0XFD070564</p>
3775 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3776 # ng port is granted, the port is continued to be granted if the following
3777 # immediate commands are to the same memory page (same bank and same row)
3778 # . See also related PCCFG.pagematch_limit register.
3779 # PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0
3781 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
3782 # bled and arurgent is asserted by the master, that port becomes the highe
3783 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
3784 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
3785 # urgent signal can be asserted anytime and as long as required which is i
3786 # ndependent of address handshaking (it is not associated with any particu
3788 # PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1
3790 # If set to 1, enables aging function for the read channel of the port.
3791 # PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0
3793 # Determines the initial load value of read aging counters. These counters
3794 # will be parallel loaded after reset, or after each grant to the corresp
3795 # onding port. The aging counters down-count every clock cycle where the p
3796 # ort is requesting but not granted. The higher significant 5-bits of the
3797 # read aging counter sets the priority of the read channel of a given port
3798 # . Port's priority will increase as the higher significant 5-bits of the
3799 # counter starts to decrease. When the aging counter becomes 0, the corres
3800 # ponding port channel will have the highest priority level (timeout condi
3801 # tion - Priority0). For multi-port configurations, the aging counters can
3802 # not be used to set port priorities when external dynamic priority inputs
3803 # (arqos) are enabled (timeout is still applicable). For single port conf
3804 # igurations, the aging counters are only used when they timeout (become 0
3805 # ) to force read-write direction switching. In this case, external dynami
3806 # c priority input, arqos (for reads only) can still be used to set the DD
3807 # RC read priority (2 priority levels: low priority read - LPR, high prior
3808 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
3809 # s register field are tied internally to 2'b00.
3810 # PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf
3812 # Port n Configuration Read Register
3813 #(OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) */
3814 mask_write 0XFD070564 0x000073FF 0x0000200F
3815 # Register : PCFGW_2 @ 0XFD070568</p>
3817 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3818 # ng port is granted, the port is continued to be granted if the following
3819 # immediate commands are to the same memory page (same bank and same row)
3820 # . See also related PCCFG.pagematch_limit register.
3821 # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0
3823 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
3824 # bled and awurgent is asserted by the master, that port becomes the highe
3825 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
3826 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
3827 # serted anytime and as long as required which is independent of address h
3828 # andshaking (it is not associated with any particular command).
3829 # PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1
3831 # If set to 1, enables aging function for the write channel of the port.
3832 # PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0
3834 # Determines the initial load value of write aging counters. These counter
3835 # s will be parallel loaded after reset, or after each grant to the corres
3836 # ponding port. The aging counters down-count every clock cycle where the
3837 # port is requesting but not granted. The higher significant 5-bits of the
3838 # write aging counter sets the initial priority of the write channel of a
3839 # given port. Port's priority will increase as the higher significant 5-b
3840 # its of the counter starts to decrease. When the aging counter becomes 0,
3841 # the corresponding port channel will have the highest priority level. Fo
3842 # r multi-port configurations, the aging counters cannot be used to set po
3843 # rt priorities when external dynamic priority inputs (awqos) are enabled
3844 # (timeout is still applicable). For single port configurations, the aging
3845 # counters are only used when they timeout (become 0) to force read-write
3846 # direction switching. Note: The two LSBs of this register field are tied
3847 # internally to 2'b00.
3848 # PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf
3850 # Port n Configuration Write Register
3851 #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) */
3852 mask_write 0XFD070568 0x000073FF 0x0000200F
3853 # Register : PCTRL_2 @ 0XFD0705F0</p>
3856 # PSU_DDRC_PCTRL_2_PORT_EN 0x1
3858 # Port n Control Register
3859 #(OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) */
3860 mask_write 0XFD0705F0 0x00000001 0x00000001
3861 # Register : PCFGQOS0_2 @ 0XFD0705F4</p>
3863 # This bitfield indicates the traffic class of region2. For dual address q
3864 # ueue configurations, region2 maps to the red address queue. Valid values
3865 # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
3866 # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
3867 # ased to LPR traffic.
3868 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2
3870 # This bitfield indicates the traffic class of region 1. Valid values are:
3871 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
3872 # maps to the blue address queue. In this case, valid values are 0: LPR a
3873 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
3874 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
3876 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0
3878 # This bitfield indicates the traffic class of region 0. Valid values are:
3879 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
3880 # maps to the blue address queue. In this case, valid values are: 0: LPR
3881 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
3882 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
3884 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0
3886 # Separation level2 indicating the end of region1 mapping; start of region
3887 # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
3888 # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
3889 # that for PA, arqos values are used directly as port priorities, where t
3890 # he higher the value corresponds to higher port priority. All of the map_
3891 # level* registers must be set to distinct values.
3892 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb
3894 # Separation level1 indicating the end of region0 mapping; start of region
3895 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
3896 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
3897 # lues are used directly as port priorities, where the higher the value co
3898 # rresponds to higher port priority. All of the map_level* registers must
3899 # be set to distinct values.
3900 # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3
3902 # Port n Read QoS Configuration Register 0
3903 #(OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) */
3904 mask_write 0XFD0705F4 0x03330F0F 0x02000B03
3905 # Register : PCFGQOS1_2 @ 0XFD0705F8</p>
3907 # Specifies the timeout value for transactions mapped to the red address q
3909 # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0
3911 # Specifies the timeout value for transactions mapped to the blue address
3913 # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0
3915 # Port n Read QoS Configuration Register 1
3916 #(OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) */
3917 mask_write 0XFD0705F8 0x07FF07FF 0x00000000
3918 # Register : PCFGR_3 @ 0XFD070614</p>
3920 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3921 # ng port is granted, the port is continued to be granted if the following
3922 # immediate commands are to the same memory page (same bank and same row)
3923 # . See also related PCCFG.pagematch_limit register.
3924 # PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0
3926 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
3927 # bled and arurgent is asserted by the master, that port becomes the highe
3928 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
3929 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
3930 # urgent signal can be asserted anytime and as long as required which is i
3931 # ndependent of address handshaking (it is not associated with any particu
3933 # PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1
3935 # If set to 1, enables aging function for the read channel of the port.
3936 # PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0
3938 # Determines the initial load value of read aging counters. These counters
3939 # will be parallel loaded after reset, or after each grant to the corresp
3940 # onding port. The aging counters down-count every clock cycle where the p
3941 # ort is requesting but not granted. The higher significant 5-bits of the
3942 # read aging counter sets the priority of the read channel of a given port
3943 # . Port's priority will increase as the higher significant 5-bits of the
3944 # counter starts to decrease. When the aging counter becomes 0, the corres
3945 # ponding port channel will have the highest priority level (timeout condi
3946 # tion - Priority0). For multi-port configurations, the aging counters can
3947 # not be used to set port priorities when external dynamic priority inputs
3948 # (arqos) are enabled (timeout is still applicable). For single port conf
3949 # igurations, the aging counters are only used when they timeout (become 0
3950 # ) to force read-write direction switching. In this case, external dynami
3951 # c priority input, arqos (for reads only) can still be used to set the DD
3952 # RC read priority (2 priority levels: low priority read - LPR, high prior
3953 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
3954 # s register field are tied internally to 2'b00.
3955 # PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf
3957 # Port n Configuration Read Register
3958 #(OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) */
3959 mask_write 0XFD070614 0x000073FF 0x0000200F
3960 # Register : PCFGW_3 @ 0XFD070618</p>
3962 # If set to 1, enables the Page Match feature. If enabled, once a requesti
3963 # ng port is granted, the port is continued to be granted if the following
3964 # immediate commands are to the same memory page (same bank and same row)
3965 # . See also related PCCFG.pagematch_limit register.
3966 # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0
3968 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
3969 # bled and awurgent is asserted by the master, that port becomes the highe
3970 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
3971 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
3972 # serted anytime and as long as required which is independent of address h
3973 # andshaking (it is not associated with any particular command).
3974 # PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1
3976 # If set to 1, enables aging function for the write channel of the port.
3977 # PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0
3979 # Determines the initial load value of write aging counters. These counter
3980 # s will be parallel loaded after reset, or after each grant to the corres
3981 # ponding port. The aging counters down-count every clock cycle where the
3982 # port is requesting but not granted. The higher significant 5-bits of the
3983 # write aging counter sets the initial priority of the write channel of a
3984 # given port. Port's priority will increase as the higher significant 5-b
3985 # its of the counter starts to decrease. When the aging counter becomes 0,
3986 # the corresponding port channel will have the highest priority level. Fo
3987 # r multi-port configurations, the aging counters cannot be used to set po
3988 # rt priorities when external dynamic priority inputs (awqos) are enabled
3989 # (timeout is still applicable). For single port configurations, the aging
3990 # counters are only used when they timeout (become 0) to force read-write
3991 # direction switching. Note: The two LSBs of this register field are tied
3992 # internally to 2'b00.
3993 # PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf
3995 # Port n Configuration Write Register
3996 #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) */
3997 mask_write 0XFD070618 0x000073FF 0x0000200F
3998 # Register : PCTRL_3 @ 0XFD0706A0</p>
4001 # PSU_DDRC_PCTRL_3_PORT_EN 0x1
4003 # Port n Control Register
4004 #(OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) */
4005 mask_write 0XFD0706A0 0x00000001 0x00000001
4006 # Register : PCFGQOS0_3 @ 0XFD0706A4</p>
4008 # This bitfield indicates the traffic class of region 1. Valid values are:
4009 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4010 # maps to the blue address queue. In this case, valid values are 0: LPR a
4011 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4012 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4014 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1
4016 # This bitfield indicates the traffic class of region 0. Valid values are:
4017 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4018 # maps to the blue address queue. In this case, valid values are: 0: LPR
4019 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4020 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4022 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0
4024 # Separation level1 indicating the end of region0 mapping; start of region
4025 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4026 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4027 # lues are used directly as port priorities, where the higher the value co
4028 # rresponds to higher port priority. All of the map_level* registers must
4029 # be set to distinct values.
4030 # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3
4032 # Port n Read QoS Configuration Register 0
4033 #(OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) */
4034 mask_write 0XFD0706A4 0x0033000F 0x00100003
4035 # Register : PCFGQOS1_3 @ 0XFD0706A8</p>
4037 # Specifies the timeout value for transactions mapped to the red address q
4039 # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0
4041 # Specifies the timeout value for transactions mapped to the blue address
4043 # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f
4045 # Port n Read QoS Configuration Register 1
4046 #(OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) */
4047 mask_write 0XFD0706A8 0x07FF07FF 0x0000004F
4048 # Register : PCFGWQOS0_3 @ 0XFD0706AC</p>
4050 # This bitfield indicates the traffic class of region 1. Valid values are:
4051 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4052 # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
4054 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1
4056 # This bitfield indicates the traffic class of region 0. Valid values are:
4057 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4058 # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
4060 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0
4062 # Separation level indicating the end of region0 mapping; start of region0
4063 # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
4064 # . Note that for PA, awqos values are used directly as port priorities, w
4065 # here the higher the value corresponds to higher port priority.
4066 # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3
4068 # Port n Write QoS Configuration Register 0
4069 #(OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) */
4070 mask_write 0XFD0706AC 0x0033000F 0x00100003
4071 # Register : PCFGWQOS1_3 @ 0XFD0706B0</p>
4073 # Specifies the timeout value for write transactions.
4074 # PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f
4076 # Port n Write QoS Configuration Register 1
4077 #(OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) */
4078 mask_write 0XFD0706B0 0x000007FF 0x0000004F
4079 # Register : PCFGR_4 @ 0XFD0706C4</p>
4081 # If set to 1, enables the Page Match feature. If enabled, once a requesti
4082 # ng port is granted, the port is continued to be granted if the following
4083 # immediate commands are to the same memory page (same bank and same row)
4084 # . See also related PCCFG.pagematch_limit register.
4085 # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0
4087 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4088 # bled and arurgent is asserted by the master, that port becomes the highe
4089 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4090 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4091 # urgent signal can be asserted anytime and as long as required which is i
4092 # ndependent of address handshaking (it is not associated with any particu
4094 # PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1
4096 # If set to 1, enables aging function for the read channel of the port.
4097 # PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0
4099 # Determines the initial load value of read aging counters. These counters
4100 # will be parallel loaded after reset, or after each grant to the corresp
4101 # onding port. The aging counters down-count every clock cycle where the p
4102 # ort is requesting but not granted. The higher significant 5-bits of the
4103 # read aging counter sets the priority of the read channel of a given port
4104 # . Port's priority will increase as the higher significant 5-bits of the
4105 # counter starts to decrease. When the aging counter becomes 0, the corres
4106 # ponding port channel will have the highest priority level (timeout condi
4107 # tion - Priority0). For multi-port configurations, the aging counters can
4108 # not be used to set port priorities when external dynamic priority inputs
4109 # (arqos) are enabled (timeout is still applicable). For single port conf
4110 # igurations, the aging counters are only used when they timeout (become 0
4111 # ) to force read-write direction switching. In this case, external dynami
4112 # c priority input, arqos (for reads only) can still be used to set the DD
4113 # RC read priority (2 priority levels: low priority read - LPR, high prior
4114 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4115 # s register field are tied internally to 2'b00.
4116 # PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf
4118 # Port n Configuration Read Register
4119 #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) */
4120 mask_write 0XFD0706C4 0x000073FF 0x0000200F
4121 # Register : PCFGW_4 @ 0XFD0706C8</p>
4123 # If set to 1, enables the Page Match feature. If enabled, once a requesti
4124 # ng port is granted, the port is continued to be granted if the following
4125 # immediate commands are to the same memory page (same bank and same row)
4126 # . See also related PCCFG.pagematch_limit register.
4127 # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0
4129 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4130 # bled and awurgent is asserted by the master, that port becomes the highe
4131 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4132 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4133 # serted anytime and as long as required which is independent of address h
4134 # andshaking (it is not associated with any particular command).
4135 # PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1
4137 # If set to 1, enables aging function for the write channel of the port.
4138 # PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0
4140 # Determines the initial load value of write aging counters. These counter
4141 # s will be parallel loaded after reset, or after each grant to the corres
4142 # ponding port. The aging counters down-count every clock cycle where the
4143 # port is requesting but not granted. The higher significant 5-bits of the
4144 # write aging counter sets the initial priority of the write channel of a
4145 # given port. Port's priority will increase as the higher significant 5-b
4146 # its of the counter starts to decrease. When the aging counter becomes 0,
4147 # the corresponding port channel will have the highest priority level. Fo
4148 # r multi-port configurations, the aging counters cannot be used to set po
4149 # rt priorities when external dynamic priority inputs (awqos) are enabled
4150 # (timeout is still applicable). For single port configurations, the aging
4151 # counters are only used when they timeout (become 0) to force read-write
4152 # direction switching. Note: The two LSBs of this register field are tied
4153 # internally to 2'b00.
4154 # PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf
4156 # Port n Configuration Write Register
4157 #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) */
4158 mask_write 0XFD0706C8 0x000073FF 0x0000200F
4159 # Register : PCTRL_4 @ 0XFD070750</p>
4162 # PSU_DDRC_PCTRL_4_PORT_EN 0x1
4164 # Port n Control Register
4165 #(OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) */
4166 mask_write 0XFD070750 0x00000001 0x00000001
4167 # Register : PCFGQOS0_4 @ 0XFD070754</p>
4169 # This bitfield indicates the traffic class of region 1. Valid values are:
4170 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4171 # maps to the blue address queue. In this case, valid values are 0: LPR a
4172 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4173 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4175 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1
4177 # This bitfield indicates the traffic class of region 0. Valid values are:
4178 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4179 # maps to the blue address queue. In this case, valid values are: 0: LPR
4180 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4181 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4183 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0
4185 # Separation level1 indicating the end of region0 mapping; start of region
4186 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4187 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4188 # lues are used directly as port priorities, where the higher the value co
4189 # rresponds to higher port priority. All of the map_level* registers must
4190 # be set to distinct values.
4191 # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3
4193 # Port n Read QoS Configuration Register 0
4194 #(OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) */
4195 mask_write 0XFD070754 0x0033000F 0x00100003
4196 # Register : PCFGQOS1_4 @ 0XFD070758</p>
4198 # Specifies the timeout value for transactions mapped to the red address q
4200 # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0
4202 # Specifies the timeout value for transactions mapped to the blue address
4204 # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f
4206 # Port n Read QoS Configuration Register 1
4207 #(OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) */
4208 mask_write 0XFD070758 0x07FF07FF 0x0000004F
4209 # Register : PCFGWQOS0_4 @ 0XFD07075C</p>
4211 # This bitfield indicates the traffic class of region 1. Valid values are:
4212 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4213 # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
4215 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1
4217 # This bitfield indicates the traffic class of region 0. Valid values are:
4218 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4219 # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
4221 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0
4223 # Separation level indicating the end of region0 mapping; start of region0
4224 # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
4225 # . Note that for PA, awqos values are used directly as port priorities, w
4226 # here the higher the value corresponds to higher port priority.
4227 # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3
4229 # Port n Write QoS Configuration Register 0
4230 #(OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) */
4231 mask_write 0XFD07075C 0x0033000F 0x00100003
4232 # Register : PCFGWQOS1_4 @ 0XFD070760</p>
4234 # Specifies the timeout value for write transactions.
4235 # PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f
4237 # Port n Write QoS Configuration Register 1
4238 #(OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) */
4239 mask_write 0XFD070760 0x000007FF 0x0000004F
4240 # Register : PCFGR_5 @ 0XFD070774</p>
4242 # If set to 1, enables the Page Match feature. If enabled, once a requesti
4243 # ng port is granted, the port is continued to be granted if the following
4244 # immediate commands are to the same memory page (same bank and same row)
4245 # . See also related PCCFG.pagematch_limit register.
4246 # PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0
4248 # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
4249 # bled and arurgent is asserted by the master, that port becomes the highe
4250 # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
4251 # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
4252 # urgent signal can be asserted anytime and as long as required which is i
4253 # ndependent of address handshaking (it is not associated with any particu
4255 # PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1
4257 # If set to 1, enables aging function for the read channel of the port.
4258 # PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0
4260 # Determines the initial load value of read aging counters. These counters
4261 # will be parallel loaded after reset, or after each grant to the corresp
4262 # onding port. The aging counters down-count every clock cycle where the p
4263 # ort is requesting but not granted. The higher significant 5-bits of the
4264 # read aging counter sets the priority of the read channel of a given port
4265 # . Port's priority will increase as the higher significant 5-bits of the
4266 # counter starts to decrease. When the aging counter becomes 0, the corres
4267 # ponding port channel will have the highest priority level (timeout condi
4268 # tion - Priority0). For multi-port configurations, the aging counters can
4269 # not be used to set port priorities when external dynamic priority inputs
4270 # (arqos) are enabled (timeout is still applicable). For single port conf
4271 # igurations, the aging counters are only used when they timeout (become 0
4272 # ) to force read-write direction switching. In this case, external dynami
4273 # c priority input, arqos (for reads only) can still be used to set the DD
4274 # RC read priority (2 priority levels: low priority read - LPR, high prior
4275 # ity read - HPR) on a command by command basis. Note: The two LSBs of thi
4276 # s register field are tied internally to 2'b00.
4277 # PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf
4279 # Port n Configuration Read Register
4280 #(OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) */
4281 mask_write 0XFD070774 0x000073FF 0x0000200F
4282 # Register : PCFGW_5 @ 0XFD070778</p>
4284 # If set to 1, enables the Page Match feature. If enabled, once a requesti
4285 # ng port is granted, the port is continued to be granted if the following
4286 # immediate commands are to the same memory page (same bank and same row)
4287 # . See also related PCCFG.pagematch_limit register.
4288 # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0
4290 # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
4291 # bled and awurgent is asserted by the master, that port becomes the highe
4292 # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
4293 # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
4294 # serted anytime and as long as required which is independent of address h
4295 # andshaking (it is not associated with any particular command).
4296 # PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1
4298 # If set to 1, enables aging function for the write channel of the port.
4299 # PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0
4301 # Determines the initial load value of write aging counters. These counter
4302 # s will be parallel loaded after reset, or after each grant to the corres
4303 # ponding port. The aging counters down-count every clock cycle where the
4304 # port is requesting but not granted. The higher significant 5-bits of the
4305 # write aging counter sets the initial priority of the write channel of a
4306 # given port. Port's priority will increase as the higher significant 5-b
4307 # its of the counter starts to decrease. When the aging counter becomes 0,
4308 # the corresponding port channel will have the highest priority level. Fo
4309 # r multi-port configurations, the aging counters cannot be used to set po
4310 # rt priorities when external dynamic priority inputs (awqos) are enabled
4311 # (timeout is still applicable). For single port configurations, the aging
4312 # counters are only used when they timeout (become 0) to force read-write
4313 # direction switching. Note: The two LSBs of this register field are tied
4314 # internally to 2'b00.
4315 # PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf
4317 # Port n Configuration Write Register
4318 #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) */
4319 mask_write 0XFD070778 0x000073FF 0x0000200F
4320 # Register : PCTRL_5 @ 0XFD070800</p>
4323 # PSU_DDRC_PCTRL_5_PORT_EN 0x1
4325 # Port n Control Register
4326 #(OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) */
4327 mask_write 0XFD070800 0x00000001 0x00000001
4328 # Register : PCFGQOS0_5 @ 0XFD070804</p>
4330 # This bitfield indicates the traffic class of region 1. Valid values are:
4331 # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
4332 # maps to the blue address queue. In this case, valid values are 0: LPR a
4333 # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
4334 # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
4336 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1
4338 # This bitfield indicates the traffic class of region 0. Valid values are:
4339 # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
4340 # maps to the blue address queue. In this case, valid values are: 0: LPR
4341 # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
4342 # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
4344 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0
4346 # Separation level1 indicating the end of region0 mapping; start of region
4347 # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
4348 # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
4349 # lues are used directly as port priorities, where the higher the value co
4350 # rresponds to higher port priority. All of the map_level* registers must
4351 # be set to distinct values.
4352 # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3
4354 # Port n Read QoS Configuration Register 0
4355 #(OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) */
4356 mask_write 0XFD070804 0x0033000F 0x00100003
4357 # Register : PCFGQOS1_5 @ 0XFD070808</p>
4359 # Specifies the timeout value for transactions mapped to the red address q
4361 # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0
4363 # Specifies the timeout value for transactions mapped to the blue address
4365 # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f
4367 # Port n Read QoS Configuration Register 1
4368 #(OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) */
4369 mask_write 0XFD070808 0x07FF07FF 0x0000004F
4370 # Register : PCFGWQOS0_5 @ 0XFD07080C</p>
4372 # This bitfield indicates the traffic class of region 1. Valid values are:
4373 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4374 # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
4376 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1
4378 # This bitfield indicates the traffic class of region 0. Valid values are:
4379 # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
4380 # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
4382 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0
4384 # Separation level indicating the end of region0 mapping; start of region0
4385 # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
4386 # . Note that for PA, awqos values are used directly as port priorities, w
4387 # here the higher the value corresponds to higher port priority.
4388 # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3
4390 # Port n Write QoS Configuration Register 0
4391 #(OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) */
4392 mask_write 0XFD07080C 0x0033000F 0x00100003
4393 # Register : PCFGWQOS1_5 @ 0XFD070810</p>
4395 # Specifies the timeout value for write transactions.
4396 # PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f
4398 # Port n Write QoS Configuration Register 1
4399 #(OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) */
4400 mask_write 0XFD070810 0x000007FF 0x0000004F
4401 # Register : SARBASE0 @ 0XFD070F04</p>
4403 # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
4404 # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
4405 # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
4406 # PSU_DDRC_SARBASE0_BASE_ADDR 0x0
4408 # SAR Base Address Register n
4409 #(OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) */
4410 mask_write 0XFD070F04 0x000001FF 0x00000000
4411 # Register : SARSIZE0 @ 0XFD070F08</p>
4413 # Number of blocks for address region n. This register determines the tota
4414 # l size of the region in multiples of minimum block size as specified by
4415 # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
4416 # as number of blocks = nblocks + 1. For example, if register is programme
4417 # d to 0, region will have 1 block.
4418 # PSU_DDRC_SARSIZE0_NBLOCKS 0x0
4420 # SAR Size Register n
4421 #(OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) */
4422 mask_write 0XFD070F08 0x000000FF 0x00000000
4423 # Register : SARBASE1 @ 0XFD070F0C</p>
4425 # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
4426 # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
4427 # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
4428 # PSU_DDRC_SARBASE1_BASE_ADDR 0x10
4430 # SAR Base Address Register n
4431 #(OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) */
4432 mask_write 0XFD070F0C 0x000001FF 0x00000010
4433 # Register : SARSIZE1 @ 0XFD070F10</p>
4435 # Number of blocks for address region n. This register determines the tota
4436 # l size of the region in multiples of minimum block size as specified by
4437 # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
4438 # as number of blocks = nblocks + 1. For example, if register is programme
4439 # d to 0, region will have 1 block.
4440 # PSU_DDRC_SARSIZE1_NBLOCKS 0xf
4442 # SAR Size Register n
4443 #(OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) */
4444 mask_write 0XFD070F10 0x000000FF 0x0000000F
4445 # Register : DFITMG0_SHADOW @ 0XFD072190</p>
4447 # Specifies the number of DFI clock cycles after an assertion or de-assert
4448 # ion of the DFI control signals that the control signals at the PHY-DRAM
4449 # interface reflect the assertion or de-assertion. If the DFI clock and th
4450 # e memory clock are not phase-aligned, this timing parameter should be ro
4451 # unded up to the next integer value. Note that if using RDIMM, it is nece
4452 # ssary to increment this parameter by RDIMM's extra cycle of latency in t
4453 # erms of DFI clock.
4454 # PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7
4456 # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
4457 # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
4458 # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
4459 # - 1 in terms of SDR clock cycles Refer to PHY specification for correct
4461 # PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1
4463 # Time from the assertion of a read command on the DFI interface to the as
4464 # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
4465 # ect value. This corresponds to the DFI parameter trddata_en. Note that,
4466 # depending on the PHY, if using RDIMM, it may be necessary to use the val
4467 # ue (CL + 1) in the calculation of trddata_en. This is to compensate for
4468 # the extra cycle of latency through the RDIMM. Unit: Clocks
4469 # PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2
4471 # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
4472 # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
4473 # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
4474 # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
4475 # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
4476 # n for correct value.
4477 # PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1
4479 # Specifies the number of clock cycles between when dfi_wrdata_en is asser
4480 # ted to when the associated write data is driven on the dfi_wrdata signal
4481 # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
4482 # specification for correct value. Note, max supported value is 8. Unit:
4484 # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0
4486 # Write latency Number of clocks from the write command to write data enab
4487 # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
4488 # lat. Refer to PHY specification for correct value.Note that, depending o
4489 # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
4490 # in the calculation of tphy_wrlat. This is to compensate for the extra c
4491 # ycle of latency through the RDIMM.
4492 # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2
4494 # DFI Timing Shadow Register 0
4495 #(OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) */
4496 mask_write 0XFD072190 0x1FBFBF3F 0x07828002
4497 # : DDR CONTROLLER RESET
4498 # Register : RST_DDR_SS @ 0XFD1A0108</p>
4500 # DDR block level reset inside of the DDR Sub System
4501 # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0
4503 # APM block level reset inside of the DDR Sub System
4504 # PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0
4506 # DDR sub system block level reset
4507 #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) */
4508 mask_write 0XFD1A0108 0x0000000C 0x00000000
4510 # Register : PGCR0 @ 0XFD080010</p>
4513 # PSU_DDR_PHY_PGCR0_ADCP 0x0
4515 # Reserved. Returns zeroes on reads.
4516 # PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0
4519 # PSU_DDR_PHY_PGCR0_PHYFRST 0x1
4521 # Oscillator Mode Address/Command Delay Line Select
4522 # PSU_DDR_PHY_PGCR0_OSCACDL 0x3
4524 # Reserved. Returns zeroes on reads.
4525 # PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0
4527 # Digital Test Output Select
4528 # PSU_DDR_PHY_PGCR0_DTOSEL 0x0
4530 # Reserved. Returns zeroes on reads.
4531 # PSU_DDR_PHY_PGCR0_RESERVED_13 0x0
4533 # Oscillator Mode Division
4534 # PSU_DDR_PHY_PGCR0_OSCDIV 0xf
4537 # PSU_DDR_PHY_PGCR0_OSCEN 0x0
4539 # Reserved. Returns zeroes on reads.
4540 # PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0
4542 # PHY General Configuration Register 0
4543 #(OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) */
4544 mask_write 0XFD080010 0xFFFFFFFF 0x07001E00
4545 # Register : PGCR2 @ 0XFD080018</p>
4547 # Clear Training Status Registers
4548 # PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0
4550 # Clear Impedance Calibration
4551 # PSU_DDR_PHY_PGCR2_CLRZCAL 0x0
4553 # Clear Parity Error
4554 # PSU_DDR_PHY_PGCR2_CLRPERR 0x0
4556 # Initialization Complete Pin Configuration
4557 # PSU_DDR_PHY_PGCR2_ICPC 0x0
4559 # Data Training PUB Mode Exit Timer
4560 # PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf
4562 # Initialization Bypass
4563 # PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0
4566 # PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0
4569 # PSU_DDR_PHY_PGCR2_TREFPRD 0x10010
4571 # PHY General Configuration Register 2
4572 #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) */
4573 mask_write 0XFD080018 0xFFFFFFFF 0x00F10010
4574 # Register : PGCR3 @ 0XFD08001C</p>
4577 # PSU_DDR_PHY_PGCR3_CKNEN 0x55
4580 # PSU_DDR_PHY_PGCR3_CKEN 0xaa
4582 # Reserved. Return zeroes on reads.
4583 # PSU_DDR_PHY_PGCR3_RESERVED_15 0x0
4585 # Enable Clock Gating for AC [0] ctl_rd_clk
4586 # PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2
4588 # Enable Clock Gating for AC [0] ddr_clk
4589 # PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2
4591 # Enable Clock Gating for AC [0] ctl_clk
4592 # PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2
4594 # Reserved. Return zeroes on reads.
4595 # PSU_DDR_PHY_PGCR3_RESERVED_8 0x0
4597 # Controls DDL Bypass Modes
4598 # PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2
4600 # IO Loop-Back Select
4601 # PSU_DDR_PHY_PGCR3_IOLB 0x0
4603 # AC Receive FIFO Read Mode
4604 # PSU_DDR_PHY_PGCR3_RDMODE 0x0
4606 # Read FIFO Reset Disable
4607 # PSU_DDR_PHY_PGCR3_DISRST 0x0
4609 # Clock Level when Clock Gating
4610 # PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0
4612 # PHY General Configuration Register 3
4613 #(OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) */
4614 mask_write 0XFD08001C 0xFFFFFFFF 0x55AA5480
4615 # Register : PGCR5 @ 0XFD080024</p>
4617 # Frequency B Ratio Term
4618 # PSU_DDR_PHY_PGCR5_FRQBT 0x1
4620 # Frequency A Ratio Term
4621 # PSU_DDR_PHY_PGCR5_FRQAT 0x1
4623 # DFI Disconnect Time Period
4624 # PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0
4626 # Receiver bias core side control
4627 # PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf
4629 # Reserved. Return zeroes on reads.
4630 # PSU_DDR_PHY_PGCR5_RESERVED_3 0x0
4632 # Internal VREF generator REFSEL ragne select
4633 # PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1
4635 # DDL Page Read Write select
4636 # PSU_DDR_PHY_PGCR5_DDLPGACT 0x0
4638 # DDL Page Read Write select
4639 # PSU_DDR_PHY_PGCR5_DDLPGRW 0x0
4641 # PHY General Configuration Register 5
4642 #(OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) */
4643 mask_write 0XFD080024 0xFFFFFFFF 0x010100F4
4644 # Register : PTR0 @ 0XFD080040</p>
4646 # PLL Power-Down Time
4647 # PSU_DDR_PHY_PTR0_TPLLPD 0x56
4649 # PLL Gear Shift Time
4650 # PSU_DDR_PHY_PTR0_TPLLGS 0x2155
4653 # PSU_DDR_PHY_PTR0_TPHYRST 0x10
4655 # PHY Timing Register 0
4656 #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) */
4657 mask_write 0XFD080040 0xFFFFFFFF 0x0AC85550
4658 # Register : PTR1 @ 0XFD080044</p>
4661 # PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141
4663 # Reserved. Returns zeroes on reads.
4664 # PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0
4667 # PSU_DDR_PHY_PTR1_TPLLRST 0xaff
4669 # PHY Timing Register 1
4670 #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) */
4671 mask_write 0XFD080044 0xFFFFFFFF 0x41410AFF
4672 # Register : PLLCR0 @ 0XFD080068</p>
4675 # PSU_DDR_PHY_PLLCR0_PLLBYP 0x0
4678 # PSU_DDR_PHY_PLLCR0_PLLRST 0x0
4681 # PSU_DDR_PHY_PLLCR0_PLLPD 0x0
4683 # Reference Stop Mode
4684 # PSU_DDR_PHY_PLLCR0_RSTOPM 0x0
4686 # PLL Frequency Select
4687 # PSU_DDR_PHY_PLLCR0_FRQSEL 0x1
4690 # PSU_DDR_PHY_PLLCR0_RLOCKM 0x0
4692 # Charge Pump Proportional Current Control
4693 # PSU_DDR_PHY_PLLCR0_CPPC 0x8
4695 # Charge Pump Integrating Current Control
4696 # PSU_DDR_PHY_PLLCR0_CPIC 0x0
4699 # PSU_DDR_PHY_PLLCR0_GSHIFT 0x0
4701 # Reserved. Return zeroes on reads.
4702 # PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0
4704 # Analog Test Enable
4705 # PSU_DDR_PHY_PLLCR0_ATOEN 0x0
4707 # Analog Test Control
4708 # PSU_DDR_PHY_PLLCR0_ATC 0x0
4710 # Digital Test Control
4711 # PSU_DDR_PHY_PLLCR0_DTC 0x0
4713 # PLL Control Register 0 (Type B PLL Only)
4714 #(OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) */
4715 mask_write 0XFD080068 0xFFFFFFFF 0x01100000
4716 # Register : DSGCR @ 0XFD080090</p>
4718 # Reserved. Return zeroes on reads.
4719 # PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0
4721 # When RDBI enabled, this bit is used to select RDBI CL calculation, if it
4722 # is 1b1, calculation will use RDBICL, otherwise use default calculation.
4723 # PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0
4725 # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
4727 # PSU_DDR_PHY_DSGCR_RDBICL 0x2
4729 # PHY Impedance Update Enable
4730 # PSU_DDR_PHY_DSGCR_PHYZUEN 0x1
4732 # Reserved. Return zeroes on reads.
4733 # PSU_DDR_PHY_DSGCR_RESERVED_22 0x0
4735 # SDRAM Reset Output Enable
4736 # PSU_DDR_PHY_DSGCR_RSTOE 0x1
4738 # Single Data Rate Mode
4739 # PSU_DDR_PHY_DSGCR_SDRMODE 0x0
4741 # Reserved. Return zeroes on reads.
4742 # PSU_DDR_PHY_DSGCR_RESERVED_18 0x0
4744 # ATO Analog Test Enable
4745 # PSU_DDR_PHY_DSGCR_ATOAE 0x0
4748 # PSU_DDR_PHY_DSGCR_DTOOE 0x0
4751 # PSU_DDR_PHY_DSGCR_DTOIOM 0x0
4753 # DTO Power Down Receiver
4754 # PSU_DDR_PHY_DSGCR_DTOPDR 0x1
4756 # Reserved. Return zeroes on reads
4757 # PSU_DDR_PHY_DSGCR_RESERVED_13 0x0
4759 # DTO On-Die Termination
4760 # PSU_DDR_PHY_DSGCR_DTOODT 0x0
4762 # PHY Update Acknowledge Delay
4763 # PSU_DDR_PHY_DSGCR_PUAD 0x5
4765 # Controller Update Acknowledge Enable
4766 # PSU_DDR_PHY_DSGCR_CUAEN 0x1
4768 # Reserved. Return zeroes on reads
4769 # PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0
4771 # Controller Impedance Update Enable
4772 # PSU_DDR_PHY_DSGCR_CTLZUEN 0x0
4774 # Reserved. Return zeroes on reads
4775 # PSU_DDR_PHY_DSGCR_RESERVED_1 0x0
4777 # PHY Update Request Enable
4778 # PSU_DDR_PHY_DSGCR_PUREN 0x1
4780 # DDR System General Configuration Register
4781 #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) */
4782 mask_write 0XFD080090 0xFFFFFFFF 0x02A04161
4783 # Register : GPR0 @ 0XFD0800C0</p>
4785 # General Purpose Register 0
4786 # PSU_DDR_PHY_GPR0_GPR0 0xd3
4788 # General Purpose Register 0
4789 #(OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) */
4790 mask_write 0XFD0800C0 0xFFFFFFFF 0x000000D3
4791 # Register : DCR @ 0XFD080100</p>
4793 # DDR4 Gear Down Timing.
4794 # PSU_DDR_PHY_DCR_GEARDN 0x0
4796 # Un-used Bank Group
4797 # PSU_DDR_PHY_DCR_UBG 0x0
4799 # Un-buffered DIMM Address Mirroring
4800 # PSU_DDR_PHY_DCR_UDIMM 0x0
4803 # PSU_DDR_PHY_DCR_DDR2T 0x0
4805 # No Simultaneous Rank Access
4806 # PSU_DDR_PHY_DCR_NOSRA 0x1
4808 # Reserved. Return zeroes on reads.
4809 # PSU_DDR_PHY_DCR_RESERVED_26_18 0x0
4812 # PSU_DDR_PHY_DCR_BYTEMASK 0x1
4815 # PSU_DDR_PHY_DCR_DDRTYPE 0x0
4817 # Multi-Purpose Register (MPR) DQ (DDR3 Only)
4818 # PSU_DDR_PHY_DCR_MPRDQ 0x0
4820 # Primary DQ (DDR3 Only)
4821 # PSU_DDR_PHY_DCR_PDQ 0x0
4824 # PSU_DDR_PHY_DCR_DDR8BNK 0x1
4827 # PSU_DDR_PHY_DCR_DDRMD 0x4
4829 # DRAM Configuration Register
4830 #(OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) */
4831 mask_write 0XFD080100 0xFFFFFFFF 0x0800040C
4832 # Register : DTPR0 @ 0XFD080110</p>
4834 # Reserved. Return zeroes on reads.
4835 # PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0
4837 # Activate to activate command delay (different banks)
4838 # PSU_DDR_PHY_DTPR0_TRRD 0x6
4840 # Reserved. Return zeroes on reads.
4841 # PSU_DDR_PHY_DTPR0_RESERVED_23 0x0
4843 # Activate to precharge command delay
4844 # PSU_DDR_PHY_DTPR0_TRAS 0x24
4846 # Reserved. Return zeroes on reads.
4847 # PSU_DDR_PHY_DTPR0_RESERVED_15 0x0
4849 # Precharge command period
4850 # PSU_DDR_PHY_DTPR0_TRP 0xf
4852 # Reserved. Return zeroes on reads.
4853 # PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0
4855 # Internal read to precharge command delay
4856 # PSU_DDR_PHY_DTPR0_TRTP 0x8
4858 # DRAM Timing Parameters Register 0
4859 #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) */
4860 mask_write 0XFD080110 0xFFFFFFFF 0x06240F08
4861 # Register : DTPR1 @ 0XFD080114</p>
4863 # Reserved. Return zeroes on reads.
4864 # PSU_DDR_PHY_DTPR1_RESERVED_31 0x0
4866 # Minimum delay from when write leveling mode is programmed to the first D
4867 # QS/DQS# rising edge.
4868 # PSU_DDR_PHY_DTPR1_TWLMRD 0x28
4870 # Reserved. Return zeroes on reads.
4871 # PSU_DDR_PHY_DTPR1_RESERVED_23 0x0
4873 # 4-bank activate period
4874 # PSU_DDR_PHY_DTPR1_TFAW 0x20
4876 # Reserved. Return zeroes on reads.
4877 # PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0
4879 # Load mode update delay (DDR4 and DDR3 only)
4880 # PSU_DDR_PHY_DTPR1_TMOD 0x0
4882 # Reserved. Return zeroes on reads.
4883 # PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0
4885 # Load mode cycle time
4886 # PSU_DDR_PHY_DTPR1_TMRD 0x8
4888 # DRAM Timing Parameters Register 1
4889 #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) */
4890 mask_write 0XFD080114 0xFFFFFFFF 0x28200008
4891 # Register : DTPR2 @ 0XFD080118</p>
4893 # Reserved. Return zeroes on reads.
4894 # PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0
4896 # Read to Write command delay. Valid values are
4897 # PSU_DDR_PHY_DTPR2_TRTW 0x0
4899 # Reserved. Return zeroes on reads.
4900 # PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0
4902 # Read to ODT delay (DDR3 only)
4903 # PSU_DDR_PHY_DTPR2_TRTODT 0x0
4905 # Reserved. Return zeroes on reads.
4906 # PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0
4908 # CKE minimum pulse width
4909 # PSU_DDR_PHY_DTPR2_TCKE 0x7
4911 # Reserved. Return zeroes on reads.
4912 # PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0
4914 # Self refresh exit delay
4915 # PSU_DDR_PHY_DTPR2_TXS 0x300
4917 # DRAM Timing Parameters Register 2
4918 #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) */
4919 mask_write 0XFD080118 0xFFFFFFFF 0x00070300
4920 # Register : DTPR3 @ 0XFD08011C</p>
4922 # ODT turn-off delay extension
4923 # PSU_DDR_PHY_DTPR3_TOFDX 0x4
4925 # Read to read and write to write command delay
4926 # PSU_DDR_PHY_DTPR3_TCCD 0x0
4929 # PSU_DDR_PHY_DTPR3_TDLLK 0x300
4931 # Reserved. Return zeroes on reads.
4932 # PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0
4934 # Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
4935 # PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8
4937 # Reserved. Return zeroes on reads.
4938 # PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0
4940 # DQS output access time from CK/CK# (LPDDR2/3 only)
4941 # PSU_DDR_PHY_DTPR3_TDQSCK 0x0
4943 # DRAM Timing Parameters Register 3
4944 #(OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) */
4945 mask_write 0XFD08011C 0xFFFFFFFF 0x83000800
4946 # Register : DTPR4 @ 0XFD080120</p>
4948 # Reserved. Return zeroes on reads.
4949 # PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0
4951 # ODT turn-on/turn-off delays (DDR2 only)
4952 # PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0
4954 # Reserved. Return zeroes on reads.
4955 # PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0
4957 # Refresh-to-Refresh
4958 # PSU_DDR_PHY_DTPR4_TRFC 0x116
4960 # Reserved. Return zeroes on reads.
4961 # PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0
4963 # Write leveling output delay
4964 # PSU_DDR_PHY_DTPR4_TWLO 0x2b
4966 # Reserved. Return zeroes on reads.
4967 # PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0
4969 # Power down exit delay
4970 # PSU_DDR_PHY_DTPR4_TXP 0x7
4972 # DRAM Timing Parameters Register 4
4973 #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) */
4974 mask_write 0XFD080120 0xFFFFFFFF 0x01162B07
4975 # Register : DTPR5 @ 0XFD080124</p>
4977 # Reserved. Return zeroes on reads.
4978 # PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0
4980 # Activate to activate command delay (same bank)
4981 # PSU_DDR_PHY_DTPR5_TRC 0x33
4983 # Reserved. Return zeroes on reads.
4984 # PSU_DDR_PHY_DTPR5_RESERVED_15 0x0
4986 # Activate to read or write delay
4987 # PSU_DDR_PHY_DTPR5_TRCD 0xf
4989 # Reserved. Return zeroes on reads.
4990 # PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0
4992 # Internal write to read command delay
4993 # PSU_DDR_PHY_DTPR5_TWTR 0x8
4995 # DRAM Timing Parameters Register 5
4996 #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) */
4997 mask_write 0XFD080124 0xFFFFFFFF 0x00330F08
4998 # Register : DTPR6 @ 0XFD080128</p>
5000 # PUB Write Latency Enable
5001 # PSU_DDR_PHY_DTPR6_PUBWLEN 0x0
5003 # PUB Read Latency Enable
5004 # PSU_DDR_PHY_DTPR6_PUBRLEN 0x0
5006 # Reserved. Return zeroes on reads.
5007 # PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0
5010 # PSU_DDR_PHY_DTPR6_PUBWL 0xe
5012 # Reserved. Return zeroes on reads.
5013 # PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0
5016 # PSU_DDR_PHY_DTPR6_PUBRL 0xf
5018 # DRAM Timing Parameters Register 6
5019 #(OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) */
5020 mask_write 0XFD080128 0xFFFFFFFF 0x00000E0F
5021 # Register : RDIMMGCR0 @ 0XFD080140</p>
5023 # Reserved. Return zeroes on reads.
5024 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0
5026 # RDMIMM Quad CS Enable
5027 # PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0
5029 # Reserved. Return zeroes on reads.
5030 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0
5032 # RDIMM Outputs I/O Mode
5033 # PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1
5035 # Reserved. Return zeroes on reads.
5036 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0
5038 # ERROUT# Output Enable
5039 # PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0
5042 # PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1
5044 # ERROUT# Power Down Receiver
5045 # PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0
5047 # Reserved. Return zeroes on reads.
5048 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0
5050 # ERROUT# On-Die Termination
5051 # PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0
5054 # PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0
5057 # PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0
5059 # Reserved. Return zeroes on reads.
5060 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0
5062 # Reserved. Return zeroes on reads.
5063 # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0
5065 # Rank Mirror Enable.
5066 # PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2
5068 # Reserved. Return zeroes on reads.
5069 # PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0
5071 # Stop on Parity Error
5072 # PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0
5074 # Parity Error No Registering
5075 # PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0
5078 # PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0
5080 # RDIMM General Configuration Register 0
5081 #(OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) */
5082 mask_write 0XFD080140 0xFFFFFFFF 0x08400020
5083 # Register : RDIMMGCR1 @ 0XFD080144</p>
5085 # Reserved. Return zeroes on reads.
5086 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0
5088 # Address [17] B-side Inversion Disable
5089 # PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0
5091 # Reserved. Return zeroes on reads.
5092 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0
5094 # Command word to command word programming delay
5095 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0
5097 # Reserved. Return zeroes on reads.
5098 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0
5100 # Command word to command word programming delay
5101 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0
5103 # Reserved. Return zeroes on reads.
5104 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0
5106 # Command word to command word programming delay
5107 # PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0
5109 # Reserved. Return zeroes on reads.
5110 # PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0
5112 # Stabilization time
5113 # PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80
5115 # RDIMM General Configuration Register 1
5116 #(OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) */
5117 mask_write 0XFD080144 0xFFFFFFFF 0x00000C80
5118 # Register : RDIMMCR0 @ 0XFD080150</p>
5120 # DDR4/DDR3 Control Word 7
5121 # PSU_DDR_PHY_RDIMMCR0_RC7 0x0
5123 # DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
5124 # PSU_DDR_PHY_RDIMMCR0_RC6 0x0
5126 # DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
5127 # PSU_DDR_PHY_RDIMMCR0_RC5 0x0
5129 # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
5130 # Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
5132 # PSU_DDR_PHY_RDIMMCR0_RC4 0x0
5134 # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
5135 # rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
5137 # PSU_DDR_PHY_RDIMMCR0_RC3 0x0
5139 # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
5140 # (Timing Control Word)
5141 # PSU_DDR_PHY_RDIMMCR0_RC2 0x0
5143 # DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
5144 # PSU_DDR_PHY_RDIMMCR0_RC1 0x0
5146 # DDR4/DDR3 Control Word 0 (Global Features Control Word)
5147 # PSU_DDR_PHY_RDIMMCR0_RC0 0x0
5149 # RDIMM Control Register 0
5150 #(OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) */
5151 mask_write 0XFD080150 0xFFFFFFFF 0x00000000
5152 # Register : RDIMMCR1 @ 0XFD080154</p>
5155 # PSU_DDR_PHY_RDIMMCR1_RC15 0x0
5157 # DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
5158 # PSU_DDR_PHY_RDIMMCR1_RC14 0x0
5160 # DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
5161 # PSU_DDR_PHY_RDIMMCR1_RC13 0x0
5163 # DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
5164 # PSU_DDR_PHY_RDIMMCR1_RC12 0x0
5166 # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
5167 # rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
5168 # PSU_DDR_PHY_RDIMMCR1_RC11 0x0
5170 # DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
5171 # PSU_DDR_PHY_RDIMMCR1_RC10 0x2
5173 # DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
5174 # PSU_DDR_PHY_RDIMMCR1_RC9 0x0
5176 # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
5177 # trol Word 8 (Additional Input Bus Termination Setting Control Word)
5178 # PSU_DDR_PHY_RDIMMCR1_RC8 0x0
5180 # RDIMM Control Register 1
5181 #(OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) */
5182 mask_write 0XFD080154 0xFFFFFFFF 0x00000200
5183 # Register : MR0 @ 0XFD080180</p>
5185 # Reserved. Return zeroes on reads.
5186 # PSU_DDR_PHY_MR0_RESERVED_31_8 0x6
5188 # CA Terminating Rank
5189 # PSU_DDR_PHY_MR0_CATR 0x0
5191 # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
5192 # be programmed to 0x0.
5193 # PSU_DDR_PHY_MR0_RSVD_6_5 0x1
5195 # Built-in Self-Test for RZQ
5196 # PSU_DDR_PHY_MR0_RZQI 0x2
5198 # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
5199 # be programmed to 0x0.
5200 # PSU_DDR_PHY_MR0_RSVD_2_0 0x0
5202 # LPDDR4 Mode Register 0
5203 #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) */
5204 mask_write 0XFD080180 0xFFFFFFFF 0x00000630
5205 # Register : MR1 @ 0XFD080184</p>
5207 # Reserved. Return zeroes on reads.
5208 # PSU_DDR_PHY_MR1_RESERVED_31_8 0x3
5210 # Read Postamble Length
5211 # PSU_DDR_PHY_MR1_RDPST 0x0
5213 # Write-recovery for auto-precharge command
5214 # PSU_DDR_PHY_MR1_NWR 0x0
5216 # Read Preamble Length
5217 # PSU_DDR_PHY_MR1_RDPRE 0x0
5219 # Write Preamble Length
5220 # PSU_DDR_PHY_MR1_WRPRE 0x0
5223 # PSU_DDR_PHY_MR1_BL 0x1
5225 # LPDDR4 Mode Register 1
5226 #(OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) */
5227 mask_write 0XFD080184 0xFFFFFFFF 0x00000301
5228 # Register : MR2 @ 0XFD080188</p>
5230 # Reserved. Return zeroes on reads.
5231 # PSU_DDR_PHY_MR2_RESERVED_31_8 0x0
5234 # PSU_DDR_PHY_MR2_WRL 0x0
5237 # PSU_DDR_PHY_MR2_WLS 0x0
5240 # PSU_DDR_PHY_MR2_WL 0x4
5243 # PSU_DDR_PHY_MR2_RL 0x0
5245 # LPDDR4 Mode Register 2
5246 #(OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) */
5247 mask_write 0XFD080188 0xFFFFFFFF 0x00000020
5248 # Register : MR3 @ 0XFD08018C</p>
5250 # Reserved. Return zeroes on reads.
5251 # PSU_DDR_PHY_MR3_RESERVED_31_8 0x2
5254 # PSU_DDR_PHY_MR3_DBIWR 0x0
5257 # PSU_DDR_PHY_MR3_DBIRD 0x0
5259 # Pull-down Drive Strength
5260 # PSU_DDR_PHY_MR3_PDDS 0x0
5262 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5264 # PSU_DDR_PHY_MR3_RSVD 0x0
5266 # Write Postamble Length
5267 # PSU_DDR_PHY_MR3_WRPST 0x0
5269 # Pull-up Calibration Point
5270 # PSU_DDR_PHY_MR3_PUCAL 0x0
5272 # LPDDR4 Mode Register 3
5273 #(OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) */
5274 mask_write 0XFD08018C 0xFFFFFFFF 0x00000200
5275 # Register : MR4 @ 0XFD080190</p>
5277 # Reserved. Return zeroes on reads.
5278 # PSU_DDR_PHY_MR4_RESERVED_31_16 0x0
5280 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5282 # PSU_DDR_PHY_MR4_RSVD_15_13 0x0
5285 # PSU_DDR_PHY_MR4_WRP 0x0
5288 # PSU_DDR_PHY_MR4_RDP 0x0
5290 # Read Preamble Training Mode
5291 # PSU_DDR_PHY_MR4_RPTM 0x0
5293 # Self Refresh Abort
5294 # PSU_DDR_PHY_MR4_SRA 0x0
5296 # CS to Command Latency Mode
5297 # PSU_DDR_PHY_MR4_CS2CMDL 0x0
5299 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5301 # PSU_DDR_PHY_MR4_RSVD1 0x0
5303 # Internal VREF Monitor
5304 # PSU_DDR_PHY_MR4_IVM 0x0
5306 # Temperature Controlled Refresh Mode
5307 # PSU_DDR_PHY_MR4_TCRM 0x0
5309 # Temperature Controlled Refresh Range
5310 # PSU_DDR_PHY_MR4_TCRR 0x0
5312 # Maximum Power Down Mode
5313 # PSU_DDR_PHY_MR4_MPDM 0x0
5315 # This is a JEDEC reserved bit and is recommended by JEDEC to be programme
5317 # PSU_DDR_PHY_MR4_RSVD_0 0x0
5319 # DDR4 Mode Register 4
5320 #(OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) */
5321 mask_write 0XFD080190 0xFFFFFFFF 0x00000000
5322 # Register : MR5 @ 0XFD080194</p>
5324 # Reserved. Return zeroes on reads.
5325 # PSU_DDR_PHY_MR5_RESERVED_31_16 0x0
5327 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5329 # PSU_DDR_PHY_MR5_RSVD 0x0
5332 # PSU_DDR_PHY_MR5_RDBI 0x0
5335 # PSU_DDR_PHY_MR5_WDBI 0x0
5338 # PSU_DDR_PHY_MR5_DM 0x1
5340 # CA Parity Persistent Error
5341 # PSU_DDR_PHY_MR5_CAPPE 0x1
5344 # PSU_DDR_PHY_MR5_RTTPARK 0x3
5346 # ODT Input Buffer during Power Down mode
5347 # PSU_DDR_PHY_MR5_ODTIBPD 0x0
5349 # C/A Parity Error Status
5350 # PSU_DDR_PHY_MR5_CAPES 0x0
5353 # PSU_DDR_PHY_MR5_CRCEC 0x0
5355 # C/A Parity Latency Mode
5356 # PSU_DDR_PHY_MR5_CAPM 0x0
5358 # DDR4 Mode Register 5
5359 #(OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) */
5360 mask_write 0XFD080194 0xFFFFFFFF 0x000006C0
5361 # Register : MR6 @ 0XFD080198</p>
5363 # Reserved. Return zeroes on reads.
5364 # PSU_DDR_PHY_MR6_RESERVED_31_16 0x0
5366 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5368 # PSU_DDR_PHY_MR6_RSVD_15_13 0x0
5370 # CAS_n to CAS_n command delay for same bank group (tCCD_L)
5371 # PSU_DDR_PHY_MR6_TCCDL 0x2
5373 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5375 # PSU_DDR_PHY_MR6_RSVD_9_8 0x0
5377 # VrefDQ Training Enable
5378 # PSU_DDR_PHY_MR6_VDDQTEN 0x0
5380 # VrefDQ Training Range
5381 # PSU_DDR_PHY_MR6_VDQTRG 0x0
5383 # VrefDQ Training Values
5384 # PSU_DDR_PHY_MR6_VDQTVAL 0x19
5386 # DDR4 Mode Register 6
5387 #(OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) */
5388 mask_write 0XFD080198 0xFFFFFFFF 0x00000819
5389 # Register : MR11 @ 0XFD0801AC</p>
5391 # Reserved. Return zeroes on reads.
5392 # PSU_DDR_PHY_MR11_RESERVED_31_8 0x0
5394 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5396 # PSU_DDR_PHY_MR11_RSVD 0x0
5398 # Power Down Control
5399 # PSU_DDR_PHY_MR11_PDCTL 0x0
5401 # DQ Bus Receiver On-Die-Termination
5402 # PSU_DDR_PHY_MR11_DQODT 0x0
5404 # LPDDR4 Mode Register 11
5405 #(OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) */
5406 mask_write 0XFD0801AC 0xFFFFFFFF 0x00000000
5407 # Register : MR12 @ 0XFD0801B0</p>
5409 # Reserved. Return zeroes on reads.
5410 # PSU_DDR_PHY_MR12_RESERVED_31_8 0x0
5412 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5414 # PSU_DDR_PHY_MR12_RSVD 0x0
5416 # VREF_CA Range Select.
5417 # PSU_DDR_PHY_MR12_VR_CA 0x1
5419 # Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
5420 # PSU_DDR_PHY_MR12_VREF_CA 0xd
5422 # LPDDR4 Mode Register 12
5423 #(OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) */
5424 mask_write 0XFD0801B0 0xFFFFFFFF 0x0000004D
5425 # Register : MR13 @ 0XFD0801B4</p>
5427 # Reserved. Return zeroes on reads.
5428 # PSU_DDR_PHY_MR13_RESERVED_31_8 0x0
5430 # Frequency Set Point Operation Mode
5431 # PSU_DDR_PHY_MR13_FSPOP 0x0
5433 # Frequency Set Point Write Enable
5434 # PSU_DDR_PHY_MR13_FSPWR 0x0
5437 # PSU_DDR_PHY_MR13_DMD 0x0
5439 # Refresh Rate Option
5440 # PSU_DDR_PHY_MR13_RRO 0x0
5442 # VREF Current Generator
5443 # PSU_DDR_PHY_MR13_VRCG 0x1
5446 # PSU_DDR_PHY_MR13_VRO 0x0
5448 # Read Preamble Training Mode
5449 # PSU_DDR_PHY_MR13_RPT 0x0
5451 # Command Bus Training
5452 # PSU_DDR_PHY_MR13_CBT 0x0
5454 # LPDDR4 Mode Register 13
5455 #(OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) */
5456 mask_write 0XFD0801B4 0xFFFFFFFF 0x00000008
5457 # Register : MR14 @ 0XFD0801B8</p>
5459 # Reserved. Return zeroes on reads.
5460 # PSU_DDR_PHY_MR14_RESERVED_31_8 0x0
5462 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5464 # PSU_DDR_PHY_MR14_RSVD 0x0
5466 # VREFDQ Range Selects.
5467 # PSU_DDR_PHY_MR14_VR_DQ 0x1
5469 # Reserved. Return zeroes on reads.
5470 # PSU_DDR_PHY_MR14_VREF_DQ 0xd
5472 # LPDDR4 Mode Register 14
5473 #(OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) */
5474 mask_write 0XFD0801B8 0xFFFFFFFF 0x0000004D
5475 # Register : MR22 @ 0XFD0801D8</p>
5477 # Reserved. Return zeroes on reads.
5478 # PSU_DDR_PHY_MR22_RESERVED_31_8 0x0
5480 # These are JEDEC reserved bits and are recommended by JEDEC to be program
5482 # PSU_DDR_PHY_MR22_RSVD 0x0
5484 # CA ODT termination disable.
5485 # PSU_DDR_PHY_MR22_ODTD_CA 0x0
5488 # PSU_DDR_PHY_MR22_ODTE_CS 0x0
5491 # PSU_DDR_PHY_MR22_ODTE_CK 0x0
5493 # Controller ODT value for VOH calibration.
5494 # PSU_DDR_PHY_MR22_CODT 0x0
5496 # LPDDR4 Mode Register 22
5497 #(OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) */
5498 mask_write 0XFD0801D8 0xFFFFFFFF 0x00000000
5499 # Register : DTCR0 @ 0XFD080200</p>
5501 # Refresh During Training
5502 # PSU_DDR_PHY_DTCR0_RFSHDT 0x8
5504 # Reserved. Return zeroes on reads.
5505 # PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0
5507 # Data Training Debug Rank Select
5508 # PSU_DDR_PHY_DTCR0_DTDRS 0x0
5510 # Data Training with Early/Extended Gate
5511 # PSU_DDR_PHY_DTCR0_DTEXG 0x0
5513 # Data Training Extended Write DQS
5514 # PSU_DDR_PHY_DTCR0_DTEXD 0x0
5516 # Data Training Debug Step
5517 # PSU_DDR_PHY_DTCR0_DTDSTP 0x0
5519 # Data Training Debug Enable
5520 # PSU_DDR_PHY_DTCR0_DTDEN 0x0
5522 # Data Training Debug Byte Select
5523 # PSU_DDR_PHY_DTCR0_DTDBS 0x0
5525 # Data Training read DBI deskewing configuration
5526 # PSU_DDR_PHY_DTCR0_DTRDBITR 0x2
5528 # Reserved. Return zeroes on reads.
5529 # PSU_DDR_PHY_DTCR0_RESERVED_13 0x0
5531 # Data Training Write Bit Deskew Data Mask
5532 # PSU_DDR_PHY_DTCR0_DTWBDDM 0x1
5534 # Refreshes Issued During Entry to Training
5535 # PSU_DDR_PHY_DTCR0_RFSHEN 0x1
5537 # Data Training Compare Data
5538 # PSU_DDR_PHY_DTCR0_DTCMPD 0x1
5540 # Data Training Using MPR
5541 # PSU_DDR_PHY_DTCR0_DTMPR 0x1
5543 # Reserved. Return zeroes on reads.
5544 # PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0
5546 # Data Training Repeat Number
5547 # PSU_DDR_PHY_DTCR0_DTRPTN 0x7
5549 # Data Training Configuration Register 0
5550 #(OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) */
5551 mask_write 0XFD080200 0xFFFFFFFF 0x800091C7
5552 # Register : DTCR1 @ 0XFD080204</p>
5555 # PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0
5558 # PSU_DDR_PHY_DTCR1_RANKEN 0x1
5560 # Reserved. Return zeroes on reads.
5561 # PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0
5563 # Data Training Rank
5564 # PSU_DDR_PHY_DTCR1_DTRANK 0x0
5566 # Reserved. Return zeroes on reads.
5567 # PSU_DDR_PHY_DTCR1_RESERVED_11 0x0
5569 # Read Leveling Gate Sampling Difference
5570 # PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2
5572 # Reserved. Return zeroes on reads.
5573 # PSU_DDR_PHY_DTCR1_RESERVED_7 0x0
5575 # Read Leveling Gate Shift
5576 # PSU_DDR_PHY_DTCR1_RDLVLGS 0x3
5578 # Reserved. Return zeroes on reads.
5579 # PSU_DDR_PHY_DTCR1_RESERVED_3 0x0
5581 # Read Preamble Training enable
5582 # PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1
5584 # Read Leveling Enable
5585 # PSU_DDR_PHY_DTCR1_RDLVLEN 0x1
5587 # Basic Gate Training Enable
5588 # PSU_DDR_PHY_DTCR1_BSTEN 0x0
5590 # Data Training Configuration Register 1
5591 #(OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) */
5592 mask_write 0XFD080204 0xFFFFFFFF 0x00010236
5593 # Register : CATR0 @ 0XFD080240</p>
5595 # Reserved. Return zeroes on reads.
5596 # PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0
5598 # Minimum time (in terms of number of dram clocks) between two consectuve
5599 # CA calibration command
5600 # PSU_DDR_PHY_CATR0_CACD 0x14
5602 # Reserved. Return zeroes on reads.
5603 # PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0
5605 # Minimum time (in terms of number of dram clocks) PUB should wait before
5606 # sampling the CA response after Calibration command has been sent to the
5608 # PSU_DDR_PHY_CATR0_CAADR 0x10
5610 # CA_1 Response Byte Lane 1
5611 # PSU_DDR_PHY_CATR0_CA1BYTE1 0x5
5613 # CA_1 Response Byte Lane 0
5614 # PSU_DDR_PHY_CATR0_CA1BYTE0 0x4
5616 # CA Training Register 0
5617 #(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */
5618 mask_write 0XFD080240 0xFFFFFFFF 0x00141054
5619 # Register : DQSDR0 @ 0XFD080250</p>
5621 # Number of delay taps by which the DQS gate LCDL will be updated when DQS
5623 # PSU_DDR_PHY_DQSDR0_DFTDLY 0x0
5625 # Drift Impedance Update
5626 # PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0
5629 # PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0
5631 # Reserved. Return zeroes on reads.
5632 # PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0
5634 # Drift Read Spacing
5635 # PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0
5637 # Drift Back-to-Back Reads
5638 # PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8
5641 # PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8
5643 # Reserved. Return zeroes on reads.
5644 # PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0
5647 # PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0
5649 # DQS Drift Update Mode
5650 # PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0
5652 # DQS Drift Detection Mode
5653 # PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0
5655 # DQS Drift Detection Enable
5656 # PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0
5658 # DQS Drift Register 0
5659 #(OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) */
5660 mask_write 0XFD080250 0xFFFFFFFF 0x00088000
5661 # Register : BISTLSR @ 0XFD080414</p>
5663 # LFSR seed for pseudo-random BIST patterns
5664 # PSU_DDR_PHY_BISTLSR_SEED 0x12341000
5666 # BIST LFSR Seed Register
5667 #(OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) */
5668 mask_write 0XFD080414 0xFFFFFFFF 0x12341000
5669 # Register : RIOCR5 @ 0XFD0804F4</p>
5671 # Reserved. Return zeroes on reads.
5672 # PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0
5674 # Reserved. Return zeros on reads.
5675 # PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0
5677 # SDRAM On-die Termination Output Enable (OE) Mode Selection.
5678 # PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5
5680 # Rank I/O Configuration Register 5
5681 #(OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) */
5682 mask_write 0XFD0804F4 0xFFFFFFFF 0x00000005
5683 # Register : ACIOCR0 @ 0XFD080500</p>
5685 # Address/Command Slew Rate (D3F I/O Only)
5686 # PSU_DDR_PHY_ACIOCR0_ACSR 0x0
5688 # SDRAM Reset I/O Mode
5689 # PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1
5691 # SDRAM Reset Power Down Receiver
5692 # PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1
5694 # Reserved. Return zeroes on reads.
5695 # PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0
5697 # SDRAM Reset On-Die Termination
5698 # PSU_DDR_PHY_ACIOCR0_RSTODT 0x0
5700 # Reserved. Return zeroes on reads.
5701 # PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0
5703 # CK Duty Cycle Correction
5704 # PSU_DDR_PHY_ACIOCR0_CKDCC 0x0
5706 # AC Power Down Receiver Mode
5707 # PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2
5709 # AC On-die Termination Mode
5710 # PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2
5712 # Reserved. Return zeroes on reads.
5713 # PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0
5715 # Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
5716 # PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0
5718 # AC I/O Configuration Register 0
5719 #(OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) */
5720 mask_write 0XFD080500 0xFFFFFFFF 0x30000028
5721 # Register : ACIOCR2 @ 0XFD080508</p>
5723 # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
5725 # PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0
5727 # Clock gating for Output Enable D slices [0]
5728 # PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0
5730 # Clock gating for Power Down Receiver D slices [0]
5731 # PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0
5733 # Clock gating for Termination Enable D slices [0]
5734 # PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0
5736 # Clock gating for CK# D slices [1:0]
5737 # PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2
5739 # Clock gating for CK D slices [1:0]
5740 # PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2
5742 # Clock gating for AC D slices [23:0]
5743 # PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0
5745 # AC I/O Configuration Register 2
5746 #(OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) */
5747 mask_write 0XFD080508 0xFFFFFFFF 0x0A000000
5748 # Register : ACIOCR3 @ 0XFD08050C</p>
5750 # SDRAM Parity Output Enable (OE) Mode Selection
5751 # PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0
5753 # SDRAM Bank Group Output Enable (OE) Mode Selection
5754 # PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0
5756 # SDRAM Bank Address Output Enable (OE) Mode Selection
5757 # PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0
5759 # SDRAM A[17] Output Enable (OE) Mode Selection
5760 # PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0
5762 # SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
5763 # PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0
5765 # SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
5766 # PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0
5768 # Reserved. Return zeroes on reads.
5769 # PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0
5771 # Reserved. Return zeros on reads.
5772 # PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0
5774 # SDRAM CK Output Enable (OE) Mode Selection.
5775 # PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9
5777 # AC I/O Configuration Register 3
5778 #(OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) */
5779 mask_write 0XFD08050C 0xFFFFFFFF 0x00000009
5780 # Register : ACIOCR4 @ 0XFD080510</p>
5782 # Clock gating for AC LB slices and loopback read valid slices
5783 # PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0
5785 # Clock gating for Output Enable D slices [1]
5786 # PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0
5788 # Clock gating for Power Down Receiver D slices [1]
5789 # PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0
5791 # Clock gating for Termination Enable D slices [1]
5792 # PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0
5794 # Clock gating for CK# D slices [3:2]
5795 # PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2
5797 # Clock gating for CK D slices [3:2]
5798 # PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2
5800 # Clock gating for AC D slices [47:24]
5801 # PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0
5803 # AC I/O Configuration Register 4
5804 #(OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) */
5805 mask_write 0XFD080510 0xFFFFFFFF 0x0A000000
5806 # Register : IOVCR0 @ 0XFD080520</p>
5808 # Reserved. Return zeroes on reads.
5809 # PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0
5811 # Address/command lane VREF Pad Enable
5812 # PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0
5814 # Address/command lane Internal VREF Enable
5815 # PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0
5817 # Address/command lane Single-End VREF Enable
5818 # PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1
5820 # Address/command lane Internal VREF Enable
5821 # PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1
5823 # External VREF generato REFSEL range select
5824 # PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0
5826 # Address/command lane External VREF Select
5827 # PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0
5829 # Single ended VREF generator REFSEL range select
5830 # PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1
5832 # Address/command lane Single-End VREF Select
5833 # PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30
5835 # Internal VREF generator REFSEL ragne select
5836 # PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1
5838 # REFSEL Control for internal AC IOs
5839 # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e
5841 # IO VREF Control Register 0
5842 #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) */
5843 mask_write 0XFD080520 0xFFFFFFFF 0x0300B0CE
5844 # Register : VTCR0 @ 0XFD080528</p>
5846 # Number of ctl_clk required to meet (> 150ns) timing requirements during
5847 # DRAM DQ VREF training
5848 # PSU_DDR_PHY_VTCR0_TVREF 0x7
5850 # DRM DQ VREF training Enable
5851 # PSU_DDR_PHY_VTCR0_DVEN 0x1
5853 # Per Device Addressability Enable
5854 # PSU_DDR_PHY_VTCR0_PDAEN 0x1
5856 # Reserved. Returns zeroes on reads.
5857 # PSU_DDR_PHY_VTCR0_RESERVED_26 0x0
5860 # PSU_DDR_PHY_VTCR0_VWCR 0x4
5862 # DRAM DQ VREF step size used during DRAM VREF training
5863 # PSU_DDR_PHY_VTCR0_DVSS 0x0
5865 # Maximum VREF limit value used during DRAM VREF training
5866 # PSU_DDR_PHY_VTCR0_DVMAX 0x32
5868 # Minimum VREF limit value used during DRAM VREF training
5869 # PSU_DDR_PHY_VTCR0_DVMIN 0x0
5871 # Initial DRAM DQ VREF value used during DRAM VREF training
5872 # PSU_DDR_PHY_VTCR0_DVINIT 0x19
5874 # VREF Training Control Register 0
5875 #(OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) */
5876 mask_write 0XFD080528 0xFFFFFFFF 0xF9032019
5877 # Register : VTCR1 @ 0XFD08052C</p>
5879 # Host VREF step size used during VREF training. The register value of N i
5880 # ndicates step size of (N+1)
5881 # PSU_DDR_PHY_VTCR1_HVSS 0x0
5883 # Reserved. Returns zeroes on reads.
5884 # PSU_DDR_PHY_VTCR1_RESERVED_27 0x0
5886 # Maximum VREF limit value used during DRAM VREF training.
5887 # PSU_DDR_PHY_VTCR1_HVMAX 0x7f
5889 # Reserved. Returns zeroes on reads.
5890 # PSU_DDR_PHY_VTCR1_RESERVED_19 0x0
5892 # Minimum VREF limit value used during DRAM VREF training.
5893 # PSU_DDR_PHY_VTCR1_HVMIN 0x0
5895 # Reserved. Returns zeroes on reads.
5896 # PSU_DDR_PHY_VTCR1_RESERVED_11 0x0
5898 # Static Host Vref Rank Value
5899 # PSU_DDR_PHY_VTCR1_SHRNK 0x0
5901 # Static Host Vref Rank Enable
5902 # PSU_DDR_PHY_VTCR1_SHREN 0x1
5904 # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
5905 # ements during Host IO VREF training
5906 # PSU_DDR_PHY_VTCR1_TVREFIO 0x7
5908 # Eye LCDL Offset value for VREF training
5909 # PSU_DDR_PHY_VTCR1_EOFF 0x0
5911 # Number of LCDL Eye points for which VREF training is repeated
5912 # PSU_DDR_PHY_VTCR1_ENUM 0x0
5914 # HOST (IO) internal VREF training Enable
5915 # PSU_DDR_PHY_VTCR1_HVEN 0x1
5917 # Host IO Type Control
5918 # PSU_DDR_PHY_VTCR1_HVIO 0x1
5920 # VREF Training Control Register 1
5921 #(OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) */
5922 mask_write 0XFD08052C 0xFFFFFFFF 0x07F001E3
5923 # Register : ACBDLR1 @ 0XFD080544</p>
5925 # Reserved. Return zeroes on reads.
5926 # PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0
5928 # Delay select for the BDL on Parity.
5929 # PSU_DDR_PHY_ACBDLR1_PARBD 0x0
5931 # Reserved. Return zeroes on reads.
5932 # PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0
5934 # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
5936 # PSU_DDR_PHY_ACBDLR1_A16BD 0x0
5938 # Reserved. Return zeroes on reads.
5939 # PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0
5941 # Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
5942 # s pin is connected to CAS.
5943 # PSU_DDR_PHY_ACBDLR1_A17BD 0x0
5945 # Reserved. Return zeroes on reads.
5946 # PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0
5948 # Delay select for the BDL on ACTN.
5949 # PSU_DDR_PHY_ACBDLR1_ACTBD 0x0
5951 # AC Bit Delay Line Register 1
5952 #(OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) */
5953 mask_write 0XFD080544 0xFFFFFFFF 0x00000000
5954 # Register : ACBDLR2 @ 0XFD080548</p>
5956 # Reserved. Return zeroes on reads.
5957 # PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0
5959 # Delay select for the BDL on BG[1].
5960 # PSU_DDR_PHY_ACBDLR2_BG1BD 0x0
5962 # Reserved. Return zeroes on reads.
5963 # PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0
5965 # Delay select for the BDL on BG[0].
5966 # PSU_DDR_PHY_ACBDLR2_BG0BD 0x0
5968 # Reser.ved Return zeroes on reads.
5969 # PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0
5971 # Delay select for the BDL on BA[1].
5972 # PSU_DDR_PHY_ACBDLR2_BA1BD 0x0
5974 # Reserved. Return zeroes on reads.
5975 # PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0
5977 # Delay select for the BDL on BA[0].
5978 # PSU_DDR_PHY_ACBDLR2_BA0BD 0x0
5980 # AC Bit Delay Line Register 2
5981 #(OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) */
5982 mask_write 0XFD080548 0xFFFFFFFF 0x00000000
5983 # Register : ACBDLR6 @ 0XFD080558</p>
5985 # Reserved. Return zeroes on reads.
5986 # PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0
5988 # Delay select for the BDL on Address A[3].
5989 # PSU_DDR_PHY_ACBDLR6_A03BD 0x0
5991 # Reserved. Return zeroes on reads.
5992 # PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0
5994 # Delay select for the BDL on Address A[2].
5995 # PSU_DDR_PHY_ACBDLR6_A02BD 0x0
5997 # Reserved. Return zeroes on reads.
5998 # PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0
6000 # Delay select for the BDL on Address A[1].
6001 # PSU_DDR_PHY_ACBDLR6_A01BD 0x0
6003 # Reserved. Return zeroes on reads.
6004 # PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0
6006 # Delay select for the BDL on Address A[0].
6007 # PSU_DDR_PHY_ACBDLR6_A00BD 0x0
6009 # AC Bit Delay Line Register 6
6010 #(OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) */
6011 mask_write 0XFD080558 0xFFFFFFFF 0x00000000
6012 # Register : ACBDLR7 @ 0XFD08055C</p>
6014 # Reserved. Return zeroes on reads.
6015 # PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0
6017 # Delay select for the BDL on Address A[7].
6018 # PSU_DDR_PHY_ACBDLR7_A07BD 0x0
6020 # Reserved. Return zeroes on reads.
6021 # PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0
6023 # Delay select for the BDL on Address A[6].
6024 # PSU_DDR_PHY_ACBDLR7_A06BD 0x0
6026 # Reserved. Return zeroes on reads.
6027 # PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0
6029 # Delay select for the BDL on Address A[5].
6030 # PSU_DDR_PHY_ACBDLR7_A05BD 0x0
6032 # Reserved. Return zeroes on reads.
6033 # PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0
6035 # Delay select for the BDL on Address A[4].
6036 # PSU_DDR_PHY_ACBDLR7_A04BD 0x0
6038 # AC Bit Delay Line Register 7
6039 #(OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) */
6040 mask_write 0XFD08055C 0xFFFFFFFF 0x00000000
6041 # Register : ACBDLR8 @ 0XFD080560</p>
6043 # Reserved. Return zeroes on reads.
6044 # PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0
6046 # Delay select for the BDL on Address A[11].
6047 # PSU_DDR_PHY_ACBDLR8_A11BD 0x0
6049 # Reserved. Return zeroes on reads.
6050 # PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0
6052 # Delay select for the BDL on Address A[10].
6053 # PSU_DDR_PHY_ACBDLR8_A10BD 0x0
6055 # Reserved. Return zeroes on reads.
6056 # PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0
6058 # Delay select for the BDL on Address A[9].
6059 # PSU_DDR_PHY_ACBDLR8_A09BD 0x0
6061 # Reserved. Return zeroes on reads.
6062 # PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0
6064 # Delay select for the BDL on Address A[8].
6065 # PSU_DDR_PHY_ACBDLR8_A08BD 0x0
6067 # AC Bit Delay Line Register 8
6068 #(OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) */
6069 mask_write 0XFD080560 0xFFFFFFFF 0x00000000
6070 # Register : ACBDLR9 @ 0XFD080564</p>
6072 # Reserved. Return zeroes on reads.
6073 # PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0
6075 # Delay select for the BDL on Address A[15].
6076 # PSU_DDR_PHY_ACBDLR9_A15BD 0x0
6078 # Reserved. Return zeroes on reads.
6079 # PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0
6081 # Delay select for the BDL on Address A[14].
6082 # PSU_DDR_PHY_ACBDLR9_A14BD 0x0
6084 # Reserved. Return zeroes on reads.
6085 # PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0
6087 # Delay select for the BDL on Address A[13].
6088 # PSU_DDR_PHY_ACBDLR9_A13BD 0x0
6090 # Reserved. Return zeroes on reads.
6091 # PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0
6093 # Delay select for the BDL on Address A[12].
6094 # PSU_DDR_PHY_ACBDLR9_A12BD 0x0
6096 # AC Bit Delay Line Register 9
6097 #(OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) */
6098 mask_write 0XFD080564 0xFFFFFFFF 0x00000000
6099 # Register : ZQCR @ 0XFD080680</p>
6101 # Reserved. Return zeroes on reads.
6102 # PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0
6105 # PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0
6107 # Programmable Wait for Frequency B
6108 # PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11
6110 # Programmable Wait for Frequency A
6111 # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15
6113 # ZQ VREF Pad Enable
6114 # PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0
6116 # ZQ Internal VREF Enable
6117 # PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1
6119 # Choice of termination mode
6120 # PSU_DDR_PHY_ZQCR_ODT_MODE 0x1
6122 # Force ZCAL VT update
6123 # PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0
6126 # PSU_DDR_PHY_ZQCR_IODLMT 0x2
6128 # Averaging algorithm enable, if set, enables averaging algorithm
6129 # PSU_DDR_PHY_ZQCR_AVGEN 0x1
6131 # Maximum number of averaging rounds to be used by averaging algorithm
6132 # PSU_DDR_PHY_ZQCR_AVGMAX 0x2
6134 # ZQ Calibration Type
6135 # PSU_DDR_PHY_ZQCR_ZCALT 0x0
6138 # PSU_DDR_PHY_ZQCR_ZQPD 0x0
6140 # ZQ Impedance Control Register
6141 #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) */
6142 mask_write 0XFD080680 0xFFFFFFFF 0x008AAA58
6143 # Register : ZQ0PR0 @ 0XFD080684</p>
6145 # Pull-down drive strength ZCTRL over-ride enable
6146 # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0
6148 # Pull-up drive strength ZCTRL over-ride enable
6149 # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0
6151 # Pull-down termination ZCTRL over-ride enable
6152 # PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0
6154 # Pull-up termination ZCTRL over-ride enable
6155 # PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0
6157 # Calibration segment bypass
6158 # PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0
6160 # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
6161 # is driven by the PUB
6162 # PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0
6164 # Termination adjustment
6165 # PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0
6167 # Pulldown drive strength adjustment
6168 # PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0
6170 # Pullup drive strength adjustment
6171 # PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0
6173 # DRAM Impedance Divide Ratio
6174 # PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7
6176 # HOST Impedance Divide Ratio
6177 # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9
6179 # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
6180 # ve strength calibration)
6181 # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd
6183 # Impedance Divide Ratio (pullup drive calibration during asymmetric drive
6184 # strength calibration)
6185 # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd
6187 # ZQ n Impedance Control Program Register 0
6188 #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) */
6189 mask_write 0XFD080684 0xFFFFFFFF 0x000079DD
6190 # Register : ZQ0OR0 @ 0XFD080694</p>
6192 # Reserved. Return zeros on reads.
6193 # PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0
6195 # Override value for the pull-up output impedance
6196 # PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1
6198 # Reserved. Return zeros on reads.
6199 # PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0
6201 # Override value for the pull-down output impedance
6202 # PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210
6204 # ZQ n Impedance Control Override Data Register 0
6205 #(OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) */
6206 mask_write 0XFD080694 0xFFFFFFFF 0x01E10210
6207 # Register : ZQ0OR1 @ 0XFD080698</p>
6209 # Reserved. Return zeros on reads.
6210 # PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0
6212 # Override value for the pull-up termination
6213 # PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1
6215 # Reserved. Return zeros on reads.
6216 # PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0
6218 # Override value for the pull-down termination
6219 # PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0
6221 # ZQ n Impedance Control Override Data Register 1
6222 #(OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) */
6223 mask_write 0XFD080698 0xFFFFFFFF 0x01E10000
6224 # Register : ZQ1PR0 @ 0XFD0806A4</p>
6226 # Pull-down drive strength ZCTRL over-ride enable
6227 # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0
6229 # Pull-up drive strength ZCTRL over-ride enable
6230 # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0
6232 # Pull-down termination ZCTRL over-ride enable
6233 # PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0
6235 # Pull-up termination ZCTRL over-ride enable
6236 # PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0
6238 # Calibration segment bypass
6239 # PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0
6241 # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
6242 # is driven by the PUB
6243 # PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0
6245 # Termination adjustment
6246 # PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0
6248 # Pulldown drive strength adjustment
6249 # PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1
6251 # Pullup drive strength adjustment
6252 # PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0
6254 # DRAM Impedance Divide Ratio
6255 # PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7
6257 # HOST Impedance Divide Ratio
6258 # PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb
6260 # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
6261 # ve strength calibration)
6262 # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd
6264 # Impedance Divide Ratio (pullup drive calibration during asymmetric drive
6265 # strength calibration)
6266 # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb
6268 # ZQ n Impedance Control Program Register 0
6269 #(OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) */
6270 mask_write 0XFD0806A4 0xFFFFFFFF 0x00087BDB
6271 # Register : DX0GCR0 @ 0XFD080700</p>
6273 # Calibration Bypass
6274 # PSU_DDR_PHY_DX0GCR0_CALBYP 0x0
6276 # Master Delay Line Enable
6277 # PSU_DDR_PHY_DX0GCR0_MDLEN 0x1
6279 # Configurable ODT(TE) Phase Shift
6280 # PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0
6282 # DQS Duty Cycle Correction
6283 # PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0
6285 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
6286 # input for the respective bypte lane of the PHY
6287 # PSU_DDR_PHY_DX0GCR0_RDDLY 0x8
6289 # Reserved. Return zeroes on reads.
6290 # PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0
6292 # DQSNSE Power Down Receiver
6293 # PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0
6295 # DQSSE Power Down Receiver
6296 # PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0
6298 # RTT On Additive Latency
6299 # PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0
6302 # PSU_DDR_PHY_DX0GCR0_RTTOH 0x3
6304 # Configurable PDR Phase Shift
6305 # PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0
6308 # PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0
6310 # DQSG Power Down Receiver
6311 # PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0
6313 # Reserved. Return zeroes on reads.
6314 # PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0
6316 # DQSG On-Die Termination
6317 # PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0
6319 # DQSG Output Enable
6320 # PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1
6322 # Reserved. Return zeroes on reads.
6323 # PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0
6325 # DATX8 n General Configuration Register 0
6326 #(OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) */
6327 mask_write 0XFD080700 0xFFFFFFFF 0x40800604
6328 # Register : DX0GCR4 @ 0XFD080710</p>
6330 # Byte lane VREF IOM (Used only by D4MU IOs)
6331 # PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0
6333 # Byte Lane VREF Pad Enable
6334 # PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0
6336 # Byte Lane Internal VREF Enable
6337 # PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3
6339 # Byte Lane Single-End VREF Enable
6340 # PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1
6342 # Reserved. Returns zeros on reads.
6343 # PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0
6345 # External VREF generator REFSEL range select
6346 # PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0
6348 # Byte Lane External VREF Select
6349 # PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0
6351 # Single ended VREF generator REFSEL range select
6352 # PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1
6354 # Byte Lane Single-End VREF Select
6355 # PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30
6357 # Reserved. Returns zeros on reads.
6358 # PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0
6360 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6361 # PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf
6363 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6364 # PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0
6366 # DATX8 n General Configuration Register 4
6367 #(OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) */
6368 mask_write 0XFD080710 0xFFFFFFFF 0x0E00B03C
6369 # Register : DX0GCR5 @ 0XFD080714</p>
6371 # Reserved. Returns zeros on reads.
6372 # PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0
6374 # Byte Lane internal VREF Select for Rank 3
6375 # PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9
6377 # Reserved. Returns zeros on reads.
6378 # PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0
6380 # Byte Lane internal VREF Select for Rank 2
6381 # PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9
6383 # Reserved. Returns zeros on reads.
6384 # PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0
6386 # Byte Lane internal VREF Select for Rank 1
6387 # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55
6389 # Reserved. Returns zeros on reads.
6390 # PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0
6392 # Byte Lane internal VREF Select for Rank 0
6393 # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55
6395 # DATX8 n General Configuration Register 5
6396 #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */
6397 mask_write 0XFD080714 0xFFFFFFFF 0x09095555
6398 # Register : DX0GCR6 @ 0XFD080718</p>
6400 # Reserved. Returns zeros on reads.
6401 # PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0
6403 # DRAM DQ VREF Select for Rank3
6404 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9
6406 # Reserved. Returns zeros on reads.
6407 # PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0
6409 # DRAM DQ VREF Select for Rank2
6410 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9
6412 # Reserved. Returns zeros on reads.
6413 # PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0
6415 # DRAM DQ VREF Select for Rank1
6416 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b
6418 # Reserved. Returns zeros on reads.
6419 # PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0
6421 # DRAM DQ VREF Select for Rank0
6422 # PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b
6424 # DATX8 n General Configuration Register 6
6425 #(OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) */
6426 mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B
6427 # Register : DX1GCR0 @ 0XFD080800</p>
6429 # Calibration Bypass
6430 # PSU_DDR_PHY_DX1GCR0_CALBYP 0x0
6432 # Master Delay Line Enable
6433 # PSU_DDR_PHY_DX1GCR0_MDLEN 0x1
6435 # Configurable ODT(TE) Phase Shift
6436 # PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0
6438 # DQS Duty Cycle Correction
6439 # PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0
6441 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
6442 # input for the respective bypte lane of the PHY
6443 # PSU_DDR_PHY_DX1GCR0_RDDLY 0x8
6445 # Reserved. Return zeroes on reads.
6446 # PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0
6448 # DQSNSE Power Down Receiver
6449 # PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0
6451 # DQSSE Power Down Receiver
6452 # PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0
6454 # RTT On Additive Latency
6455 # PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0
6458 # PSU_DDR_PHY_DX1GCR0_RTTOH 0x3
6460 # Configurable PDR Phase Shift
6461 # PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0
6464 # PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0
6466 # DQSG Power Down Receiver
6467 # PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0
6469 # Reserved. Return zeroes on reads.
6470 # PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0
6472 # DQSG On-Die Termination
6473 # PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0
6475 # DQSG Output Enable
6476 # PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1
6478 # Reserved. Return zeroes on reads.
6479 # PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0
6481 # DATX8 n General Configuration Register 0
6482 #(OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) */
6483 mask_write 0XFD080800 0xFFFFFFFF 0x40800604
6484 # Register : DX1GCR4 @ 0XFD080810</p>
6486 # Byte lane VREF IOM (Used only by D4MU IOs)
6487 # PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0
6489 # Byte Lane VREF Pad Enable
6490 # PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0
6492 # Byte Lane Internal VREF Enable
6493 # PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3
6495 # Byte Lane Single-End VREF Enable
6496 # PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1
6498 # Reserved. Returns zeros on reads.
6499 # PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0
6501 # External VREF generator REFSEL range select
6502 # PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0
6504 # Byte Lane External VREF Select
6505 # PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0
6507 # Single ended VREF generator REFSEL range select
6508 # PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1
6510 # Byte Lane Single-End VREF Select
6511 # PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30
6513 # Reserved. Returns zeros on reads.
6514 # PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0
6516 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6517 # PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf
6519 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6520 # PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0
6522 # DATX8 n General Configuration Register 4
6523 #(OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) */
6524 mask_write 0XFD080810 0xFFFFFFFF 0x0E00B03C
6525 # Register : DX1GCR5 @ 0XFD080814</p>
6527 # Reserved. Returns zeros on reads.
6528 # PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0
6530 # Byte Lane internal VREF Select for Rank 3
6531 # PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9
6533 # Reserved. Returns zeros on reads.
6534 # PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0
6536 # Byte Lane internal VREF Select for Rank 2
6537 # PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9
6539 # Reserved. Returns zeros on reads.
6540 # PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0
6542 # Byte Lane internal VREF Select for Rank 1
6543 # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55
6545 # Reserved. Returns zeros on reads.
6546 # PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0
6548 # Byte Lane internal VREF Select for Rank 0
6549 # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55
6551 # DATX8 n General Configuration Register 5
6552 #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */
6553 mask_write 0XFD080814 0xFFFFFFFF 0x09095555
6554 # Register : DX1GCR6 @ 0XFD080818</p>
6556 # Reserved. Returns zeros on reads.
6557 # PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0
6559 # DRAM DQ VREF Select for Rank3
6560 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9
6562 # Reserved. Returns zeros on reads.
6563 # PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0
6565 # DRAM DQ VREF Select for Rank2
6566 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9
6568 # Reserved. Returns zeros on reads.
6569 # PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0
6571 # DRAM DQ VREF Select for Rank1
6572 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b
6574 # Reserved. Returns zeros on reads.
6575 # PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0
6577 # DRAM DQ VREF Select for Rank0
6578 # PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b
6580 # DATX8 n General Configuration Register 6
6581 #(OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) */
6582 mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B
6583 # Register : DX2GCR0 @ 0XFD080900</p>
6585 # Calibration Bypass
6586 # PSU_DDR_PHY_DX2GCR0_CALBYP 0x0
6588 # Master Delay Line Enable
6589 # PSU_DDR_PHY_DX2GCR0_MDLEN 0x1
6591 # Configurable ODT(TE) Phase Shift
6592 # PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0
6594 # DQS Duty Cycle Correction
6595 # PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0
6597 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
6598 # input for the respective bypte lane of the PHY
6599 # PSU_DDR_PHY_DX2GCR0_RDDLY 0x8
6601 # Reserved. Return zeroes on reads.
6602 # PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0
6604 # DQSNSE Power Down Receiver
6605 # PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0
6607 # DQSSE Power Down Receiver
6608 # PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0
6610 # RTT On Additive Latency
6611 # PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0
6614 # PSU_DDR_PHY_DX2GCR0_RTTOH 0x3
6616 # Configurable PDR Phase Shift
6617 # PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0
6620 # PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0
6622 # DQSG Power Down Receiver
6623 # PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0
6625 # Reserved. Return zeroes on reads.
6626 # PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0
6628 # DQSG On-Die Termination
6629 # PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0
6631 # DQSG Output Enable
6632 # PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1
6634 # Reserved. Return zeroes on reads.
6635 # PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0
6637 # DATX8 n General Configuration Register 0
6638 #(OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) */
6639 mask_write 0XFD080900 0xFFFFFFFF 0x40800604
6640 # Register : DX2GCR1 @ 0XFD080904</p>
6642 # Enables the PDR mode for DQ[7:0]
6643 # PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0
6645 # Reserved. Returns zeroes on reads.
6646 # PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0
6648 # Select the delayed or non-delayed read data strobe #
6649 # PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1
6651 # Select the delayed or non-delayed read data strobe
6652 # PSU_DDR_PHY_DX2GCR1_QSSEL 0x1
6654 # Enables Read Data Strobe in a byte lane
6655 # PSU_DDR_PHY_DX2GCR1_OEEN 0x1
6657 # Enables PDR in a byte lane
6658 # PSU_DDR_PHY_DX2GCR1_PDREN 0x1
6660 # Enables ODT/TE in a byte lane
6661 # PSU_DDR_PHY_DX2GCR1_TEEN 0x1
6663 # Enables Write Data strobe in a byte lane
6664 # PSU_DDR_PHY_DX2GCR1_DSEN 0x1
6666 # Enables DM pin in a byte lane
6667 # PSU_DDR_PHY_DX2GCR1_DMEN 0x1
6669 # Enables DQ corresponding to each bit in a byte
6670 # PSU_DDR_PHY_DX2GCR1_DQEN 0xff
6672 # DATX8 n General Configuration Register 1
6673 #(OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) */
6674 mask_write 0XFD080904 0xFFFFFFFF 0x00007FFF
6675 # Register : DX2GCR4 @ 0XFD080910</p>
6677 # Byte lane VREF IOM (Used only by D4MU IOs)
6678 # PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0
6680 # Byte Lane VREF Pad Enable
6681 # PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0
6683 # Byte Lane Internal VREF Enable
6684 # PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3
6686 # Byte Lane Single-End VREF Enable
6687 # PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1
6689 # Reserved. Returns zeros on reads.
6690 # PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0
6692 # External VREF generator REFSEL range select
6693 # PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0
6695 # Byte Lane External VREF Select
6696 # PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0
6698 # Single ended VREF generator REFSEL range select
6699 # PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1
6701 # Byte Lane Single-End VREF Select
6702 # PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30
6704 # Reserved. Returns zeros on reads.
6705 # PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0
6707 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6708 # PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf
6710 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6711 # PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0
6713 # DATX8 n General Configuration Register 4
6714 #(OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) */
6715 mask_write 0XFD080910 0xFFFFFFFF 0x0E00B03C
6716 # Register : DX2GCR5 @ 0XFD080914</p>
6718 # Reserved. Returns zeros on reads.
6719 # PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0
6721 # Byte Lane internal VREF Select for Rank 3
6722 # PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9
6724 # Reserved. Returns zeros on reads.
6725 # PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0
6727 # Byte Lane internal VREF Select for Rank 2
6728 # PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9
6730 # Reserved. Returns zeros on reads.
6731 # PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0
6733 # Byte Lane internal VREF Select for Rank 1
6734 # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55
6736 # Reserved. Returns zeros on reads.
6737 # PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0
6739 # Byte Lane internal VREF Select for Rank 0
6740 # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55
6742 # DATX8 n General Configuration Register 5
6743 #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */
6744 mask_write 0XFD080914 0xFFFFFFFF 0x09095555
6745 # Register : DX2GCR6 @ 0XFD080918</p>
6747 # Reserved. Returns zeros on reads.
6748 # PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0
6750 # DRAM DQ VREF Select for Rank3
6751 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9
6753 # Reserved. Returns zeros on reads.
6754 # PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0
6756 # DRAM DQ VREF Select for Rank2
6757 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9
6759 # Reserved. Returns zeros on reads.
6760 # PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0
6762 # DRAM DQ VREF Select for Rank1
6763 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b
6765 # Reserved. Returns zeros on reads.
6766 # PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0
6768 # DRAM DQ VREF Select for Rank0
6769 # PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b
6771 # DATX8 n General Configuration Register 6
6772 #(OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) */
6773 mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B
6774 # Register : DX3GCR0 @ 0XFD080A00</p>
6776 # Calibration Bypass
6777 # PSU_DDR_PHY_DX3GCR0_CALBYP 0x0
6779 # Master Delay Line Enable
6780 # PSU_DDR_PHY_DX3GCR0_MDLEN 0x1
6782 # Configurable ODT(TE) Phase Shift
6783 # PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0
6785 # DQS Duty Cycle Correction
6786 # PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0
6788 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
6789 # input for the respective bypte lane of the PHY
6790 # PSU_DDR_PHY_DX3GCR0_RDDLY 0x8
6792 # Reserved. Return zeroes on reads.
6793 # PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0
6795 # DQSNSE Power Down Receiver
6796 # PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0
6798 # DQSSE Power Down Receiver
6799 # PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0
6801 # RTT On Additive Latency
6802 # PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0
6805 # PSU_DDR_PHY_DX3GCR0_RTTOH 0x3
6807 # Configurable PDR Phase Shift
6808 # PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0
6811 # PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0
6813 # DQSG Power Down Receiver
6814 # PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0
6816 # Reserved. Return zeroes on reads.
6817 # PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0
6819 # DQSG On-Die Termination
6820 # PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0
6822 # DQSG Output Enable
6823 # PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1
6825 # Reserved. Return zeroes on reads.
6826 # PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0
6828 # DATX8 n General Configuration Register 0
6829 #(OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) */
6830 mask_write 0XFD080A00 0xFFFFFFFF 0x40800604
6831 # Register : DX3GCR1 @ 0XFD080A04</p>
6833 # Enables the PDR mode for DQ[7:0]
6834 # PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0
6836 # Reserved. Returns zeroes on reads.
6837 # PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0
6839 # Select the delayed or non-delayed read data strobe #
6840 # PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1
6842 # Select the delayed or non-delayed read data strobe
6843 # PSU_DDR_PHY_DX3GCR1_QSSEL 0x1
6845 # Enables Read Data Strobe in a byte lane
6846 # PSU_DDR_PHY_DX3GCR1_OEEN 0x1
6848 # Enables PDR in a byte lane
6849 # PSU_DDR_PHY_DX3GCR1_PDREN 0x1
6851 # Enables ODT/TE in a byte lane
6852 # PSU_DDR_PHY_DX3GCR1_TEEN 0x1
6854 # Enables Write Data strobe in a byte lane
6855 # PSU_DDR_PHY_DX3GCR1_DSEN 0x1
6857 # Enables DM pin in a byte lane
6858 # PSU_DDR_PHY_DX3GCR1_DMEN 0x1
6860 # Enables DQ corresponding to each bit in a byte
6861 # PSU_DDR_PHY_DX3GCR1_DQEN 0xff
6863 # DATX8 n General Configuration Register 1
6864 #(OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) */
6865 mask_write 0XFD080A04 0xFFFFFFFF 0x00007FFF
6866 # Register : DX3GCR4 @ 0XFD080A10</p>
6868 # Byte lane VREF IOM (Used only by D4MU IOs)
6869 # PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0
6871 # Byte Lane VREF Pad Enable
6872 # PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0
6874 # Byte Lane Internal VREF Enable
6875 # PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3
6877 # Byte Lane Single-End VREF Enable
6878 # PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1
6880 # Reserved. Returns zeros on reads.
6881 # PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0
6883 # External VREF generator REFSEL range select
6884 # PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0
6886 # Byte Lane External VREF Select
6887 # PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0
6889 # Single ended VREF generator REFSEL range select
6890 # PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1
6892 # Byte Lane Single-End VREF Select
6893 # PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30
6895 # Reserved. Returns zeros on reads.
6896 # PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0
6898 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
6899 # PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf
6901 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
6902 # PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0
6904 # DATX8 n General Configuration Register 4
6905 #(OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) */
6906 mask_write 0XFD080A10 0xFFFFFFFF 0x0E00B03C
6907 # Register : DX3GCR5 @ 0XFD080A14</p>
6909 # Reserved. Returns zeros on reads.
6910 # PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0
6912 # Byte Lane internal VREF Select for Rank 3
6913 # PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9
6915 # Reserved. Returns zeros on reads.
6916 # PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0
6918 # Byte Lane internal VREF Select for Rank 2
6919 # PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9
6921 # Reserved. Returns zeros on reads.
6922 # PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0
6924 # Byte Lane internal VREF Select for Rank 1
6925 # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55
6927 # Reserved. Returns zeros on reads.
6928 # PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0
6930 # Byte Lane internal VREF Select for Rank 0
6931 # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55
6933 # DATX8 n General Configuration Register 5
6934 #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */
6935 mask_write 0XFD080A14 0xFFFFFFFF 0x09095555
6936 # Register : DX3GCR6 @ 0XFD080A18</p>
6938 # Reserved. Returns zeros on reads.
6939 # PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0
6941 # DRAM DQ VREF Select for Rank3
6942 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9
6944 # Reserved. Returns zeros on reads.
6945 # PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0
6947 # DRAM DQ VREF Select for Rank2
6948 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9
6950 # Reserved. Returns zeros on reads.
6951 # PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0
6953 # DRAM DQ VREF Select for Rank1
6954 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b
6956 # Reserved. Returns zeros on reads.
6957 # PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0
6959 # DRAM DQ VREF Select for Rank0
6960 # PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b
6962 # DATX8 n General Configuration Register 6
6963 #(OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) */
6964 mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B
6965 # Register : DX4GCR0 @ 0XFD080B00</p>
6967 # Calibration Bypass
6968 # PSU_DDR_PHY_DX4GCR0_CALBYP 0x0
6970 # Master Delay Line Enable
6971 # PSU_DDR_PHY_DX4GCR0_MDLEN 0x1
6973 # Configurable ODT(TE) Phase Shift
6974 # PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0
6976 # DQS Duty Cycle Correction
6977 # PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0
6979 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
6980 # input for the respective bypte lane of the PHY
6981 # PSU_DDR_PHY_DX4GCR0_RDDLY 0x8
6983 # Reserved. Return zeroes on reads.
6984 # PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0
6986 # DQSNSE Power Down Receiver
6987 # PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0
6989 # DQSSE Power Down Receiver
6990 # PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0
6992 # RTT On Additive Latency
6993 # PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0
6996 # PSU_DDR_PHY_DX4GCR0_RTTOH 0x3
6998 # Configurable PDR Phase Shift
6999 # PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0
7002 # PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0
7004 # DQSG Power Down Receiver
7005 # PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0
7007 # Reserved. Return zeroes on reads.
7008 # PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0
7010 # DQSG On-Die Termination
7011 # PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0
7013 # DQSG Output Enable
7014 # PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1
7016 # Reserved. Return zeroes on reads.
7017 # PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0
7019 # DATX8 n General Configuration Register 0
7020 #(OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) */
7021 mask_write 0XFD080B00 0xFFFFFFFF 0x40800604
7022 # Register : DX4GCR1 @ 0XFD080B04</p>
7024 # Enables the PDR mode for DQ[7:0]
7025 # PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0
7027 # Reserved. Returns zeroes on reads.
7028 # PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0
7030 # Select the delayed or non-delayed read data strobe #
7031 # PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1
7033 # Select the delayed or non-delayed read data strobe
7034 # PSU_DDR_PHY_DX4GCR1_QSSEL 0x1
7036 # Enables Read Data Strobe in a byte lane
7037 # PSU_DDR_PHY_DX4GCR1_OEEN 0x1
7039 # Enables PDR in a byte lane
7040 # PSU_DDR_PHY_DX4GCR1_PDREN 0x1
7042 # Enables ODT/TE in a byte lane
7043 # PSU_DDR_PHY_DX4GCR1_TEEN 0x1
7045 # Enables Write Data strobe in a byte lane
7046 # PSU_DDR_PHY_DX4GCR1_DSEN 0x1
7048 # Enables DM pin in a byte lane
7049 # PSU_DDR_PHY_DX4GCR1_DMEN 0x1
7051 # Enables DQ corresponding to each bit in a byte
7052 # PSU_DDR_PHY_DX4GCR1_DQEN 0xff
7054 # DATX8 n General Configuration Register 1
7055 #(OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) */
7056 mask_write 0XFD080B04 0xFFFFFFFF 0x00007FFF
7057 # Register : DX4GCR4 @ 0XFD080B10</p>
7059 # Byte lane VREF IOM (Used only by D4MU IOs)
7060 # PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0
7062 # Byte Lane VREF Pad Enable
7063 # PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0
7065 # Byte Lane Internal VREF Enable
7066 # PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3
7068 # Byte Lane Single-End VREF Enable
7069 # PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1
7071 # Reserved. Returns zeros on reads.
7072 # PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0
7074 # External VREF generator REFSEL range select
7075 # PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0
7077 # Byte Lane External VREF Select
7078 # PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0
7080 # Single ended VREF generator REFSEL range select
7081 # PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1
7083 # Byte Lane Single-End VREF Select
7084 # PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30
7086 # Reserved. Returns zeros on reads.
7087 # PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0
7089 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7090 # PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf
7092 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7093 # PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0
7095 # DATX8 n General Configuration Register 4
7096 #(OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) */
7097 mask_write 0XFD080B10 0xFFFFFFFF 0x0E00B03C
7098 # Register : DX4GCR5 @ 0XFD080B14</p>
7100 # Reserved. Returns zeros on reads.
7101 # PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0
7103 # Byte Lane internal VREF Select for Rank 3
7104 # PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9
7106 # Reserved. Returns zeros on reads.
7107 # PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0
7109 # Byte Lane internal VREF Select for Rank 2
7110 # PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9
7112 # Reserved. Returns zeros on reads.
7113 # PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0
7115 # Byte Lane internal VREF Select for Rank 1
7116 # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55
7118 # Reserved. Returns zeros on reads.
7119 # PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0
7121 # Byte Lane internal VREF Select for Rank 0
7122 # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55
7124 # DATX8 n General Configuration Register 5
7125 #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */
7126 mask_write 0XFD080B14 0xFFFFFFFF 0x09095555
7127 # Register : DX4GCR6 @ 0XFD080B18</p>
7129 # Reserved. Returns zeros on reads.
7130 # PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0
7132 # DRAM DQ VREF Select for Rank3
7133 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9
7135 # Reserved. Returns zeros on reads.
7136 # PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0
7138 # DRAM DQ VREF Select for Rank2
7139 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9
7141 # Reserved. Returns zeros on reads.
7142 # PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0
7144 # DRAM DQ VREF Select for Rank1
7145 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b
7147 # Reserved. Returns zeros on reads.
7148 # PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0
7150 # DRAM DQ VREF Select for Rank0
7151 # PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b
7153 # DATX8 n General Configuration Register 6
7154 #(OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) */
7155 mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B
7156 # Register : DX5GCR0 @ 0XFD080C00</p>
7158 # Calibration Bypass
7159 # PSU_DDR_PHY_DX5GCR0_CALBYP 0x0
7161 # Master Delay Line Enable
7162 # PSU_DDR_PHY_DX5GCR0_MDLEN 0x1
7164 # Configurable ODT(TE) Phase Shift
7165 # PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0
7167 # DQS Duty Cycle Correction
7168 # PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0
7170 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7171 # input for the respective bypte lane of the PHY
7172 # PSU_DDR_PHY_DX5GCR0_RDDLY 0x8
7174 # Reserved. Return zeroes on reads.
7175 # PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0
7177 # DQSNSE Power Down Receiver
7178 # PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0
7180 # DQSSE Power Down Receiver
7181 # PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0
7183 # RTT On Additive Latency
7184 # PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0
7187 # PSU_DDR_PHY_DX5GCR0_RTTOH 0x3
7189 # Configurable PDR Phase Shift
7190 # PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0
7193 # PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0
7195 # DQSG Power Down Receiver
7196 # PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0
7198 # Reserved. Return zeroes on reads.
7199 # PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0
7201 # DQSG On-Die Termination
7202 # PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0
7204 # DQSG Output Enable
7205 # PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1
7207 # Reserved. Return zeroes on reads.
7208 # PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0
7210 # DATX8 n General Configuration Register 0
7211 #(OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) */
7212 mask_write 0XFD080C00 0xFFFFFFFF 0x40800604
7213 # Register : DX5GCR1 @ 0XFD080C04</p>
7215 # Enables the PDR mode for DQ[7:0]
7216 # PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0
7218 # Reserved. Returns zeroes on reads.
7219 # PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0
7221 # Select the delayed or non-delayed read data strobe #
7222 # PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1
7224 # Select the delayed or non-delayed read data strobe
7225 # PSU_DDR_PHY_DX5GCR1_QSSEL 0x1
7227 # Enables Read Data Strobe in a byte lane
7228 # PSU_DDR_PHY_DX5GCR1_OEEN 0x1
7230 # Enables PDR in a byte lane
7231 # PSU_DDR_PHY_DX5GCR1_PDREN 0x1
7233 # Enables ODT/TE in a byte lane
7234 # PSU_DDR_PHY_DX5GCR1_TEEN 0x1
7236 # Enables Write Data strobe in a byte lane
7237 # PSU_DDR_PHY_DX5GCR1_DSEN 0x1
7239 # Enables DM pin in a byte lane
7240 # PSU_DDR_PHY_DX5GCR1_DMEN 0x1
7242 # Enables DQ corresponding to each bit in a byte
7243 # PSU_DDR_PHY_DX5GCR1_DQEN 0xff
7245 # DATX8 n General Configuration Register 1
7246 #(OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) */
7247 mask_write 0XFD080C04 0xFFFFFFFF 0x00007FFF
7248 # Register : DX5GCR4 @ 0XFD080C10</p>
7250 # Byte lane VREF IOM (Used only by D4MU IOs)
7251 # PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0
7253 # Byte Lane VREF Pad Enable
7254 # PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0
7256 # Byte Lane Internal VREF Enable
7257 # PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3
7259 # Byte Lane Single-End VREF Enable
7260 # PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1
7262 # Reserved. Returns zeros on reads.
7263 # PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0
7265 # External VREF generator REFSEL range select
7266 # PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0
7268 # Byte Lane External VREF Select
7269 # PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0
7271 # Single ended VREF generator REFSEL range select
7272 # PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1
7274 # Byte Lane Single-End VREF Select
7275 # PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30
7277 # Reserved. Returns zeros on reads.
7278 # PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0
7280 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7281 # PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf
7283 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7284 # PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0
7286 # DATX8 n General Configuration Register 4
7287 #(OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) */
7288 mask_write 0XFD080C10 0xFFFFFFFF 0x0E00B03C
7289 # Register : DX5GCR5 @ 0XFD080C14</p>
7291 # Reserved. Returns zeros on reads.
7292 # PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0
7294 # Byte Lane internal VREF Select for Rank 3
7295 # PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9
7297 # Reserved. Returns zeros on reads.
7298 # PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0
7300 # Byte Lane internal VREF Select for Rank 2
7301 # PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9
7303 # Reserved. Returns zeros on reads.
7304 # PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0
7306 # Byte Lane internal VREF Select for Rank 1
7307 # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55
7309 # Reserved. Returns zeros on reads.
7310 # PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0
7312 # Byte Lane internal VREF Select for Rank 0
7313 # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55
7315 # DATX8 n General Configuration Register 5
7316 #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */
7317 mask_write 0XFD080C14 0xFFFFFFFF 0x09095555
7318 # Register : DX5GCR6 @ 0XFD080C18</p>
7320 # Reserved. Returns zeros on reads.
7321 # PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0
7323 # DRAM DQ VREF Select for Rank3
7324 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9
7326 # Reserved. Returns zeros on reads.
7327 # PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0
7329 # DRAM DQ VREF Select for Rank2
7330 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9
7332 # Reserved. Returns zeros on reads.
7333 # PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0
7335 # DRAM DQ VREF Select for Rank1
7336 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b
7338 # Reserved. Returns zeros on reads.
7339 # PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0
7341 # DRAM DQ VREF Select for Rank0
7342 # PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b
7344 # DATX8 n General Configuration Register 6
7345 #(OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) */
7346 mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B
7347 # Register : DX6GCR0 @ 0XFD080D00</p>
7349 # Calibration Bypass
7350 # PSU_DDR_PHY_DX6GCR0_CALBYP 0x0
7352 # Master Delay Line Enable
7353 # PSU_DDR_PHY_DX6GCR0_MDLEN 0x1
7355 # Configurable ODT(TE) Phase Shift
7356 # PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0
7358 # DQS Duty Cycle Correction
7359 # PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0
7361 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7362 # input for the respective bypte lane of the PHY
7363 # PSU_DDR_PHY_DX6GCR0_RDDLY 0x8
7365 # Reserved. Return zeroes on reads.
7366 # PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0
7368 # DQSNSE Power Down Receiver
7369 # PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0
7371 # DQSSE Power Down Receiver
7372 # PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0
7374 # RTT On Additive Latency
7375 # PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0
7378 # PSU_DDR_PHY_DX6GCR0_RTTOH 0x3
7380 # Configurable PDR Phase Shift
7381 # PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0
7384 # PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0
7386 # DQSG Power Down Receiver
7387 # PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0
7389 # Reserved. Return zeroes on reads.
7390 # PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0
7392 # DQSG On-Die Termination
7393 # PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0
7395 # DQSG Output Enable
7396 # PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1
7398 # Reserved. Return zeroes on reads.
7399 # PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0
7401 # DATX8 n General Configuration Register 0
7402 #(OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) */
7403 mask_write 0XFD080D00 0xFFFFFFFF 0x40800604
7404 # Register : DX6GCR1 @ 0XFD080D04</p>
7406 # Enables the PDR mode for DQ[7:0]
7407 # PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0
7409 # Reserved. Returns zeroes on reads.
7410 # PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0
7412 # Select the delayed or non-delayed read data strobe #
7413 # PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1
7415 # Select the delayed or non-delayed read data strobe
7416 # PSU_DDR_PHY_DX6GCR1_QSSEL 0x1
7418 # Enables Read Data Strobe in a byte lane
7419 # PSU_DDR_PHY_DX6GCR1_OEEN 0x1
7421 # Enables PDR in a byte lane
7422 # PSU_DDR_PHY_DX6GCR1_PDREN 0x1
7424 # Enables ODT/TE in a byte lane
7425 # PSU_DDR_PHY_DX6GCR1_TEEN 0x1
7427 # Enables Write Data strobe in a byte lane
7428 # PSU_DDR_PHY_DX6GCR1_DSEN 0x1
7430 # Enables DM pin in a byte lane
7431 # PSU_DDR_PHY_DX6GCR1_DMEN 0x1
7433 # Enables DQ corresponding to each bit in a byte
7434 # PSU_DDR_PHY_DX6GCR1_DQEN 0xff
7436 # DATX8 n General Configuration Register 1
7437 #(OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) */
7438 mask_write 0XFD080D04 0xFFFFFFFF 0x00007FFF
7439 # Register : DX6GCR4 @ 0XFD080D10</p>
7441 # Byte lane VREF IOM (Used only by D4MU IOs)
7442 # PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0
7444 # Byte Lane VREF Pad Enable
7445 # PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0
7447 # Byte Lane Internal VREF Enable
7448 # PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3
7450 # Byte Lane Single-End VREF Enable
7451 # PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1
7453 # Reserved. Returns zeros on reads.
7454 # PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0
7456 # External VREF generator REFSEL range select
7457 # PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0
7459 # Byte Lane External VREF Select
7460 # PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0
7462 # Single ended VREF generator REFSEL range select
7463 # PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1
7465 # Byte Lane Single-End VREF Select
7466 # PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30
7468 # Reserved. Returns zeros on reads.
7469 # PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0
7471 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7472 # PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf
7474 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7475 # PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0
7477 # DATX8 n General Configuration Register 4
7478 #(OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) */
7479 mask_write 0XFD080D10 0xFFFFFFFF 0x0E00B03C
7480 # Register : DX6GCR5 @ 0XFD080D14</p>
7482 # Reserved. Returns zeros on reads.
7483 # PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0
7485 # Byte Lane internal VREF Select for Rank 3
7486 # PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9
7488 # Reserved. Returns zeros on reads.
7489 # PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0
7491 # Byte Lane internal VREF Select for Rank 2
7492 # PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9
7494 # Reserved. Returns zeros on reads.
7495 # PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0
7497 # Byte Lane internal VREF Select for Rank 1
7498 # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55
7500 # Reserved. Returns zeros on reads.
7501 # PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0
7503 # Byte Lane internal VREF Select for Rank 0
7504 # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55
7506 # DATX8 n General Configuration Register 5
7507 #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */
7508 mask_write 0XFD080D14 0xFFFFFFFF 0x09095555
7509 # Register : DX6GCR6 @ 0XFD080D18</p>
7511 # Reserved. Returns zeros on reads.
7512 # PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0
7514 # DRAM DQ VREF Select for Rank3
7515 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9
7517 # Reserved. Returns zeros on reads.
7518 # PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0
7520 # DRAM DQ VREF Select for Rank2
7521 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9
7523 # Reserved. Returns zeros on reads.
7524 # PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0
7526 # DRAM DQ VREF Select for Rank1
7527 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b
7529 # Reserved. Returns zeros on reads.
7530 # PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0
7532 # DRAM DQ VREF Select for Rank0
7533 # PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b
7535 # DATX8 n General Configuration Register 6
7536 #(OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) */
7537 mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B
7538 # Register : DX7GCR0 @ 0XFD080E00</p>
7540 # Calibration Bypass
7541 # PSU_DDR_PHY_DX7GCR0_CALBYP 0x0
7543 # Master Delay Line Enable
7544 # PSU_DDR_PHY_DX7GCR0_MDLEN 0x1
7546 # Configurable ODT(TE) Phase Shift
7547 # PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0
7549 # DQS Duty Cycle Correction
7550 # PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0
7552 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7553 # input for the respective bypte lane of the PHY
7554 # PSU_DDR_PHY_DX7GCR0_RDDLY 0x8
7556 # Reserved. Return zeroes on reads.
7557 # PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0
7559 # DQSNSE Power Down Receiver
7560 # PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0
7562 # DQSSE Power Down Receiver
7563 # PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0
7565 # RTT On Additive Latency
7566 # PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0
7569 # PSU_DDR_PHY_DX7GCR0_RTTOH 0x3
7571 # Configurable PDR Phase Shift
7572 # PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0
7575 # PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0
7577 # DQSG Power Down Receiver
7578 # PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0
7580 # Reserved. Return zeroes on reads.
7581 # PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0
7583 # DQSG On-Die Termination
7584 # PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0
7586 # DQSG Output Enable
7587 # PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1
7589 # Reserved. Return zeroes on reads.
7590 # PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0
7592 # DATX8 n General Configuration Register 0
7593 #(OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) */
7594 mask_write 0XFD080E00 0xFFFFFFFF 0x40800604
7595 # Register : DX7GCR1 @ 0XFD080E04</p>
7597 # Enables the PDR mode for DQ[7:0]
7598 # PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0
7600 # Reserved. Returns zeroes on reads.
7601 # PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0
7603 # Select the delayed or non-delayed read data strobe #
7604 # PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1
7606 # Select the delayed or non-delayed read data strobe
7607 # PSU_DDR_PHY_DX7GCR1_QSSEL 0x1
7609 # Enables Read Data Strobe in a byte lane
7610 # PSU_DDR_PHY_DX7GCR1_OEEN 0x1
7612 # Enables PDR in a byte lane
7613 # PSU_DDR_PHY_DX7GCR1_PDREN 0x1
7615 # Enables ODT/TE in a byte lane
7616 # PSU_DDR_PHY_DX7GCR1_TEEN 0x1
7618 # Enables Write Data strobe in a byte lane
7619 # PSU_DDR_PHY_DX7GCR1_DSEN 0x1
7621 # Enables DM pin in a byte lane
7622 # PSU_DDR_PHY_DX7GCR1_DMEN 0x1
7624 # Enables DQ corresponding to each bit in a byte
7625 # PSU_DDR_PHY_DX7GCR1_DQEN 0xff
7627 # DATX8 n General Configuration Register 1
7628 #(OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) */
7629 mask_write 0XFD080E04 0xFFFFFFFF 0x00007FFF
7630 # Register : DX7GCR4 @ 0XFD080E10</p>
7632 # Byte lane VREF IOM (Used only by D4MU IOs)
7633 # PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0
7635 # Byte Lane VREF Pad Enable
7636 # PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0
7638 # Byte Lane Internal VREF Enable
7639 # PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3
7641 # Byte Lane Single-End VREF Enable
7642 # PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1
7644 # Reserved. Returns zeros on reads.
7645 # PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0
7647 # External VREF generator REFSEL range select
7648 # PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0
7650 # Byte Lane External VREF Select
7651 # PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0
7653 # Single ended VREF generator REFSEL range select
7654 # PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1
7656 # Byte Lane Single-End VREF Select
7657 # PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30
7659 # Reserved. Returns zeros on reads.
7660 # PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0
7662 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7663 # PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf
7665 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7666 # PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0
7668 # DATX8 n General Configuration Register 4
7669 #(OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) */
7670 mask_write 0XFD080E10 0xFFFFFFFF 0x0E00B03C
7671 # Register : DX7GCR5 @ 0XFD080E14</p>
7673 # Reserved. Returns zeros on reads.
7674 # PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0
7676 # Byte Lane internal VREF Select for Rank 3
7677 # PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9
7679 # Reserved. Returns zeros on reads.
7680 # PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0
7682 # Byte Lane internal VREF Select for Rank 2
7683 # PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9
7685 # Reserved. Returns zeros on reads.
7686 # PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0
7688 # Byte Lane internal VREF Select for Rank 1
7689 # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55
7691 # Reserved. Returns zeros on reads.
7692 # PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0
7694 # Byte Lane internal VREF Select for Rank 0
7695 # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55
7697 # DATX8 n General Configuration Register 5
7698 #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */
7699 mask_write 0XFD080E14 0xFFFFFFFF 0x09095555
7700 # Register : DX7GCR6 @ 0XFD080E18</p>
7702 # Reserved. Returns zeros on reads.
7703 # PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0
7705 # DRAM DQ VREF Select for Rank3
7706 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9
7708 # Reserved. Returns zeros on reads.
7709 # PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0
7711 # DRAM DQ VREF Select for Rank2
7712 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9
7714 # Reserved. Returns zeros on reads.
7715 # PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0
7717 # DRAM DQ VREF Select for Rank1
7718 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b
7720 # Reserved. Returns zeros on reads.
7721 # PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0
7723 # DRAM DQ VREF Select for Rank0
7724 # PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b
7726 # DATX8 n General Configuration Register 6
7727 #(OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) */
7728 mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B
7729 # Register : DX8GCR0 @ 0XFD080F00</p>
7731 # Calibration Bypass
7732 # PSU_DDR_PHY_DX8GCR0_CALBYP 0x0
7734 # Master Delay Line Enable
7735 # PSU_DDR_PHY_DX8GCR0_MDLEN 0x1
7737 # Configurable ODT(TE) Phase Shift
7738 # PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0
7740 # DQS Duty Cycle Correction
7741 # PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0
7743 # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
7744 # input for the respective bypte lane of the PHY
7745 # PSU_DDR_PHY_DX8GCR0_RDDLY 0x8
7747 # Reserved. Return zeroes on reads.
7748 # PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0
7750 # DQSNSE Power Down Receiver
7751 # PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0
7753 # DQSSE Power Down Receiver
7754 # PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0
7756 # RTT On Additive Latency
7757 # PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0
7760 # PSU_DDR_PHY_DX8GCR0_RTTOH 0x3
7762 # Configurable PDR Phase Shift
7763 # PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0
7766 # PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0
7768 # DQSG Power Down Receiver
7769 # PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1
7771 # Reserved. Return zeroes on reads.
7772 # PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0
7774 # DQSG On-Die Termination
7775 # PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0
7777 # DQSG Output Enable
7778 # PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1
7780 # Reserved. Return zeroes on reads.
7781 # PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0
7783 # DATX8 n General Configuration Register 0
7784 #(OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) */
7785 mask_write 0XFD080F00 0xFFFFFFFF 0x40800624
7786 # Register : DX8GCR1 @ 0XFD080F04</p>
7788 # Enables the PDR mode for DQ[7:0]
7789 # PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0
7791 # Reserved. Returns zeroes on reads.
7792 # PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0
7794 # Select the delayed or non-delayed read data strobe #
7795 # PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1
7797 # Select the delayed or non-delayed read data strobe
7798 # PSU_DDR_PHY_DX8GCR1_QSSEL 0x1
7800 # Enables Read Data Strobe in a byte lane
7801 # PSU_DDR_PHY_DX8GCR1_OEEN 0x1
7803 # Enables PDR in a byte lane
7804 # PSU_DDR_PHY_DX8GCR1_PDREN 0x1
7806 # Enables ODT/TE in a byte lane
7807 # PSU_DDR_PHY_DX8GCR1_TEEN 0x1
7809 # Enables Write Data strobe in a byte lane
7810 # PSU_DDR_PHY_DX8GCR1_DSEN 0x1
7812 # Enables DM pin in a byte lane
7813 # PSU_DDR_PHY_DX8GCR1_DMEN 0x1
7815 # Enables DQ corresponding to each bit in a byte
7816 # PSU_DDR_PHY_DX8GCR1_DQEN 0x0
7818 # DATX8 n General Configuration Register 1
7819 #(OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) */
7820 mask_write 0XFD080F04 0xFFFFFFFF 0x00007F00
7821 # Register : DX8GCR4 @ 0XFD080F10</p>
7823 # Byte lane VREF IOM (Used only by D4MU IOs)
7824 # PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0
7826 # Byte Lane VREF Pad Enable
7827 # PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0
7829 # Byte Lane Internal VREF Enable
7830 # PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3
7832 # Byte Lane Single-End VREF Enable
7833 # PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1
7835 # Reserved. Returns zeros on reads.
7836 # PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0
7838 # External VREF generator REFSEL range select
7839 # PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0
7841 # Byte Lane External VREF Select
7842 # PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0
7844 # Single ended VREF generator REFSEL range select
7845 # PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1
7847 # Byte Lane Single-End VREF Select
7848 # PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30
7850 # Reserved. Returns zeros on reads.
7851 # PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0
7853 # VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7854 # PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf
7856 # VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7857 # PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0
7859 # DATX8 n General Configuration Register 4
7860 #(OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) */
7861 mask_write 0XFD080F10 0xFFFFFFFF 0x0E00B03C
7862 # Register : DX8GCR5 @ 0XFD080F14</p>
7864 # Reserved. Returns zeros on reads.
7865 # PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0
7867 # Byte Lane internal VREF Select for Rank 3
7868 # PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9
7870 # Reserved. Returns zeros on reads.
7871 # PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0
7873 # Byte Lane internal VREF Select for Rank 2
7874 # PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9
7876 # Reserved. Returns zeros on reads.
7877 # PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0
7879 # Byte Lane internal VREF Select for Rank 1
7880 # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55
7882 # Reserved. Returns zeros on reads.
7883 # PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0
7885 # Byte Lane internal VREF Select for Rank 0
7886 # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55
7888 # DATX8 n General Configuration Register 5
7889 #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */
7890 mask_write 0XFD080F14 0xFFFFFFFF 0x09095555
7891 # Register : DX8GCR6 @ 0XFD080F18</p>
7893 # Reserved. Returns zeros on reads.
7894 # PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0
7896 # DRAM DQ VREF Select for Rank3
7897 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9
7899 # Reserved. Returns zeros on reads.
7900 # PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0
7902 # DRAM DQ VREF Select for Rank2
7903 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9
7905 # Reserved. Returns zeros on reads.
7906 # PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0
7908 # DRAM DQ VREF Select for Rank1
7909 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b
7911 # Reserved. Returns zeros on reads.
7912 # PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0
7914 # DRAM DQ VREF Select for Rank0
7915 # PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b
7917 # DATX8 n General Configuration Register 6
7918 #(OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) */
7919 mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B
7920 # Register : DX8SL0OSC @ 0XFD081400</p>
7922 # Reserved. Return zeroes on reads.
7923 # PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0
7925 # Enable Clock Gating for DX ddr_clk
7926 # PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2
7928 # Enable Clock Gating for DX ctl_rd_clk
7929 # PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2
7931 # Enable Clock Gating for DX ctl_clk
7932 # PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2
7934 # Selects the level to which clocks will be stalled when clock gating is e
7936 # PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0
7939 # PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0
7941 # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
7942 # PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0
7944 # Loopback DQS Gating
7945 # PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0
7947 # Loopback DQS Shift
7948 # PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0
7950 # PHY High-Speed Reset
7951 # PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1
7954 # PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1
7956 # Delay Line Test Start
7957 # PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0
7959 # Delay Line Test Mode
7960 # PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0
7962 # Reserved. Caution, do not write to this register field.
7963 # PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3
7965 # Oscillator Mode Write-Data Delay Line Select
7966 # PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3
7968 # Reserved. Caution, do not write to this register field.
7969 # PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3
7971 # Oscillator Mode Write-Leveling Delay Line Select
7972 # PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3
7974 # Oscillator Mode Division
7975 # PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf
7978 # PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0
7980 # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
7981 # opback, and Gated Clock Control Register
7982 #(OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) */
7983 mask_write 0XFD081400 0xFFFFFFFF 0x2A019FFE
7984 # Register : DX8SL0PLLCR0 @ 0XFD081404</p>
7987 # PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0
7990 # PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0
7993 # PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0
7995 # Reference Stop Mode
7996 # PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0
7998 # PLL Frequency Select
7999 # PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1
8002 # PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0
8004 # Charge Pump Proportional Current Control
8005 # PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8
8007 # Charge Pump Integrating Current Control
8008 # PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0
8011 # PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0
8013 # Reserved. Return zeroes on reads.
8014 # PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0
8016 # Analog Test Enable (ATOEN)
8017 # PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0
8019 # Analog Test Control
8020 # PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0
8022 # Digital Test Control
8023 # PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0
8025 # DAXT8 0-1 PLL Control Register 0
8026 #(OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) */
8027 mask_write 0XFD081404 0xFFFFFFFF 0x01100000
8028 # Register : DX8SL0DQSCTL @ 0XFD08141C</p>
8030 # Reserved. Return zeroes on reads.
8031 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0
8033 # Read Path Rise-to-Rise Mode
8034 # PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1
8036 # Reserved. Return zeroes on reads.
8037 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0
8039 # Write Path Rise-to-Rise Mode
8040 # PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1
8042 # DQS Gate Extension
8043 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0
8045 # Low Power PLL Power Down
8046 # PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1
8048 # Low Power I/O Power Down
8049 # PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1
8051 # Reserved. Return zeroes on reads.
8052 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0
8055 # PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1
8057 # Unused DQ I/O Mode
8058 # PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0
8060 # Reserved. Return zeroes on reads.
8061 # PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0
8064 # PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3
8067 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0
8070 # PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0
8072 # DATX8 0-1 DQS Control Register
8073 #(OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) */
8074 mask_write 0XFD08141C 0xFFFFFFFF 0x01264300
8075 # Register : DX8SL0DXCTL2 @ 0XFD08142C</p>
8077 # Reserved. Return zeroes on reads.
8078 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0
8080 # Configurable Read Data Enable
8081 # PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0
8083 # OX Extension during Post-amble
8084 # PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0
8086 # OE Extension during Pre-amble
8087 # PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1
8089 # Reserved. Return zeroes on reads.
8090 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0
8092 # I/O Assisted Gate Select
8093 # PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0
8095 # I/O Loopback Select
8096 # PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0
8098 # Reserved. Return zeroes on reads.
8099 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0
8101 # Low Power Wakeup Threshold
8102 # PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc
8104 # Read Data Bus Inversion Enable
8105 # PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0
8107 # Write Data Bus Inversion Enable
8108 # PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0
8110 # PUB Read FIFO Bypass
8111 # PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0
8113 # DATX8 Receive FIFO Read Mode
8114 # PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0
8116 # Disables the Read FIFO Reset
8117 # PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0
8119 # Read DQS Gate I/O Loopback
8120 # PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0
8122 # Reserved. Return zeroes on reads.
8123 # PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0
8125 # DATX8 0-1 DX Control Register 2
8126 #(OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) */
8127 mask_write 0XFD08142C 0xFFFFFFFF 0x00041800
8128 # Register : DX8SL0IOCR @ 0XFD081430</p>
8130 # Reserved. Return zeroes on reads.
8131 # PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0
8133 # PVREF_DAC REFSEL range select
8134 # PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7
8136 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
8137 # PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0
8140 # PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2
8142 # DX IO Transmitter Mode
8143 # PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0
8145 # DX IO Receiver Mode
8146 # PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0
8148 # DATX8 0-1 I/O Configuration Register
8149 #(OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) */
8150 mask_write 0XFD081430 0xFFFFFFFF 0x70800000
8151 # Register : DX8SL1OSC @ 0XFD081440</p>
8153 # Reserved. Return zeroes on reads.
8154 # PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0
8156 # Enable Clock Gating for DX ddr_clk
8157 # PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2
8159 # Enable Clock Gating for DX ctl_rd_clk
8160 # PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2
8162 # Enable Clock Gating for DX ctl_clk
8163 # PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2
8165 # Selects the level to which clocks will be stalled when clock gating is e
8167 # PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0
8170 # PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0
8172 # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
8173 # PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0
8175 # Loopback DQS Gating
8176 # PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0
8178 # Loopback DQS Shift
8179 # PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0
8181 # PHY High-Speed Reset
8182 # PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1
8185 # PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1
8187 # Delay Line Test Start
8188 # PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0
8190 # Delay Line Test Mode
8191 # PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0
8193 # Reserved. Caution, do not write to this register field.
8194 # PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3
8196 # Oscillator Mode Write-Data Delay Line Select
8197 # PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3
8199 # Reserved. Caution, do not write to this register field.
8200 # PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3
8202 # Oscillator Mode Write-Leveling Delay Line Select
8203 # PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3
8205 # Oscillator Mode Division
8206 # PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf
8209 # PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0
8211 # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
8212 # opback, and Gated Clock Control Register
8213 #(OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) */
8214 mask_write 0XFD081440 0xFFFFFFFF 0x2A019FFE
8215 # Register : DX8SL1PLLCR0 @ 0XFD081444</p>
8218 # PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0
8221 # PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0
8224 # PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0
8226 # Reference Stop Mode
8227 # PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0
8229 # PLL Frequency Select
8230 # PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1
8233 # PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0
8235 # Charge Pump Proportional Current Control
8236 # PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8
8238 # Charge Pump Integrating Current Control
8239 # PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0
8242 # PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0
8244 # Reserved. Return zeroes on reads.
8245 # PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0
8247 # Analog Test Enable (ATOEN)
8248 # PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0
8250 # Analog Test Control
8251 # PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0
8253 # Digital Test Control
8254 # PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0
8256 # DAXT8 0-1 PLL Control Register 0
8257 #(OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) */
8258 mask_write 0XFD081444 0xFFFFFFFF 0x01100000
8259 # Register : DX8SL1DQSCTL @ 0XFD08145C</p>
8261 # Reserved. Return zeroes on reads.
8262 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0
8264 # Read Path Rise-to-Rise Mode
8265 # PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1
8267 # Reserved. Return zeroes on reads.
8268 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0
8270 # Write Path Rise-to-Rise Mode
8271 # PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1
8273 # DQS Gate Extension
8274 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0
8276 # Low Power PLL Power Down
8277 # PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1
8279 # Low Power I/O Power Down
8280 # PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1
8282 # Reserved. Return zeroes on reads.
8283 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0
8286 # PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1
8288 # Unused DQ I/O Mode
8289 # PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0
8291 # Reserved. Return zeroes on reads.
8292 # PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0
8295 # PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3
8298 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0
8301 # PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0
8303 # DATX8 0-1 DQS Control Register
8304 #(OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) */
8305 mask_write 0XFD08145C 0xFFFFFFFF 0x01264300
8306 # Register : DX8SL1DXCTL2 @ 0XFD08146C</p>
8308 # Reserved. Return zeroes on reads.
8309 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0
8311 # Configurable Read Data Enable
8312 # PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0
8314 # OX Extension during Post-amble
8315 # PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0
8317 # OE Extension during Pre-amble
8318 # PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1
8320 # Reserved. Return zeroes on reads.
8321 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0
8323 # I/O Assisted Gate Select
8324 # PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0
8326 # I/O Loopback Select
8327 # PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0
8329 # Reserved. Return zeroes on reads.
8330 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0
8332 # Low Power Wakeup Threshold
8333 # PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc
8335 # Read Data Bus Inversion Enable
8336 # PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0
8338 # Write Data Bus Inversion Enable
8339 # PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0
8341 # PUB Read FIFO Bypass
8342 # PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0
8344 # DATX8 Receive FIFO Read Mode
8345 # PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0
8347 # Disables the Read FIFO Reset
8348 # PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0
8350 # Read DQS Gate I/O Loopback
8351 # PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0
8353 # Reserved. Return zeroes on reads.
8354 # PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0
8356 # DATX8 0-1 DX Control Register 2
8357 #(OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) */
8358 mask_write 0XFD08146C 0xFFFFFFFF 0x00041800
8359 # Register : DX8SL1IOCR @ 0XFD081470</p>
8361 # Reserved. Return zeroes on reads.
8362 # PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0
8364 # PVREF_DAC REFSEL range select
8365 # PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7
8367 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
8368 # PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0
8371 # PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2
8373 # DX IO Transmitter Mode
8374 # PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0
8376 # DX IO Receiver Mode
8377 # PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0
8379 # DATX8 0-1 I/O Configuration Register
8380 #(OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) */
8381 mask_write 0XFD081470 0xFFFFFFFF 0x70800000
8382 # Register : DX8SL2OSC @ 0XFD081480</p>
8384 # Reserved. Return zeroes on reads.
8385 # PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0
8387 # Enable Clock Gating for DX ddr_clk
8388 # PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2
8390 # Enable Clock Gating for DX ctl_rd_clk
8391 # PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2
8393 # Enable Clock Gating for DX ctl_clk
8394 # PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2
8396 # Selects the level to which clocks will be stalled when clock gating is e
8398 # PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0
8401 # PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0
8403 # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
8404 # PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0
8406 # Loopback DQS Gating
8407 # PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0
8409 # Loopback DQS Shift
8410 # PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0
8412 # PHY High-Speed Reset
8413 # PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1
8416 # PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1
8418 # Delay Line Test Start
8419 # PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0
8421 # Delay Line Test Mode
8422 # PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0
8424 # Reserved. Caution, do not write to this register field.
8425 # PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3
8427 # Oscillator Mode Write-Data Delay Line Select
8428 # PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3
8430 # Reserved. Caution, do not write to this register field.
8431 # PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3
8433 # Oscillator Mode Write-Leveling Delay Line Select
8434 # PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3
8436 # Oscillator Mode Division
8437 # PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf
8440 # PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0
8442 # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
8443 # opback, and Gated Clock Control Register
8444 #(OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) */
8445 mask_write 0XFD081480 0xFFFFFFFF 0x2A019FFE
8446 # Register : DX8SL2PLLCR0 @ 0XFD081484</p>
8449 # PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0
8452 # PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0
8455 # PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0
8457 # Reference Stop Mode
8458 # PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0
8460 # PLL Frequency Select
8461 # PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1
8464 # PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0
8466 # Charge Pump Proportional Current Control
8467 # PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8
8469 # Charge Pump Integrating Current Control
8470 # PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0
8473 # PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0
8475 # Reserved. Return zeroes on reads.
8476 # PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0
8478 # Analog Test Enable (ATOEN)
8479 # PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0
8481 # Analog Test Control
8482 # PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0
8484 # Digital Test Control
8485 # PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0
8487 # DAXT8 0-1 PLL Control Register 0
8488 #(OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) */
8489 mask_write 0XFD081484 0xFFFFFFFF 0x01100000
8490 # Register : DX8SL2DQSCTL @ 0XFD08149C</p>
8492 # Reserved. Return zeroes on reads.
8493 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0
8495 # Read Path Rise-to-Rise Mode
8496 # PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1
8498 # Reserved. Return zeroes on reads.
8499 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0
8501 # Write Path Rise-to-Rise Mode
8502 # PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1
8504 # DQS Gate Extension
8505 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0
8507 # Low Power PLL Power Down
8508 # PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1
8510 # Low Power I/O Power Down
8511 # PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1
8513 # Reserved. Return zeroes on reads.
8514 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0
8517 # PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1
8519 # Unused DQ I/O Mode
8520 # PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0
8522 # Reserved. Return zeroes on reads.
8523 # PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0
8526 # PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3
8529 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0
8532 # PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0
8534 # DATX8 0-1 DQS Control Register
8535 #(OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) */
8536 mask_write 0XFD08149C 0xFFFFFFFF 0x01264300
8537 # Register : DX8SL2DXCTL2 @ 0XFD0814AC</p>
8539 # Reserved. Return zeroes on reads.
8540 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0
8542 # Configurable Read Data Enable
8543 # PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0
8545 # OX Extension during Post-amble
8546 # PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0
8548 # OE Extension during Pre-amble
8549 # PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1
8551 # Reserved. Return zeroes on reads.
8552 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0
8554 # I/O Assisted Gate Select
8555 # PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0
8557 # I/O Loopback Select
8558 # PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0
8560 # Reserved. Return zeroes on reads.
8561 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0
8563 # Low Power Wakeup Threshold
8564 # PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc
8566 # Read Data Bus Inversion Enable
8567 # PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0
8569 # Write Data Bus Inversion Enable
8570 # PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0
8572 # PUB Read FIFO Bypass
8573 # PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0
8575 # DATX8 Receive FIFO Read Mode
8576 # PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0
8578 # Disables the Read FIFO Reset
8579 # PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0
8581 # Read DQS Gate I/O Loopback
8582 # PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0
8584 # Reserved. Return zeroes on reads.
8585 # PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0
8587 # DATX8 0-1 DX Control Register 2
8588 #(OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) */
8589 mask_write 0XFD0814AC 0xFFFFFFFF 0x00041800
8590 # Register : DX8SL2IOCR @ 0XFD0814B0</p>
8592 # Reserved. Return zeroes on reads.
8593 # PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0
8595 # PVREF_DAC REFSEL range select
8596 # PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7
8598 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
8599 # PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0
8602 # PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2
8604 # DX IO Transmitter Mode
8605 # PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0
8607 # DX IO Receiver Mode
8608 # PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0
8610 # DATX8 0-1 I/O Configuration Register
8611 #(OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) */
8612 mask_write 0XFD0814B0 0xFFFFFFFF 0x70800000
8613 # Register : DX8SL3OSC @ 0XFD0814C0</p>
8615 # Reserved. Return zeroes on reads.
8616 # PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0
8618 # Enable Clock Gating for DX ddr_clk
8619 # PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2
8621 # Enable Clock Gating for DX ctl_rd_clk
8622 # PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2
8624 # Enable Clock Gating for DX ctl_clk
8625 # PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2
8627 # Selects the level to which clocks will be stalled when clock gating is e
8629 # PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0
8632 # PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0
8634 # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
8635 # PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0
8637 # Loopback DQS Gating
8638 # PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0
8640 # Loopback DQS Shift
8641 # PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0
8643 # PHY High-Speed Reset
8644 # PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1
8647 # PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1
8649 # Delay Line Test Start
8650 # PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0
8652 # Delay Line Test Mode
8653 # PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0
8655 # Reserved. Caution, do not write to this register field.
8656 # PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3
8658 # Oscillator Mode Write-Data Delay Line Select
8659 # PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3
8661 # Reserved. Caution, do not write to this register field.
8662 # PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3
8664 # Oscillator Mode Write-Leveling Delay Line Select
8665 # PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3
8667 # Oscillator Mode Division
8668 # PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf
8671 # PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0
8673 # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
8674 # opback, and Gated Clock Control Register
8675 #(OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) */
8676 mask_write 0XFD0814C0 0xFFFFFFFF 0x2A019FFE
8677 # Register : DX8SL3PLLCR0 @ 0XFD0814C4</p>
8680 # PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0
8683 # PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0
8686 # PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0
8688 # Reference Stop Mode
8689 # PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0
8691 # PLL Frequency Select
8692 # PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1
8695 # PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0
8697 # Charge Pump Proportional Current Control
8698 # PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8
8700 # Charge Pump Integrating Current Control
8701 # PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0
8704 # PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0
8706 # Reserved. Return zeroes on reads.
8707 # PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0
8709 # Analog Test Enable (ATOEN)
8710 # PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0
8712 # Analog Test Control
8713 # PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0
8715 # Digital Test Control
8716 # PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0
8718 # DAXT8 0-1 PLL Control Register 0
8719 #(OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) */
8720 mask_write 0XFD0814C4 0xFFFFFFFF 0x01100000
8721 # Register : DX8SL3DQSCTL @ 0XFD0814DC</p>
8723 # Reserved. Return zeroes on reads.
8724 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0
8726 # Read Path Rise-to-Rise Mode
8727 # PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1
8729 # Reserved. Return zeroes on reads.
8730 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0
8732 # Write Path Rise-to-Rise Mode
8733 # PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1
8735 # DQS Gate Extension
8736 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0
8738 # Low Power PLL Power Down
8739 # PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1
8741 # Low Power I/O Power Down
8742 # PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1
8744 # Reserved. Return zeroes on reads.
8745 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0
8748 # PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1
8750 # Unused DQ I/O Mode
8751 # PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0
8753 # Reserved. Return zeroes on reads.
8754 # PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0
8757 # PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3
8760 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0
8763 # PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0
8765 # DATX8 0-1 DQS Control Register
8766 #(OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) */
8767 mask_write 0XFD0814DC 0xFFFFFFFF 0x01264300
8768 # Register : DX8SL3DXCTL2 @ 0XFD0814EC</p>
8770 # Reserved. Return zeroes on reads.
8771 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0
8773 # Configurable Read Data Enable
8774 # PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0
8776 # OX Extension during Post-amble
8777 # PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0
8779 # OE Extension during Pre-amble
8780 # PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1
8782 # Reserved. Return zeroes on reads.
8783 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0
8785 # I/O Assisted Gate Select
8786 # PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0
8788 # I/O Loopback Select
8789 # PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0
8791 # Reserved. Return zeroes on reads.
8792 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0
8794 # Low Power Wakeup Threshold
8795 # PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc
8797 # Read Data Bus Inversion Enable
8798 # PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0
8800 # Write Data Bus Inversion Enable
8801 # PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0
8803 # PUB Read FIFO Bypass
8804 # PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0
8806 # DATX8 Receive FIFO Read Mode
8807 # PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0
8809 # Disables the Read FIFO Reset
8810 # PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0
8812 # Read DQS Gate I/O Loopback
8813 # PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0
8815 # Reserved. Return zeroes on reads.
8816 # PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0
8818 # DATX8 0-1 DX Control Register 2
8819 #(OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) */
8820 mask_write 0XFD0814EC 0xFFFFFFFF 0x00041800
8821 # Register : DX8SL3IOCR @ 0XFD0814F0</p>
8823 # Reserved. Return zeroes on reads.
8824 # PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0
8826 # PVREF_DAC REFSEL range select
8827 # PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7
8829 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
8830 # PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0
8833 # PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2
8835 # DX IO Transmitter Mode
8836 # PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0
8838 # DX IO Receiver Mode
8839 # PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0
8841 # DATX8 0-1 I/O Configuration Register
8842 #(OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) */
8843 mask_write 0XFD0814F0 0xFFFFFFFF 0x70800000
8844 # Register : DX8SL4OSC @ 0XFD081500</p>
8846 # Reserved. Return zeroes on reads.
8847 # PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0
8849 # Enable Clock Gating for DX ddr_clk
8850 # PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2
8852 # Enable Clock Gating for DX ctl_rd_clk
8853 # PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2
8855 # Enable Clock Gating for DX ctl_clk
8856 # PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2
8858 # Selects the level to which clocks will be stalled when clock gating is e
8860 # PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0
8863 # PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0
8865 # Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
8866 # PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0
8868 # Loopback DQS Gating
8869 # PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0
8871 # Loopback DQS Shift
8872 # PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0
8874 # PHY High-Speed Reset
8875 # PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1
8878 # PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1
8880 # Delay Line Test Start
8881 # PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0
8883 # Delay Line Test Mode
8884 # PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0
8886 # Reserved. Caution, do not write to this register field.
8887 # PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3
8889 # Oscillator Mode Write-Data Delay Line Select
8890 # PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3
8892 # Reserved. Caution, do not write to this register field.
8893 # PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3
8895 # Oscillator Mode Write-Leveling Delay Line Select
8896 # PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3
8898 # Oscillator Mode Division
8899 # PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf
8902 # PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0
8904 # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo
8905 # opback, and Gated Clock Control Register
8906 #(OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) */
8907 mask_write 0XFD081500 0xFFFFFFFF 0x2A019FFE
8908 # Register : DX8SL4PLLCR0 @ 0XFD081504</p>
8911 # PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0
8914 # PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0
8917 # PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0
8919 # Reference Stop Mode
8920 # PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0
8922 # PLL Frequency Select
8923 # PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1
8926 # PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0
8928 # Charge Pump Proportional Current Control
8929 # PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8
8931 # Charge Pump Integrating Current Control
8932 # PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0
8935 # PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0
8937 # Reserved. Return zeroes on reads.
8938 # PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0
8940 # Analog Test Enable (ATOEN)
8941 # PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0
8943 # Analog Test Control
8944 # PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0
8946 # Digital Test Control
8947 # PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0
8949 # DAXT8 0-1 PLL Control Register 0
8950 #(OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) */
8951 mask_write 0XFD081504 0xFFFFFFFF 0x01100000
8952 # Register : DX8SL4DQSCTL @ 0XFD08151C</p>
8954 # Reserved. Return zeroes on reads.
8955 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0
8957 # Read Path Rise-to-Rise Mode
8958 # PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1
8960 # Reserved. Return zeroes on reads.
8961 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0
8963 # Write Path Rise-to-Rise Mode
8964 # PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1
8966 # DQS Gate Extension
8967 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0
8969 # Low Power PLL Power Down
8970 # PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1
8972 # Low Power I/O Power Down
8973 # PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1
8975 # Reserved. Return zeroes on reads.
8976 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0
8979 # PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1
8981 # Unused DQ I/O Mode
8982 # PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0
8984 # Reserved. Return zeroes on reads.
8985 # PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0
8988 # PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3
8991 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0
8994 # PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0
8996 # DATX8 0-1 DQS Control Register
8997 #(OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) */
8998 mask_write 0XFD08151C 0xFFFFFFFF 0x01264300
8999 # Register : DX8SL4DXCTL2 @ 0XFD08152C</p>
9001 # Reserved. Return zeroes on reads.
9002 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0
9004 # Configurable Read Data Enable
9005 # PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0
9007 # OX Extension during Post-amble
9008 # PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0
9010 # OE Extension during Pre-amble
9011 # PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1
9013 # Reserved. Return zeroes on reads.
9014 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0
9016 # I/O Assisted Gate Select
9017 # PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0
9019 # I/O Loopback Select
9020 # PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0
9022 # Reserved. Return zeroes on reads.
9023 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0
9025 # Low Power Wakeup Threshold
9026 # PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc
9028 # Read Data Bus Inversion Enable
9029 # PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0
9031 # Write Data Bus Inversion Enable
9032 # PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0
9034 # PUB Read FIFO Bypass
9035 # PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0
9037 # DATX8 Receive FIFO Read Mode
9038 # PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0
9040 # Disables the Read FIFO Reset
9041 # PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0
9043 # Read DQS Gate I/O Loopback
9044 # PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0
9046 # Reserved. Return zeroes on reads.
9047 # PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0
9049 # DATX8 0-1 DX Control Register 2
9050 #(OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) */
9051 mask_write 0XFD08152C 0xFFFFFFFF 0x00041800
9052 # Register : DX8SL4IOCR @ 0XFD081530</p>
9054 # Reserved. Return zeroes on reads.
9055 # PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0
9057 # PVREF_DAC REFSEL range select
9058 # PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7
9060 # IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
9061 # PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0
9064 # PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2
9066 # DX IO Transmitter Mode
9067 # PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0
9069 # DX IO Receiver Mode
9070 # PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0
9072 # DATX8 0-1 I/O Configuration Register
9073 #(OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) */
9074 mask_write 0XFD081530 0xFFFFFFFF 0x70800000
9075 # Register : DX8SLbPLLCR0 @ 0XFD0817C4</p>
9078 # PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0
9081 # PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0
9084 # PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0
9086 # Reference Stop Mode
9087 # PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0
9089 # PLL Frequency Select
9090 # PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1
9093 # PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0
9095 # Charge Pump Proportional Current Control
9096 # PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8
9098 # Charge Pump Integrating Current Control
9099 # PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0
9102 # PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0
9104 # Reserved. Return zeroes on reads.
9105 # PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0
9107 # Analog Test Enable (ATOEN)
9108 # PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0
9110 # Analog Test Control
9111 # PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0
9113 # Digital Test Control
9114 # PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0
9116 # DAXT8 0-8 PLL Control Register 0
9117 #(OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) */
9118 mask_write 0XFD0817C4 0xFFFFFFFF 0x01100000
9119 # Register : DX8SLbDQSCTL @ 0XFD0817DC</p>
9121 # Reserved. Return zeroes on reads.
9122 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0
9124 # Read Path Rise-to-Rise Mode
9125 # PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1
9127 # Reserved. Return zeroes on reads.
9128 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0
9130 # Write Path Rise-to-Rise Mode
9131 # PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1
9133 # DQS Gate Extension
9134 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0
9136 # Low Power PLL Power Down
9137 # PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1
9139 # Low Power I/O Power Down
9140 # PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1
9142 # Reserved. Return zeroes on reads.
9143 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0
9146 # PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1
9148 # Unused DQ I/O Mode
9149 # PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0
9151 # Reserved. Return zeroes on reads.
9152 # PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0
9155 # PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3
9158 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc
9161 # PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4
9163 # DATX8 0-8 DQS Control Register
9164 #(OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) */
9165 mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4
9168 set psu_ddr_qos_init_data {
9171 set psu_mio_init_data {
9173 # Register : MIO_PIN_0 @ 0XFF180000</p>
9175 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
9177 # PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1
9179 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9180 # PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0
9182 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9183 # , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
9184 # ]- (Test Scan Port) 3= Not Used
9185 # PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0
9187 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g
9188 # pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy
9189 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
9190 # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
9191 # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
9192 # lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out
9193 # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
9194 # lk- (Trace Port Clock)
9195 # PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0
9197 # Configures MIO Pin 0 peripheral interface mapping. S
9198 #(OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) */
9199 mask_write 0XFF180000 0x000000FE 0x00000002
9200 # Register : MIO_PIN_1 @ 0XFF180004</p>
9202 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
9203 # SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
9204 # PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1
9206 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9207 # PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0
9209 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9210 # , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
9211 # ]- (Test Scan Port) 3= Not Used
9212 # PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0
9214 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g
9215 # pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_
9216 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
9217 # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
9218 # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou
9219 # tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
9220 # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
9222 # PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0
9224 # Configures MIO Pin 1 peripheral interface mapping
9225 #(OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) */
9226 mask_write 0XFF180004 0x000000FE 0x00000002
9227 # Register : MIO_PIN_2 @ 0XFF180008</p>
9229 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
9230 # Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
9231 # PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1
9233 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9234 # PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0
9236 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9237 # , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
9238 # ]- (Test Scan Port) 3= Not Used
9239 # PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0
9241 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g
9242 # pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_
9243 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
9244 # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
9245 # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I
9246 # nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
9247 # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
9248 # PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0
9250 # Configures MIO Pin 2 peripheral interface mapping
9251 #(OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) */
9252 mask_write 0XFF180008 0x000000FE 0x00000002
9253 # Register : MIO_PIN_3 @ 0XFF18000C</p>
9255 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
9256 # Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
9257 # PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1
9259 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9260 # PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0
9262 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9263 # , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
9264 # ]- (Test Scan Port) 3= Not Used
9265 # PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0
9267 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g
9268 # pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy
9269 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
9270 # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
9271 # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
9272 # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out-
9273 # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
9274 # output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
9275 # PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0
9277 # Configures MIO Pin 3 peripheral interface mapping
9278 #(OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) */
9279 mask_write 0XFF18000C 0x000000FE 0x00000002
9280 # Register : MIO_PIN_4 @ 0XFF180010</p>
9282 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
9283 # QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
9284 # PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1
9286 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9287 # PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0
9289 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9290 # , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
9291 # ]- (Test Scan Port) 3= Not Used
9292 # PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0
9294 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g
9295 # pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy
9296 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
9297 # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
9298 # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
9299 # 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc
9300 # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
9301 # utput, tracedq[2]- (Trace Port Databus)
9302 # PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0
9304 # Configures MIO Pin 4 peripheral interface mapping
9305 #(OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) */
9306 mask_write 0XFF180010 0x000000FE 0x00000002
9307 # Register : MIO_PIN_5 @ 0XFF180014</p>
9309 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
9310 # (QSPI Slave Select)
9311 # PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1
9313 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9314 # PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0
9316 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9317 # , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
9318 # ]- (Test Scan Port) 3= Not Used
9319 # PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0
9321 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g
9322 # pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_
9323 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
9324 # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
9325 # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
9326 # spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC
9327 # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
9328 # trace, Output, tracedq[3]- (Trace Port Databus)
9329 # PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0
9331 # Configures MIO Pin 5 peripheral interface mapping
9332 #(OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) */
9333 mask_write 0XFF180014 0x000000FE 0x00000002
9334 # Register : MIO_PIN_6 @ 0XFF180018</p>
9336 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l
9337 # pbk- (QSPI Clock to be fed-back)
9338 # PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1
9340 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9341 # PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0
9343 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9344 # , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6
9345 # ]- (Test Scan Port) 3= Not Used
9346 # PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0
9348 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g
9349 # pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_
9350 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
9351 # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
9352 # ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s
9353 # pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT
9354 # C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
9355 # Output, tracedq[4]- (Trace Port Databus)
9356 # PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0
9358 # Configures MIO Pin 6 peripheral interface mapping
9359 #(OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) */
9360 mask_write 0XFF180018 0x000000FE 0x00000002
9361 # Register : MIO_PIN_7 @ 0XFF18001C</p>
9363 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_
9364 # upper- (QSPI Slave Select upper)
9365 # PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1
9367 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9368 # PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0
9370 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9371 # , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7
9372 # ]- (Test Scan Port) 3= Not Used
9373 # PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0
9375 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g
9376 # pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy
9377 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
9378 # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
9379 # Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma
9380 # ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua
9381 # 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t
9382 # racedq[5]- (Trace Port Databus)
9383 # PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0
9385 # Configures MIO Pin 7 peripheral interface mapping
9386 #(OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) */
9387 mask_write 0XFF18001C 0x000000FE 0x00000002
9388 # Register : MIO_PIN_8 @ 0XFF180020</p>
9390 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0
9391 # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D
9393 # PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1
9395 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
9396 # PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0
9398 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9399 # , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8
9400 # ]- (Test Scan Port) 3= Not Used
9401 # PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0
9403 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g
9404 # pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy
9405 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
9406 # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
9407 # tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste
9408 # r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_
9409 # txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra
9411 # PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0
9413 # Configures MIO Pin 8 peripheral interface mapping
9414 #(OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) */
9415 mask_write 0XFF180020 0x000000FE 0x00000002
9416 # Register : MIO_PIN_9 @ 0XFF180024</p>
9418 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1
9419 # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D
9421 # PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1
9423 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
9425 # PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0
9427 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9428 # , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9
9429 # ]- (Test Scan Port) 3= Not Used
9430 # PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0
9432 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g
9433 # pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_
9434 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
9435 # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
9436 # atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S
9437 # elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3,
9438 # Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA
9439 # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data
9441 # PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0
9443 # Configures MIO Pin 9 peripheral interface mapping
9444 #(OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) */
9445 mask_write 0XFF180024 0x000000FE 0x00000002
9446 # Register : MIO_PIN_10 @ 0XFF180028</p>
9448 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2
9449 # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D
9451 # PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1
9453 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
9455 # PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0
9457 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9458 # , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[
9459 # 10]- (Test Scan Port) 3= Not Used
9460 # PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0
9462 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0=
9463 # gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph
9464 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
9465 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
9466 # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
9467 # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
9468 # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
9469 # t, tracedq[8]- (Trace Port Databus)
9470 # PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0
9472 # Configures MIO Pin 10 peripheral interface mapping
9473 #(OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) */
9474 mask_write 0XFF180028 0x000000FE 0x00000002
9475 # Register : MIO_PIN_11 @ 0XFF18002C</p>
9477 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3
9478 # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D
9480 # PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1
9482 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
9484 # PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0
9486 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9487 # , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[
9488 # 11]- (Test Scan Port) 3= Not Used
9489 # PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0
9491 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0=
9492 # gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p
9493 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
9494 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
9495 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
9496 # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
9497 # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
9498 # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
9499 # PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0
9501 # Configures MIO Pin 11 peripheral interface mapping
9502 #(OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) */
9503 mask_write 0XFF18002C 0x000000FE 0x00000002
9504 # Register : MIO_PIN_12 @ 0XFF180030</p>
9506 # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_
9507 # upper- (QSPI Upper Clock)
9508 # PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1
9510 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
9511 # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
9512 # PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0
9514 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
9515 # , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[
9516 # 12]- (Test Scan Port) 3= Not Used
9517 # PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0
9519 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0=
9520 # gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p
9521 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
9522 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT
9523 # AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_
9524 # sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O
9525 # utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace
9526 # dq[10]- (Trace Port Databus)
9527 # PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0
9529 # Configures MIO Pin 12 peripheral interface mapping
9530 #(OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) */
9531 mask_write 0XFF180030 0x000000FE 0x00000002
9532 # Register : MIO_PIN_13 @ 0XFF180034</p>
9534 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9535 # PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0
9537 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA
9539 # PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0
9541 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
9542 # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t
9543 # est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output,
9544 # test_scan_out[13]- (Test Scan Port) 3= Not Used
9545 # PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0
9547 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0=
9548 # gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph
9549 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
9550 # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA
9551 # G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1,
9552 # Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR
9553 # T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data
9555 # PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0
9557 # Configures MIO Pin 13 peripheral interface mapping
9558 #(OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) */
9559 mask_write 0XFF180034 0x000000FE 0x00000000
9560 # Register : MIO_PIN_14 @ 0XFF180038</p>
9562 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9563 # PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0
9565 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND
9566 # Command Latch Enable)
9567 # PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0
9569 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
9570 # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t
9571 # est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output,
9572 # test_scan_out[14]- (Test Scan Port) 3= Not Used
9573 # PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0
9575 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0=
9576 # gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph
9577 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
9578 # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT
9579 # AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0,
9580 # Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver
9581 # serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
9582 # PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2
9584 # Configures MIO Pin 14 peripheral interface mapping
9585 #(OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) */
9586 mask_write 0XFF180038 0x000000FE 0x00000040
9587 # Register : MIO_PIN_15 @ 0XFF18003C</p>
9589 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9590 # PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0
9592 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND
9593 # Address Latch Enable)
9594 # PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0
9596 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
9597 # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t
9598 # est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output,
9599 # test_scan_out[15]- (Test Scan Port) 3= Not Used
9600 # PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0
9602 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0=
9603 # gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p
9604 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
9605 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT
9606 # AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp
9607 # ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou
9608 # t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria
9609 # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
9610 # PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2
9612 # Configures MIO Pin 15 peripheral interface mapping
9613 #(OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) */
9614 mask_write 0XFF18003C 0x000000FE 0x00000040
9615 # Register : MIO_PIN_16 @ 0XFF180040</p>
9617 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9618 # PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0
9620 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
9621 # NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
9622 # PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0
9624 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
9625 # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t
9626 # est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
9627 # test_scan_out[16]- (Test Scan Port) 3= Not Used
9628 # PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0
9630 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0=
9631 # gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p
9632 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
9633 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
9634 # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
9635 # pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
9636 # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
9637 # Output, tracedq[14]- (Trace Port Databus)
9638 # PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2
9640 # Configures MIO Pin 16 peripheral interface mapping
9641 #(OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) */
9642 mask_write 0XFF180040 0x000000FE 0x00000040
9643 # Register : MIO_PIN_17 @ 0XFF180044</p>
9645 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9646 # PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0
9648 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
9649 # NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
9650 # PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0
9652 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
9653 # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t
9654 # est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
9655 # test_scan_out[17]- (Test Scan Port) 3= Not Used
9656 # PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0
9658 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0=
9659 # gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph
9660 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
9661 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
9662 # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
9663 # = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
9664 # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
9665 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
9666 # PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2
9668 # Configures MIO Pin 17 peripheral interface mapping
9669 #(OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) */
9670 mask_write 0XFF180044 0x000000FE 0x00000040
9671 # Register : MIO_PIN_18 @ 0XFF180048</p>
9673 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9674 # PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0
9676 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
9677 # NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
9678 # PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0
9680 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
9681 # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t
9682 # est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output,
9683 # test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
9685 # PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0
9687 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0=
9688 # gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph
9689 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
9690 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
9691 # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
9692 # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
9693 # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
9694 # PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6
9696 # Configures MIO Pin 18 peripheral interface mapping
9697 #(OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) */
9698 mask_write 0XFF180048 0x000000FE 0x000000C0
9699 # Register : MIO_PIN_19 @ 0XFF18004C</p>
9701 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9702 # PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0
9704 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
9705 # NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
9706 # PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0
9708 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
9709 # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t
9710 # est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output,
9711 # test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
9713 # PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0
9715 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0=
9716 # gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p
9717 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
9718 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
9719 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
9720 # Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
9721 # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
9722 # PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6
9724 # Configures MIO Pin 19 peripheral interface mapping
9725 #(OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) */
9726 mask_write 0XFF18004C 0x000000FE 0x000000C0
9727 # Register : MIO_PIN_20 @ 0XFF180050</p>
9729 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9730 # PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0
9732 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
9733 # NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
9734 # PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0
9736 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
9737 # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t
9738 # est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output,
9739 # test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
9741 # PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0
9743 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0=
9744 # gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p
9745 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
9746 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
9747 # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
9748 # ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
9749 # 1_txd- (UART transmitter serial output) 7= Not Used
9750 # PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6
9752 # Configures MIO Pin 20 peripheral interface mapping
9753 #(OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) */
9754 mask_write 0XFF180050 0x000000FE 0x000000C0
9755 # Register : MIO_PIN_21 @ 0XFF180054</p>
9757 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9758 # PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0
9760 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
9761 # NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
9762 # PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0
9764 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
9765 # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes
9766 # t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t
9767 # est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
9769 # PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0
9771 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0=
9772 # gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph
9773 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
9774 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
9775 # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
9776 # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc
9777 # 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
9778 # UART receiver serial input) 7= Not Used
9779 # PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6
9781 # Configures MIO Pin 21 peripheral interface mapping
9782 #(OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) */
9783 mask_write 0XFF180054 0x000000FE 0x000000C0
9784 # Register : MIO_PIN_22 @ 0XFF180058</p>
9786 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9787 # PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0
9789 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN
9791 # PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0
9793 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
9794 # (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) =
9795 # test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c
9796 # su_ext_tamper- (CSU Ext Tamper)
9797 # PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0
9799 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0=
9800 # gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph
9801 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
9802 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
9803 # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
9804 # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
9805 # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
9807 # PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0
9809 # Configures MIO Pin 22 peripheral interface mapping
9810 #(OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) */
9811 mask_write 0XFF180058 0x000000FE 0x00000000
9812 # Register : MIO_PIN_23 @ 0XFF18005C</p>
9814 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9815 # PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0
9817 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (
9818 # NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
9819 # PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0
9821 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
9822 # (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po
9823 # rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp
9824 # ut, csu_ext_tamper- (CSU Ext Tamper)
9825 # PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0
9827 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0=
9828 # gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p
9829 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
9830 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
9831 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
9832 # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
9833 # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
9835 # PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0
9837 # Configures MIO Pin 23 peripheral interface mapping
9838 #(OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) */
9839 mask_write 0XFF18005C 0x000000FE 0x00000000
9840 # Register : MIO_PIN_24 @ 0XFF180060</p>
9842 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9843 # PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0
9845 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
9846 # NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
9847 # PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0
9849 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
9850 # card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test
9851 # Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
9852 # csu, Input, csu_ext_tamper- (CSU Ext Tamper)
9853 # PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0
9855 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0=
9856 # gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p
9857 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
9858 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
9859 # Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T
9860 # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
9862 # PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1
9864 # Configures MIO Pin 24 peripheral interface mapping
9865 #(OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) */
9866 mask_write 0XFF180060 0x000000FE 0x00000020
9867 # Register : MIO_PIN_25 @ 0XFF180064</p>
9869 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
9870 # PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0
9872 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
9874 # PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0
9876 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
9877 # rd write protect from connector) 2= test_scan, Input, test_scan_in[25]-
9878 # (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
9879 # ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
9880 # PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0
9882 # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0=
9883 # gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph
9884 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
9885 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
9886 # (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou
9887 # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
9889 # PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1
9891 # Configures MIO Pin 25 peripheral interface mapping
9892 #(OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) */
9893 mask_write 0XFF180064 0x000000FE 0x00000020
9894 # Register : MIO_PIN_26 @ 0XFF180068</p>
9896 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
9897 # clk- (TX RGMII clock)
9898 # PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0
9900 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
9902 # PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0
9904 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU
9905 # GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca
9906 # n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta
9907 # mper- (CSU Ext Tamper)
9908 # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0
9910 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g
9911 # pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_
9912 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
9913 # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
9914 # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl
9915 # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
9916 # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
9917 # Trace Port Databus)
9918 # PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0
9920 # Configures MIO Pin 26 peripheral interface mapping
9921 #(OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) */
9922 mask_write 0XFF180068 0x000000FE 0x00000000
9923 # Register : MIO_PIN_27 @ 0XFF18006C</p>
9925 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
9926 # [0]- (TX RGMII data)
9927 # PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0
9929 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
9931 # PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0
9933 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU
9934 # GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca
9935 # n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
9936 # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
9937 # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3
9939 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g
9940 # pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy
9941 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
9942 # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
9943 # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
9944 # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
9945 # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
9947 # PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0
9949 # Configures MIO Pin 27 peripheral interface mapping
9950 #(OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) */
9951 mask_write 0XFF18006C 0x000000FE 0x00000018
9952 # Register : MIO_PIN_28 @ 0XFF180070</p>
9954 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
9955 # [1]- (TX RGMII data)
9956 # PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0
9958 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
9960 # PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0
9962 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU
9963 # GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca
9964 # n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
9965 # lug_detect- (Dp Aux Hot Plug)
9966 # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3
9968 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g
9969 # pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy
9970 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
9971 # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
9972 # G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
9973 # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
9974 # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
9975 # PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0
9977 # Configures MIO Pin 28 peripheral interface mapping
9978 #(OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) */
9979 mask_write 0XFF180070 0x000000FE 0x00000018
9980 # Register : MIO_PIN_29 @ 0XFF180074</p>
9982 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
9983 # [2]- (TX RGMII data)
9984 # PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0
9986 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
9987 # PCIE Reset signal)
9988 # PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0
9990 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU
9991 # GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca
9992 # n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
9993 # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
9994 # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3
9996 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g
9997 # pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_
9998 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
9999 # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
10000 # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output,
10001 # spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
10002 # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
10003 # ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
10004 # PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0
10006 # Configures MIO Pin 29 peripheral interface mapping
10007 #(OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) */
10008 mask_write 0XFF180074 0x000000FE 0x00000018
10009 # Register : MIO_PIN_30 @ 0XFF180078</p>
10011 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
10012 # [3]- (TX RGMII data)
10013 # PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0
10015 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10016 # PCIE Reset signal)
10017 # PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0
10019 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU
10020 # GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca
10021 # n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
10022 # lug_detect- (Dp Aux Hot Plug)
10023 # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3
10025 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g
10026 # pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_
10027 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10028 # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
10029 # ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0
10030 # , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock
10031 # ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
10032 # tracedq[8]- (Trace Port Databus)
10033 # PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0
10035 # Configures MIO Pin 30 peripheral interface mapping
10036 #(OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) */
10037 mask_write 0XFF180078 0x000000FE 0x00000018
10038 # Register : MIO_PIN_31 @ 0XFF18007C</p>
10040 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
10041 # ctl- (TX RGMII control)
10042 # PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0
10044 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10045 # PCIE Reset signal)
10046 # PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0
10048 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU
10049 # GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca
10050 # n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta
10051 # mper- (CSU Ext Tamper)
10052 # PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0
10054 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g
10055 # pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy
10056 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10057 # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
10058 # Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
10059 # spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT
10060 # C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp
10061 # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
10062 # PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0
10064 # Configures MIO Pin 31 peripheral interface mapping
10065 #(OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) */
10066 mask_write 0XFF18007C 0x000000FE 0x00000000
10067 # Register : MIO_PIN_32 @ 0XFF180080</p>
10069 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
10070 # lk- (RX RGMII clock)
10071 # PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0
10073 # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
10074 # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
10075 # PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0
10077 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM
10078 # U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc
10079 # an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t
10080 # amper- (CSU Ext Tamper)
10081 # PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1
10083 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g
10084 # pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy
10085 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10086 # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10087 # tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
10088 # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T
10089 # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t
10090 # race, Output, tracedq[10]- (Trace Port Databus)
10091 # PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0
10093 # Configures MIO Pin 32 peripheral interface mapping
10094 #(OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) */
10095 mask_write 0XFF180080 0x000000FE 0x00000008
10096 # Register : MIO_PIN_33 @ 0XFF180084</p>
10098 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
10099 # 0]- (RX RGMII data)
10100 # PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0
10102 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10103 # PCIE Reset signal)
10104 # PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0
10106 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM
10107 # U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc
10108 # an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t
10109 # amper- (CSU Ext Tamper)
10110 # PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1
10112 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g
10113 # pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_
10114 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10115 # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
10116 # atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas
10117 # ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1
10118 # , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq
10119 # [11]- (Trace Port Databus)
10120 # PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0
10122 # Configures MIO Pin 33 peripheral interface mapping
10123 #(OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) */
10124 mask_write 0XFF180084 0x000000FE 0x00000008
10125 # Register : MIO_PIN_34 @ 0XFF180088</p>
10127 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
10128 # 1]- (RX RGMII data)
10129 # PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0
10131 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10132 # PCIE Reset signal)
10133 # PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0
10135 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM
10136 # U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc
10137 # an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_
10138 # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
10139 # PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1
10141 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g
10142 # pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_
10143 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10144 # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
10145 # ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master
10146 # Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx
10147 # d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po
10149 # PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0
10151 # Configures MIO Pin 34 peripheral interface mapping
10152 #(OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) */
10153 mask_write 0XFF180088 0x000000FE 0x00000008
10154 # Register : MIO_PIN_35 @ 0XFF18008C</p>
10156 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
10157 # 2]- (RX RGMII data)
10158 # PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0
10160 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10161 # PCIE Reset signal)
10162 # PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0
10164 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM
10165 # U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc
10166 # an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_
10167 # plug_detect- (Dp Aux Hot Plug)
10168 # PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1
10170 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g
10171 # pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy
10172 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10173 # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
10174 # Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
10175 # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2
10176 # , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (
10177 # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po
10179 # PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0
10181 # Configures MIO Pin 35 peripheral interface mapping
10182 #(OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) */
10183 mask_write 0XFF18008C 0x000000FE 0x00000008
10184 # Register : MIO_PIN_36 @ 0XFF180090</p>
10186 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
10187 # 3]- (RX RGMII data)
10188 # PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0
10190 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10191 # PCIE Reset signal)
10192 # PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0
10194 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM
10195 # U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc
10196 # an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_
10197 # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
10198 # PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1
10200 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0=
10201 # gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p
10202 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
10203 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
10204 # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
10205 # pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
10206 # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
10207 # Output, tracedq[14]- (Trace Port Databus)
10208 # PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0
10210 # Configures MIO Pin 36 peripheral interface mapping
10211 #(OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) */
10212 mask_write 0XFF180090 0x000000FE 0x00000008
10213 # Register : MIO_PIN_37 @ 0XFF180094</p>
10215 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
10216 # tl- (RX RGMII control )
10217 # PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0
10219 # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
10220 # PCIE Reset signal)
10221 # PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0
10223 # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM
10224 # U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc
10225 # an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_
10226 # plug_detect- (Dp Aux Hot Plug)
10227 # PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1
10229 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0=
10230 # gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph
10231 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
10232 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
10233 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
10234 # = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
10235 # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
10236 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
10237 # PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0
10239 # Configures MIO Pin 37 peripheral interface mapping
10240 #(OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) */
10241 mask_write 0XFF180094 0x000000FE 0x00000008
10242 # Register : MIO_PIN_38 @ 0XFF180098</p>
10244 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
10245 # clk- (TX RGMII clock)
10246 # PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0
10248 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10249 # PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0
10251 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
10252 # (SDSDIO clock) 2= Not Used 3= Not Used
10253 # PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0
10255 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0=
10256 # gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph
10257 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
10258 # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA
10259 # G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s
10260 # clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In
10261 # put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
10262 # (Trace Port Clock)
10263 # PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0
10265 # Configures MIO Pin 38 peripheral interface mapping
10266 #(OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) */
10267 mask_write 0XFF180098 0x000000FE 0x00000000
10268 # Register : MIO_PIN_39 @ 0XFF18009C</p>
10270 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
10271 # [0]- (TX RGMII data)
10272 # PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0
10274 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10275 # PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0
10277 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
10278 # card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b
10279 # us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
10280 # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2
10282 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0=
10283 # gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p
10284 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
10285 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT
10286 # AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0,
10287 # Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U
10288 # ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
10290 # PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0
10292 # Configures MIO Pin 39 peripheral interface mapping
10293 #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) */
10294 mask_write 0XFF18009C 0x000000FE 0x00000010
10295 # Register : MIO_PIN_40 @ 0XFF1800A0</p>
10297 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
10298 # [1]- (TX RGMII data)
10299 # PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0
10301 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10302 # PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0
10304 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
10305 # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1
10306 # , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[
10307 # 5]- (8-bit Data bus) 3= Not Used
10308 # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2
10310 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0=
10311 # gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p
10312 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
10313 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ
10314 # TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3
10315 # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi
10316 # tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
10317 # PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0
10319 # Configures MIO Pin 40 peripheral interface mapping
10320 #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) */
10321 mask_write 0XFF1800A0 0x000000FE 0x00000010
10322 # Register : MIO_PIN_41 @ 0XFF1800A4</p>
10324 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
10325 # [2]- (TX RGMII data)
10326 # PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0
10328 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10329 # PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0
10331 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
10332 # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s
10333 # d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
10334 # t[6]- (8-bit Data bus) 3= Not Used
10335 # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2
10337 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0=
10338 # gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph
10339 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
10340 # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA
10341 # G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu
10342 # t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out
10343 # - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp
10344 # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
10345 # PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0
10347 # Configures MIO Pin 41 peripheral interface mapping
10348 #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) */
10349 mask_write 0XFF1800A4 0x000000FE 0x00000010
10350 # Register : MIO_PIN_42 @ 0XFF1800A8</p>
10352 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
10353 # [3]- (TX RGMII data)
10354 # PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0
10356 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10357 # PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0
10359 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
10360 # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s
10361 # d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
10362 # t[7]- (8-bit Data bus) 3= Not Used
10363 # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2
10365 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0=
10366 # gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph
10367 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
10368 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
10369 # atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp
10370 # i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
10371 # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
10372 # t, tracedq[2]- (Trace Port Databus)
10373 # PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0
10375 # Configures MIO Pin 42 peripheral interface mapping
10376 #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) */
10377 mask_write 0XFF1800A8 0x000000FE 0x00000010
10378 # Register : MIO_PIN_43 @ 0XFF1800AC</p>
10380 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
10381 # ctl- (TX RGMII control)
10382 # PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0
10384 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10385 # PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0
10387 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
10388 # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
10389 # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
10390 # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0
10392 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0=
10393 # gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p
10394 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
10395 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
10396 # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal)
10397 # 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
10398 # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
10399 # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
10400 # PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0
10402 # Configures MIO Pin 43 peripheral interface mapping
10403 #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) */
10404 mask_write 0XFF1800AC 0x000000FE 0x00000000
10405 # Register : MIO_PIN_44 @ 0XFF1800B0</p>
10407 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
10408 # lk- (RX RGMII clock)
10409 # PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0
10411 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10412 # PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0
10414 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
10415 # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
10416 # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
10417 # PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2
10419 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0=
10420 # gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p
10421 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
10422 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
10423 # Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4
10424 # = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in-
10425 # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
10427 # PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0
10429 # Configures MIO Pin 44 peripheral interface mapping
10430 #(OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) */
10431 mask_write 0XFF1800B0 0x000000FE 0x00000010
10432 # Register : MIO_PIN_45 @ 0XFF1800B4</p>
10434 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
10435 # 0]- (RX RGMII data)
10436 # PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0
10438 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10439 # PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0
10441 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
10442 # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
10443 # d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
10444 # PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2
10446 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0=
10447 # gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph
10448 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
10449 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
10450 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M
10451 # aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
10452 # a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
10453 # PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0
10455 # Configures MIO Pin 45 peripheral interface mapping
10456 #(OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) */
10457 mask_write 0XFF1800B4 0x000000FE 0x00000010
10458 # Register : MIO_PIN_46 @ 0XFF1800B8</p>
10460 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
10461 # 1]- (RX RGMII data)
10462 # PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0
10464 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10465 # PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0
10467 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
10468 # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
10469 # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
10470 # t[0]- (8-bit Data bus) 3= Not Used
10471 # PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2
10473 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0=
10474 # gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph
10475 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
10476 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
10477 # atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast
10478 # er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
10479 # rxd- (UART receiver serial input) 7= Not Used
10480 # PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0
10482 # Configures MIO Pin 46 peripheral interface mapping
10483 #(OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) */
10484 mask_write 0XFF1800B8 0x000000FE 0x00000010
10485 # Register : MIO_PIN_47 @ 0XFF1800BC</p>
10487 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
10488 # 2]- (RX RGMII data)
10489 # PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0
10491 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10492 # PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0
10494 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
10495 # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
10496 # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
10497 # t[1]- (8-bit Data bus) 3= Not Used
10498 # PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2
10500 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0=
10501 # gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p
10502 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
10503 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
10504 # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste
10505 # r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt
10506 # c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
10507 # (UART transmitter serial output) 7= Not Used
10508 # PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0
10510 # Configures MIO Pin 47 peripheral interface mapping
10511 #(OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) */
10512 mask_write 0XFF1800BC 0x000000FE 0x00000010
10513 # Register : MIO_PIN_48 @ 0XFF1800C0</p>
10515 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
10516 # 3]- (RX RGMII data)
10517 # PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0
10519 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10520 # PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0
10522 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
10523 # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
10524 # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
10525 # t[2]- (8-bit Data bus) 3= Not Used
10526 # PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2
10528 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0=
10529 # gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p
10530 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
10531 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
10532 # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
10533 # pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
10534 # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
10536 # PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0
10538 # Configures MIO Pin 48 peripheral interface mapping
10539 #(OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) */
10540 mask_write 0XFF1800C0 0x000000FE 0x00000010
10541 # Register : MIO_PIN_49 @ 0XFF1800C4</p>
10543 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
10544 # tl- (RX RGMII control )
10545 # PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0
10547 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10548 # PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0
10550 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
10551 # (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
10552 # 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
10553 # PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2
10555 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0=
10556 # gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph
10557 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
10558 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
10559 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
10560 # = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
10561 # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
10563 # PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0
10565 # Configures MIO Pin 49 peripheral interface mapping
10566 #(OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) */
10567 mask_write 0XFF1800C4 0x000000FE 0x00000010
10568 # Register : MIO_PIN_50 @ 0XFF1800C8</p>
10570 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
10572 # PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0
10574 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10575 # PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0
10577 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
10578 # rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
10579 # icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
10580 # PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2
10582 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0=
10583 # gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph
10584 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
10585 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
10586 # atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5=
10587 # ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
10588 # iver serial input) 7= Not Used
10589 # PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0
10591 # Configures MIO Pin 50 peripheral interface mapping
10592 #(OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) */
10593 mask_write 0XFF1800C8 0x000000FE 0x00000010
10594 # Register : MIO_PIN_51 @ 0XFF1800CC</p>
10596 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
10598 # PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0
10600 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
10601 # PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0
10603 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
10604 # o1_clk_out- (SDSDIO clock) 3= Not Used
10605 # PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2
10607 # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0=
10608 # gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p
10609 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
10610 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
10611 # (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat
10612 # a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa
10613 # ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
10614 # serial output) 7= Not Used
10615 # PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0
10617 # Configures MIO Pin 51 peripheral interface mapping
10618 #(OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) */
10619 mask_write 0XFF1800CC 0x000000FE 0x00000010
10620 # Register : MIO_PIN_52 @ 0XFF1800D0</p>
10622 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
10623 # clk- (TX RGMII clock)
10624 # PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0
10626 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
10628 # PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1
10630 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10632 # PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0
10634 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
10635 # pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
10636 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10637 # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
10638 # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
10639 # lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
10640 # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
10641 # lk- (Trace Port Clock)
10642 # PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0
10644 # Configures MIO Pin 52 peripheral interface mapping
10645 #(OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) */
10646 mask_write 0XFF1800D0 0x000000FE 0x00000004
10647 # Register : MIO_PIN_53 @ 0XFF1800D4</p>
10649 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
10650 # [0]- (TX RGMII data)
10651 # PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0
10653 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
10654 # (Data bus direction control)
10655 # PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1
10657 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10659 # PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0
10661 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
10662 # pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
10663 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10664 # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
10665 # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
10666 # tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
10667 # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
10669 # PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0
10671 # Configures MIO Pin 53 peripheral interface mapping
10672 #(OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) */
10673 mask_write 0XFF1800D4 0x000000FE 0x00000004
10674 # Register : MIO_PIN_54 @ 0XFF1800D8</p>
10676 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
10677 # [1]- (TX RGMII data)
10678 # PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0
10680 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10681 # ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
10683 # PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1
10685 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10687 # PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0
10689 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
10690 # pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
10691 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10692 # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
10693 # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
10694 # nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
10695 # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
10696 # PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0
10698 # Configures MIO Pin 54 peripheral interface mapping
10699 #(OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) */
10700 mask_write 0XFF1800D8 0x000000FE 0x00000004
10701 # Register : MIO_PIN_55 @ 0XFF1800DC</p>
10703 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
10704 # [2]- (TX RGMII data)
10705 # PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0
10707 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
10708 # (Data flow control signal from the PHY)
10709 # PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1
10711 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10713 # PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0
10715 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
10716 # pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
10717 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10718 # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
10719 # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
10720 # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
10721 # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
10722 # output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
10723 # PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0
10725 # Configures MIO Pin 55 peripheral interface mapping
10726 #(OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) */
10727 mask_write 0XFF1800DC 0x000000FE 0x00000004
10728 # Register : MIO_PIN_56 @ 0XFF1800E0</p>
10730 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
10731 # [3]- (TX RGMII data)
10732 # PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0
10734 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10735 # ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
10737 # PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1
10739 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10741 # PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0
10743 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
10744 # pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
10745 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10746 # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
10747 # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
10748 # 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
10749 # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
10750 # utput, tracedq[2]- (Trace Port Databus)
10751 # PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0
10753 # Configures MIO Pin 56 peripheral interface mapping
10754 #(OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) */
10755 mask_write 0XFF1800E0 0x000000FE 0x00000004
10756 # Register : MIO_PIN_57 @ 0XFF1800E4</p>
10758 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
10759 # ctl- (TX RGMII control)
10760 # PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0
10762 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10763 # ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
10765 # PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1
10767 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10769 # PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0
10771 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
10772 # pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
10773 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10774 # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
10775 # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
10776 # spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
10777 # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
10778 # trace, Output, tracedq[3]- (Trace Port Databus)
10779 # PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0
10781 # Configures MIO Pin 57 peripheral interface mapping
10782 #(OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) */
10783 mask_write 0XFF1800E4 0x000000FE 0x00000004
10784 # Register : MIO_PIN_58 @ 0XFF1800E8</p>
10786 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
10787 # lk- (RX RGMII clock)
10788 # PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0
10790 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
10791 # (Asserted to end or interrupt transfers)
10792 # PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1
10794 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10796 # PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0
10798 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
10799 # pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
10800 # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
10801 # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
10802 # TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
10803 # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
10804 # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
10805 # Trace Port Databus)
10806 # PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0
10808 # Configures MIO Pin 58 peripheral interface mapping
10809 #(OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) */
10810 mask_write 0XFF1800E8 0x000000FE 0x00000004
10811 # Register : MIO_PIN_59 @ 0XFF1800EC</p>
10813 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
10814 # 0]- (RX RGMII data)
10815 # PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0
10817 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10818 # ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
10820 # PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1
10822 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10824 # PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0
10826 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
10827 # pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
10828 # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
10829 # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
10830 # TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
10831 # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
10832 # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
10834 # PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0
10836 # Configures MIO Pin 59 peripheral interface mapping
10837 #(OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) */
10838 mask_write 0XFF1800EC 0x000000FE 0x00000004
10839 # Register : MIO_PIN_60 @ 0XFF1800F0</p>
10841 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
10842 # 1]- (RX RGMII data)
10843 # PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0
10845 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10846 # ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
10848 # PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1
10850 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10852 # PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0
10854 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
10855 # pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
10856 # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
10857 # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
10858 # G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
10859 # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
10860 # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
10861 # PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0
10863 # Configures MIO Pin 60 peripheral interface mapping
10864 #(OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) */
10865 mask_write 0XFF1800F0 0x000000FE 0x00000004
10866 # Register : MIO_PIN_61 @ 0XFF1800F4</p>
10868 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
10869 # 2]- (RX RGMII data)
10870 # PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0
10872 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10873 # ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
10875 # PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1
10877 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10879 # PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0
10881 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
10882 # pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
10883 # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
10884 # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
10885 # TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
10886 # spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
10887 # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
10888 # ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
10889 # PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0
10891 # Configures MIO Pin 61 peripheral interface mapping
10892 #(OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) */
10893 mask_write 0XFF1800F4 0x000000FE 0x00000004
10894 # Register : MIO_PIN_62 @ 0XFF1800F8</p>
10896 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
10897 # 3]- (RX RGMII data)
10898 # PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0
10900 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10901 # ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
10903 # PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1
10905 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10907 # PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0
10909 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
10910 # gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
10911 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
10912 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
10913 # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
10914 # i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
10915 # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
10916 # t, tracedq[8]- (Trace Port Databus)
10917 # PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0
10919 # Configures MIO Pin 62 peripheral interface mapping
10920 #(OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) */
10921 mask_write 0XFF1800F8 0x000000FE 0x00000004
10922 # Register : MIO_PIN_63 @ 0XFF1800FC</p>
10924 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
10925 # tl- (RX RGMII control )
10926 # PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0
10928 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
10929 # ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
10931 # PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1
10933 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
10935 # PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0
10937 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
10938 # gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
10939 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
10940 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
10941 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
10942 # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
10943 # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
10944 # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
10945 # PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0
10947 # Configures MIO Pin 63 peripheral interface mapping
10948 #(OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) */
10949 mask_write 0XFF1800FC 0x000000FE 0x00000004
10950 # Register : MIO_PIN_64 @ 0XFF180100</p>
10952 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
10953 # clk- (TX RGMII clock)
10954 # PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1
10956 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
10958 # PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0
10960 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
10961 # (SDSDIO clock) 2= Not Used 3= Not Used
10962 # PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0
10964 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0=
10965 # gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p
10966 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
10967 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
10968 # Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4
10969 # = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in-
10970 # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
10971 # trace, Output, tracedq[10]- (Trace Port Databus)
10972 # PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0
10974 # Configures MIO Pin 64 peripheral interface mapping
10975 #(OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) */
10976 mask_write 0XFF180100 0x000000FE 0x00000002
10977 # Register : MIO_PIN_65 @ 0XFF180104</p>
10979 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
10980 # [0]- (TX RGMII data)
10981 # PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1
10983 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
10984 # (Data bus direction control)
10985 # PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0
10987 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
10988 # card detect from connector) 2= Not Used 3= Not Used
10989 # PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0
10991 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0=
10992 # gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph
10993 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
10994 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
10995 # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M
10996 # aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u
10997 # a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
10998 # dq[11]- (Trace Port Databus)
10999 # PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0
11001 # Configures MIO Pin 65 peripheral interface mapping
11002 #(OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) */
11003 mask_write 0XFF180104 0x000000FE 0x00000002
11004 # Register : MIO_PIN_66 @ 0XFF180108</p>
11006 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
11007 # [1]- (TX RGMII data)
11008 # PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1
11010 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11011 # ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
11013 # PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0
11015 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
11016 # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
11018 # PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0
11020 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0=
11021 # gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph
11022 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11023 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11024 # atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast
11025 # er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_
11026 # rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
11028 # PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0
11030 # Configures MIO Pin 66 peripheral interface mapping
11031 #(OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) */
11032 mask_write 0XFF180108 0x000000FE 0x00000002
11033 # Register : MIO_PIN_67 @ 0XFF18010C</p>
11035 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
11036 # [2]- (TX RGMII data)
11037 # PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1
11039 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
11040 # (Data flow control signal from the PHY)
11041 # PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0
11043 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
11044 # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
11045 # ot Used 3= Not Used
11046 # PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0
11048 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0=
11049 # gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p
11050 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11051 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11052 # (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste
11053 # r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt
11054 # c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
11055 # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
11057 # PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0
11059 # Configures MIO Pin 67 peripheral interface mapping
11060 #(OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) */
11061 mask_write 0XFF18010C 0x000000FE 0x00000002
11062 # Register : MIO_PIN_68 @ 0XFF180110</p>
11064 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
11065 # [3]- (TX RGMII data)
11066 # PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1
11068 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11069 # ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
11071 # PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0
11073 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
11074 # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
11075 # ot Used 3= Not Used
11076 # PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0
11078 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0=
11079 # gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p
11080 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11081 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11082 # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
11083 # pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
11084 # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11085 # Output, tracedq[14]- (Trace Port Databus)
11086 # PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0
11088 # Configures MIO Pin 68 peripheral interface mapping
11089 #(OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) */
11090 mask_write 0XFF180110 0x000000FE 0x00000002
11091 # Register : MIO_PIN_69 @ 0XFF180114</p>
11093 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
11094 # ctl- (TX RGMII control)
11095 # PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1
11097 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11098 # ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
11100 # PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0
11102 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
11103 # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
11104 # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
11105 # PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0
11107 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0=
11108 # gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph
11109 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11110 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11111 # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
11112 # = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
11113 # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
11114 # 7= trace, Output, tracedq[15]- (Trace Port Databus)
11115 # PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0
11117 # Configures MIO Pin 69 peripheral interface mapping
11118 #(OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) */
11119 mask_write 0XFF180114 0x000000FE 0x00000002
11120 # Register : MIO_PIN_70 @ 0XFF180118</p>
11122 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
11123 # lk- (RX RGMII clock)
11124 # PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1
11126 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
11127 # (Asserted to end or interrupt transfers)
11128 # PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0
11130 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
11131 # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
11132 # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
11133 # PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0
11135 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0=
11136 # gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph
11137 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11138 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11139 # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
11140 # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
11141 # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
11143 # PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0
11145 # Configures MIO Pin 70 peripheral interface mapping
11146 #(OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) */
11147 mask_write 0XFF180118 0x000000FE 0x00000002
11148 # Register : MIO_PIN_71 @ 0XFF18011C</p>
11150 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
11151 # 0]- (RX RGMII data)
11152 # PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1
11154 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11155 # ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
11157 # PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0
11159 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
11160 # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
11161 # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
11162 # t[0]- (8-bit Data bus) 3= Not Used
11163 # PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0
11165 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0=
11166 # gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p
11167 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11168 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11169 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
11170 # Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
11171 # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
11172 # PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0
11174 # Configures MIO Pin 71 peripheral interface mapping
11175 #(OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) */
11176 mask_write 0XFF18011C 0x000000FE 0x00000002
11177 # Register : MIO_PIN_72 @ 0XFF180120</p>
11179 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
11180 # 1]- (RX RGMII data)
11181 # PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1
11183 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11184 # ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
11186 # PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0
11188 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
11189 # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
11190 # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
11191 # t[1]- (8-bit Data bus) 3= Not Used
11192 # PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0
11194 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0=
11195 # gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p
11196 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11197 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
11198 # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
11199 # ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
11200 # al output) 7= Not Used
11201 # PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0
11203 # Configures MIO Pin 72 peripheral interface mapping
11204 #(OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) */
11205 mask_write 0XFF180120 0x000000FE 0x00000002
11206 # Register : MIO_PIN_73 @ 0XFF180124</p>
11208 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
11209 # 2]- (RX RGMII data)
11210 # PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1
11212 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11213 # ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
11215 # PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0
11217 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
11218 # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
11219 # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
11220 # t[2]- (8-bit Data bus) 3= Not Used
11221 # PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0
11223 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0=
11224 # gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph
11225 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11226 # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
11227 # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
11228 # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
11229 # Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
11230 # PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0
11232 # Configures MIO Pin 73 peripheral interface mapping
11233 #(OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) */
11234 mask_write 0XFF180124 0x000000FE 0x00000002
11235 # Register : MIO_PIN_74 @ 0XFF180128</p>
11237 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
11238 # 3]- (RX RGMII data)
11239 # PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1
11241 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11242 # ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
11244 # PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0
11246 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
11247 # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
11248 # d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
11249 # t[3]- (8-bit Data bus) 3= Not Used
11250 # PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0
11252 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0=
11253 # gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph
11254 # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
11255 # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
11256 # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
11257 # i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
11258 # UART receiver serial input) 7= Not Used
11259 # PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0
11261 # Configures MIO Pin 74 peripheral interface mapping
11262 #(OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) */
11263 mask_write 0XFF180128 0x000000FE 0x00000002
11264 # Register : MIO_PIN_75 @ 0XFF18012C</p>
11266 # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
11267 # tl- (RX RGMII control )
11268 # PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1
11270 # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
11271 # ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
11273 # PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0
11275 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
11276 # (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
11277 # , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
11278 # PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0
11280 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0=
11281 # gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p
11282 # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
11283 # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
11284 # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
11285 # 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
11286 # xd- (UART transmitter serial output) 7= Not Used
11287 # PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0
11289 # Configures MIO Pin 75 peripheral interface mapping
11290 #(OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) */
11291 mask_write 0XFF18012C 0x000000FE 0x00000002
11292 # Register : MIO_PIN_76 @ 0XFF180130</p>
11294 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11295 # PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0
11297 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11298 # PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0
11300 # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
11301 # rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
11302 # clock) 3= Not Used
11303 # PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0
11305 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0=
11306 # gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p
11307 # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
11308 # 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI
11309 # O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
11310 # _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
11311 # PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6
11313 # Configures MIO Pin 76 peripheral interface mapping
11314 #(OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) */
11315 mask_write 0XFF180130 0x000000FE 0x000000C0
11316 # Register : MIO_PIN_77 @ 0XFF180134</p>
11318 # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
11319 # PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0
11321 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11322 # PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0
11324 # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
11325 # 1_cd_n- (SD card detect from connector) 3= Not Used
11326 # PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0
11328 # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0=
11329 # gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph
11330 # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
11331 # c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M
11332 # DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input,
11333 # gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5
11334 # = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou
11335 # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
11336 # ut, gem3_mdio_out- (MDIO Data) 7= Not Used
11337 # PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6
11339 # Configures MIO Pin 77 peripheral interface mapping
11340 #(OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) */
11341 mask_write 0XFF180134 0x000000FE 0x000000C0
11342 # Register : MIO_MST_TRI0 @ 0XFF180204</p>
11344 # Master Tri-state Enable for pin 0, active high
11345 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0
11347 # Master Tri-state Enable for pin 1, active high
11348 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0
11350 # Master Tri-state Enable for pin 2, active high
11351 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0
11353 # Master Tri-state Enable for pin 3, active high
11354 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0
11356 # Master Tri-state Enable for pin 4, active high
11357 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0
11359 # Master Tri-state Enable for pin 5, active high
11360 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0
11362 # Master Tri-state Enable for pin 6, active high
11363 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0
11365 # Master Tri-state Enable for pin 7, active high
11366 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0
11368 # Master Tri-state Enable for pin 8, active high
11369 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0
11371 # Master Tri-state Enable for pin 9, active high
11372 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0
11374 # Master Tri-state Enable for pin 10, active high
11375 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0
11377 # Master Tri-state Enable for pin 11, active high
11378 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0
11380 # Master Tri-state Enable for pin 12, active high
11381 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0
11383 # Master Tri-state Enable for pin 13, active high
11384 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0
11386 # Master Tri-state Enable for pin 14, active high
11387 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0
11389 # Master Tri-state Enable for pin 15, active high
11390 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0
11392 # Master Tri-state Enable for pin 16, active high
11393 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0
11395 # Master Tri-state Enable for pin 17, active high
11396 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0
11398 # Master Tri-state Enable for pin 18, active high
11399 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1
11401 # Master Tri-state Enable for pin 19, active high
11402 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0
11404 # Master Tri-state Enable for pin 20, active high
11405 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0
11407 # Master Tri-state Enable for pin 21, active high
11408 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1
11410 # Master Tri-state Enable for pin 22, active high
11411 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0
11413 # Master Tri-state Enable for pin 23, active high
11414 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0
11416 # Master Tri-state Enable for pin 24, active high
11417 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0
11419 # Master Tri-state Enable for pin 25, active high
11420 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1
11422 # Master Tri-state Enable for pin 26, active high
11423 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0
11425 # Master Tri-state Enable for pin 27, active high
11426 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0
11428 # Master Tri-state Enable for pin 28, active high
11429 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1
11431 # Master Tri-state Enable for pin 29, active high
11432 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0
11434 # Master Tri-state Enable for pin 30, active high
11435 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1
11437 # Master Tri-state Enable for pin 31, active high
11438 # PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0
11440 # MIO pin Tri-state Enables, 31:0
11441 #(OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) */
11442 mask_write 0XFF180204 0xFFFFFFFF 0x52240000
11443 # Register : MIO_MST_TRI1 @ 0XFF180208</p>
11445 # Master Tri-state Enable for pin 32, active high
11446 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0
11448 # Master Tri-state Enable for pin 33, active high
11449 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0
11451 # Master Tri-state Enable for pin 34, active high
11452 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0
11454 # Master Tri-state Enable for pin 35, active high
11455 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0
11457 # Master Tri-state Enable for pin 36, active high
11458 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0
11460 # Master Tri-state Enable for pin 37, active high
11461 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0
11463 # Master Tri-state Enable for pin 38, active high
11464 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0
11466 # Master Tri-state Enable for pin 39, active high
11467 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0
11469 # Master Tri-state Enable for pin 40, active high
11470 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0
11472 # Master Tri-state Enable for pin 41, active high
11473 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0
11475 # Master Tri-state Enable for pin 42, active high
11476 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0
11478 # Master Tri-state Enable for pin 43, active high
11479 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0
11481 # Master Tri-state Enable for pin 44, active high
11482 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1
11484 # Master Tri-state Enable for pin 45, active high
11485 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1
11487 # Master Tri-state Enable for pin 46, active high
11488 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0
11490 # Master Tri-state Enable for pin 47, active high
11491 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0
11493 # Master Tri-state Enable for pin 48, active high
11494 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0
11496 # Master Tri-state Enable for pin 49, active high
11497 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0
11499 # Master Tri-state Enable for pin 50, active high
11500 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0
11502 # Master Tri-state Enable for pin 51, active high
11503 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0
11505 # Master Tri-state Enable for pin 52, active high
11506 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1
11508 # Master Tri-state Enable for pin 53, active high
11509 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1
11511 # Master Tri-state Enable for pin 54, active high
11512 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0
11514 # Master Tri-state Enable for pin 55, active high
11515 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1
11517 # Master Tri-state Enable for pin 56, active high
11518 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0
11520 # Master Tri-state Enable for pin 57, active high
11521 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0
11523 # Master Tri-state Enable for pin 58, active high
11524 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0
11526 # Master Tri-state Enable for pin 59, active high
11527 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0
11529 # Master Tri-state Enable for pin 60, active high
11530 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0
11532 # Master Tri-state Enable for pin 61, active high
11533 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0
11535 # Master Tri-state Enable for pin 62, active high
11536 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0
11538 # Master Tri-state Enable for pin 63, active high
11539 # PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0
11541 # MIO pin Tri-state Enables, 63:32
11542 #(OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) */
11543 mask_write 0XFF180208 0xFFFFFFFF 0x00B03000
11544 # Register : MIO_MST_TRI2 @ 0XFF18020C</p>
11546 # Master Tri-state Enable for pin 64, active high
11547 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0
11549 # Master Tri-state Enable for pin 65, active high
11550 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0
11552 # Master Tri-state Enable for pin 66, active high
11553 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0
11555 # Master Tri-state Enable for pin 67, active high
11556 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0
11558 # Master Tri-state Enable for pin 68, active high
11559 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0
11561 # Master Tri-state Enable for pin 69, active high
11562 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0
11564 # Master Tri-state Enable for pin 70, active high
11565 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1
11567 # Master Tri-state Enable for pin 71, active high
11568 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1
11570 # Master Tri-state Enable for pin 72, active high
11571 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1
11573 # Master Tri-state Enable for pin 73, active high
11574 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1
11576 # Master Tri-state Enable for pin 74, active high
11577 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1
11579 # Master Tri-state Enable for pin 75, active high
11580 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1
11582 # Master Tri-state Enable for pin 76, active high
11583 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0
11585 # Master Tri-state Enable for pin 77, active high
11586 # PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0
11588 # MIO pin Tri-state Enables, 77:64
11589 #(OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) */
11590 mask_write 0XFF18020C 0x00003FFF 0x00000FC0
11591 # Register : bank0_ctrl0 @ 0XFF180138</p>
11593 # Each bit applies to a single IO. Bit 0 for MIO[0].
11594 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1
11596 # Each bit applies to a single IO. Bit 0 for MIO[0].
11597 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1
11599 # Each bit applies to a single IO. Bit 0 for MIO[0].
11600 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1
11602 # Each bit applies to a single IO. Bit 0 for MIO[0].
11603 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1
11605 # Each bit applies to a single IO. Bit 0 for MIO[0].
11606 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1
11608 # Each bit applies to a single IO. Bit 0 for MIO[0].
11609 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1
11611 # Each bit applies to a single IO. Bit 0 for MIO[0].
11612 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1
11614 # Each bit applies to a single IO. Bit 0 for MIO[0].
11615 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1
11617 # Each bit applies to a single IO. Bit 0 for MIO[0].
11618 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1
11620 # Each bit applies to a single IO. Bit 0 for MIO[0].
11621 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1
11623 # Each bit applies to a single IO. Bit 0 for MIO[0].
11624 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1
11626 # Each bit applies to a single IO. Bit 0 for MIO[0].
11627 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1
11629 # Each bit applies to a single IO. Bit 0 for MIO[0].
11630 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1
11632 # Each bit applies to a single IO. Bit 0 for MIO[0].
11633 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1
11635 # Each bit applies to a single IO. Bit 0 for MIO[0].
11636 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1
11638 # Each bit applies to a single IO. Bit 0 for MIO[0].
11639 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1
11641 # Each bit applies to a single IO. Bit 0 for MIO[0].
11642 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1
11644 # Each bit applies to a single IO. Bit 0 for MIO[0].
11645 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1
11647 # Each bit applies to a single IO. Bit 0 for MIO[0].
11648 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1
11650 # Each bit applies to a single IO. Bit 0 for MIO[0].
11651 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1
11653 # Each bit applies to a single IO. Bit 0 for MIO[0].
11654 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1
11656 # Each bit applies to a single IO. Bit 0 for MIO[0].
11657 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1
11659 # Each bit applies to a single IO. Bit 0 for MIO[0].
11660 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1
11662 # Each bit applies to a single IO. Bit 0 for MIO[0].
11663 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1
11665 # Each bit applies to a single IO. Bit 0 for MIO[0].
11666 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1
11668 # Each bit applies to a single IO. Bit 0 for MIO[0].
11669 # PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1
11671 # Drive0 control to MIO Bank 0 - control MIO[25:0]
11672 #(OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) */
11673 mask_write 0XFF180138 0x03FFFFFF 0x03FFFFFF
11674 # Register : bank0_ctrl1 @ 0XFF18013C</p>
11676 # Each bit applies to a single IO. Bit 0 for MIO[0].
11677 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1
11679 # Each bit applies to a single IO. Bit 0 for MIO[0].
11680 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1
11682 # Each bit applies to a single IO. Bit 0 for MIO[0].
11683 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1
11685 # Each bit applies to a single IO. Bit 0 for MIO[0].
11686 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1
11688 # Each bit applies to a single IO. Bit 0 for MIO[0].
11689 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1
11691 # Each bit applies to a single IO. Bit 0 for MIO[0].
11692 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1
11694 # Each bit applies to a single IO. Bit 0 for MIO[0].
11695 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1
11697 # Each bit applies to a single IO. Bit 0 for MIO[0].
11698 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1
11700 # Each bit applies to a single IO. Bit 0 for MIO[0].
11701 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1
11703 # Each bit applies to a single IO. Bit 0 for MIO[0].
11704 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1
11706 # Each bit applies to a single IO. Bit 0 for MIO[0].
11707 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1
11709 # Each bit applies to a single IO. Bit 0 for MIO[0].
11710 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1
11712 # Each bit applies to a single IO. Bit 0 for MIO[0].
11713 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1
11715 # Each bit applies to a single IO. Bit 0 for MIO[0].
11716 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1
11718 # Each bit applies to a single IO. Bit 0 for MIO[0].
11719 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1
11721 # Each bit applies to a single IO. Bit 0 for MIO[0].
11722 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1
11724 # Each bit applies to a single IO. Bit 0 for MIO[0].
11725 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1
11727 # Each bit applies to a single IO. Bit 0 for MIO[0].
11728 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1
11730 # Each bit applies to a single IO. Bit 0 for MIO[0].
11731 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1
11733 # Each bit applies to a single IO. Bit 0 for MIO[0].
11734 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1
11736 # Each bit applies to a single IO. Bit 0 for MIO[0].
11737 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1
11739 # Each bit applies to a single IO. Bit 0 for MIO[0].
11740 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1
11742 # Each bit applies to a single IO. Bit 0 for MIO[0].
11743 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1
11745 # Each bit applies to a single IO. Bit 0 for MIO[0].
11746 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1
11748 # Each bit applies to a single IO. Bit 0 for MIO[0].
11749 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1
11751 # Each bit applies to a single IO. Bit 0 for MIO[0].
11752 # PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1
11754 # Drive1 control to MIO Bank 0 - control MIO[25:0]
11755 #(OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) */
11756 mask_write 0XFF18013C 0x03FFFFFF 0x03FFFFFF
11757 # Register : bank0_ctrl3 @ 0XFF180140</p>
11759 # Each bit applies to a single IO. Bit 0 for MIO[0].
11760 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0
11762 # Each bit applies to a single IO. Bit 0 for MIO[0].
11763 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0
11765 # Each bit applies to a single IO. Bit 0 for MIO[0].
11766 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0
11768 # Each bit applies to a single IO. Bit 0 for MIO[0].
11769 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0
11771 # Each bit applies to a single IO. Bit 0 for MIO[0].
11772 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0
11774 # Each bit applies to a single IO. Bit 0 for MIO[0].
11775 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0
11777 # Each bit applies to a single IO. Bit 0 for MIO[0].
11778 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0
11780 # Each bit applies to a single IO. Bit 0 for MIO[0].
11781 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0
11783 # Each bit applies to a single IO. Bit 0 for MIO[0].
11784 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0
11786 # Each bit applies to a single IO. Bit 0 for MIO[0].
11787 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0
11789 # Each bit applies to a single IO. Bit 0 for MIO[0].
11790 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0
11792 # Each bit applies to a single IO. Bit 0 for MIO[0].
11793 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0
11795 # Each bit applies to a single IO. Bit 0 for MIO[0].
11796 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0
11798 # Each bit applies to a single IO. Bit 0 for MIO[0].
11799 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0
11801 # Each bit applies to a single IO. Bit 0 for MIO[0].
11802 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0
11804 # Each bit applies to a single IO. Bit 0 for MIO[0].
11805 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0
11807 # Each bit applies to a single IO. Bit 0 for MIO[0].
11808 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0
11810 # Each bit applies to a single IO. Bit 0 for MIO[0].
11811 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0
11813 # Each bit applies to a single IO. Bit 0 for MIO[0].
11814 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0
11816 # Each bit applies to a single IO. Bit 0 for MIO[0].
11817 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0
11819 # Each bit applies to a single IO. Bit 0 for MIO[0].
11820 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0
11822 # Each bit applies to a single IO. Bit 0 for MIO[0].
11823 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0
11825 # Each bit applies to a single IO. Bit 0 for MIO[0].
11826 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0
11828 # Each bit applies to a single IO. Bit 0 for MIO[0].
11829 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0
11831 # Each bit applies to a single IO. Bit 0 for MIO[0].
11832 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0
11834 # Each bit applies to a single IO. Bit 0 for MIO[0].
11835 # PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0
11837 # Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
11838 #(OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) */
11839 mask_write 0XFF180140 0x03FFFFFF 0x00000000
11840 # Register : bank0_ctrl4 @ 0XFF180144</p>
11842 # Each bit applies to a single IO. Bit 0 for MIO[0].
11843 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
11845 # Each bit applies to a single IO. Bit 0 for MIO[0].
11846 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
11848 # Each bit applies to a single IO. Bit 0 for MIO[0].
11849 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
11851 # Each bit applies to a single IO. Bit 0 for MIO[0].
11852 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
11854 # Each bit applies to a single IO. Bit 0 for MIO[0].
11855 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
11857 # Each bit applies to a single IO. Bit 0 for MIO[0].
11858 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
11860 # Each bit applies to a single IO. Bit 0 for MIO[0].
11861 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
11863 # Each bit applies to a single IO. Bit 0 for MIO[0].
11864 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
11866 # Each bit applies to a single IO. Bit 0 for MIO[0].
11867 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
11869 # Each bit applies to a single IO. Bit 0 for MIO[0].
11870 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
11872 # Each bit applies to a single IO. Bit 0 for MIO[0].
11873 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
11875 # Each bit applies to a single IO. Bit 0 for MIO[0].
11876 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
11878 # Each bit applies to a single IO. Bit 0 for MIO[0].
11879 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
11881 # Each bit applies to a single IO. Bit 0 for MIO[0].
11882 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
11884 # Each bit applies to a single IO. Bit 0 for MIO[0].
11885 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
11887 # Each bit applies to a single IO. Bit 0 for MIO[0].
11888 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
11890 # Each bit applies to a single IO. Bit 0 for MIO[0].
11891 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
11893 # Each bit applies to a single IO. Bit 0 for MIO[0].
11894 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
11896 # Each bit applies to a single IO. Bit 0 for MIO[0].
11897 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
11899 # Each bit applies to a single IO. Bit 0 for MIO[0].
11900 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
11902 # Each bit applies to a single IO. Bit 0 for MIO[0].
11903 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
11905 # Each bit applies to a single IO. Bit 0 for MIO[0].
11906 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
11908 # Each bit applies to a single IO. Bit 0 for MIO[0].
11909 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
11911 # Each bit applies to a single IO. Bit 0 for MIO[0].
11912 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
11914 # Each bit applies to a single IO. Bit 0 for MIO[0].
11915 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
11917 # Each bit applies to a single IO. Bit 0 for MIO[0].
11918 # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
11920 # When mio_bank0_pull_enable is set, this selects pull up or pull down for
11921 # MIO Bank 0 - control MIO[25:0]
11922 #(OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) */
11923 mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF
11924 # Register : bank0_ctrl5 @ 0XFF180148</p>
11926 # Each bit applies to a single IO. Bit 0 for MIO[0].
11927 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1
11929 # Each bit applies to a single IO. Bit 0 for MIO[0].
11930 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1
11932 # Each bit applies to a single IO. Bit 0 for MIO[0].
11933 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1
11935 # Each bit applies to a single IO. Bit 0 for MIO[0].
11936 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1
11938 # Each bit applies to a single IO. Bit 0 for MIO[0].
11939 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1
11941 # Each bit applies to a single IO. Bit 0 for MIO[0].
11942 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1
11944 # Each bit applies to a single IO. Bit 0 for MIO[0].
11945 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1
11947 # Each bit applies to a single IO. Bit 0 for MIO[0].
11948 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1
11950 # Each bit applies to a single IO. Bit 0 for MIO[0].
11951 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1
11953 # Each bit applies to a single IO. Bit 0 for MIO[0].
11954 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1
11956 # Each bit applies to a single IO. Bit 0 for MIO[0].
11957 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1
11959 # Each bit applies to a single IO. Bit 0 for MIO[0].
11960 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1
11962 # Each bit applies to a single IO. Bit 0 for MIO[0].
11963 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1
11965 # Each bit applies to a single IO. Bit 0 for MIO[0].
11966 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1
11968 # Each bit applies to a single IO. Bit 0 for MIO[0].
11969 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1
11971 # Each bit applies to a single IO. Bit 0 for MIO[0].
11972 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1
11974 # Each bit applies to a single IO. Bit 0 for MIO[0].
11975 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1
11977 # Each bit applies to a single IO. Bit 0 for MIO[0].
11978 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1
11980 # Each bit applies to a single IO. Bit 0 for MIO[0].
11981 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1
11983 # Each bit applies to a single IO. Bit 0 for MIO[0].
11984 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1
11986 # Each bit applies to a single IO. Bit 0 for MIO[0].
11987 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1
11989 # Each bit applies to a single IO. Bit 0 for MIO[0].
11990 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1
11992 # Each bit applies to a single IO. Bit 0 for MIO[0].
11993 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1
11995 # Each bit applies to a single IO. Bit 0 for MIO[0].
11996 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1
11998 # Each bit applies to a single IO. Bit 0 for MIO[0].
11999 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1
12001 # Each bit applies to a single IO. Bit 0 for MIO[0].
12002 # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1
12004 # When set, this enables mio_bank0_pullupdown to selects pull up or pull d
12005 # own for MIO Bank 0 - control MIO[25:0]
12006 #(OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) */
12007 mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF
12008 # Register : bank0_ctrl6 @ 0XFF18014C</p>
12010 # Each bit applies to a single IO. Bit 0 for MIO[0].
12011 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
12013 # Each bit applies to a single IO. Bit 0 for MIO[0].
12014 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
12016 # Each bit applies to a single IO. Bit 0 for MIO[0].
12017 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
12019 # Each bit applies to a single IO. Bit 0 for MIO[0].
12020 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
12022 # Each bit applies to a single IO. Bit 0 for MIO[0].
12023 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
12025 # Each bit applies to a single IO. Bit 0 for MIO[0].
12026 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
12028 # Each bit applies to a single IO. Bit 0 for MIO[0].
12029 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
12031 # Each bit applies to a single IO. Bit 0 for MIO[0].
12032 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
12034 # Each bit applies to a single IO. Bit 0 for MIO[0].
12035 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
12037 # Each bit applies to a single IO. Bit 0 for MIO[0].
12038 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
12040 # Each bit applies to a single IO. Bit 0 for MIO[0].
12041 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
12043 # Each bit applies to a single IO. Bit 0 for MIO[0].
12044 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
12046 # Each bit applies to a single IO. Bit 0 for MIO[0].
12047 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
12049 # Each bit applies to a single IO. Bit 0 for MIO[0].
12050 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
12052 # Each bit applies to a single IO. Bit 0 for MIO[0].
12053 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
12055 # Each bit applies to a single IO. Bit 0 for MIO[0].
12056 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
12058 # Each bit applies to a single IO. Bit 0 for MIO[0].
12059 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
12061 # Each bit applies to a single IO. Bit 0 for MIO[0].
12062 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
12064 # Each bit applies to a single IO. Bit 0 for MIO[0].
12065 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
12067 # Each bit applies to a single IO. Bit 0 for MIO[0].
12068 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
12070 # Each bit applies to a single IO. Bit 0 for MIO[0].
12071 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
12073 # Each bit applies to a single IO. Bit 0 for MIO[0].
12074 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
12076 # Each bit applies to a single IO. Bit 0 for MIO[0].
12077 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
12079 # Each bit applies to a single IO. Bit 0 for MIO[0].
12080 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
12082 # Each bit applies to a single IO. Bit 0 for MIO[0].
12083 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
12085 # Each bit applies to a single IO. Bit 0 for MIO[0].
12086 # PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
12088 # Slew rate control to MIO Bank 0 - control MIO[25:0]
12089 #(OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) */
12090 mask_write 0XFF18014C 0x03FFFFFF 0x00000000
12091 # Register : bank1_ctrl0 @ 0XFF180154</p>
12093 # Each bit applies to a single IO. Bit 0 for MIO[26].
12094 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1
12096 # Each bit applies to a single IO. Bit 0 for MIO[26].
12097 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1
12099 # Each bit applies to a single IO. Bit 0 for MIO[26].
12100 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1
12102 # Each bit applies to a single IO. Bit 0 for MIO[26].
12103 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1
12105 # Each bit applies to a single IO. Bit 0 for MIO[26].
12106 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1
12108 # Each bit applies to a single IO. Bit 0 for MIO[26].
12109 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1
12111 # Each bit applies to a single IO. Bit 0 for MIO[26].
12112 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1
12114 # Each bit applies to a single IO. Bit 0 for MIO[26].
12115 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1
12117 # Each bit applies to a single IO. Bit 0 for MIO[26].
12118 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1
12120 # Each bit applies to a single IO. Bit 0 for MIO[26].
12121 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1
12123 # Each bit applies to a single IO. Bit 0 for MIO[26].
12124 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1
12126 # Each bit applies to a single IO. Bit 0 for MIO[26].
12127 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1
12129 # Each bit applies to a single IO. Bit 0 for MIO[26].
12130 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1
12132 # Each bit applies to a single IO. Bit 0 for MIO[26].
12133 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1
12135 # Each bit applies to a single IO. Bit 0 for MIO[26].
12136 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1
12138 # Each bit applies to a single IO. Bit 0 for MIO[26].
12139 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1
12141 # Each bit applies to a single IO. Bit 0 for MIO[26].
12142 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1
12144 # Each bit applies to a single IO. Bit 0 for MIO[26].
12145 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1
12147 # Each bit applies to a single IO. Bit 0 for MIO[26].
12148 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1
12150 # Each bit applies to a single IO. Bit 0 for MIO[26].
12151 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1
12153 # Each bit applies to a single IO. Bit 0 for MIO[26].
12154 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1
12156 # Each bit applies to a single IO. Bit 0 for MIO[26].
12157 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1
12159 # Each bit applies to a single IO. Bit 0 for MIO[26].
12160 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1
12162 # Each bit applies to a single IO. Bit 0 for MIO[26].
12163 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1
12165 # Each bit applies to a single IO. Bit 0 for MIO[26].
12166 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1
12168 # Each bit applies to a single IO. Bit 0 for MIO[26].
12169 # PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1
12171 # Drive0 control to MIO Bank 1 - control MIO[51:26]
12172 #(OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) */
12173 mask_write 0XFF180154 0x03FFFFFF 0x03FFFFFF
12174 # Register : bank1_ctrl1 @ 0XFF180158</p>
12176 # Each bit applies to a single IO. Bit 0 for MIO[26].
12177 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1
12179 # Each bit applies to a single IO. Bit 0 for MIO[26].
12180 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1
12182 # Each bit applies to a single IO. Bit 0 for MIO[26].
12183 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1
12185 # Each bit applies to a single IO. Bit 0 for MIO[26].
12186 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1
12188 # Each bit applies to a single IO. Bit 0 for MIO[26].
12189 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1
12191 # Each bit applies to a single IO. Bit 0 for MIO[26].
12192 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1
12194 # Each bit applies to a single IO. Bit 0 for MIO[26].
12195 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1
12197 # Each bit applies to a single IO. Bit 0 for MIO[26].
12198 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1
12200 # Each bit applies to a single IO. Bit 0 for MIO[26].
12201 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1
12203 # Each bit applies to a single IO. Bit 0 for MIO[26].
12204 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1
12206 # Each bit applies to a single IO. Bit 0 for MIO[26].
12207 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1
12209 # Each bit applies to a single IO. Bit 0 for MIO[26].
12210 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1
12212 # Each bit applies to a single IO. Bit 0 for MIO[26].
12213 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1
12215 # Each bit applies to a single IO. Bit 0 for MIO[26].
12216 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1
12218 # Each bit applies to a single IO. Bit 0 for MIO[26].
12219 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1
12221 # Each bit applies to a single IO. Bit 0 for MIO[26].
12222 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1
12224 # Each bit applies to a single IO. Bit 0 for MIO[26].
12225 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1
12227 # Each bit applies to a single IO. Bit 0 for MIO[26].
12228 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1
12230 # Each bit applies to a single IO. Bit 0 for MIO[26].
12231 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1
12233 # Each bit applies to a single IO. Bit 0 for MIO[26].
12234 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1
12236 # Each bit applies to a single IO. Bit 0 for MIO[26].
12237 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1
12239 # Each bit applies to a single IO. Bit 0 for MIO[26].
12240 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1
12242 # Each bit applies to a single IO. Bit 0 for MIO[26].
12243 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1
12245 # Each bit applies to a single IO. Bit 0 for MIO[26].
12246 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1
12248 # Each bit applies to a single IO. Bit 0 for MIO[26].
12249 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1
12251 # Each bit applies to a single IO. Bit 0 for MIO[26].
12252 # PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1
12254 # Drive1 control to MIO Bank 1 - control MIO[51:26]
12255 #(OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) */
12256 mask_write 0XFF180158 0x03FFFFFF 0x03FFFFFF
12257 # Register : bank1_ctrl3 @ 0XFF18015C</p>
12259 # Each bit applies to a single IO. Bit 0 for MIO[26].
12260 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0
12262 # Each bit applies to a single IO. Bit 0 for MIO[26].
12263 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0
12265 # Each bit applies to a single IO. Bit 0 for MIO[26].
12266 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0
12268 # Each bit applies to a single IO. Bit 0 for MIO[26].
12269 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0
12271 # Each bit applies to a single IO. Bit 0 for MIO[26].
12272 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0
12274 # Each bit applies to a single IO. Bit 0 for MIO[26].
12275 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0
12277 # Each bit applies to a single IO. Bit 0 for MIO[26].
12278 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0
12280 # Each bit applies to a single IO. Bit 0 for MIO[26].
12281 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0
12283 # Each bit applies to a single IO. Bit 0 for MIO[26].
12284 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0
12286 # Each bit applies to a single IO. Bit 0 for MIO[26].
12287 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0
12289 # Each bit applies to a single IO. Bit 0 for MIO[26].
12290 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0
12292 # Each bit applies to a single IO. Bit 0 for MIO[26].
12293 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0
12295 # Each bit applies to a single IO. Bit 0 for MIO[26].
12296 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0
12298 # Each bit applies to a single IO. Bit 0 for MIO[26].
12299 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0
12301 # Each bit applies to a single IO. Bit 0 for MIO[26].
12302 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0
12304 # Each bit applies to a single IO. Bit 0 for MIO[26].
12305 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0
12307 # Each bit applies to a single IO. Bit 0 for MIO[26].
12308 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0
12310 # Each bit applies to a single IO. Bit 0 for MIO[26].
12311 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0
12313 # Each bit applies to a single IO. Bit 0 for MIO[26].
12314 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0
12316 # Each bit applies to a single IO. Bit 0 for MIO[26].
12317 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0
12319 # Each bit applies to a single IO. Bit 0 for MIO[26].
12320 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0
12322 # Each bit applies to a single IO. Bit 0 for MIO[26].
12323 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0
12325 # Each bit applies to a single IO. Bit 0 for MIO[26].
12326 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0
12328 # Each bit applies to a single IO. Bit 0 for MIO[26].
12329 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0
12331 # Each bit applies to a single IO. Bit 0 for MIO[26].
12332 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0
12334 # Each bit applies to a single IO. Bit 0 for MIO[26].
12335 # PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0
12337 # Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
12338 #(OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) */
12339 mask_write 0XFF18015C 0x03FFFFFF 0x00000000
12340 # Register : bank1_ctrl4 @ 0XFF180160</p>
12342 # Each bit applies to a single IO. Bit 0 for MIO[26].
12343 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
12345 # Each bit applies to a single IO. Bit 0 for MIO[26].
12346 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
12348 # Each bit applies to a single IO. Bit 0 for MIO[26].
12349 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
12351 # Each bit applies to a single IO. Bit 0 for MIO[26].
12352 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
12354 # Each bit applies to a single IO. Bit 0 for MIO[26].
12355 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
12357 # Each bit applies to a single IO. Bit 0 for MIO[26].
12358 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
12360 # Each bit applies to a single IO. Bit 0 for MIO[26].
12361 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
12363 # Each bit applies to a single IO. Bit 0 for MIO[26].
12364 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
12366 # Each bit applies to a single IO. Bit 0 for MIO[26].
12367 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
12369 # Each bit applies to a single IO. Bit 0 for MIO[26].
12370 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
12372 # Each bit applies to a single IO. Bit 0 for MIO[26].
12373 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
12375 # Each bit applies to a single IO. Bit 0 for MIO[26].
12376 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
12378 # Each bit applies to a single IO. Bit 0 for MIO[26].
12379 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
12381 # Each bit applies to a single IO. Bit 0 for MIO[26].
12382 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
12384 # Each bit applies to a single IO. Bit 0 for MIO[26].
12385 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
12387 # Each bit applies to a single IO. Bit 0 for MIO[26].
12388 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
12390 # Each bit applies to a single IO. Bit 0 for MIO[26].
12391 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
12393 # Each bit applies to a single IO. Bit 0 for MIO[26].
12394 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
12396 # Each bit applies to a single IO. Bit 0 for MIO[26].
12397 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
12399 # Each bit applies to a single IO. Bit 0 for MIO[26].
12400 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
12402 # Each bit applies to a single IO. Bit 0 for MIO[26].
12403 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
12405 # Each bit applies to a single IO. Bit 0 for MIO[26].
12406 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
12408 # Each bit applies to a single IO. Bit 0 for MIO[26].
12409 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
12411 # Each bit applies to a single IO. Bit 0 for MIO[26].
12412 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
12414 # Each bit applies to a single IO. Bit 0 for MIO[26].
12415 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
12417 # Each bit applies to a single IO. Bit 0 for MIO[26].
12418 # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
12420 # When mio_bank1_pull_enable is set, this selects pull up or pull down for
12421 # MIO Bank 1 - control MIO[51:26]
12422 #(OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) */
12423 mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF
12424 # Register : bank1_ctrl5 @ 0XFF180164</p>
12426 # Each bit applies to a single IO. Bit 0 for MIO[26].
12427 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1
12429 # Each bit applies to a single IO. Bit 0 for MIO[26].
12430 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1
12432 # Each bit applies to a single IO. Bit 0 for MIO[26].
12433 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1
12435 # Each bit applies to a single IO. Bit 0 for MIO[26].
12436 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1
12438 # Each bit applies to a single IO. Bit 0 for MIO[26].
12439 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1
12441 # Each bit applies to a single IO. Bit 0 for MIO[26].
12442 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1
12444 # Each bit applies to a single IO. Bit 0 for MIO[26].
12445 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1
12447 # Each bit applies to a single IO. Bit 0 for MIO[26].
12448 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1
12450 # Each bit applies to a single IO. Bit 0 for MIO[26].
12451 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1
12453 # Each bit applies to a single IO. Bit 0 for MIO[26].
12454 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1
12456 # Each bit applies to a single IO. Bit 0 for MIO[26].
12457 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1
12459 # Each bit applies to a single IO. Bit 0 for MIO[26].
12460 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1
12462 # Each bit applies to a single IO. Bit 0 for MIO[26].
12463 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1
12465 # Each bit applies to a single IO. Bit 0 for MIO[26].
12466 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1
12468 # Each bit applies to a single IO. Bit 0 for MIO[26].
12469 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1
12471 # Each bit applies to a single IO. Bit 0 for MIO[26].
12472 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1
12474 # Each bit applies to a single IO. Bit 0 for MIO[26].
12475 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1
12477 # Each bit applies to a single IO. Bit 0 for MIO[26].
12478 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1
12480 # Each bit applies to a single IO. Bit 0 for MIO[26].
12481 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1
12483 # Each bit applies to a single IO. Bit 0 for MIO[26].
12484 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1
12486 # Each bit applies to a single IO. Bit 0 for MIO[26].
12487 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1
12489 # Each bit applies to a single IO. Bit 0 for MIO[26].
12490 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1
12492 # Each bit applies to a single IO. Bit 0 for MIO[26].
12493 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1
12495 # Each bit applies to a single IO. Bit 0 for MIO[26].
12496 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1
12498 # Each bit applies to a single IO. Bit 0 for MIO[26].
12499 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1
12501 # Each bit applies to a single IO. Bit 0 for MIO[26].
12502 # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1
12504 # When set, this enables mio_bank1_pullupdown to selects pull up or pull d
12505 # own for MIO Bank 1 - control MIO[51:26]
12506 #(OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) */
12507 mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF
12508 # Register : bank1_ctrl6 @ 0XFF180168</p>
12510 # Each bit applies to a single IO. Bit 0 for MIO[26].
12511 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
12513 # Each bit applies to a single IO. Bit 0 for MIO[26].
12514 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
12516 # Each bit applies to a single IO. Bit 0 for MIO[26].
12517 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
12519 # Each bit applies to a single IO. Bit 0 for MIO[26].
12520 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
12522 # Each bit applies to a single IO. Bit 0 for MIO[26].
12523 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
12525 # Each bit applies to a single IO. Bit 0 for MIO[26].
12526 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
12528 # Each bit applies to a single IO. Bit 0 for MIO[26].
12529 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
12531 # Each bit applies to a single IO. Bit 0 for MIO[26].
12532 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
12534 # Each bit applies to a single IO. Bit 0 for MIO[26].
12535 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
12537 # Each bit applies to a single IO. Bit 0 for MIO[26].
12538 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
12540 # Each bit applies to a single IO. Bit 0 for MIO[26].
12541 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
12543 # Each bit applies to a single IO. Bit 0 for MIO[26].
12544 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
12546 # Each bit applies to a single IO. Bit 0 for MIO[26].
12547 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
12549 # Each bit applies to a single IO. Bit 0 for MIO[26].
12550 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
12552 # Each bit applies to a single IO. Bit 0 for MIO[26].
12553 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
12555 # Each bit applies to a single IO. Bit 0 for MIO[26].
12556 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
12558 # Each bit applies to a single IO. Bit 0 for MIO[26].
12559 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
12561 # Each bit applies to a single IO. Bit 0 for MIO[26].
12562 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
12564 # Each bit applies to a single IO. Bit 0 for MIO[26].
12565 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
12567 # Each bit applies to a single IO. Bit 0 for MIO[26].
12568 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
12570 # Each bit applies to a single IO. Bit 0 for MIO[26].
12571 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
12573 # Each bit applies to a single IO. Bit 0 for MIO[26].
12574 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
12576 # Each bit applies to a single IO. Bit 0 for MIO[26].
12577 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
12579 # Each bit applies to a single IO. Bit 0 for MIO[26].
12580 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
12582 # Each bit applies to a single IO. Bit 0 for MIO[26].
12583 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
12585 # Each bit applies to a single IO. Bit 0 for MIO[26].
12586 # PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
12588 # Slew rate control to MIO Bank 1 - control MIO[51:26]
12589 #(OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) */
12590 mask_write 0XFF180168 0x03FFFFFF 0x00000000
12591 # Register : bank2_ctrl0 @ 0XFF180170</p>
12593 # Each bit applies to a single IO. Bit 0 for MIO[52].
12594 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1
12596 # Each bit applies to a single IO. Bit 0 for MIO[52].
12597 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1
12599 # Each bit applies to a single IO. Bit 0 for MIO[52].
12600 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1
12602 # Each bit applies to a single IO. Bit 0 for MIO[52].
12603 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1
12605 # Each bit applies to a single IO. Bit 0 for MIO[52].
12606 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1
12608 # Each bit applies to a single IO. Bit 0 for MIO[52].
12609 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1
12611 # Each bit applies to a single IO. Bit 0 for MIO[52].
12612 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1
12614 # Each bit applies to a single IO. Bit 0 for MIO[52].
12615 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1
12617 # Each bit applies to a single IO. Bit 0 for MIO[52].
12618 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1
12620 # Each bit applies to a single IO. Bit 0 for MIO[52].
12621 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1
12623 # Each bit applies to a single IO. Bit 0 for MIO[52].
12624 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1
12626 # Each bit applies to a single IO. Bit 0 for MIO[52].
12627 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1
12629 # Each bit applies to a single IO. Bit 0 for MIO[52].
12630 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1
12632 # Each bit applies to a single IO. Bit 0 for MIO[52].
12633 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1
12635 # Each bit applies to a single IO. Bit 0 for MIO[52].
12636 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1
12638 # Each bit applies to a single IO. Bit 0 for MIO[52].
12639 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1
12641 # Each bit applies to a single IO. Bit 0 for MIO[52].
12642 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1
12644 # Each bit applies to a single IO. Bit 0 for MIO[52].
12645 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1
12647 # Each bit applies to a single IO. Bit 0 for MIO[52].
12648 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1
12650 # Each bit applies to a single IO. Bit 0 for MIO[52].
12651 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1
12653 # Each bit applies to a single IO. Bit 0 for MIO[52].
12654 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1
12656 # Each bit applies to a single IO. Bit 0 for MIO[52].
12657 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1
12659 # Each bit applies to a single IO. Bit 0 for MIO[52].
12660 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1
12662 # Each bit applies to a single IO. Bit 0 for MIO[52].
12663 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1
12665 # Each bit applies to a single IO. Bit 0 for MIO[52].
12666 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1
12668 # Each bit applies to a single IO. Bit 0 for MIO[52].
12669 # PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1
12671 # Drive0 control to MIO Bank 2 - control MIO[77:52]
12672 #(OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) */
12673 mask_write 0XFF180170 0x03FFFFFF 0x03FFFFFF
12674 # Register : bank2_ctrl1 @ 0XFF180174</p>
12676 # Each bit applies to a single IO. Bit 0 for MIO[52].
12677 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1
12679 # Each bit applies to a single IO. Bit 0 for MIO[52].
12680 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1
12682 # Each bit applies to a single IO. Bit 0 for MIO[52].
12683 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1
12685 # Each bit applies to a single IO. Bit 0 for MIO[52].
12686 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1
12688 # Each bit applies to a single IO. Bit 0 for MIO[52].
12689 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1
12691 # Each bit applies to a single IO. Bit 0 for MIO[52].
12692 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1
12694 # Each bit applies to a single IO. Bit 0 for MIO[52].
12695 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1
12697 # Each bit applies to a single IO. Bit 0 for MIO[52].
12698 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1
12700 # Each bit applies to a single IO. Bit 0 for MIO[52].
12701 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1
12703 # Each bit applies to a single IO. Bit 0 for MIO[52].
12704 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1
12706 # Each bit applies to a single IO. Bit 0 for MIO[52].
12707 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1
12709 # Each bit applies to a single IO. Bit 0 for MIO[52].
12710 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1
12712 # Each bit applies to a single IO. Bit 0 for MIO[52].
12713 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1
12715 # Each bit applies to a single IO. Bit 0 for MIO[52].
12716 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1
12718 # Each bit applies to a single IO. Bit 0 for MIO[52].
12719 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1
12721 # Each bit applies to a single IO. Bit 0 for MIO[52].
12722 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1
12724 # Each bit applies to a single IO. Bit 0 for MIO[52].
12725 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1
12727 # Each bit applies to a single IO. Bit 0 for MIO[52].
12728 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1
12730 # Each bit applies to a single IO. Bit 0 for MIO[52].
12731 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1
12733 # Each bit applies to a single IO. Bit 0 for MIO[52].
12734 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1
12736 # Each bit applies to a single IO. Bit 0 for MIO[52].
12737 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1
12739 # Each bit applies to a single IO. Bit 0 for MIO[52].
12740 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1
12742 # Each bit applies to a single IO. Bit 0 for MIO[52].
12743 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1
12745 # Each bit applies to a single IO. Bit 0 for MIO[52].
12746 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1
12748 # Each bit applies to a single IO. Bit 0 for MIO[52].
12749 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1
12751 # Each bit applies to a single IO. Bit 0 for MIO[52].
12752 # PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1
12754 # Drive1 control to MIO Bank 2 - control MIO[77:52]
12755 #(OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) */
12756 mask_write 0XFF180174 0x03FFFFFF 0x03FFFFFF
12757 # Register : bank2_ctrl3 @ 0XFF180178</p>
12759 # Each bit applies to a single IO. Bit 0 for MIO[52].
12760 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0
12762 # Each bit applies to a single IO. Bit 0 for MIO[52].
12763 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0
12765 # Each bit applies to a single IO. Bit 0 for MIO[52].
12766 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0
12768 # Each bit applies to a single IO. Bit 0 for MIO[52].
12769 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0
12771 # Each bit applies to a single IO. Bit 0 for MIO[52].
12772 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0
12774 # Each bit applies to a single IO. Bit 0 for MIO[52].
12775 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0
12777 # Each bit applies to a single IO. Bit 0 for MIO[52].
12778 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0
12780 # Each bit applies to a single IO. Bit 0 for MIO[52].
12781 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0
12783 # Each bit applies to a single IO. Bit 0 for MIO[52].
12784 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0
12786 # Each bit applies to a single IO. Bit 0 for MIO[52].
12787 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0
12789 # Each bit applies to a single IO. Bit 0 for MIO[52].
12790 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0
12792 # Each bit applies to a single IO. Bit 0 for MIO[52].
12793 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0
12795 # Each bit applies to a single IO. Bit 0 for MIO[52].
12796 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0
12798 # Each bit applies to a single IO. Bit 0 for MIO[52].
12799 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0
12801 # Each bit applies to a single IO. Bit 0 for MIO[52].
12802 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0
12804 # Each bit applies to a single IO. Bit 0 for MIO[52].
12805 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0
12807 # Each bit applies to a single IO. Bit 0 for MIO[52].
12808 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0
12810 # Each bit applies to a single IO. Bit 0 for MIO[52].
12811 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0
12813 # Each bit applies to a single IO. Bit 0 for MIO[52].
12814 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0
12816 # Each bit applies to a single IO. Bit 0 for MIO[52].
12817 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0
12819 # Each bit applies to a single IO. Bit 0 for MIO[52].
12820 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0
12822 # Each bit applies to a single IO. Bit 0 for MIO[52].
12823 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0
12825 # Each bit applies to a single IO. Bit 0 for MIO[52].
12826 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0
12828 # Each bit applies to a single IO. Bit 0 for MIO[52].
12829 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0
12831 # Each bit applies to a single IO. Bit 0 for MIO[52].
12832 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0
12834 # Each bit applies to a single IO. Bit 0 for MIO[52].
12835 # PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0
12837 # Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
12838 #(OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) */
12839 mask_write 0XFF180178 0x03FFFFFF 0x00000000
12840 # Register : bank2_ctrl4 @ 0XFF18017C</p>
12842 # Each bit applies to a single IO. Bit 0 for MIO[52].
12843 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1
12845 # Each bit applies to a single IO. Bit 0 for MIO[52].
12846 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1
12848 # Each bit applies to a single IO. Bit 0 for MIO[52].
12849 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1
12851 # Each bit applies to a single IO. Bit 0 for MIO[52].
12852 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1
12854 # Each bit applies to a single IO. Bit 0 for MIO[52].
12855 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1
12857 # Each bit applies to a single IO. Bit 0 for MIO[52].
12858 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1
12860 # Each bit applies to a single IO. Bit 0 for MIO[52].
12861 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1
12863 # Each bit applies to a single IO. Bit 0 for MIO[52].
12864 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1
12866 # Each bit applies to a single IO. Bit 0 for MIO[52].
12867 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1
12869 # Each bit applies to a single IO. Bit 0 for MIO[52].
12870 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1
12872 # Each bit applies to a single IO. Bit 0 for MIO[52].
12873 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1
12875 # Each bit applies to a single IO. Bit 0 for MIO[52].
12876 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1
12878 # Each bit applies to a single IO. Bit 0 for MIO[52].
12879 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1
12881 # Each bit applies to a single IO. Bit 0 for MIO[52].
12882 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1
12884 # Each bit applies to a single IO. Bit 0 for MIO[52].
12885 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1
12887 # Each bit applies to a single IO. Bit 0 for MIO[52].
12888 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1
12890 # Each bit applies to a single IO. Bit 0 for MIO[52].
12891 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1
12893 # Each bit applies to a single IO. Bit 0 for MIO[52].
12894 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1
12896 # Each bit applies to a single IO. Bit 0 for MIO[52].
12897 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1
12899 # Each bit applies to a single IO. Bit 0 for MIO[52].
12900 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1
12902 # Each bit applies to a single IO. Bit 0 for MIO[52].
12903 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1
12905 # Each bit applies to a single IO. Bit 0 for MIO[52].
12906 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1
12908 # Each bit applies to a single IO. Bit 0 for MIO[52].
12909 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1
12911 # Each bit applies to a single IO. Bit 0 for MIO[52].
12912 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1
12914 # Each bit applies to a single IO. Bit 0 for MIO[52].
12915 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1
12917 # Each bit applies to a single IO. Bit 0 for MIO[52].
12918 # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1
12920 # When mio_bank2_pull_enable is set, this selects pull up or pull down for
12921 # MIO Bank 2 - control MIO[77:52]
12922 #(OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) */
12923 mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF
12924 # Register : bank2_ctrl5 @ 0XFF180180</p>
12926 # Each bit applies to a single IO. Bit 0 for MIO[52].
12927 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1
12929 # Each bit applies to a single IO. Bit 0 for MIO[52].
12930 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1
12932 # Each bit applies to a single IO. Bit 0 for MIO[52].
12933 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1
12935 # Each bit applies to a single IO. Bit 0 for MIO[52].
12936 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1
12938 # Each bit applies to a single IO. Bit 0 for MIO[52].
12939 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1
12941 # Each bit applies to a single IO. Bit 0 for MIO[52].
12942 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1
12944 # Each bit applies to a single IO. Bit 0 for MIO[52].
12945 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1
12947 # Each bit applies to a single IO. Bit 0 for MIO[52].
12948 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1
12950 # Each bit applies to a single IO. Bit 0 for MIO[52].
12951 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1
12953 # Each bit applies to a single IO. Bit 0 for MIO[52].
12954 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1
12956 # Each bit applies to a single IO. Bit 0 for MIO[52].
12957 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1
12959 # Each bit applies to a single IO. Bit 0 for MIO[52].
12960 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1
12962 # Each bit applies to a single IO. Bit 0 for MIO[52].
12963 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1
12965 # Each bit applies to a single IO. Bit 0 for MIO[52].
12966 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1
12968 # Each bit applies to a single IO. Bit 0 for MIO[52].
12969 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1
12971 # Each bit applies to a single IO. Bit 0 for MIO[52].
12972 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1
12974 # Each bit applies to a single IO. Bit 0 for MIO[52].
12975 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1
12977 # Each bit applies to a single IO. Bit 0 for MIO[52].
12978 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1
12980 # Each bit applies to a single IO. Bit 0 for MIO[52].
12981 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1
12983 # Each bit applies to a single IO. Bit 0 for MIO[52].
12984 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1
12986 # Each bit applies to a single IO. Bit 0 for MIO[52].
12987 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1
12989 # Each bit applies to a single IO. Bit 0 for MIO[52].
12990 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1
12992 # Each bit applies to a single IO. Bit 0 for MIO[52].
12993 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1
12995 # Each bit applies to a single IO. Bit 0 for MIO[52].
12996 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1
12998 # Each bit applies to a single IO. Bit 0 for MIO[52].
12999 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1
13001 # Each bit applies to a single IO. Bit 0 for MIO[52].
13002 # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1
13004 # When set, this enables mio_bank2_pullupdown to selects pull up or pull d
13005 # own for MIO Bank 2 - control MIO[77:52]
13006 #(OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) */
13007 mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF
13008 # Register : bank2_ctrl6 @ 0XFF180184</p>
13010 # Each bit applies to a single IO. Bit 0 for MIO[52].
13011 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0
13013 # Each bit applies to a single IO. Bit 0 for MIO[52].
13014 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0
13016 # Each bit applies to a single IO. Bit 0 for MIO[52].
13017 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0
13019 # Each bit applies to a single IO. Bit 0 for MIO[52].
13020 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0
13022 # Each bit applies to a single IO. Bit 0 for MIO[52].
13023 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0
13025 # Each bit applies to a single IO. Bit 0 for MIO[52].
13026 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0
13028 # Each bit applies to a single IO. Bit 0 for MIO[52].
13029 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0
13031 # Each bit applies to a single IO. Bit 0 for MIO[52].
13032 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0
13034 # Each bit applies to a single IO. Bit 0 for MIO[52].
13035 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0
13037 # Each bit applies to a single IO. Bit 0 for MIO[52].
13038 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0
13040 # Each bit applies to a single IO. Bit 0 for MIO[52].
13041 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0
13043 # Each bit applies to a single IO. Bit 0 for MIO[52].
13044 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0
13046 # Each bit applies to a single IO. Bit 0 for MIO[52].
13047 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0
13049 # Each bit applies to a single IO. Bit 0 for MIO[52].
13050 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0
13052 # Each bit applies to a single IO. Bit 0 for MIO[52].
13053 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0
13055 # Each bit applies to a single IO. Bit 0 for MIO[52].
13056 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0
13058 # Each bit applies to a single IO. Bit 0 for MIO[52].
13059 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0
13061 # Each bit applies to a single IO. Bit 0 for MIO[52].
13062 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0
13064 # Each bit applies to a single IO. Bit 0 for MIO[52].
13065 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0
13067 # Each bit applies to a single IO. Bit 0 for MIO[52].
13068 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0
13070 # Each bit applies to a single IO. Bit 0 for MIO[52].
13071 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0
13073 # Each bit applies to a single IO. Bit 0 for MIO[52].
13074 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0
13076 # Each bit applies to a single IO. Bit 0 for MIO[52].
13077 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0
13079 # Each bit applies to a single IO. Bit 0 for MIO[52].
13080 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0
13082 # Each bit applies to a single IO. Bit 0 for MIO[52].
13083 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0
13085 # Each bit applies to a single IO. Bit 0 for MIO[52].
13086 # PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0
13088 # Slew rate control to MIO Bank 2 - control MIO[77:52]
13089 #(OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) */
13090 mask_write 0XFF180184 0x03FFFFFF 0x00000000
13092 # Register : MIO_LOOPBACK @ 0XFF180200</p>
13094 # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1
13095 # = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
13097 # PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0
13099 # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
13100 # = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
13101 # PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0
13103 # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping.
13104 # 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0
13105 # inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
13107 # PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0
13109 # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1
13110 # = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
13111 # . The other SPI core will appear on the LS Slave Select.
13112 # PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0
13114 # Loopback function within MIO
13115 #(OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) */
13116 mask_write 0XFF180200 0x0000000F 0x00000000
13119 set psu_peripherals_init_data {
13122 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
13124 # PCIE config reset
13125 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0
13127 # PCIE control block level reset
13128 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0
13130 # PCIE bridge block level reset (AXI interface)
13131 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0
13133 # Display Port block level reset (includes DPDMA)
13134 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0
13137 # PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0
13139 # GDMA block level reset
13140 # PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0
13142 # Pixel Processor (submodule of GPU) block level reset
13143 # PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0
13145 # Pixel Processor (submodule of GPU) block level reset
13146 # PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0
13148 # GPU block level reset
13149 # PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0
13151 # GT block level reset
13152 # PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0
13154 # Sata block level reset
13155 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0
13157 # FPD Block level software controlled reset
13158 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) */
13159 mask_write 0XFD1A0100 0x000F807E 0x00000000
13162 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13164 # Block level reset
13165 # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0
13167 # Block level reset
13168 # PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0
13170 # Block level reset
13171 # PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0
13173 # Software control register for the IOU block. Each bit will cause a singl
13174 # erperipheral or part of the peripheral to be reset.
13175 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) */
13176 mask_write 0XFF5E0238 0x001A0000 0x00000000
13177 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
13179 # Reset entire full power domain.
13180 # PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0
13183 # PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0
13186 # PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0
13188 # Real Time Clock reset
13189 # PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0
13192 # PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0
13195 # PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0
13197 # reset entire RPU power island
13198 # PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0
13201 # PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0
13203 # Software control register for the LPD block.
13204 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) */
13205 mask_write 0XFF5E023C 0x0093C018 0x00000000
13207 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
13210 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0
13212 # Software controlled reset for the GEMs
13213 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */
13214 mask_write 0XFF5E0230 0x00000008 0x00000000
13216 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13218 # Block level reset
13219 # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0
13221 # Software control register for the IOU block. Each bit will cause a singl
13222 # erperipheral or part of the peripheral to be reset.
13223 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */
13224 mask_write 0XFF5E0238 0x00000001 0x00000000
13226 # Register : IOU_TAPDLY_BYPASS @ 0XFF180390</p>
13228 # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
13229 # ss the Tap delay on the Rx clock signal of LQSPI
13230 # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1
13232 # IOU tap delay bypass for the LQSPI and NAND controllers
13233 #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */
13234 mask_write 0XFF180390 0x00000004 0x00000004
13237 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
13239 # USB 0 reset for control registers
13240 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0
13242 # USB 0 sleep circuit reset
13243 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0
13246 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0
13248 # Software control register for the LPD block.
13249 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */
13250 mask_write 0XFF5E023C 0x00000540 0x00000000
13251 # : USB0 PIPE POWER PRESENT
13252 # Register : fpd_power_prsnt @ 0XFF9D0080</p>
13254 # This bit is used to choose between PIPE power present and 1'b1
13255 # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1
13258 #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */
13259 mask_write 0XFF9D0080 0x00000001 0x00000001
13260 # Register : fpd_pipe_clk @ 0XFF9D007C</p>
13262 # This bit is used to choose between PIPE clock coming from SerDes and the
13264 # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0
13267 #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */
13268 mask_write 0XFF9D007C 0x00000001 0x00000000
13270 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13272 # Block level reset
13273 # PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0
13275 # Software control register for the IOU block. Each bit will cause a singl
13276 # erperipheral or part of the peripheral to be reset.
13277 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) */
13278 mask_write 0XFF5E0238 0x00000040 0x00000000
13279 # Register : CTRL_REG_SD @ 0XFF180310</p>
13281 # SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
13282 # PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0
13284 # SD eMMC selection
13285 #(OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) */
13286 mask_write 0XFF180310 0x00008000 0x00000000
13287 # Register : SD_CONFIG_REG2 @ 0XFF180320</p>
13289 # Should be set based on the final product usage 00 - Removable SCard Slot
13290 # 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
13291 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0
13293 # 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
13294 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1
13296 # 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
13297 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0
13299 # 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
13300 # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1
13302 # SD Config Register 2
13303 #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) */
13304 mask_write 0XFF180320 0x33800000 0x02800000
13306 # Register : SD_CONFIG_REG1 @ 0XFF18031C</p>
13308 # Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
13309 # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8
13311 # Configures the Number of Taps (Phases) of the rxclk_in that is supported
13313 # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28
13315 # SD Config Register 1
13316 #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) */
13317 mask_write 0XFF18031C 0x7FFE0000 0x64500000
13318 # Register : SD_DLL_CTRL @ 0XFF180358</p>
13321 # PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1
13323 # SDIO status register
13324 #(OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) */
13325 mask_write 0XFF180358 0x00000008 0x00000008
13327 # Register : SD_CONFIG_REG3 @ 0XFF180324</p>
13329 # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S
13330 # etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other
13331 # source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
13332 # = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
13333 # PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0
13335 # SD Config Register 3
13336 #(OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) */
13337 mask_write 0XFF180324 0x03C00000 0x00000000
13339 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13341 # Block level reset
13342 # PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0
13344 # Software control register for the IOU block. Each bit will cause a singl
13345 # erperipheral or part of the peripheral to be reset.
13346 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) */
13347 mask_write 0XFF5E0238 0x00000100 0x00000000
13349 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13351 # Block level reset
13352 # PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0
13354 # Block level reset
13355 # PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0
13357 # Software control register for the IOU block. Each bit will cause a singl
13358 # erperipheral or part of the peripheral to be reset.
13359 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) */
13360 mask_write 0XFF5E0238 0x00000600 0x00000000
13362 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13364 # Block level reset
13365 # PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0
13367 # Software control register for the IOU block. Each bit will cause a singl
13368 # erperipheral or part of the peripheral to be reset.
13369 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) */
13370 mask_write 0XFF5E0238 0x00008000 0x00000000
13373 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13375 # Block level reset
13376 # PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0
13378 # Block level reset
13379 # PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0
13381 # Block level reset
13382 # PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0
13384 # Block level reset
13385 # PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0
13387 # Software control register for the IOU block. Each bit will cause a singl
13388 # erperipheral or part of the peripheral to be reset.
13389 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) */
13390 mask_write 0XFF5E0238 0x00007800 0x00000000
13392 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13394 # Block level reset
13395 # PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0
13397 # Block level reset
13398 # PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0
13400 # Software control register for the IOU block. Each bit will cause a singl
13401 # erperipheral or part of the peripheral to be reset.
13402 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) */
13403 mask_write 0XFF5E0238 0x00000006 0x00000000
13405 # Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
13407 # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
13408 # PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
13410 # Baud Rate Divider Register
13411 #(OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) */
13412 mask_write 0XFF000034 0x000000FF 0x00000005
13413 # Register : Baud_rate_gen_reg0 @ 0XFF000018</p>
13415 # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
13416 # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
13417 # PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f
13419 # Baud Rate Generator Register.
13420 #(OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) */
13421 mask_write 0XFF000018 0x0000FFFF 0x0000008F
13422 # Register : Control_reg0 @ 0XFF000000</p>
13424 # Stop transmitter break: 0: no affect 1: stop transmission of the break a
13425 # fter a minimum of one character length and transmit a high level during
13426 # 12 bit periods. It can be set regardless of the value of STTBRK.
13427 # PSU_UART0_CONTROL_REG0_STPBRK 0x0
13429 # Start transmitter break: 0: no affect 1: start to transmit a break after
13430 # the characters currently present in the FIFO and the transmit shift reg
13431 # ister have been transmitted. It can only be set if STPBRK (Stop transmit
13432 # ter break) is not high.
13433 # PSU_UART0_CONTROL_REG0_STTBRK 0x0
13435 # Restart receiver timeout counter: 1: receiver timeout counter is restart
13436 # ed. This bit is self clearing once the restart has completed.
13437 # PSU_UART0_CONTROL_REG0_RSTTO 0x0
13439 # Transmit disable: 0: enable transmitter 1: disable transmitter
13440 # PSU_UART0_CONTROL_REG0_TXDIS 0x0
13442 # Transmit enable: 0: disable transmitter 1: enable transmitter, provided
13443 # the TXDIS field is set to 0.
13444 # PSU_UART0_CONTROL_REG0_TXEN 0x1
13446 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN
13447 # PSU_UART0_CONTROL_REG0_RXDIS 0x0
13449 # Receive enable: 0: disable 1: enable When set to one, the receiver logic
13450 # is enabled, provided the RXDIS field is set to zero.
13451 # PSU_UART0_CONTROL_REG0_RXEN 0x1
13453 # Software reset for Tx data path: 0: no affect 1: transmitter logic is re
13454 # set and all pending transmitter data is discarded This bit is self clear
13455 # ing once the reset has completed.
13456 # PSU_UART0_CONTROL_REG0_TXRES 0x1
13458 # Software reset for Rx data path: 0: no affect 1: receiver logic is reset
13459 # and all pending receiver data is discarded. This bit is self clearing o
13460 # nce the reset has completed.
13461 # PSU_UART0_CONTROL_REG0_RXRES 0x1
13463 # UART Control Register
13464 #(OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) */
13465 mask_write 0XFF000000 0x000001FF 0x00000017
13466 # Register : mode_reg0 @ 0XFF000004</p>
13468 # Channel mode: Defines the mode of operation of the UART. 00: normal 01:
13469 # automatic echo 10: local loopback 11: remote loopback
13470 # PSU_UART0_MODE_REG0_CHMODE 0x0
13472 # Number of stop bits: Defines the number of stop bits to detect on receiv
13473 # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
13474 # op bits 11: reserved
13475 # PSU_UART0_MODE_REG0_NBSTOP 0x0
13477 # Parity type select: Defines the expected parity to check on receive and
13478 # the parity to generate on transmit. 000: even parity 001: odd parity 010
13479 # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
13481 # PSU_UART0_MODE_REG0_PAR 0x4
13483 # Character length select: Defines the number of bits in each character. 1
13484 # 1: 6 bits 10: 7 bits 0x: 8 bits
13485 # PSU_UART0_MODE_REG0_CHRL 0x0
13487 # Clock source select: This field defines whether a pre-scalar of 8 is app
13488 # lied to the baud rate generator input clock. 0: clock source is uart_ref
13489 # _clk 1: clock source is uart_ref_clk/8
13490 # PSU_UART0_MODE_REG0_CLKS 0x0
13492 # UART Mode Register
13493 #(OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) */
13494 mask_write 0XFF000004 0x000003FF 0x00000020
13495 # Register : Baud_rate_divider_reg0 @ 0XFF010034</p>
13497 # Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
13498 # PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5
13500 # Baud Rate Divider Register
13501 #(OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) */
13502 mask_write 0XFF010034 0x000000FF 0x00000005
13503 # Register : Baud_rate_gen_reg0 @ 0XFF010018</p>
13505 # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
13506 # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
13507 # PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f
13509 # Baud Rate Generator Register.
13510 #(OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) */
13511 mask_write 0XFF010018 0x0000FFFF 0x0000008F
13512 # Register : Control_reg0 @ 0XFF010000</p>
13514 # Stop transmitter break: 0: no affect 1: stop transmission of the break a
13515 # fter a minimum of one character length and transmit a high level during
13516 # 12 bit periods. It can be set regardless of the value of STTBRK.
13517 # PSU_UART1_CONTROL_REG0_STPBRK 0x0
13519 # Start transmitter break: 0: no affect 1: start to transmit a break after
13520 # the characters currently present in the FIFO and the transmit shift reg
13521 # ister have been transmitted. It can only be set if STPBRK (Stop transmit
13522 # ter break) is not high.
13523 # PSU_UART1_CONTROL_REG0_STTBRK 0x0
13525 # Restart receiver timeout counter: 1: receiver timeout counter is restart
13526 # ed. This bit is self clearing once the restart has completed.
13527 # PSU_UART1_CONTROL_REG0_RSTTO 0x0
13529 # Transmit disable: 0: enable transmitter 1: disable transmitter
13530 # PSU_UART1_CONTROL_REG0_TXDIS 0x0
13532 # Transmit enable: 0: disable transmitter 1: enable transmitter, provided
13533 # the TXDIS field is set to 0.
13534 # PSU_UART1_CONTROL_REG0_TXEN 0x1
13536 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN
13537 # PSU_UART1_CONTROL_REG0_RXDIS 0x0
13539 # Receive enable: 0: disable 1: enable When set to one, the receiver logic
13540 # is enabled, provided the RXDIS field is set to zero.
13541 # PSU_UART1_CONTROL_REG0_RXEN 0x1
13543 # Software reset for Tx data path: 0: no affect 1: transmitter logic is re
13544 # set and all pending transmitter data is discarded This bit is self clear
13545 # ing once the reset has completed.
13546 # PSU_UART1_CONTROL_REG0_TXRES 0x1
13548 # Software reset for Rx data path: 0: no affect 1: receiver logic is reset
13549 # and all pending receiver data is discarded. This bit is self clearing o
13550 # nce the reset has completed.
13551 # PSU_UART1_CONTROL_REG0_RXRES 0x1
13553 # UART Control Register
13554 #(OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) */
13555 mask_write 0XFF010000 0x000001FF 0x00000017
13556 # Register : mode_reg0 @ 0XFF010004</p>
13558 # Channel mode: Defines the mode of operation of the UART. 00: normal 01:
13559 # automatic echo 10: local loopback 11: remote loopback
13560 # PSU_UART1_MODE_REG0_CHMODE 0x0
13562 # Number of stop bits: Defines the number of stop bits to detect on receiv
13563 # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
13564 # op bits 11: reserved
13565 # PSU_UART1_MODE_REG0_NBSTOP 0x0
13567 # Parity type select: Defines the expected parity to check on receive and
13568 # the parity to generate on transmit. 000: even parity 001: odd parity 010
13569 # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
13571 # PSU_UART1_MODE_REG0_PAR 0x4
13573 # Character length select: Defines the number of bits in each character. 1
13574 # 1: 6 bits 10: 7 bits 0x: 8 bits
13575 # PSU_UART1_MODE_REG0_CHRL 0x0
13577 # Clock source select: This field defines whether a pre-scalar of 8 is app
13578 # lied to the baud rate generator input clock. 0: clock source is uart_ref
13579 # _clk 1: clock source is uart_ref_clk/8
13580 # PSU_UART1_MODE_REG0_CLKS 0x0
13582 # UART Mode Register
13583 #(OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) */
13584 mask_write 0XFF010004 0x000003FF 0x00000020
13586 # Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
13588 # Block level reset
13589 # PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0
13591 # Software control register for the IOU block. Each bit will cause a singl
13592 # erperipheral or part of the peripheral to be reset.
13593 #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) */
13594 mask_write 0XFF5E0238 0x00040000 0x00000000
13596 # Register : slcr_adma @ 0XFF4B0024</p>
13598 # TrustZone Classification for ADMA
13599 # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF
13601 # RPU TrustZone settings
13602 #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */
13603 mask_write 0XFF4B0024 0x000000FF 0x000000FF
13605 # : CSU TAMPER STATUS
13606 # Register : tamper_status @ 0XFFCA5000</p>
13609 # PSU_CSU_TAMPER_STATUS_TAMPER_0 0
13612 # PSU_CSU_TAMPER_STATUS_TAMPER_1 0
13614 # JTAG toggle detect
13615 # PSU_CSU_TAMPER_STATUS_TAMPER_2 0
13618 # PSU_CSU_TAMPER_STATUS_TAMPER_3 0
13620 # AMS over temperature alarm for LPD
13621 # PSU_CSU_TAMPER_STATUS_TAMPER_4 0
13623 # AMS over temperature alarm for APU
13624 # PSU_CSU_TAMPER_STATUS_TAMPER_5 0
13626 # AMS voltage alarm for VCCPINT_FPD
13627 # PSU_CSU_TAMPER_STATUS_TAMPER_6 0
13629 # AMS voltage alarm for VCCPINT_LPD
13630 # PSU_CSU_TAMPER_STATUS_TAMPER_7 0
13632 # AMS voltage alarm for VCCPAUX
13633 # PSU_CSU_TAMPER_STATUS_TAMPER_8 0
13635 # AMS voltage alarm for DDRPHY
13636 # PSU_CSU_TAMPER_STATUS_TAMPER_9 0
13638 # AMS voltage alarm for PSIO bank 0/1/2
13639 # PSU_CSU_TAMPER_STATUS_TAMPER_10 0
13641 # AMS voltage alarm for PSIO bank 3 (dedicated pins)
13642 # PSU_CSU_TAMPER_STATUS_TAMPER_11 0
13644 # AMS voltaage alarm for GT
13645 # PSU_CSU_TAMPER_STATUS_TAMPER_12 0
13647 # Tamper Response Status
13648 #(OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) */
13649 mask_write 0XFFCA5000 0x00001FFF 0x00000000
13650 # : CSU TAMPER RESPONSE
13651 # : CPU QOS DEFAULT
13652 # Register : ACE_CTRL @ 0XFD5C0060</p>
13654 # Set ACE outgoing AWQOS value
13655 # PSU_APU_ACE_CTRL_AWQOS 0X0
13657 # Set ACE outgoing ARQOS value
13658 # PSU_APU_ACE_CTRL_ARQOS 0X0
13660 # ACE Control Register
13661 #(OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) */
13662 mask_write 0XFD5C0060 0x000F000F 0x00000000
13663 # : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
13664 # Register : CONTROL @ 0XFFA60040</p>
13666 # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and
13667 # the only module that potentially draws current from the battery will be
13668 # BBRAM. The value read through this bit does not necessarily reflect whe
13669 # ther RTC is enabled or not. It is expected that RTC is enabled every tim
13670 # e it is being configured. If RTC is not used in the design, FSBL will di
13671 # sable it by writing a 0 to this bit.
13672 # PSU_RTC_CONTROL_BATTERY_DISABLE 0X1
13674 # This register controls various functionalities within the RTC
13675 #(OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) */
13676 mask_write 0XFFA60040 0x80000000 0x80000000
13677 # : TIMESTAMP COUNTER
13678 # Register : base_frequency_ID_register @ 0XFF260020</p>
13680 # Frequency in number of ticks per second. Valid range from 10 MHz to 100
13682 # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0
13684 # Program this register to match the clock frequency of the timestamp gene
13685 # rator, in ticks per second. For example, for a 50 MHz clock, program 0x0
13686 # 2FAF080. This register is not accessible to the read-only programming in
13688 #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) */
13689 mask_write 0XFF260020 0xFFFFFFFF 0x05F5B9F0
13690 # Register : counter_control_register @ 0XFF260000</p>
13692 # Enable 0: The counter is disabled and not incrementing. 1: The counter i
13693 # s enabled and is incrementing.
13694 # PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1
13696 # Controls the counter increments. This register is not accessible to the
13697 # read-only programming interface.
13698 #(OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) */
13699 mask_write 0XFF260000 0x00000001 0x00000001
13701 # : PCIE GPIO RESET
13703 # : DIR MODE BANK 0
13704 # : DIR MODE BANK 1
13705 # Register : DIRM_1 @ 0XFF0A0244</p>
13707 # Operation is the same as DIRM_0[DIRECTION_0]
13708 # PSU_GPIO_DIRM_1_DIRECTION_1 0x20
13710 # Direction mode (GPIO Bank1, MIO)
13711 #(OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) */
13712 mask_write 0XFF0A0244 0x03FFFFFF 0x00000020
13713 # : DIR MODE BANK 2
13714 # : OUTPUT ENABLE BANK 0
13715 # : OUTPUT ENABLE BANK 1
13716 # Register : OEN_1 @ 0XFF0A0248</p>
13718 # Operation is the same as OEN_0[OP_ENABLE_0]
13719 # PSU_GPIO_OEN_1_OP_ENABLE_1 0x20
13721 # Output enable (GPIO Bank1, MIO)
13722 #(OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) */
13723 mask_write 0XFF0A0248 0x03FFFFFF 0x00000020
13724 # : OUTPUT ENABLE BANK 2
13725 # : MASK_DATA_0_LSW LOW BANK [15:0]
13726 # : MASK_DATA_0_MSW LOW BANK [25:16]
13727 # : MASK_DATA_1_LSW LOW BANK [41:26]
13728 # Register : MASK_DATA_1_LSW @ 0XFF0A0008</p>
13730 # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
13731 # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
13733 # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
13734 # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
13736 # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
13737 #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */
13738 mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020
13739 # : MASK_DATA_1_MSW HIGH BANK [51:42]
13740 # : MASK_DATA_1_LSW HIGH BANK [67:52]
13741 # : MASK_DATA_1_LSW HIGH BANK [77:68]
13743 mask_delay 0x00000000 1
13744 # : MASK_DATA_0_LSW LOW BANK [15:0]
13745 # : MASK_DATA_0_MSW LOW BANK [25:16]
13746 # : MASK_DATA_1_LSW LOW BANK [41:26]
13747 # Register : MASK_DATA_1_LSW @ 0XFF0A0008</p>
13749 # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
13750 # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
13752 # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
13753 # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0
13755 # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
13756 #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) */
13757 mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0000
13758 # : MASK_DATA_1_MSW HIGH BANK [51:42]
13759 # : MASK_DATA_1_LSW HIGH BANK [67:52]
13760 # : MASK_DATA_1_LSW HIGH BANK [77:68]
13762 mask_delay 0x00000000 5
13765 set psu_post_config_data {
13769 set psu_peripherals_powerdwn_data {
13770 # : POWER DOWN REQUEST INTERRUPT ENABLE
13771 # : POWER DOWN TRIGGER
13774 set psu_lpd_xppu_data {
13776 # : APERTURE PERMISIION LIST
13777 # : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF
13778 # : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF
13779 # : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF
13780 # : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF
13781 # : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF
13782 # : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF
13783 # : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF
13784 # : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF
13785 # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
13786 # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF
13787 # : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF
13788 # : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF
13789 # : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF
13790 # : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF
13791 # : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF
13792 # : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF
13793 # : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF
13794 # : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF
13795 # : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF
13796 # : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF
13797 # : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF
13798 # : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF
13799 # : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF
13800 # : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF
13801 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13802 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13803 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13804 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13805 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13806 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13807 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13808 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13809 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13810 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13811 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13812 # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF
13813 # : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF
13814 # : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF
13815 # : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF
13816 # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
13817 # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
13818 # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
13819 # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF
13820 # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
13821 # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
13822 # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
13823 # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
13824 # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF
13825 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
13826 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
13827 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
13828 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
13829 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
13830 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
13831 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
13832 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
13833 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13834 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13835 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13836 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13837 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13838 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13839 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13840 # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF
13841 # : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF
13842 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13843 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13844 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13845 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13846 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13847 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13848 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13849 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13850 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13851 # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF
13852 # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
13853 # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
13854 # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF
13855 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13856 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13857 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13858 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13859 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13860 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13861 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13862 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13863 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13864 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13865 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13866 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13867 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13868 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13869 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13870 # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF
13871 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13872 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13873 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13874 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13875 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13876 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13877 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13878 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13879 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13880 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13881 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13882 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13883 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13884 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13885 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13886 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13887 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13888 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13889 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13890 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13891 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13892 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13893 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13894 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13895 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13896 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13897 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13898 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13899 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13900 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13901 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13902 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13903 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13904 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13905 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13906 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13907 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13908 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13909 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13910 # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF
13911 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13912 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13913 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13914 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13915 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13916 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13917 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13918 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13919 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13920 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13921 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13922 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13923 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13924 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13925 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13926 # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF
13927 # : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF
13928 # : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF
13929 # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
13930 # : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF
13931 # : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF
13932 # : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF
13933 # : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF
13934 # : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF
13935 # : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF
13936 # : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF
13937 # : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF
13938 # : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF
13939 # : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF
13940 # : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF
13941 # : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF
13942 # : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF
13943 # : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF
13944 # : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF
13945 # : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF
13946 # : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF
13947 # : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF
13948 # : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF
13949 # : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF
13950 # : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF
13951 # : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF
13952 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13953 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13954 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13955 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13956 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13957 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13958 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13959 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13960 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13961 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13962 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13963 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13964 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13965 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13966 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13967 # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF
13968 # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
13969 # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF
13970 # : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF
13971 # : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF
13972 # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
13973 # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF
13974 # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
13975 # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF
13976 # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
13977 # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF
13978 # : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF
13979 # : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF
13980 # : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF
13981 # : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF
13982 # : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF
13983 # : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF
13984 # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
13985 # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
13986 # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
13987 # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF
13988 # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
13989 # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF
13990 # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
13991 # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF
13992 # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
13993 # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
13994 # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
13995 # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF
13996 # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
13997 # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
13998 # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
13999 # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF
14000 # : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF
14001 # : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF
14002 # : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF
14003 # : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF
14004 # : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF
14005 # : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF
14006 # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
14007 # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
14008 # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF
14009 # : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF
14010 # : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF
14011 # : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF
14012 # : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF
14013 # : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF
14014 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14015 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14016 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14017 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14018 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14019 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14020 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14021 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14022 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14023 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14024 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14025 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14026 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14027 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14028 # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF
14029 # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
14030 # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
14031 # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF
14032 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14033 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14034 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14035 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14036 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14037 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14038 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14039 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14040 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14041 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14042 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14043 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14044 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14045 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14046 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14047 # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF
14048 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14049 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14050 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14051 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14052 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14053 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14054 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14055 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14056 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14057 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14058 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14059 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14060 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14061 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14062 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14063 # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF
14064 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14065 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14066 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14067 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14068 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14069 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14070 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14071 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14072 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14073 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14074 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14075 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14076 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14077 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14078 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14079 # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF
14080 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14081 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14082 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14083 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14084 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14085 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14086 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14087 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14088 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14089 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14090 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14091 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14092 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14093 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14094 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14095 # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF
14096 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14097 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14098 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14099 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14100 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14101 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14102 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14103 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14104 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14105 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14106 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14107 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14108 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14109 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14110 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14111 # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF
14112 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14113 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14114 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14115 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14116 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14117 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14118 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14119 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14120 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14121 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14122 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14123 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14124 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14125 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14126 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14127 # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF
14128 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14129 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14130 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14131 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14132 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14133 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14134 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14135 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14136 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14137 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14138 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14139 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14140 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14141 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14142 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14143 # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF
14144 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14145 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14146 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14147 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14148 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14149 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14150 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14151 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14152 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14153 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14154 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14155 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14156 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14157 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14158 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14159 # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF
14160 # : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF
14161 # : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF
14162 # : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF
14163 # : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF
14164 # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
14165 # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
14166 # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
14167 # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF
14168 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14169 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14170 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14171 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14172 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14173 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14174 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14175 # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF
14176 # : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF
14180 set psu_ddr_xmpu0_data {
14184 set psu_ddr_xmpu1_data {
14188 set psu_ddr_xmpu2_data {
14192 set psu_ddr_xmpu3_data {
14196 set psu_ddr_xmpu4_data {
14200 set psu_ddr_xmpu5_data {
14204 set psu_ocm_xmpu_data {
14208 set psu_fpd_xmpu_data {
14212 set psu_protection_lock_data {
14213 # : LOCKING PROTECTION MODULE
14215 # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF
14217 # : LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14218 # : LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14219 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14220 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14221 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14222 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14223 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14224 # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER
14227 set psu_apply_master_tz {
14230 # Register : slcr_dpdma @ 0XFD690040</p>
14232 # TrustZone classification for DisplayPort DMA
14233 # PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1
14235 # DPDMA TrustZone Settings
14236 #(OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) */
14237 mask_write 0XFD690040 0x00000001 0x00000001
14240 # Register : slcr_pcie @ 0XFD690030</p>
14242 # TrustZone classification for DMA Channel 0
14243 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1
14245 # TrustZone classification for DMA Channel 1
14246 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1
14248 # TrustZone classification for DMA Channel 2
14249 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1
14251 # TrustZone classification for DMA Channel 3
14252 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1
14254 # TrustZone classification for Ingress Address Translation 0
14255 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1
14257 # TrustZone classification for Ingress Address Translation 1
14258 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1
14260 # TrustZone classification for Ingress Address Translation 2
14261 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1
14263 # TrustZone classification for Ingress Address Translation 3
14264 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1
14266 # TrustZone classification for Ingress Address Translation 4
14267 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1
14269 # TrustZone classification for Ingress Address Translation 5
14270 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1
14272 # TrustZone classification for Ingress Address Translation 6
14273 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1
14275 # TrustZone classification for Ingress Address Translation 7
14276 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1
14278 # TrustZone classification for Egress Address Translation 0
14279 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1
14281 # TrustZone classification for Egress Address Translation 1
14282 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1
14284 # TrustZone classification for Egress Address Translation 2
14285 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1
14287 # TrustZone classification for Egress Address Translation 3
14288 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1
14290 # TrustZone classification for Egress Address Translation 4
14291 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1
14293 # TrustZone classification for Egress Address Translation 5
14294 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1
14296 # TrustZone classification for Egress Address Translation 6
14297 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1
14299 # TrustZone classification for Egress Address Translation 7
14300 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1
14302 # TrustZone classification for DMA Registers
14303 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1
14305 # TrustZone classification for MSIx Table
14306 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1
14308 # TrustZone classification for MSIx PBA
14309 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1
14311 # TrustZone classification for ECAM
14312 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1
14314 # TrustZone classification for Bridge Common Registers
14315 # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1
14317 # PCIe TrustZone settings. This register may only be modified during bootu
14318 # p (while PCIe block is disabled)
14319 #(OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) */
14320 mask_write 0XFD690030 0x01FFFFFF 0x01FFFFFF
14322 # Register : slcr_usb @ 0XFF4B0034</p>
14324 # TrustZone Classification for USB3_0
14325 # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1
14327 # TrustZone Classification for USB3_1
14328 # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1
14330 # USB3 TrustZone settings
14331 #(OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) */
14332 mask_write 0XFF4B0034 0x00000003 0x00000003
14334 # Register : IOU_AXI_RPRTCN @ 0XFF240004</p>
14336 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14337 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14338 # ccess [2] = '1'' : Instruction access
14339 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2
14341 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14342 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14343 # ccess [2] = '1'' : Instruction access
14344 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2
14346 # AXI read protection type selection
14347 #(OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) */
14348 mask_write 0XFF240004 0x003F0000 0x00120000
14349 # Register : IOU_AXI_WPRTCN @ 0XFF240000</p>
14351 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14352 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14353 # ccess [2] = '1'' : Instruction access
14354 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2
14356 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14357 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14358 # ccess [2] = '1'' : Instruction access
14359 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2
14361 # AXI write protection type selection
14362 #(OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) */
14363 mask_write 0XFF240000 0x003F0000 0x00120000
14365 # Register : IOU_AXI_RPRTCN @ 0XFF240004</p>
14367 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14368 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14369 # ccess [2] = '1'' : Instruction access
14370 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2
14372 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14373 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14374 # ccess [2] = '1'' : Instruction access
14375 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2
14377 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14378 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14379 # ccess [2] = '1'' : Instruction access
14380 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2
14382 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14383 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14384 # ccess [2] = '1'' : Instruction access
14385 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2
14387 # AXI read protection type selection
14388 #(OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) */
14389 mask_write 0XFF240004 0x00000FFF 0x00000492
14390 # Register : IOU_AXI_WPRTCN @ 0XFF240000</p>
14392 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14393 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14394 # ccess [2] = '1'' : Instruction access
14395 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2
14397 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14398 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14399 # ccess [2] = '1'' : Instruction access
14400 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2
14402 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14403 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14404 # ccess [2] = '1'' : Instruction access
14405 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2
14407 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14408 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14409 # ccess [2] = '1'' : Instruction access
14410 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2
14412 # AXI write protection type selection
14413 #(OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) */
14414 mask_write 0XFF240000 0x00000FFF 0x00000492
14416 # Register : IOU_AXI_WPRTCN @ 0XFF240000</p>
14418 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14419 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14420 # ccess [2] = '1'' : Instruction access
14421 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2
14423 # AXI write protection type selection
14424 #(OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) */
14425 mask_write 0XFF240000 0x0E000000 0x04000000
14427 # Register : IOU_AXI_RPRTCN @ 0XFF240004</p>
14429 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14430 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14431 # ccess [2] = '1'' : Instruction access
14432 # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2
14434 # AXI read protection type selection
14435 #(OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) */
14436 mask_write 0XFF240004 0x01C00000 0x00800000
14437 # Register : IOU_AXI_WPRTCN @ 0XFF240000</p>
14439 # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
14440 # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
14441 # ccess [2] = '1'' : Instruction access
14442 # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2
14444 # AXI write protection type selection
14445 #(OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) */
14446 mask_write 0XFF240000 0x01C00000 0x00800000
14448 # Register : slcr_adma @ 0XFF4B0024</p>
14450 # TrustZone Classification for ADMA
14451 # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF
14453 # RPU TrustZone settings
14454 #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */
14455 mask_write 0XFF4B0024 0x000000FF 0x000000FF
14456 # Register : slcr_gdma @ 0XFD690050</p>
14458 # TrustZone Classification for GDMA
14459 # PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF
14461 # GDMA Trustzone Settings
14462 #(OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) */
14463 mask_write 0XFD690050 0x000000FF 0x000000FF
14466 set psu_serdes_init_data {
14467 # : SERDES INITIALIZATION
14468 # : GT REFERENCE CLOCK SOURCE SELECTION
14469 # Register : PLL_REF_SEL0 @ 0XFD410000</p>
14471 # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
14472 # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
14473 # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
14474 # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
14476 # PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD
14478 # PLL0 Reference Selection Register
14479 #(OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) */
14480 mask_write 0XFD410000 0x0000001F 0x0000000D
14481 # Register : PLL_REF_SEL1 @ 0XFD410004</p>
14483 # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
14484 # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
14485 # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
14486 # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
14488 # PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9
14490 # PLL1 Reference Selection Register
14491 #(OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) */
14492 mask_write 0XFD410004 0x0000001F 0x00000009
14493 # Register : PLL_REF_SEL2 @ 0XFD410008</p>
14495 # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
14496 # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
14497 # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
14498 # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
14500 # PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8
14502 # PLL2 Reference Selection Register
14503 #(OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) */
14504 mask_write 0XFD410008 0x0000001F 0x00000008
14505 # Register : PLL_REF_SEL3 @ 0XFD41000C</p>
14507 # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
14508 # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
14509 # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
14510 # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
14512 # PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF
14514 # PLL3 Reference Selection Register
14515 #(OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) */
14516 mask_write 0XFD41000C 0x0000001F 0x0000000F
14517 # : GT REFERENCE CLOCK FREQUENCY SELECTION
14518 # Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
14520 # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
14521 # ut. Set to 0 to select lane0 ref clock mux output.
14522 # PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1
14524 # Lane0 Ref Clock Selection Register
14525 #(OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) */
14526 mask_write 0XFD402860 0x00000080 0x00000080
14527 # Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
14529 # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
14530 # ut. Set to 0 to select lane1 ref clock mux output.
14531 # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0
14533 # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
14534 # cer output from ref clock network
14535 # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1
14537 # Lane1 Ref Clock Selection Register
14538 #(OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) */
14539 mask_write 0XFD402864 0x00000088 0x00000008
14540 # Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
14542 # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
14543 # ut. Set to 0 to select lane2 ref clock mux output.
14544 # PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1
14546 # Lane2 Ref Clock Selection Register
14547 #(OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) */
14548 mask_write 0XFD402868 0x00000080 0x00000080
14549 # Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
14551 # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
14552 # ut. Set to 0 to select lane3 ref clock mux output.
14553 # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0
14555 # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
14556 # cer output from ref clock network
14557 # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1
14559 # Lane3 Ref Clock Selection Register
14560 #(OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) */
14561 mask_write 0XFD40286C 0x00000082 0x00000002
14562 # : ENABLE SPREAD SPECTRUM
14563 # Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
14565 # Enable/Disable coarse code satureation limiting logic
14566 # PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1
14568 # Test mode register 37
14569 #(OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) */
14570 mask_write 0XFD40A094 0x00000010 0x00000010
14571 # Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
14573 # Spread Spectrum No of Steps [7:0]
14574 # PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38
14576 # Spread Spectrum No of Steps bits 7:0
14577 #(OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) */
14578 mask_write 0XFD40A368 0x000000FF 0x00000038
14579 # Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
14581 # Spread Spectrum No of Steps [10:8]
14582 # PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03
14584 # Spread Spectrum No of Steps bits 10:8
14585 #(OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) */
14586 mask_write 0XFD40A36C 0x00000007 0x00000003
14587 # Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
14589 # Spread Spectrum No of Steps [7:0]
14590 # PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0
14592 # Spread Spectrum No of Steps bits 7:0
14593 #(OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) */
14594 mask_write 0XFD40E368 0x000000FF 0x000000E0
14595 # Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
14597 # Spread Spectrum No of Steps [10:8]
14598 # PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
14600 # Spread Spectrum No of Steps bits 10:8
14601 #(OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) */
14602 mask_write 0XFD40E36C 0x00000007 0x00000003
14603 # Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
14605 # Spread Spectrum No of Steps [7:0]
14606 # PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58
14608 # Spread Spectrum No of Steps bits 7:0
14609 #(OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) */
14610 mask_write 0XFD406368 0x000000FF 0x00000058
14611 # Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
14613 # Spread Spectrum No of Steps [10:8]
14614 # PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3
14616 # Spread Spectrum No of Steps bits 10:8
14617 #(OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) */
14618 mask_write 0XFD40636C 0x00000007 0x00000003
14619 # Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
14621 # Step Size for Spread Spectrum [7:0]
14622 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C
14624 # Step Size for Spread Spectrum LSB
14625 #(OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) */
14626 mask_write 0XFD406370 0x000000FF 0x0000007C
14627 # Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
14629 # Step Size for Spread Spectrum [15:8]
14630 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33
14632 # Step Size for Spread Spectrum 1
14633 #(OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) */
14634 mask_write 0XFD406374 0x000000FF 0x00000033
14635 # Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
14637 # Step Size for Spread Spectrum [23:16]
14638 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
14640 # Step Size for Spread Spectrum 2
14641 #(OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) */
14642 mask_write 0XFD406378 0x000000FF 0x00000002
14643 # Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
14645 # Step Size for Spread Spectrum [25:24]
14646 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
14648 # Enable/Disable test mode force on SS step size
14649 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
14651 # Enable/Disable test mode force on SS no of steps
14652 # PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
14654 # Enable force on enable Spread Spectrum
14655 #(OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) */
14656 mask_write 0XFD40637C 0x00000033 0x00000030
14657 # Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
14659 # Step Size for Spread Spectrum [7:0]
14660 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4
14662 # Step Size for Spread Spectrum LSB
14663 #(OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) */
14664 mask_write 0XFD40A370 0x000000FF 0x000000F4
14665 # Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
14667 # Step Size for Spread Spectrum [15:8]
14668 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31
14670 # Step Size for Spread Spectrum 1
14671 #(OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) */
14672 mask_write 0XFD40A374 0x000000FF 0x00000031
14673 # Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
14675 # Step Size for Spread Spectrum [23:16]
14676 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2
14678 # Step Size for Spread Spectrum 2
14679 #(OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) */
14680 mask_write 0XFD40A378 0x000000FF 0x00000002
14681 # Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
14683 # Step Size for Spread Spectrum [25:24]
14684 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
14686 # Enable/Disable test mode force on SS step size
14687 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
14689 # Enable/Disable test mode force on SS no of steps
14690 # PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
14692 # Enable force on enable Spread Spectrum
14693 #(OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) */
14694 mask_write 0XFD40A37C 0x00000033 0x00000030
14695 # Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
14697 # Step Size for Spread Spectrum [7:0]
14698 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9
14700 # Step Size for Spread Spectrum LSB
14701 #(OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) */
14702 mask_write 0XFD40E370 0x000000FF 0x000000C9
14703 # Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
14705 # Step Size for Spread Spectrum [15:8]
14706 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2
14708 # Step Size for Spread Spectrum 1
14709 #(OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) */
14710 mask_write 0XFD40E374 0x000000FF 0x000000D2
14711 # Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
14713 # Step Size for Spread Spectrum [23:16]
14714 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1
14716 # Step Size for Spread Spectrum 2
14717 #(OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) */
14718 mask_write 0XFD40E378 0x000000FF 0x00000001
14719 # Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
14721 # Step Size for Spread Spectrum [25:24]
14722 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0
14724 # Enable/Disable test mode force on SS step size
14725 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1
14727 # Enable/Disable test mode force on SS no of steps
14728 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1
14730 # Enable test mode forcing on enable Spread Spectrum
14731 # PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1
14733 # Enable force on enable Spread Spectrum
14734 #(OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) */
14735 mask_write 0XFD40E37C 0x000000B3 0x000000B0
14736 # Register : L2_TM_DIG_6 @ 0XFD40906C</p>
14738 # Bypass Descrambler
14739 # PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1
14741 # Enable Bypass for <1> TM_DIG_CTRL_6
14742 # PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
14744 # Data path test modes in decoder and descram
14745 #(OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) */
14746 mask_write 0XFD40906C 0x00000003 0x00000003
14747 # Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
14749 # Bypass scrambler signal
14750 # PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1
14752 # Enable/disable scrambler bypass signal
14753 # PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
14755 # MPHY PLL Gear and bypass scrambler
14756 #(OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) */
14757 mask_write 0XFD4080F4 0x00000003 0x00000003
14758 # Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
14760 # Enable test mode force on fractional mode enable
14761 # PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1
14763 # Fractional feedback division control and fractional value for feedback d
14764 # ivision bits 26:24
14765 #(OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) */
14766 mask_write 0XFD40E360 0x00000040 0x00000040
14767 # Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
14769 # Bypass 8b10b decoder
14770 # PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1
14772 # Enable Bypass for <3> TM_DIG_CTRL_6
14773 # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1
14775 # Bypass Descrambler
14776 # PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1
14778 # Enable Bypass for <1> TM_DIG_CTRL_6
14779 # PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1
14781 # Data path test modes in decoder and descram
14782 #(OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) */
14783 mask_write 0XFD40D06C 0x0000000F 0x0000000F
14784 # Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
14786 # Enable/disable encoder bypass signal
14787 # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1
14789 # Bypass scrambler signal
14790 # PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1
14792 # Enable/disable scrambler bypass signal
14793 # PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1
14795 # MPHY PLL Gear and bypass scrambler
14796 #(OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) */
14797 mask_write 0XFD40C0F4 0x0000000B 0x0000000B
14798 # : ENABLE CHICKEN BIT FOR PCIE AND USB
14799 # Register : L0_TM_AUX_0 @ 0XFD4010CC</p>
14802 # PSU_SERDES_L0_TM_AUX_0_BIT_2 1
14805 #(OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) */
14806 mask_write 0XFD4010CC 0x00000020 0x00000020
14807 # Register : L2_TM_AUX_0 @ 0XFD4090CC</p>
14810 # PSU_SERDES_L2_TM_AUX_0_BIT_2 1
14813 #(OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) */
14814 mask_write 0XFD4090CC 0x00000020 0x00000020
14815 # : ENABLING EYE SURF
14816 # Register : L0_TM_DIG_8 @ 0XFD401074</p>
14819 # PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1
14821 # Test modes for Elastic buffer and enabling Eye Surf
14822 #(OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) */
14823 mask_write 0XFD401074 0x00000010 0x00000010
14824 # Register : L1_TM_DIG_8 @ 0XFD405074</p>
14827 # PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1
14829 # Test modes for Elastic buffer and enabling Eye Surf
14830 #(OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) */
14831 mask_write 0XFD405074 0x00000010 0x00000010
14832 # Register : L2_TM_DIG_8 @ 0XFD409074</p>
14835 # PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1
14837 # Test modes for Elastic buffer and enabling Eye Surf
14838 #(OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) */
14839 mask_write 0XFD409074 0x00000010 0x00000010
14840 # Register : L3_TM_DIG_8 @ 0XFD40D074</p>
14843 # PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1
14845 # Test modes for Elastic buffer and enabling Eye Surf
14846 #(OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) */
14847 mask_write 0XFD40D074 0x00000010 0x00000010
14848 # : ILL SETTINGS FOR GAIN AND LOCK SETTINGS
14849 # Register : L0_TM_MISC2 @ 0XFD40189C</p>
14851 # ILL calib counts BYPASSED with calcode bits
14852 # PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
14855 #(OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) */
14856 mask_write 0XFD40189C 0x00000080 0x00000080
14857 # Register : L0_TM_IQ_ILL1 @ 0XFD4018F8</p>
14859 # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
14861 # PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64
14864 #(OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) */
14865 mask_write 0XFD4018F8 0x000000FF 0x00000064
14866 # Register : L0_TM_IQ_ILL2 @ 0XFD4018FC</p>
14868 # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
14869 # PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64
14872 #(OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) */
14873 mask_write 0XFD4018FC 0x000000FF 0x00000064
14874 # Register : L0_TM_ILL12 @ 0XFD401990</p>
14876 # G1A pll ctr bypass value
14877 # PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11
14879 # ill pll counter values
14880 #(OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) */
14881 mask_write 0XFD401990 0x000000FF 0x00000011
14882 # Register : L0_TM_E_ILL1 @ 0XFD401924</p>
14884 # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
14886 # PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4
14889 #(OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) */
14890 mask_write 0XFD401924 0x000000FF 0x00000004
14891 # Register : L0_TM_E_ILL2 @ 0XFD401928</p>
14893 # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
14894 # PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE
14897 #(OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) */
14898 mask_write 0XFD401928 0x000000FF 0x000000FE
14899 # Register : L0_TM_IQ_ILL3 @ 0XFD401900</p>
14901 # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
14902 # PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64
14905 #(OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) */
14906 mask_write 0XFD401900 0x000000FF 0x00000064
14907 # Register : L0_TM_E_ILL3 @ 0XFD40192C</p>
14909 # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
14910 # PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
14913 #(OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) */
14914 mask_write 0XFD40192C 0x000000FF 0x00000000
14915 # Register : L0_TM_ILL8 @ 0XFD401980</p>
14917 # ILL calibration code change wait time
14918 # PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
14920 # ILL cal routine control
14921 #(OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) */
14922 mask_write 0XFD401980 0x000000FF 0x000000FF
14923 # Register : L0_TM_IQ_ILL8 @ 0XFD401914</p>
14925 # IQ ILL polytrim bypass value
14926 # PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
14929 #(OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) */
14930 mask_write 0XFD401914 0x000000FF 0x000000F7
14931 # Register : L0_TM_IQ_ILL9 @ 0XFD401918</p>
14933 # bypass IQ polytrim
14934 # PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
14936 # enables for lf,constant gm trim and polytirm
14937 #(OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) */
14938 mask_write 0XFD401918 0x00000001 0x00000001
14939 # Register : L0_TM_E_ILL8 @ 0XFD401940</p>
14941 # E ILL polytrim bypass value
14942 # PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
14945 #(OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) */
14946 mask_write 0XFD401940 0x000000FF 0x000000F7
14947 # Register : L0_TM_E_ILL9 @ 0XFD401944</p>
14949 # bypass E polytrim
14950 # PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
14952 # enables for lf,constant gm trim and polytirm
14953 #(OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) */
14954 mask_write 0XFD401944 0x00000001 0x00000001
14955 # Register : L0_TM_ILL13 @ 0XFD401994</p>
14957 # ILL cal idle val refcnt
14958 # PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
14960 # ill cal idle value count
14961 #(OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) */
14962 mask_write 0XFD401994 0x00000007 0x00000007
14963 # Register : L1_TM_ILL13 @ 0XFD405994</p>
14965 # ILL cal idle val refcnt
14966 # PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
14968 # ill cal idle value count
14969 #(OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) */
14970 mask_write 0XFD405994 0x00000007 0x00000007
14971 # Register : L2_TM_MISC2 @ 0XFD40989C</p>
14973 # ILL calib counts BYPASSED with calcode bits
14974 # PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
14977 #(OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) */
14978 mask_write 0XFD40989C 0x00000080 0x00000080
14979 # Register : L2_TM_IQ_ILL1 @ 0XFD4098F8</p>
14981 # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
14983 # PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A
14986 #(OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) */
14987 mask_write 0XFD4098F8 0x000000FF 0x0000001A
14988 # Register : L2_TM_IQ_ILL2 @ 0XFD4098FC</p>
14990 # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
14991 # PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A
14994 #(OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) */
14995 mask_write 0XFD4098FC 0x000000FF 0x0000001A
14996 # Register : L2_TM_ILL12 @ 0XFD409990</p>
14998 # G1A pll ctr bypass value
14999 # PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10
15001 # ill pll counter values
15002 #(OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) */
15003 mask_write 0XFD409990 0x000000FF 0x00000010
15004 # Register : L2_TM_E_ILL1 @ 0XFD409924</p>
15006 # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
15008 # PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE
15011 #(OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) */
15012 mask_write 0XFD409924 0x000000FF 0x000000FE
15013 # Register : L2_TM_E_ILL2 @ 0XFD409928</p>
15015 # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
15016 # PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0
15019 #(OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) */
15020 mask_write 0XFD409928 0x000000FF 0x00000000
15021 # Register : L2_TM_IQ_ILL3 @ 0XFD409900</p>
15023 # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
15024 # PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A
15027 #(OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) */
15028 mask_write 0XFD409900 0x000000FF 0x0000001A
15029 # Register : L2_TM_E_ILL3 @ 0XFD40992C</p>
15031 # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
15032 # PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0
15035 #(OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) */
15036 mask_write 0XFD40992C 0x000000FF 0x00000000
15037 # Register : L2_TM_ILL8 @ 0XFD409980</p>
15039 # ILL calibration code change wait time
15040 # PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
15042 # ILL cal routine control
15043 #(OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) */
15044 mask_write 0XFD409980 0x000000FF 0x000000FF
15045 # Register : L2_TM_IQ_ILL8 @ 0XFD409914</p>
15047 # IQ ILL polytrim bypass value
15048 # PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
15051 #(OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) */
15052 mask_write 0XFD409914 0x000000FF 0x000000F7
15053 # Register : L2_TM_IQ_ILL9 @ 0XFD409918</p>
15055 # bypass IQ polytrim
15056 # PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
15058 # enables for lf,constant gm trim and polytirm
15059 #(OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) */
15060 mask_write 0XFD409918 0x00000001 0x00000001
15061 # Register : L2_TM_E_ILL8 @ 0XFD409940</p>
15063 # E ILL polytrim bypass value
15064 # PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
15067 #(OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) */
15068 mask_write 0XFD409940 0x000000FF 0x000000F7
15069 # Register : L2_TM_E_ILL9 @ 0XFD409944</p>
15071 # bypass E polytrim
15072 # PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
15074 # enables for lf,constant gm trim and polytirm
15075 #(OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) */
15076 mask_write 0XFD409944 0x00000001 0x00000001
15077 # Register : L2_TM_ILL13 @ 0XFD409994</p>
15079 # ILL cal idle val refcnt
15080 # PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
15082 # ill cal idle value count
15083 #(OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) */
15084 mask_write 0XFD409994 0x00000007 0x00000007
15085 # Register : L3_TM_MISC2 @ 0XFD40D89C</p>
15087 # ILL calib counts BYPASSED with calcode bits
15088 # PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1
15091 #(OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) */
15092 mask_write 0XFD40D89C 0x00000080 0x00000080
15093 # Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8</p>
15095 # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
15097 # PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D
15100 #(OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) */
15101 mask_write 0XFD40D8F8 0x000000FF 0x0000007D
15102 # Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC</p>
15104 # IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
15105 # PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D
15108 #(OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) */
15109 mask_write 0XFD40D8FC 0x000000FF 0x0000007D
15110 # Register : L3_TM_ILL12 @ 0XFD40D990</p>
15112 # G1A pll ctr bypass value
15113 # PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1
15115 # ill pll counter values
15116 #(OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) */
15117 mask_write 0XFD40D990 0x000000FF 0x00000001
15118 # Register : L3_TM_E_ILL1 @ 0XFD40D924</p>
15120 # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
15122 # PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C
15125 #(OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) */
15126 mask_write 0XFD40D924 0x000000FF 0x0000009C
15127 # Register : L3_TM_E_ILL2 @ 0XFD40D928</p>
15129 # E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
15130 # PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39
15133 #(OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) */
15134 mask_write 0XFD40D928 0x000000FF 0x00000039
15135 # Register : L3_TM_ILL11 @ 0XFD40D98C</p>
15137 # G2A_PCIe1 PLL ctr bypass value
15138 # PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2
15140 # ill pll counter values
15141 #(OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) */
15142 mask_write 0XFD40D98C 0x000000F0 0x00000020
15143 # Register : L3_TM_IQ_ILL3 @ 0XFD40D900</p>
15145 # IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
15146 # PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D
15149 #(OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) */
15150 mask_write 0XFD40D900 0x000000FF 0x0000007D
15151 # Register : L3_TM_E_ILL3 @ 0XFD40D92C</p>
15153 # E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
15154 # PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64
15157 #(OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) */
15158 mask_write 0XFD40D92C 0x000000FF 0x00000064
15159 # Register : L3_TM_ILL8 @ 0XFD40D980</p>
15161 # ILL calibration code change wait time
15162 # PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF
15164 # ILL cal routine control
15165 #(OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) */
15166 mask_write 0XFD40D980 0x000000FF 0x000000FF
15167 # Register : L3_TM_IQ_ILL8 @ 0XFD40D914</p>
15169 # IQ ILL polytrim bypass value
15170 # PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7
15173 #(OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) */
15174 mask_write 0XFD40D914 0x000000FF 0x000000F7
15175 # Register : L3_TM_IQ_ILL9 @ 0XFD40D918</p>
15177 # bypass IQ polytrim
15178 # PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1
15180 # enables for lf,constant gm trim and polytirm
15181 #(OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) */
15182 mask_write 0XFD40D918 0x00000001 0x00000001
15183 # Register : L3_TM_E_ILL8 @ 0XFD40D940</p>
15185 # E ILL polytrim bypass value
15186 # PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7
15189 #(OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) */
15190 mask_write 0XFD40D940 0x000000FF 0x000000F7
15191 # Register : L3_TM_E_ILL9 @ 0XFD40D944</p>
15193 # bypass E polytrim
15194 # PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1
15196 # enables for lf,constant gm trim and polytirm
15197 #(OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) */
15198 mask_write 0XFD40D944 0x00000001 0x00000001
15199 # Register : L3_TM_ILL13 @ 0XFD40D994</p>
15201 # ILL cal idle val refcnt
15202 # PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7
15204 # ill cal idle value count
15205 #(OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) */
15206 mask_write 0XFD40D994 0x00000007 0x00000007
15207 # : SYMBOL LOCK AND WAIT
15208 # Register : L0_TM_DIG_10 @ 0XFD40107C</p>
15210 # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
15211 # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
15213 # test control for changing cdr lock wait time
15214 #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) */
15215 mask_write 0XFD40107C 0x0000000F 0x00000001
15216 # Register : L1_TM_DIG_10 @ 0XFD40507C</p>
15218 # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
15219 # PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
15221 # test control for changing cdr lock wait time
15222 #(OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) */
15223 mask_write 0XFD40507C 0x0000000F 0x00000001
15224 # Register : L2_TM_DIG_10 @ 0XFD40907C</p>
15226 # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
15227 # PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
15229 # test control for changing cdr lock wait time
15230 #(OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) */
15231 mask_write 0XFD40907C 0x0000000F 0x00000001
15232 # Register : L3_TM_DIG_10 @ 0XFD40D07C</p>
15234 # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
15235 # PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1
15237 # test control for changing cdr lock wait time
15238 #(OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) */
15239 mask_write 0XFD40D07C 0x0000000F 0x00000001
15240 # : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG
15241 # Register : L0_TM_RST_DLY @ 0XFD4019A4</p>
15243 # Delay apb reset by specified amount
15244 # PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF
15246 # reset delay for apb reset w.r.t pso of hsrx
15247 #(OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) */
15248 mask_write 0XFD4019A4 0x000000FF 0x000000FF
15249 # Register : L0_TM_ANA_BYP_15 @ 0XFD401038</p>
15251 # Enable Bypass for <7> of TM_ANA_BYPS_15
15252 # PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
15254 # Bypass control for pcs-pma interface. EQ supplies, main master supply an
15255 # d ps for samp c2c
15256 #(OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) */
15257 mask_write 0XFD401038 0x00000040 0x00000040
15258 # Register : L0_TM_ANA_BYP_12 @ 0XFD40102C</p>
15260 # Enable Bypass for <7> of TM_ANA_BYPS_12
15261 # PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
15263 # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
15265 #(OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) */
15266 mask_write 0XFD40102C 0x00000040 0x00000040
15267 # Register : L1_TM_RST_DLY @ 0XFD4059A4</p>
15269 # Delay apb reset by specified amount
15270 # PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF
15272 # reset delay for apb reset w.r.t pso of hsrx
15273 #(OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) */
15274 mask_write 0XFD4059A4 0x000000FF 0x000000FF
15275 # Register : L1_TM_ANA_BYP_15 @ 0XFD405038</p>
15277 # Enable Bypass for <7> of TM_ANA_BYPS_15
15278 # PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
15280 # Bypass control for pcs-pma interface. EQ supplies, main master supply an
15281 # d ps for samp c2c
15282 #(OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) */
15283 mask_write 0XFD405038 0x00000040 0x00000040
15284 # Register : L1_TM_ANA_BYP_12 @ 0XFD40502C</p>
15286 # Enable Bypass for <7> of TM_ANA_BYPS_12
15287 # PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
15289 # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
15291 #(OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) */
15292 mask_write 0XFD40502C 0x00000040 0x00000040
15293 # Register : L2_TM_RST_DLY @ 0XFD4099A4</p>
15295 # Delay apb reset by specified amount
15296 # PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF
15298 # reset delay for apb reset w.r.t pso of hsrx
15299 #(OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) */
15300 mask_write 0XFD4099A4 0x000000FF 0x000000FF
15301 # Register : L2_TM_ANA_BYP_15 @ 0XFD409038</p>
15303 # Enable Bypass for <7> of TM_ANA_BYPS_15
15304 # PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
15306 # Bypass control for pcs-pma interface. EQ supplies, main master supply an
15307 # d ps for samp c2c
15308 #(OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) */
15309 mask_write 0XFD409038 0x00000040 0x00000040
15310 # Register : L2_TM_ANA_BYP_12 @ 0XFD40902C</p>
15312 # Enable Bypass for <7> of TM_ANA_BYPS_12
15313 # PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
15315 # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
15317 #(OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) */
15318 mask_write 0XFD40902C 0x00000040 0x00000040
15319 # Register : L3_TM_RST_DLY @ 0XFD40D9A4</p>
15321 # Delay apb reset by specified amount
15322 # PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF
15324 # reset delay for apb reset w.r.t pso of hsrx
15325 #(OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) */
15326 mask_write 0XFD40D9A4 0x000000FF 0x000000FF
15327 # Register : L3_TM_ANA_BYP_15 @ 0XFD40D038</p>
15329 # Enable Bypass for <7> of TM_ANA_BYPS_15
15330 # PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1
15332 # Bypass control for pcs-pma interface. EQ supplies, main master supply an
15333 # d ps for samp c2c
15334 #(OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) */
15335 mask_write 0XFD40D038 0x00000040 0x00000040
15336 # Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C</p>
15338 # Enable Bypass for <7> of TM_ANA_BYPS_12
15339 # PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1
15341 # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena
15343 #(OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) */
15344 mask_write 0XFD40D02C 0x00000040 0x00000040
15345 # : DISABLE FPL/FFL
15346 # Register : L0_TM_MISC3 @ 0XFD4019AC</p>
15348 # CDR fast phase lock control
15349 # PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0
15351 # CDR fast frequency lock control
15352 # PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0
15354 # debug bus selection bit, cdr fast phase and freq controls
15355 #(OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) */
15356 mask_write 0XFD4019AC 0x00000003 0x00000000
15357 # Register : L1_TM_MISC3 @ 0XFD4059AC</p>
15359 # CDR fast phase lock control
15360 # PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0
15362 # CDR fast frequency lock control
15363 # PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0
15365 # debug bus selection bit, cdr fast phase and freq controls
15366 #(OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) */
15367 mask_write 0XFD4059AC 0x00000003 0x00000000
15368 # Register : L2_TM_MISC3 @ 0XFD4099AC</p>
15370 # CDR fast phase lock control
15371 # PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0
15373 # CDR fast frequency lock control
15374 # PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0
15376 # debug bus selection bit, cdr fast phase and freq controls
15377 #(OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) */
15378 mask_write 0XFD4099AC 0x00000003 0x00000000
15379 # Register : L3_TM_MISC3 @ 0XFD40D9AC</p>
15381 # CDR fast phase lock control
15382 # PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0
15384 # CDR fast frequency lock control
15385 # PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0
15387 # debug bus selection bit, cdr fast phase and freq controls
15388 #(OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) */
15389 mask_write 0XFD40D9AC 0x00000003 0x00000000
15390 # : DISABLE DYNAMIC OFFSET CALIBRATION
15391 # Register : L0_TM_EQ11 @ 0XFD401978</p>
15393 # Force EQ offset correction algo off if not forced on
15394 # PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
15396 # eq dynamic offset correction
15397 #(OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) */
15398 mask_write 0XFD401978 0x00000010 0x00000010
15399 # Register : L1_TM_EQ11 @ 0XFD405978</p>
15401 # Force EQ offset correction algo off if not forced on
15402 # PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
15404 # eq dynamic offset correction
15405 #(OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) */
15406 mask_write 0XFD405978 0x00000010 0x00000010
15407 # Register : L2_TM_EQ11 @ 0XFD409978</p>
15409 # Force EQ offset correction algo off if not forced on
15410 # PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
15412 # eq dynamic offset correction
15413 #(OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) */
15414 mask_write 0XFD409978 0x00000010 0x00000010
15415 # Register : L3_TM_EQ11 @ 0XFD40D978</p>
15417 # Force EQ offset correction algo off if not forced on
15418 # PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1
15420 # eq dynamic offset correction
15421 #(OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) */
15422 mask_write 0XFD40D978 0x00000010 0x00000010
15423 # : DISABLE ECO FOR PCIE
15424 # Register : eco_0 @ 0XFD3D001C</p>
15427 # PSU_SIOU_ECO_0_FIELD 0x1
15429 # ECO Register for future use
15430 #(OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) */
15431 mask_write 0XFD3D001C 0xFFFFFFFF 0x00000001
15432 # : GT LANE SETTINGS
15433 # Register : ICM_CFG0 @ 0XFD410010</p>
15435 # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
15436 # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
15437 # PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1
15439 # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
15440 # 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
15441 # PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4
15443 # ICM Configuration Register 0
15444 #(OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) */
15445 mask_write 0XFD410010 0x00000077 0x00000041
15446 # Register : ICM_CFG1 @ 0XFD410014</p>
15448 # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
15449 # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
15450 # PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3
15452 # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
15453 # 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
15454 # PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2
15456 # ICM Configuration Register 1
15457 #(OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) */
15458 mask_write 0XFD410014 0x00000077 0x00000023
15459 # : CHECKING PLL LOCK
15460 # : ENABLE SERIAL DATA MUX DEEMPH
15461 # Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
15463 # Enable/disable DP post2 path
15464 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1
15466 # Override enable/disable of DP post2 path
15467 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1
15469 # Override enable/disable of DP post1 path
15470 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1
15472 # Enable/disable DP main path
15473 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1
15475 # Override enable/disable of DP main path
15476 # PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1
15478 # Post or pre or main DP path selection
15479 #(OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) */
15480 mask_write 0XFD404CB4 0x00000037 0x00000037
15481 # Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
15483 # Test register force for enabling/disablign TX deemphasis bits <17:0>
15484 # PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
15486 # Enable Override of TX deemphasis
15487 #(OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) */
15488 mask_write 0XFD4041D8 0x00000001 0x00000001
15489 # Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8</p>
15491 # Test register force for enabling/disablign TX deemphasis bits <17:0>
15492 # PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1
15494 # Enable Override of TX deemphasis
15495 #(OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) */
15496 mask_write 0XFD40C1D8 0x00000001 0x00000001
15497 # : CDR AND RX EQUALIZATION SETTINGS
15498 # Register : L3_TM_CDR5 @ 0XFD40DC14</p>
15500 # FPHL FSM accumulate cycles
15501 # PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7
15503 # FFL Phase0 int gain aka 2ol SD update rate
15504 # PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6
15506 # Fast phase lock controls -- FSM accumulator cycle control and phase 0 in
15508 #(OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) */
15509 mask_write 0XFD40DC14 0x000000FF 0x000000E6
15510 # Register : L3_TM_CDR16 @ 0XFD40DC40</p>
15512 # FFL Phase0 prop gain aka 1ol SD update rate
15513 # PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC
15515 # Fast phase lock controls -- phase 0 prop gain
15516 #(OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) */
15517 mask_write 0XFD40DC40 0x0000001F 0x0000000C
15518 # Register : L3_TM_EQ0 @ 0XFD40D94C</p>
15520 # EQ stg 2 controls BYPASSED
15521 # PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1
15523 # eq stg1 and stg2 controls
15524 #(OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) */
15525 mask_write 0XFD40D94C 0x00000020 0x00000020
15526 # Register : L3_TM_EQ1 @ 0XFD40D950</p>
15529 # PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2
15531 # EQ stg 2 preamp mode val
15532 # PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1
15534 # eq stg1 and stg2 controls
15535 #(OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) */
15536 mask_write 0XFD40D950 0x00000007 0x00000006
15537 # : GEM SERDES SETTINGS
15538 # : ENABLE PRE EMPHAIS AND VOLTAGE SWING
15539 # Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
15541 # Margining factor value
15542 # PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0
15545 #(OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) */
15546 mask_write 0XFD404CC0 0x0000001F 0x00000000
15547 # Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
15549 # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
15550 # phasis, Others: reserved
15551 # PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0
15553 # Override for PIPE TX de-emphasis
15554 #(OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) */
15555 mask_write 0XFD404048 0x000000FF 0x00000000
15556 # Register : L3_TX_ANA_TM_18 @ 0XFD40C048</p>
15558 # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
15559 # phasis, Others: reserved
15560 # PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1
15562 # Override for PIPE TX de-emphasis
15563 #(OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) */
15564 mask_write 0XFD40C048 0x000000FF 0x00000001
15567 set psu_resetout_init_data {
15568 # : TAKING SERDES PERIPHERAL OUT OF RESET RESET
15569 # : PUTTING USB0 IN RESET
15570 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
15572 # USB 0 reset for control registers
15573 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0
15575 # Software control register for the LPD block.
15576 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */
15577 mask_write 0XFF5E023C 0x00000400 0x00000000
15579 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
15581 # USB 0 sleep circuit reset
15582 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0
15585 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0
15587 # Software control register for the LPD block.
15588 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) */
15589 mask_write 0XFF5E023C 0x00000140 0x00000000
15590 # : PUTTING GEM0 IN RESET
15591 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
15594 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0
15596 # Software controlled reset for the GEMs
15597 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */
15598 mask_write 0XFF5E0230 0x00000008 0x00000000
15599 # : PUTTING SATA IN RESET
15600 # Register : sata_misc_ctrl @ 0XFD3D0100</p>
15602 # Sata PM clock control select
15603 # PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3
15605 # Misc Contorls for SATA.This register may only be modified during bootup
15606 # (while SATA block is disabled)
15607 #(OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) */
15608 mask_write 0XFD3D0100 0x00000003 0x00000003
15609 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
15611 # Sata block level reset
15612 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0
15614 # FPD Block level software controlled reset
15615 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) */
15616 mask_write 0XFD1A0100 0x00000002 0x00000000
15617 # : PUTTING PCIE CFG AND BRIDGE IN RESET
15618 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
15620 # PCIE config reset
15621 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0
15623 # PCIE bridge block level reset (AXI interface)
15624 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0
15626 # FPD Block level software controlled reset
15627 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) */
15628 mask_write 0XFD1A0100 0x000C0000 0x00000000
15629 # : PUTTING DP IN RESET
15630 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
15632 # Display Port block level reset (includes DPDMA)
15633 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0
15635 # FPD Block level software controlled reset
15636 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) */
15637 mask_write 0XFD1A0100 0x00010000 0x00000000
15638 # Register : DP_PHY_RESET @ 0XFD4A0200</p>
15640 # Set to '1' to hold the GT in reset. Clear to release.
15641 # PSU_DP_DP_PHY_RESET_GT_RESET 0X0
15643 # Reset the transmitter PHY.
15644 #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) */
15645 mask_write 0XFD4A0200 0x00000002 0x00000000
15646 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
15648 # Two bits per lane. When set to 11, moves the GT to power down mode. When
15649 # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
15651 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0
15653 # Control PHY Power down
15654 #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) */
15655 mask_write 0XFD4A0238 0x0000000F 0x00000000
15657 # Register : GUSB2PHYCFG @ 0XFE20C200</p>
15659 # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc
15660 # ks. Specifies the response time for a MAC request to the Packet FIFO Con
15661 # troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th
15662 # e required values for the minimum SoC bus frequency of 60 MHz. USB turna
15663 # round time is a critical certification criteria when using long cables a
15664 # nd five hub levels. The required values for this field: - 4'h5: When the
15665 # MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
15666 # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim
15667 # e is not critical, this field can be set to a larger value. Note: This f
15668 # ield is valid only in device mode.
15669 # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9
15671 # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP
15672 # I Transceiver Select signal (for HS) and the assertion of the TxValid si
15673 # gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima
15674 # tely 2.5 us) is introduced from the time when the Transceiver Select is
15675 # set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the
15676 # chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you
15677 # enable the hibernation feature when the device core comes out of power-
15678 # off, you must re-initialize this bit with the appropriate value because
15679 # the core does not save and restore this bit value during hibernation. -
15680 # This bit is valid only in device mode.
15681 # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0
15683 # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use
15684 # s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th
15685 # e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert
15686 # ion from the core is not transferred to the external PHY. - 1'b1: utmi_s
15687 # leep_n and utmi_l1_suspend_n assertion from the core is transferred to t
15688 # he external PHY. Note: This bit must be set high for Port0 if PHY is use
15689 # d. Note: In Device mode - Before issuing any device endpoint command whe
15690 # n operating in 2.0 speeds, disable this bit and enable it after the comm
15691 # and completes. Without disabling this bit, if a command is issued when t
15692 # he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
15693 # f, the command will not get completed.
15694 # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0
15696 # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T
15697 # he application uses this bit to select a high-speed PHY or a full-speed
15698 # transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a
15699 # lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans
15700 # ceiver. This bit is always 1, with Write Only access. If both interface
15701 # types are selected in coreConsultant (that is, parameters' values are no
15702 # t zero), the application uses this bit to select the active interface is
15703 # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
15704 # er is not supported. This bit always reads as 1'b0.
15705 # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0
15707 # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend
15708 # mode if Suspend conditions are valid. For DRD/OTG configurations, it is
15709 # recommended that this bit is set to 0 during coreConsultant configurati
15710 # on. If it is set to 1, then the application must clear this bit after po
15711 # wer-on reset. Application needs to set it to 1 after the core initializa
15712 # tion completes. For all other configurations, this bit can be set to 1 d
15713 # uring core configuration. Note: - In host mode, on reset, this bit is se
15714 # t to 1. Software can override this bit after reset. - In device mode, be
15715 # fore issuing any device endpoint command when operating in 2.0 speeds, d
15716 # isable this bit and enable it after the command completes. If you issue
15717 # a command without disabling this bit when the device is in L2 state and
15718 # if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
15720 # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1
15722 # Full-Speed Serial Interface Select (FSIntf) The application uses this bi
15723 # t to select a unidirectional or bidirectional USB 1.1 full-speed serial
15724 # transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in
15725 # terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir
15726 # ectional full-speed serial interface. This bit is set to 0 with Read Onl
15727 # y access. Note: USB 1.1 full-speed serial interface is not supported. Th
15728 # is bit always reads as 1'b0.
15729 # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0
15731 # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se
15732 # lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int
15733 # erface This bit is writable only if UTMI+ and ULPI is specified for High
15734 # -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_
15735 # INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
15736 # n the interface selected through DWC_USB3_HSPHY_INTERFACE.
15737 # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1
15739 # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi
15740 # t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte
15741 # rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en
15742 # abled 2.0 ports must have the same clock frequency as Port0 clock freque
15743 # ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge
15744 # ther for different ports at the same time (that is, all the ports must b
15745 # e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If
15746 # any of the USB 2.0 ports is selected as ULPI port for operation, then a
15747 # ll the USB 2.0 ports must be operating at 60 MHz.
15748 # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0
15750 # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat
15751 # ed by the application in this field, is multiplied by a bit-time factor;
15752 # this factor is added to the high-speed/full-speed interpacket timeout d
15753 # uration in the core to account for additional delays introduced by the P
15754 # HY. This may be required, since the delay introduced by the PHY in gener
15755 # ating the linestate condition may vary among PHYs. The USB standard time
15756 # out value for high-speed operation is 736 to 816 (inclusive) bit times.
15757 # The USB standard timeout value for full-speed operation is 16 to 18 (inc
15758 # lusive) bit times. The application must program this field based on the
15759 # speed of connection. The number of bit times added per PHY clock are: Hi
15760 # gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P
15761 # HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.
15762 # 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
15763 # k = 0.25 bit times
15764 # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7
15766 # ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive
15767 # 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char
15768 # ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
15769 # y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
15770 # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1
15772 # Global USB2 PHY Configuration Register The application must program this
15773 # register before starting any transactions on either the SoC bus or the
15774 # USB. In Device-only configurations, only one register is needed. In Host
15775 # mode, per-port registers are implemented.
15776 #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) */
15777 mask_write 0XFE20C200 0x00023FFF 0x00022457
15778 # Register : GFLADJ @ 0XFE20C630</p>
15780 # This field indicates the frame length adjustment to be applied when SOF/
15781 # ITP counter is running on the ref_clk. This register value is used to ad
15782 # just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i
15783 # nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must
15784 # be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t
15785 # o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows:
15786 # FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe
15787 # riod)) * ref_clk_period where - the ref_clk_period_integer is the intege
15788 # r value of the ref_clk period got by truncating the decimal (fractional)
15789 # value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c
15790 # lk_period is the ref_clk period including the fractional value. Examples
15791 # : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA
15792 # DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin
15793 # g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE
15794 # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
15795 # 0.8333 = 5208 (ignoring the fractional value)
15796 # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0
15798 # Global Frame Length Adjustment Register This register provides options f
15799 # or the software to control the core behavior with respect to SOF (Start
15800 # of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer
15801 # functionality. It provides an option to override the fladj_30mhz_reg sid
15802 # eband signal. In addition, it enables running SOF or ITP frame timer cou
15803 # nters completely from the ref_clk. This facilitates hardware LPM in host
15804 # mode with the SOF or ITP counters being run from the ref_clk signal.
15805 #(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */
15806 mask_write 0XFE20C630 0x003FFF00 0x00000000
15807 # Register : GUCTL1 @ 0XFE20C11C</p>
15809 # When this bit is set to '0', termsel, xcvrsel will become 0 during end o
15810 # f resume while the opmode will become 0 once controller completes end of
15811 # resume and enters U0 state (2 separate commandswill be issued). When th
15812 # is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
15813 # end of resume itself (only 1 command will be issued)
15814 # PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1
15817 # PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1
15819 # Global User Control Register 1
15820 #(OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) */
15821 mask_write 0XFE20C11C 0x00000600 0x00000600
15822 # Register : GUCTL @ 0XFE20C12C</p>
15824 # Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th
15825 # e Auto Retry feature. For IN transfers (non-isochronous) that encounter
15826 # data packets with CRC errors or internal overrun scenarios, the auto ret
15827 # ry feature causes the Host core to reply to the device with a non-termin
15828 # ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N
15829 # umP != 0). If the Auto Retry feature is disabled (default), the core wil
15830 # l respond with a terminating retry ACK (that is, an ACK transaction pack
15831 # et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
15832 # o Retry Enabled Note: This bit is also applicable to the device mode.
15833 # PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1
15835 # Global User Control Register: This register provides a few options for t
15836 # he software to control the core behavior in the Host mode. Most of the o
15837 # ptions are used to improve host inter-operability with different devices
15839 #(OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) */
15840 mask_write 0XFE20C12C 0x00004000 0x00004000
15841 # : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
15842 # Register : ATTR_25 @ 0XFD480064</p>
15844 # If TRUE Completion Timeout Disable is supported. This is required to be
15845 # TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
15846 # ce Capability 2 [4]; EP=0x0001; RP=0x0001
15847 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1
15850 #(OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) */
15851 mask_write 0XFD480064 0x00000200 0x00000200
15853 # Register : ATTR_7 @ 0XFD48001C</p>
15855 # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
15856 # to be implemented, set to 32'h00000000. Bits are defined as follows: Me
15857 # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
15858 # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
15859 # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
15860 # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
15861 # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
15862 # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
15863 # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
15864 # EP=0x0004; RP=0x0000
15865 # PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0
15868 #(OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) */
15869 mask_write 0XFD48001C 0x0000FFFF 0x00000000
15870 # Register : ATTR_8 @ 0XFD480020</p>
15872 # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
15873 # to be implemented, set to 32'h00000000. Bits are defined as follows: Me
15874 # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
15875 # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
15876 # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
15877 # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
15878 # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
15879 # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
15880 # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
15881 # EP=0xFFF0; RP=0x0000
15882 # PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0
15885 #(OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) */
15886 mask_write 0XFD480020 0x0000FFFF 0x00000000
15887 # Register : ATTR_9 @ 0XFD480024</p>
15889 # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
15890 # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
15891 # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
15892 # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
15893 # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
15894 # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
15895 # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
15896 # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
15897 # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
15898 # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
15899 # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
15900 # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
15901 # PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0
15904 #(OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) */
15905 mask_write 0XFD480024 0x0000FFFF 0x00000000
15906 # Register : ATTR_10 @ 0XFD480028</p>
15908 # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
15909 # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
15910 # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
15911 # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
15912 # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
15913 # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
15914 # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
15915 # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
15916 # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
15917 # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
15918 # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
15919 # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
15920 # PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0
15923 #(OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) */
15924 mask_write 0XFD480028 0x0000FFFF 0x00000000
15925 # Register : ATTR_11 @ 0XFD48002C</p>
15927 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
15928 # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
15929 # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
15930 # et to 32'h00000000. See BAR1 description if this functions as the upper
15931 # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
15932 # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
15933 # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
15934 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
15935 # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
15936 # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
15937 # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
15938 # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
15939 # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
15940 # es.; EP=0x0004; RP=0xFFFF
15941 # PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF
15944 #(OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) */
15945 mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF
15946 # Register : ATTR_12 @ 0XFD480030</p>
15948 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
15949 # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
15950 # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
15951 # et to 32'h00000000. See BAR1 description if this functions as the upper
15952 # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
15953 # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
15954 # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
15955 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
15956 # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
15957 # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
15958 # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
15959 # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
15960 # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
15961 # es.; EP=0xFFF0; RP=0x00FF
15962 # PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF
15965 #(OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) */
15966 mask_write 0XFD480030 0x0000FFFF 0x000000FF
15967 # Register : ATTR_13 @ 0XFD480034</p>
15969 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
15970 # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
15971 # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
15972 # et to 32'h00000000. See BAR2 description if this functions as the upper
15973 # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
15974 # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
15975 # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
15976 # t decode For an endpoint, bits are defined as follows: Memory Space BAR
15977 # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
15978 # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
15979 # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
15980 # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
15981 # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
15982 # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
15983 # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
15984 # in bytes.; EP=0xFFFF; RP=0x0000
15985 # PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0
15988 #(OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) */
15989 mask_write 0XFD480034 0x0000FFFF 0x00000000
15990 # Register : ATTR_14 @ 0XFD480038</p>
15992 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
15993 # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
15994 # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
15995 # et to 32'h00000000. See BAR2 description if this functions as the upper
15996 # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
15997 # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
15998 # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
15999 # t decode For an endpoint, bits are defined as follows: Memory Space BAR
16000 # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
16001 # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
16002 # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
16003 # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
16004 # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
16005 # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
16006 # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
16007 # in bytes.; EP=0xFFFF; RP=0xFFFF
16008 # PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF
16011 #(OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) */
16012 mask_write 0XFD480038 0x0000FFFF 0x0000FFFF
16013 # Register : ATTR_15 @ 0XFD48003C</p>
16015 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
16016 # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
16017 # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
16018 # et to 32'h00000000. See BAR3 description if this functions as the upper
16019 # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
16020 # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
16021 # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
16022 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
16023 # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
16024 # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
16025 # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
16026 # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
16027 # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
16028 # es.; EP=0x0004; RP=0xFFF0
16029 # PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0
16032 #(OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) */
16033 mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0
16034 # Register : ATTR_16 @ 0XFD480040</p>
16036 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
16037 # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
16038 # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
16039 # et to 32'h00000000. See BAR3 description if this functions as the upper
16040 # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
16041 # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
16042 # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
16043 # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
16044 # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
16045 # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
16046 # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
16047 # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
16048 # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
16049 # es.; EP=0xFFF0; RP=0xFFF0
16050 # PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0
16053 #(OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) */
16054 mask_write 0XFD480040 0x0000FFFF 0x0000FFF0
16055 # Register : ATTR_17 @ 0XFD480044</p>
16057 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
16058 # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
16059 # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
16060 # et to 32'h00000000. See BAR4 description if this functions as the upper
16061 # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
16062 # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
16063 # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
16064 # refetchable Memory Limit/Base implemented For an endpoint, bits are defi
16065 # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
16066 # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
16067 # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
16068 # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
16069 # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
16070 # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
16071 # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
16073 # PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1
16076 #(OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) */
16077 mask_write 0XFD480044 0x0000FFFF 0x0000FFF1
16078 # Register : ATTR_18 @ 0XFD480048</p>
16080 # For an endpoint, specifies mask/settings for Base Address Register (BAR)
16081 # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
16082 # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
16083 # et to 32'h00000000. See BAR4 description if this functions as the upper
16084 # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
16085 # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
16086 # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
16087 # refetchable Memory Limit/Base implemented For an endpoint, bits are defi
16088 # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
16089 # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
16090 # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
16091 # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
16092 # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
16093 # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
16094 # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
16096 # PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1
16099 #(OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) */
16100 mask_write 0XFD480048 0x0000FFFF 0x0000FFF1
16101 # Register : ATTR_27 @ 0XFD48006C</p>
16103 # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1
16104 # - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa
16105 # bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo
16106 # rted; EP=0x0001; RP=0x0001
16107 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1
16109 # Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca
16110 # n withstand on transitions from L1 state to L0 (if L1 state supported).
16111 # Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to
16112 # 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For
16113 # Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
16114 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0
16117 #(OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) */
16118 mask_write 0XFD48006C 0x00000738 0x00000100
16119 # Register : ATTR_50 @ 0XFD4800C8</p>
16121 # Identifies the type of device/port as follows: 0000b PCI Express Endpoin
16122 # t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P
16123 # CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110
16124 # b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X
16125 # Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre
16126 # ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM
16127 # _FACING settings.; EP=0x0000; RP=0x0004
16128 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4
16130 # PCIe Capability's Next Capability Offset pointer to the next item in the
16131 # capabilities list, or 00h if this is the final capability.; EP=0x009C;
16133 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0
16136 #(OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) */
16137 mask_write 0XFD4800C8 0x0000FFF0 0x00000040
16138 # Register : ATTR_105 @ 0XFD4801A4</p>
16140 # Number of credits that should be advertised for Completion data received
16141 # on Virtual Channel 0. The bytes advertised must be less than or equal t
16142 # o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
16143 # PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD
16146 #(OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) */
16147 mask_write 0XFD4801A4 0x000007FF 0x000000CD
16148 # Register : ATTR_106 @ 0XFD4801A8</p>
16150 # Number of credits that should be advertised for Completion headers recei
16151 # ved on Virtual Channel 0. The sum of the posted, non posted, and complet
16152 # ion header credits must be <= 80; EP=0x0048; RP=0x0024
16153 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24
16155 # Number of credits that should be advertised for Non-Posted headers recei
16156 # ved on Virtual Channel 0. The number of non posted data credits advertis
16157 # ed by the block is equal to the number of non posted header credits. The
16158 # sum of the posted, non posted, and completion header credits must be <=
16159 # 80; EP=0x0004; RP=0x000C
16160 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC
16163 #(OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) */
16164 mask_write 0XFD4801A8 0x00003FFF 0x00000624
16165 # Register : ATTR_107 @ 0XFD4801AC</p>
16167 # Number of credits that should be advertised for Non-Posted data received
16168 # on Virtual Channel 0. The number of non posted data credits advertised
16169 # by the block is equal to two times the number of non posted header credi
16170 # ts if atomic operations are supported or is equal to the number of non p
16171 # osted header credits if atomic operations are not supported. The bytes a
16172 # dvertised must be less than or equal to the bram bytes available. See VC
16173 # 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
16174 # PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18
16177 #(OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) */
16178 mask_write 0XFD4801AC 0x000007FF 0x00000018
16179 # Register : ATTR_108 @ 0XFD4801B0</p>
16181 # Number of credits that should be advertised for Posted data received on
16182 # Virtual Channel 0. The bytes advertised must be less than or equal to th
16183 # e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
16184 # PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5
16187 #(OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) */
16188 mask_write 0XFD4801B0 0x000007FF 0x000000B5
16189 # Register : ATTR_109 @ 0XFD4801B4</p>
16191 # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_
16192 # n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000
16193 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0
16195 # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim
16196 # TRUE == trim.; EP=0x0001; RP=0x0001
16197 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1
16199 # Enables ECRC check on received TLP's 0 == don't check 1 == always check
16200 # 3 == check if enabled by ECRC check enable bit of AER cap structure; EP=
16201 # 0x0003; RP=0x0003
16202 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3
16204 # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1).
16205 # Calculated from max payload size supported and the number of brams conf
16206 # igured for transmit; EP=0x001C; RP=0x001C
16207 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c
16209 # Number of credits that should be advertised for Posted headers received
16210 # on Virtual Channel 0. The sum of the posted, non posted, and completion
16211 # header credits must be <= 80; EP=0x0004; RP=0x0020
16212 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20
16215 #(OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) */
16216 mask_write 0XFD4801B4 0x0000FFFF 0x00007E20
16217 # Register : ATTR_34 @ 0XFD480088</p>
16219 # Specifies values to be transferred to Header Type register. Bit 7 should
16220 # be set to '0' indicating single-function device. Bit 0 identifies heade
16221 # r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000;
16223 # PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1
16226 #(OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) */
16227 mask_write 0XFD480088 0x000000FF 0x00000001
16228 # Register : ATTR_53 @ 0XFD4800D4</p>
16230 # PM Capability's Next Capability Offset pointer to the next item in the c
16231 # apabilities list, or 00h if this is the final capability.; EP=0x0048; RP
16233 # PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60
16236 #(OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) */
16237 mask_write 0XFD4800D4 0x000000FF 0x00000060
16238 # Register : ATTR_41 @ 0XFD4800A4</p>
16240 # MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont
16241 # rol Register[8]. When set, adds Mask and Pending Dword to Cap structure;
16242 # EP=0x0000; RP=0x0000
16243 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0
16245 # Indicates that the MSI structures exists. If this is FALSE, then the MSI
16246 # structure cannot be accessed via either the link or the management port
16247 # .; EP=0x0001; RP=0x0000
16248 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
16250 # MSI Capability's Next Capability Offset pointer to the next item in the
16251 # capabilities list, or 00h if this is the final capability.; EP=0x0060; R
16253 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0
16255 # Indicates that the MSI structures exists. If this is FALSE, then the MSI
16256 # structure cannot be accessed via either the link or the management port
16257 # .; EP=0x0001; RP=0x0000
16258 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0
16261 #(OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) */
16262 mask_write 0XFD4800A4 0x000003FF 0x00000000
16263 # Register : ATTR_97 @ 0XFD480184</p>
16265 # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b
16266 # x4, 001000b x8.; EP=0x0004; RP=0x0004
16267 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1
16269 # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1
16270 # ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004
16271 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1
16274 #(OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) */
16275 mask_write 0XFD480184 0x00000FFF 0x00000041
16276 # Register : ATTR_100 @ 0XFD480190</p>
16278 # TRUE specifies upstream-facing port. FALSE specifies downstream-facing p
16279 # ort.; EP=0x0001; RP=0x0000
16280 # PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0
16283 #(OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) */
16284 mask_write 0XFD480190 0x00000040 0x00000000
16285 # Register : ATTR_101 @ 0XFD480194</p>
16287 # Enable the routing of message TLPs to the user through the TRN RX interf
16288 # ace. A bit value of 1 enables routing of the message TLP to the user. Me
16289 # ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1
16290 # - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I
16291 # NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit
16292 # 10 PME_Turn_Off; EP=0x0000; RP=0x07FF
16293 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF
16295 # Disable BAR filtering. Does not change the behavior of the bar hit outpu
16296 # ts; EP=0x0000; RP=0x0001
16297 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1
16300 #(OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) */
16301 mask_write 0XFD480194 0x0000FFE2 0x0000FFE2
16302 # Register : ATTR_37 @ 0XFD480094</p>
16304 # Link Bandwidth notification capability. Indicates support for the link b
16305 # andwidth notification status and interrupt mechanism. Required for Root.
16306 # ; EP=0x0000; RP=0x0001
16307 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1
16309 # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op
16310 # tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001
16312 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1
16315 #(OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) */
16316 mask_write 0XFD480094 0x00004200 0x00004200
16317 # Register : ATTR_93 @ 0XFD480174</p>
16319 # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value
16320 # (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU
16321 # NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
16322 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1
16324 # Sets a user-defined timeout for the Replay Timer to force cause the retr
16325 # ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_
16326 # REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att
16327 # ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.;
16328 # EP=0x0000; RP=0x0000
16329 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000
16332 #(OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) */
16333 mask_write 0XFD480174 0x0000FFFF 0x00009000
16334 # Register : ID @ 0XFD480200</p>
16336 # Device ID for the the PCIe Cap Structure Device ID field
16337 # PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021
16339 # Vendor ID for the PCIe Cap Structure Vendor ID field
16340 # PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee
16343 #(OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) */
16344 mask_write 0XFD480200 0xFFFFFFFF 0x10EED021
16345 # Register : SUBSYS_ID @ 0XFD480204</p>
16347 # Subsystem ID for the the PCIe Cap Structure Subsystem ID field
16348 # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7
16350 # Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
16351 # PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee
16354 #(OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) */
16355 mask_write 0XFD480204 0xFFFFFFFF 0x10EE0007
16356 # Register : REV_ID @ 0XFD480208</p>
16358 # Revision ID for the the PCIe Cap Structure
16359 # PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0
16362 #(OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) */
16363 mask_write 0XFD480208 0x000000FF 0x00000000
16364 # Register : ATTR_24 @ 0XFD480060</p>
16366 # Code identifying basic function, subclass and applicable programming int
16367 # erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000
16368 # PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400
16371 #(OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) */
16372 mask_write 0XFD480060 0x0000FFFF 0x00000400
16373 # Register : ATTR_25 @ 0XFD480064</p>
16375 # Code identifying basic function, subclass and applicable programming int
16376 # erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006
16377 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6
16379 # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10]
16380 # to be hardwired to 0.; EP=0x0001; RP=0x0001
16381 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0
16384 #(OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) */
16385 mask_write 0XFD480064 0x000001FF 0x00000006
16386 # Register : ATTR_4 @ 0XFD480010</p>
16388 # Indicates that the AER structures exists. If this is FALSE, then the AER
16389 # structure cannot be accessed via either the link or the management port
16390 # , and AER will be considered to not be present for error management task
16391 # s (such as what types of error messages are sent if an error is detected
16392 # ).; EP=0x0001; RP=0x0001
16393 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
16395 # Indicates that the AER structures exists. If this is FALSE, then the AER
16396 # structure cannot be accessed via either the link or the management port
16397 # , and AER will be considered to not be present for error management task
16398 # s (such as what types of error messages are sent if an error is detected
16399 # ).; EP=0x0001; RP=0x0001
16400 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0
16403 #(OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) */
16404 mask_write 0XFD480010 0x00001000 0x00000000
16405 # Register : ATTR_89 @ 0XFD480164</p>
16407 # VSEC's Next Capability Offset pointer to the next item in the capabiliti
16408 # es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140
16409 # PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0
16412 #(OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) */
16413 mask_write 0XFD480164 0x00001FFE 0x00000000
16414 # Register : ATTR_79 @ 0XFD48013C</p>
16416 # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the
16417 # Root Capabilities register.; EP=0x0000; RP=0x0000
16418 # PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1
16421 #(OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) */
16422 mask_write 0XFD48013C 0x00000020 0x00000020
16423 # Register : ATTR_43 @ 0XFD4800AC</p>
16425 # Indicates that the MSIX structures exists. If this is FALSE, then the MS
16426 # IX structure cannot be accessed via either the link or the management po
16427 # rt.; EP=0x0001; RP=0x0000
16428 # PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0
16431 #(OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) */
16432 mask_write 0XFD4800AC 0x00000100 0x00000000
16433 # Register : ATTR_48 @ 0XFD4800C0</p>
16435 # MSI-X Table Size. This value is transferred to the MSI-X Message Control
16436 # [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does
16437 # not implement the table; that must be implemented in user logic.; EP=0x0
16439 # PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0
16442 #(OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) */
16443 mask_write 0XFD4800C0 0x000007FF 0x00000000
16444 # Register : ATTR_46 @ 0XFD4800B8</p>
16446 # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
16447 # field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
16448 # PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0
16451 #(OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) */
16452 mask_write 0XFD4800B8 0x0000FFFF 0x00000000
16453 # Register : ATTR_47 @ 0XFD4800BC</p>
16455 # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
16456 # field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000
16457 # PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0
16460 #(OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) */
16461 mask_write 0XFD4800BC 0x00001FFF 0x00000000
16462 # Register : ATTR_44 @ 0XFD4800B0</p>
16464 # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
16465 # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
16466 # PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0
16469 #(OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) */
16470 mask_write 0XFD4800B0 0x0000FFFF 0x00000000
16471 # Register : ATTR_45 @ 0XFD4800B4</p>
16473 # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
16474 # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000
16475 # PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0
16478 #(OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) */
16479 mask_write 0XFD4800B4 0x0000FFF8 0x00000000
16480 # Register : CB @ 0XFD48031C</p>
16483 # PSU_PCIE_ATTRIB_CB_CB1 0x0
16486 #(OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) */
16487 mask_write 0XFD48031C 0x00000002 0x00000000
16488 # Register : ATTR_35 @ 0XFD48008C</p>
16490 # Active State PM Support. Indicates the level of active state power manag
16491 # ement supported by the selected PCI Express Link, encoded as follows: 0
16492 # Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte
16493 # d.; EP=0x0001; RP=0x0001
16494 # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0
16497 #(OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) */
16498 mask_write 0XFD48008C 0x00003000 0x00000000
16499 # : PUTTING PCIE CONTROL IN RESET
16500 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
16502 # PCIE control block level reset
16503 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0
16505 # FPD Block level software controlled reset
16506 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) */
16507 mask_write 0XFD1A0100 0x00020000 0x00000000
16508 # : PCIE GPIO RESET
16509 # : MASK_DATA_0_LSW LOW BANK [15:0]
16510 # : MASK_DATA_0_MSW LOW BANK [25:16]
16511 # : MASK_DATA_1_LSW LOW BANK [41:26]
16512 # Register : MASK_DATA_1_LSW @ 0XFF0A0008</p>
16514 # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
16515 # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf
16517 # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
16518 # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20
16520 # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
16521 #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */
16522 mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020
16523 # : MASK_DATA_1_MSW HIGH BANK [51:42]
16524 # : MASK_DATA_1_LSW HIGH BANK [67:52]
16525 # : MASK_DATA_1_LSW HIGH BANK [77:68]
16526 # : CHECK PLL LOCK FOR LANE0
16527 # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4</p>
16529 # Status Read value of PLL Lock
16530 # PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
16531 mask_poll 0XFD4023E4 0x00000010
16532 # : CHECK PLL LOCK FOR LANE1
16533 # Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
16535 # Status Read value of PLL Lock
16536 # PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
16537 mask_poll 0XFD4063E4 0x00000010
16538 # : CHECK PLL LOCK FOR LANE2
16539 # Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
16541 # Status Read value of PLL Lock
16542 # PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
16543 mask_poll 0XFD40A3E4 0x00000010
16544 # : CHECK PLL LOCK FOR LANE3
16545 # Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
16547 # Status Read value of PLL Lock
16548 # PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1
16549 mask_poll 0XFD40E3E4 0x00000010
16550 # : SATA AHCI VENDOR SETTING
16551 # Register : PP2C @ 0XFD0C00AC</p>
16553 # CIBGMN: COMINIT Burst Gap Minimum.
16554 # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18
16556 # CIBGMX: COMINIT Burst Gap Maximum.
16557 # PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40
16559 # CIBGN: COMINIT Burst Gap Nominal.
16560 # PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18
16562 # CINMP: COMINIT Negate Minimum Period.
16563 # PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28
16565 # PP2C - Port Phy2Cfg Register. This register controls the configuration o
16566 # f the Phy Control OOB timing for the COMINIT parameters for either Port
16567 # 0 or Port 1. The Port configured is controlled by the value programmed i
16568 # nto the Port Config Register.
16569 #(OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) */
16570 mask_write 0XFD0C00AC 0xFFFFFFFF 0x28184018
16571 # Register : PP3C @ 0XFD0C00B0</p>
16573 # CWBGMN: COMWAKE Burst Gap Minimum.
16574 # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06
16576 # CWBGMX: COMWAKE Burst Gap Maximum.
16577 # PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14
16579 # CWBGN: COMWAKE Burst Gap Nominal.
16580 # PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08
16582 # CWNMP: COMWAKE Negate Minimum Period.
16583 # PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E
16585 # PP3C - Port Phy3CfgRegister. This register controls the configuration of
16586 # the Phy Control OOB timing for the COMWAKE parameters for either Port 0
16587 # or Port 1. The Port configured is controlled by the value programmed in
16588 # to the Port Config Register.
16589 #(OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) */
16590 mask_write 0XFD0C00B0 0xFFFFFFFF 0x0E081406
16591 # Register : PP4C @ 0XFD0C00B4</p>
16593 # BMX: COM Burst Maximum.
16594 # PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13
16596 # BNM: COM Burst Nominal.
16597 # PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08
16599 # SFD: Signal Failure Detection, if the signal detection de-asserts for a
16600 # time greater than this then the OOB detector will determine this is a li
16601 # ne idle and cause the PhyInit state machine to exit the Phy Ready State.
16602 # A value of zero disables the Signal Failure Detector. The value is base
16603 # d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
16604 # a nominal time of 500ns based on a 150MHz PMCLK.
16605 # PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A
16607 # PTST: Partial to Slumber timer value, specific delay the controller shou
16608 # ld apply while in partial before entering slumber. The value is bases on
16609 # the system clock divided by 128, total delay = (Sys Clock Period) * PTS
16611 # PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06
16613 # PP4C - Port Phy4Cfg Register. This register controls the configuration o
16614 # f the Phy Control Burst timing for the COM parameters for either Port 0
16615 # or Port 1. The Port configured is controlled by the value programmed int
16616 # o the Port Config Register.
16617 #(OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) */
16618 mask_write 0XFD0C00B4 0xFFFFFFFF 0x064A0813
16619 # Register : PP5C @ 0XFD0C00B8</p>
16621 # RIT: Retry Interval Timer. The calculated value divided by two, the lowe
16622 # r digit of precision is not needed.
16623 # PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4
16625 # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev
16626 # ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
16627 # fast SERDES it is suggested that this value be 54.2us / 4
16628 # PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF
16630 # PP5C - Port Phy5Cfg Register. This register controls the configuration o
16631 # f the Phy Control Retry Interval timing for either Port 0 or Port 1. The
16632 # Port configured is controlled by the value programmed into the Port Con
16634 #(OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) */
16635 mask_write 0XFD0C00B8 0xFFFFFFFF 0x3FFC96A4
16638 set psu_resetin_init_data {
16639 # : PUTTING SERDES PERIPHERAL IN RESET
16640 # : PUTTING USB0 IN RESET
16641 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
16643 # USB 0 reset for control registers
16644 # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1
16646 # USB 0 sleep circuit reset
16647 # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1
16650 # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1
16652 # Software control register for the LPD block.
16653 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) */
16654 mask_write 0XFF5E023C 0x00000540 0x00000540
16655 # : PUTTING GEM0 IN RESET
16656 # Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
16659 # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1
16661 # Software controlled reset for the GEMs
16662 #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) */
16663 mask_write 0XFF5E0230 0x00000008 0x00000008
16664 # : PUTTING SATA IN RESET
16665 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
16667 # Sata block level reset
16668 # PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1
16670 # FPD Block level software controlled reset
16671 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) */
16672 mask_write 0XFD1A0100 0x00000002 0x00000002
16673 # : PUTTING PCIE IN RESET
16674 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
16676 # PCIE config reset
16677 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1
16679 # PCIE control block level reset
16680 # PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1
16682 # PCIE bridge block level reset (AXI interface)
16683 # PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1
16685 # FPD Block level software controlled reset
16686 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) */
16687 mask_write 0XFD1A0100 0x000E0000 0x000E0000
16688 # : PUTTING DP IN RESET
16689 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
16691 # Two bits per lane. When set to 11, moves the GT to power down mode. When
16692 # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
16694 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA
16696 # Control PHY Power down
16697 #(OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) */
16698 mask_write 0XFD4A0238 0x0000000F 0x0000000A
16699 # Register : DP_PHY_RESET @ 0XFD4A0200</p>
16701 # Set to '1' to hold the GT in reset. Clear to release.
16702 # PSU_DP_DP_PHY_RESET_GT_RESET 0X1
16704 # Reset the transmitter PHY.
16705 #(OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) */
16706 mask_write 0XFD4A0200 0x00000002 0x00000002
16707 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
16709 # Display Port block level reset (includes DPDMA)
16710 # PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1
16712 # FPD Block level software controlled reset
16713 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) */
16714 mask_write 0XFD1A0100 0x00010000 0x00010000
16717 set psu_ps_pl_isolation_removal_data {
16718 # : PS-PL POWER UP REQUEST
16719 # Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
16721 # Power-up Request Interrupt Enable for PL
16722 # PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1
16724 # Power-up Request Interrupt Enable Register. Writing a 1 to this location
16725 # will unmask the interrupt.
16726 #(OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) */
16727 mask_write 0XFFD80118 0x00800000 0x00800000
16728 # Register : REQ_PWRUP_TRIG @ 0XFFD80120</p>
16730 # Power-up Request Trigger for PL
16731 # PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1
16733 # Power-up Request Trigger Register. A write of one to this location will
16734 # generate a power-up request to the PMU.
16735 #(OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) */
16736 mask_write 0XFFD80120 0x00800000 0x00800000
16737 # : POLL ON PL POWER STATUS
16738 # Register : REQ_PWRUP_STATUS @ 0XFFD80110</p>
16740 # Power-up Request Status for PL
16741 # PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1
16742 mask_poll 0XFFD80110 0x00800000 0x00000000
16745 set psu_afi_config {
16747 # Register : RST_FPD_TOP @ 0XFD1A0100</p>
16749 # AF_FM0 block level reset
16750 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0
16752 # AF_FM1 block level reset
16753 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0
16755 # AF_FM2 block level reset
16756 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0
16758 # AF_FM3 block level reset
16759 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0
16761 # AF_FM4 block level reset
16762 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0
16764 # AF_FM5 block level reset
16765 # PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0
16767 # FPD Block level software controlled reset
16768 #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) */
16769 mask_write 0XFD1A0100 0x00001F80 0x00000000
16770 # Register : RST_LPD_TOP @ 0XFF5E023C</p>
16773 # PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0
16775 # Software control register for the LPD block.
16776 #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) */
16777 mask_write 0XFF5E023C 0x00080000 0x00000000
16778 # : AFIFM INTERFACE WIDTH
16779 # Register : afi_fs @ 0XFD615000</p>
16781 # Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit
16782 # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
16783 # width 11: reserved
16784 # PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2
16786 # Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit
16787 # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
16788 # width 11: reserved
16789 # PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2
16791 # afi fs SLCR control register. This register is static and should not be
16792 # modified during operation.
16793 #(OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) */
16794 mask_write 0XFD615000 0x00000F00 0x00000A00
16797 set psu_ps_pl_reset_config_data {
16798 # : PS PL RESET SEQUENCE
16799 # : FABRIC RESET USING EMIO
16800 # Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>
16802 # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
16803 # PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000
16805 # Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
16806 #(OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) */
16807 mask_write 0XFF0A002C 0xFFFF0000 0x80000000
16808 # Register : DIRM_5 @ 0XFF0A0344</p>
16810 # Operation is the same as DIRM_0[DIRECTION_0]
16811 # PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000
16813 # Direction mode (GPIO Bank5, EMIO)
16814 #(OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) */
16815 mask_write 0XFF0A0344 0xFFFFFFFF 0x80000000
16816 # Register : OEN_5 @ 0XFF0A0348</p>
16818 # Operation is the same as OEN_0[OP_ENABLE_0]
16819 # PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000
16821 # Output enable (GPIO Bank5, EMIO)
16822 #(OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) */
16823 mask_write 0XFF0A0348 0xFFFFFFFF 0x80000000
16824 # Register : DATA_5 @ 0XFF0A0054</p>
16827 # PSU_GPIO_DATA_5_DATA_5 0x80000000
16829 # Output Data (GPIO Bank5, EMIO)
16830 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */
16831 mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
16832 mask_delay 0x00000000 1
16833 # : FABRIC RESET USING DATA_5 TOGGLE
16834 # Register : DATA_5 @ 0XFF0A0054</p>
16837 # PSU_GPIO_DATA_5_DATA_5 0X00000000
16839 # Output Data (GPIO Bank5, EMIO)
16840 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) */
16841 mask_write 0XFF0A0054 0xFFFFFFFF 0x00000000
16842 mask_delay 0x00000000 1
16843 # : FABRIC RESET USING DATA_5 TOGGLE
16844 # Register : DATA_5 @ 0XFF0A0054</p>
16847 # PSU_GPIO_DATA_5_DATA_5 0x80000000
16849 # Output Data (GPIO Bank5, EMIO)
16850 #(OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) */
16851 mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
16855 # save current mode
16856 set saved_mode [configparams force-mem-accesses]
16858 configparams force-mem-accesses 1
16859 variable psu_mio_init_data
16860 variable psu_pll_init_data
16861 variable psu_clock_init_data
16862 variable psu_ddr_init_data
16863 variable psu_peripherals_init_data
16864 variable psu_resetin_init_data
16865 variable psu_resetout_init_data
16866 variable psu_serdes_init_data
16867 variable psu_resetin_init_data
16868 variable psu_peripherals_powerdwn_data
16869 variable psu_afi_config
16871 init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }]
16872 psu_ddr_phybringup_data
16873 init_ps [subst {$psu_peripherals_init_data $psu_resetin_init_data }]
16875 init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }]
16877 init_ps [subst {$psu_peripherals_powerdwn_data }]
16878 init_ps [subst {$psu_afi_config }]
16879 # restore original mode
16880 configparams force-mem-accesses $saved_mode
16883 proc psu_post_config {} {
16884 variable psu_post_config_data
16885 init_ps [subst {$psu_post_config_data}]
16888 proc psu_ps_pl_reset_config {} {
16889 variable psu_ps_pl_reset_config_data
16890 init_ps [subst {$psu_ps_pl_reset_config_data}]
16893 proc psu_ps_pl_isolation_removal {} {
16894 variable psu_ps_pl_isolation_removal_data
16895 init_ps [subst {$psu_ps_pl_isolation_removal_data}]
16899 proc mask_read { addr mask } {
16900 set curval "0x[string range [mrd -force $addr] end-8 end]"
16901 set maskedval [expr {$curval & $mask}]
16906 proc mask_poll { addr mask } {
16908 set curval "0x[string range [mrd -force $addr] end-8 end]"
16909 set maskedval [expr {$curval & $mask}]
16910 while { $maskedval == 0 } {
16911 set curval "0x[string range [mrd -force $addr] end-8 end]"
16912 set maskedval [expr {$curval & $mask}]
16913 set count [ expr { $count + 1 } ]
16914 if { $count == 1000 } {
16915 puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
16921 proc psu_mask_write { addr mask value } {
16922 set curval "0x[string range [mrd -force $addr] end-8 end]"
16923 set curval [expr {$curval & ~($mask)}]
16924 set maskedval [expr {$value & $mask}]
16925 set maskedval [expr {$curval | $maskedval}]
16926 mwr -force $addr $maskedval
16929 proc serdes_fixcal_code {} {
16932 array set match_pmos_code {}
16933 array set match_nmos_code {}
16934 array set match_ical_code {}
16935 array set match_rcal_code {}
16941 set L3_TM_CALIB_DIG20 0
16942 set L3_TM_CALIB_DIG19 0
16943 set L3_TM_CALIB_DIG18 0
16944 set L3_TM_CALIB_DIG16 0
16945 set L3_TM_CALIB_DIG15 0
16946 set L3_TM_CALIB_DIG14 0
16950 set rdata [mask_read 0XFD40289C 0xFFFFFFFF]
16951 set rdata [expr $rdata & ~0x03 ]
16952 set rdata [expr $rdata | 0x1]
16953 mask_write 0XFD40289C 0xFFFFFFFF $rdata
16954 #check supply good status before starting AFE sequencing
16957 set rdata [mask_read 0xFD402B1C 0xFFFFFFFF]
16958 set count [ expr { $count + 1 } ]
16959 if { [expr $rdata & 0x0000000E] == 0x0000000E } {
16962 if { $count == 1000 } {
16968 for {set i 0} {$i<23 } {incr i } {
16969 set match_pmos_code($i) 0;
16970 set match_nmos_code($i) 0;
16973 for {set i 0} {$i<7} {incr i} {
16974 set match_ical_code($i) 0;
16975 set match_rcal_code($i) 0;
16979 #Clear ICM_CFG value
16980 mask_write 0xFD410010 0xFFFFFFFF 0x00000000
16981 mask_write 0xFD410014 0xFFFFFFFF 0x00000000
16984 #This will trigger recalibration of all stages
16985 mask_write 0xFD410010 0xFFFFFFFF 0x00000001
16986 mask_write 0xFD410014 0xFFFFFFFF 0x00000000;
16988 #is calibration done? polling on L3_CALIB_DONE_STATUS
16989 mask_poll 0xFD40EF14 0x2;
16992 set p_code [mask_read 0xFD40EF18 0xFFFFFFFF];
16994 set n_code [mask_read 0xFD40EF1C 0xFFFFFFFF];
16996 set i_code [mask_read 0xFD40EF24 0xFFFFFFFF];
16998 set r_code [mask_read 0xFD40EF28 0xFFFFFFFF];
17001 #xil_printf("#SERDES initialization VALUES NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code);
17002 #PMOS code in acceptable range
17003 if {($p_code >= 0x26) && ($p_code <= 0x3C)} {
17004 set index [expr $p_code - 0x26]
17005 set value $match_pmos_code($index)
17007 set match_pmos_code($index) $value;
17009 #NMOS code in acceptable range
17010 if {($n_code >= 0x26) && ($n_code <= 0x3C)} {
17011 set index [expr $n_code - 0x26]
17012 set value $match_nmos_code($index)
17014 set match_nmos_code($index) $value;
17016 #PMOS code in acceptable range
17017 if {($i_code >= 0xC) && ($i_code <= 0x12)} {
17019 set index [expr $i_code - 0xC]
17020 set value $match_ical_code($index)
17022 set match_ical_code($index) $value;
17025 #NMOS code in acceptable range
17026 if {($r_code >= 0x6) && ($r_code <= 0xC)} {
17027 set index [expr $r_code - 0x6]
17028 set value $match_rcal_code($index)
17030 set match_rcal_code($index) $value;
17034 if {$repeat_count > 10} {
17041 #find the valid code which resulted in maximum times in 10 iterations
17042 for {set i 0 } {$i < 23} {incr i} {
17044 if {$match_pmos_code($i) >= $match_pmos_code(0) } {
17045 set match_pmos_code(0) $match_pmos_code($i)
17046 set p_code [expr 0x26 + $i]
17048 if {$match_nmos_code($i) >= $match_nmos_code(0)} {
17050 set match_nmos_code(0) $match_nmos_code($i)
17051 set n_code [expr 0x26 + $i];
17055 for {set $i 0} {$i<7} {incr i} {
17056 if {$match_ical_code($i) >= $match_ical_code(0)} {
17057 set match_ical_code(0) $match_ical_code($i)
17058 set i_code [expr 0xC + $i]
17060 if {$match_rcal_code($i) >= $match_rcal_code(0)} {
17061 set match_rcal_code(0) $match_rcal_code($i)
17062 set r_code [expr 0x6 + $i]
17065 #xil_printf("#SERDES initialization PASSED NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code);
17066 #L3_TM_CALIB_DIG20[3] PSW MSB Override
17067 #L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]
17069 set L3_TM_CALIB_DIG20 [mask_read 0xFD40EC50 0xFFFFFFF0];
17070 set L3_TM_CALIB_DIG20 [expr $L3_TM_CALIB_DIG20 | 0x8 | (($p_code>>2)&0x7)]
17073 #L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]
17074 #L3_TM_CALIB_DIG19[5] PSW Override
17075 #L3_TM_CALIB_DIG19[2] NSW MSB Override
17076 #L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]
17078 set L3_TM_CALIB_DIG19 [mask_read 0xFD40EC4C 0xFFFFFF18]
17079 set L3_TM_CALIB_DIG19 [expr $L3_TM_CALIB_DIG19 | (($p_code&0x3)<<6) | 0x20 | 0x4 | (($n_code>>3)&0x3)]
17081 #L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]
17082 #L3_TM_CALIB_DIG18[4] NSW Override
17084 set L3_TM_CALIB_DIG18 [mask_read 0xFD40EC48 0xFFFFFF0F]
17085 set L3_TM_CALIB_DIG18 [expr $L3_TM_CALIB_DIG18 | (($n_code&0x7)<<5) | 0x10]
17088 #L3_TM_CALIB_DIG16[2:0] RX Code [3:1]
17090 set L3_TM_CALIB_DIG16 [mask_read 0xFD40EC40 0xFFFFFFF8]
17091 set L3_TM_CALIB_DIG16 [expr $L3_TM_CALIB_DIG16 | (($r_code>>1)&0x7)]
17093 #L3_TM_CALIB_DIG15[7] RX Code [0]
17094 #L3_TM_CALIB_DIG15[6] RX CODE Override
17095 #L3_TM_CALIB_DIG15[3] ICAL MSB Override
17096 #L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]
17098 set L3_TM_CALIB_DIG15 [mask_read 0xFD40EC3C 0xFFFFFF30]
17099 set L3_TM_CALIB_DIG15 [expr $L3_TM_CALIB_DIG15 | (($r_code&0x1)<<7) | 0x40 | 0x8 | (($i_code>>1)&0x7)]
17101 #L3_TM_CALIB_DIG14[7] ICAL Code [0]
17102 #L3_TM_CALIB_DIG14[6] ICAL Override
17104 set L3_TM_CALIB_DIG14 [mask_read 0xFD40EC38 0xFFFFFF3F]
17105 set L3_TM_CALIB_DIG14 [expr $L3_TM_CALIB_DIG14 | (($i_code&0x1)<<7) | 0x40]
17107 #Forces the calibration values
17108 mask_write 0xFD40EC50 0xFFFFFFFF $L3_TM_CALIB_DIG20
17109 mask_write 0xFD40EC4C 0xFFFFFFFF $L3_TM_CALIB_DIG19
17110 mask_write 0xFD40EC48 0xFFFFFFFF $L3_TM_CALIB_DIG18
17111 mask_write 0xFD40EC40 0xFFFFFFFF $L3_TM_CALIB_DIG16
17112 mask_write 0xFD40EC3C 0xFFFFFFFF $L3_TM_CALIB_DIG15
17113 mask_write 0xFD40EC38 0xFFFFFFFF $L3_TM_CALIB_DIG14
17116 return $MaskStatus;
17118 proc serdes_enb_coarse_saturation {} {
17120 # * Enable PLL Coarse Code saturation Logic
17122 mask_write 0xFD402094 0xFFFFFFFF 0x00000010
17123 mask_write 0xFD406094 0xFFFFFFFF 0x00000010
17124 mask_write 0xFD40A094 0xFFFFFFFF 0x00000010
17125 mask_write 0xFD40E094 0xFFFFFFFF 0x00000010
17129 proc init_serdes {} {
17131 serdes_enb_coarse_saturation
17135 proc poll { addr mask data} {
17136 set curval "0x[string range [mrd -force $addr] end-8 end]"
17137 set maskedval [expr {$curval & $mask}]
17139 while { $maskedval != $data } {
17140 set curval "0x[string range [mrd -force $addr] end-8 end]"
17141 set maskedval [expr {$curval & $mask}]
17142 set count [ expr { $count + 1 } ]
17143 if { $count == 100000000 } {
17144 puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
17150 proc init_peripheral {} {
17151 #SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.
17152 mask_write 0xFD5F0018 0x8000001F 0x8000001F
17154 proc psu_init_xppu_aper_ram {} {
17159 proc psu_lpd_protection {} {
17162 proc psu_ddr_protection {} {
17163 set saved_mode [configparams force-mem-accesses]
17164 configparams force-mem-accesses 1
17166 variable psu_ddr_xmpu0_data
17167 variable psu_ddr_xmpu1_data
17168 variable psu_ddr_xmpu2_data
17169 variable psu_ddr_xmpu3_data
17170 variable psu_ddr_xmpu4_data
17171 variable psu_ddr_xmpu5_data
17172 init_ps [subst {$psu_ddr_xmpu0_data $psu_ddr_xmpu1_data $psu_ddr_xmpu2_data $psu_ddr_xmpu3_data $psu_ddr_xmpu4_data $psu_ddr_xmpu5_data}]
17174 configparams force-mem-accesses $saved_mode
17177 proc psu_ocm_protection {} {
17178 set saved_mode [configparams force-mem-accesses]
17179 configparams force-mem-accesses 1
17181 variable psu_ocm_xmpu_data
17182 init_ps [subst {$psu_ocm_xmpu_data }]
17184 configparams force-mem-accesses $saved_mode
17187 proc psu_fpd_protection {} {
17188 set saved_mode [configparams force-mem-accesses]
17189 configparams force-mem-accesses 1
17191 variable psu_fpd_xmpu_data
17192 init_ps [subst {$psu_fpd_xmpu_data }]
17194 configparams force-mem-accesses $saved_mode
17197 proc psu_protection_lock {} {
17198 set saved_mode [configparams force-mem-accesses]
17199 configparams force-mem-accesses 1
17201 variable psu_protection_lock_data
17202 init_ps [subst {$psu_protection_lock_data }]
17204 configparams force-mem-accesses $saved_mode
17207 proc psu_protection {} {
17208 variable psu_apply_master_tz
17209 init_ps [subst {$psu_apply_master_tz }]
17216 proc psu_ddr_phybringup_data {} {
17217 mwr -force 0xFD080004 0x00040073
17219 poll 0xFD080030 0x0000000F 0x0000000F
17220 psu_mask_write 0xFD080004 0x00000001 0x00000001
17221 #poll for PHY initialization to complete
17222 poll 0xFD080030 0x000000FF 0x0000001F
17224 psu_mask_write 0xFD070010 0x00000008 0x00000008
17225 psu_mask_write 0xFD0701B0 0x00000001 0x00000001
17226 psu_mask_write 0xFD070010 0x00000030 0x00000010
17227 psu_mask_write 0xFD070010 0x00000001 0x00000000
17228 psu_mask_write 0xFD070010 0x0000F000 0x00006000
17229 psu_mask_write 0xFD070014 0x0003FFFF 0x00000819
17230 psu_mask_write 0xFD070010 0x80000000 0x80000000
17231 poll 0xFD070018 0x00000001 0
17232 psu_mask_write 0xFD070010 0x00000030 0x00000010
17233 psu_mask_write 0xFD070010 0x00000001 0x00000000
17234 psu_mask_write 0xFD070010 0x0000F000 0x00006000
17235 psu_mask_write 0xFD070014 0x0003FFFF 0x00000899
17236 psu_mask_write 0xFD070010 0x80000000 0x80000000
17237 poll 0xFD070018 0x00000001 0
17238 psu_mask_write 0xFD070010 0x00000030 0x00000010
17239 psu_mask_write 0xFD070010 0x00000001 0x00000000
17240 psu_mask_write 0xFD070010 0x0000F000 0x00006000
17241 psu_mask_write 0xFD070014 0x0003FFFF 0x00000819
17242 psu_mask_write 0xFD070010 0x80000000 0x80000000
17243 poll 0xFD070018 0x00000001 0
17244 psu_mask_write 0xFD070010 0x00000008 0x00000000
17245 mwr -force 0xFD0701B0 0x00000001
17246 mwr -force 0xFD070320 0x00000001
17247 #//poll for DDR initialization to complete
17248 poll 0xFD070004 0x0000000F 0x00000001
17250 psu_mask_write 0xFD080014 0x00000040 0x00000040
17251 #Dummy reads before PHY training starts
17252 mrd -force 0xFD070004
17254 mrd -force 0xFD070004
17256 mrd -force 0xFD070004
17258 mrd -force 0xFD070004
17260 mrd -force 0xFD070004
17262 mrd -force 0xFD070004
17264 psu_mask_write 0xFD080004 0xFFFFFFFF 0x0004FE01
17265 #trigger PHY training
17266 poll 0xFD080030 0x00000FFF 0x00000FFF
17268 #Poll PUB_PGSR0 for Trng complete
17271 # Run Vref training in static read mode
17272 mwr -force 0xFD080200 0x100091C7
17273 mwr -force 0xFD080018 0x00F01EEF
17274 psu_mask_write 0xFD08142C 0x00000030 0x00000030
17275 psu_mask_write 0xFD08146C 0x00000030 0x00000030
17276 psu_mask_write 0xFD0814AC 0x00000030 0x00000030
17277 psu_mask_write 0xFD0814EC 0x00000030 0x00000030
17278 psu_mask_write 0xFD08152C 0x00000030 0x00000030
17279 psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001
17281 #trigger VreFPHY training
17282 poll 0xFD080030 0x00004001 0x00004001
17284 #//Poll PUB_PGSR0 for Trng complete
17285 mwr -force 0xFD080200 0x800091C7
17286 mwr -force 0xFD080018 0x00F122E7
17287 psu_mask_write 0xFD08142C 0x00000030 0x00000000
17288 psu_mask_write 0xFD08146C 0x00000030 0x00000000
17289 psu_mask_write 0xFD0814AC 0x00000030 0x00000000
17290 psu_mask_write 0xFD0814EC 0x00000030 0x00000000
17291 psu_mask_write 0xFD08152C 0x00000030 0x00000000
17292 psu_mask_write 0xFD080004 0xFFFFFFFF 0x0000C001
17294 #trigger VreFPHY training
17295 poll 0xFD080030 0x00000C01 0x00000C01
17297 #//Poll PUB_PGSR0 for Trng complete
17298 mwr -force 0xFD070180 0x01000040
17299 mwr -force 0xFD070060 0x00000000
17300 psu_mask_write 0xFD080014 0x00000040 0x00000000