git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
   4 *
   5 *  This program is free software; you can redistribute it and/or modify
   6 *  it under the terms of the GNU General Public License as published by
   7 *  the Free Software Foundation; either version 2 of the License, or
   8 *  (at your option) any later version.
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License along
  16 *  with this program; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 *
  19 ******************************************************************************/
  20
  21 #include <xil_io.h>
  22 #include "psu_init_gpl.h"
  23
  24 static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
  25 {
  26         unsigned long RegVal = 0x0;
  27         RegVal = Xil_In32 (offset);
  28         RegVal &= ~(mask);
  29         RegVal |= (val & mask);
  30         Xil_Out32 (offset, RegVal);
  31 }
  32
  33 unsigned long psu_pll_init_data() {
  34                 // : RPLL INIT
  35                 /*Register : RPLL_CFG @ 0XFF5E0034</p>
  36
  37                 PLL loop filter resistor control
  38                 PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
  39
  40                 PLL charge pump control
  41                 PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
  42
  43                 PLL loop filter high frequency capacitor control
  44                 PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
  45
  46                 Lock circuit counter setting
  47                 PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
  48
  49                 Lock circuit configuration settings for lock windowsize
  50                 PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
  51
  52                 Helper data. Values are to be looked up in a table from Data Sheet
  53                 (OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)
  54                 RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK |  0 );
  55
  56                 RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT
  57                         | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT
  58                         | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT
  59                         | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
  60                         | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
  61                         |  0 ) & RegMask); */
  62                 PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
  63         /*############################################################################################################################ */
  64
  65                 // : UPDATE FB_DIV
  66                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
  67
  68                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
  69                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
  70                 PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
  71
  72                 The integer portion of the feedback divider to the PLL
  73                 PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
  74
  75                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
  76                 PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
  77
  78                 PLL Basic Control
  79                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)
  80                 RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
  81
  82                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
  83                         | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
  84                         | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
  85                         |  0 ) & RegMask); */
  86                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
  87         /*############################################################################################################################ */
  88
  89                 // : BY PASS PLL
  90                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
  91
  92                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
  93                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
  94                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
  95
  96                 PLL Basic Control
  97                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)
  98                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
  99
 100                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 101                         |  0 ) & RegMask); */
 102                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 103         /*############################################################################################################################ */
 104
 105                 // : ASSERT RESET
 106                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 107
 108                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 109                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
 110
 111                 PLL Basic Control
 112                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)
 113                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 114
 115                 RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 116                         |  0 ) & RegMask); */
 117                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 118         /*############################################################################################################################ */
 119
 120                 // : DEASSERT RESET
 121                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 122
 123                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 124                 PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
 125
 126                 PLL Basic Control
 127                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)
 128                 RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
 129
 130                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
 131                         |  0 ) & RegMask); */
 132                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 133         /*############################################################################################################################ */
 134
 135                 // : CHECK PLL STATUS
 136                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 137
 138                 RPLL is locked
 139                 PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
 140                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
 141                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U);
 142
 143         /*############################################################################################################################ */
 144
 145                 // : REMOVE PLL BY PASS
 146                 /*Register : RPLL_CTRL @ 0XFF5E0030</p>
 147
 148                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 149                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 150                 PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
 151
 152                 PLL Basic Control
 153                 (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)
 154                 RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
 155
 156                 RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
 157                         |  0 ) & RegMask); */
 158                 PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 159         /*############################################################################################################################ */
 160
 161                 /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
 162
 163                 Divisor value for this clock.
 164                 PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
 165
 166                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 167                 (OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)
 168                 RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 169
 170                 RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 171                         |  0 ) & RegMask); */
 172                 PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 173         /*############################################################################################################################ */
 174
 175                 // : RPLL FRAC CFG
 176                 /*Register : RPLL_FRAC_CFG @ 0XFF5E0038</p>
 177
 178                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 179                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 180                 PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
 181
 182                 Fractional value for the Feedback value.
 183                 PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
 184
 185                 Fractional control for the PLL
 186                 (OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)
 187                 RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK |  0 );
 188
 189                 RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
 190                         | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
 191                         |  0 ) & RegMask); */
 192                 PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 193         /*############################################################################################################################ */
 194
 195                 // : IOPLL INIT
 196                 /*Register : IOPLL_CFG @ 0XFF5E0024</p>
 197
 198                 PLL loop filter resistor control
 199                 PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
 200
 201                 PLL charge pump control
 202                 PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
 203
 204                 PLL loop filter high frequency capacitor control
 205                 PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
 206
 207                 Lock circuit counter setting
 208                 PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
 209
 210                 Lock circuit configuration settings for lock windowsize
 211                 PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
 212
 213                 Helper data. Values are to be looked up in a table from Data Sheet
 214                 (OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)
 215                 RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK |  0 );
 216
 217                 RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT
 218                         | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT
 219                         | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT
 220                         | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
 221                         | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
 222                         |  0 ) & RegMask); */
 223                 PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU);
 224         /*############################################################################################################################ */
 225
 226                 // : UPDATE FB_DIV
 227                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 228
 229                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 230                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 231                 PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
 232
 233                 The integer portion of the feedback divider to the PLL
 234                 PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
 235
 236                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 237                 PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
 238
 239                 PLL Basic Control
 240                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)
 241                 RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
 242
 243                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
 244                         | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
 245                         | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
 246                         |  0 ) & RegMask); */
 247                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U);
 248         /*############################################################################################################################ */
 249
 250                 // : BY PASS PLL
 251                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 252
 253                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 254                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 255                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
 256
 257                 PLL Basic Control
 258                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)
 259                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 260
 261                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 262                         |  0 ) & RegMask); */
 263                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 264         /*############################################################################################################################ */
 265
 266                 // : ASSERT RESET
 267                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 268
 269                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 270                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
 271
 272                 PLL Basic Control
 273                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)
 274                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 275
 276                 RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 277                         |  0 ) & RegMask); */
 278                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 279         /*############################################################################################################################ */
 280
 281                 // : DEASSERT RESET
 282                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 283
 284                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 285                 PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
 286
 287                 PLL Basic Control
 288                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)
 289                 RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
 290
 291                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
 292                         |  0 ) & RegMask); */
 293                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 294         /*############################################################################################################################ */
 295
 296                 // : CHECK PLL STATUS
 297                 /*Register : PLL_STATUS @ 0XFF5E0040</p>
 298
 299                 IOPLL is locked
 300                 PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
 301                 (OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
 302                 mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U);
 303
 304         /*############################################################################################################################ */
 305
 306                 // : REMOVE PLL BY PASS
 307                 /*Register : IOPLL_CTRL @ 0XFF5E0020</p>
 308
 309                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 310                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 311                 PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
 312
 313                 PLL Basic Control
 314                 (OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)
 315                 RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
 316
 317                 RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
 318                         |  0 ) & RegMask); */
 319                 PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 320         /*############################################################################################################################ */
 321
 322                 /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
 323
 324                 Divisor value for this clock.
 325                 PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
 326
 327                 Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
 328                 (OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)
 329                 RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
 330
 331                 RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
 332                         |  0 ) & RegMask); */
 333                 PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 334         /*############################################################################################################################ */
 335
 336                 // : IOPLL FRAC CFG
 337                 /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028</p>
 338
 339                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 340                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 341                 PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
 342
 343                 Fractional value for the Feedback value.
 344                 PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
 345
 346                 Fractional control for the PLL
 347                 (OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)
 348                 RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK |  0 );
 349
 350                 RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
 351                         | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
 352                         |  0 ) & RegMask); */
 353                 PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 354         /*############################################################################################################################ */
 355
 356                 // : APU_PLL INIT
 357                 /*Register : APLL_CFG @ 0XFD1A0024</p>
 358
 359                 PLL loop filter resistor control
 360                 PSU_CRF_APB_APLL_CFG_RES                                                        0x2
 361
 362                 PLL charge pump control
 363                 PSU_CRF_APB_APLL_CFG_CP                                                         0x3
 364
 365                 PLL loop filter high frequency capacitor control
 366                 PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
 367
 368                 Lock circuit counter setting
 369                 PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
 370
 371                 Lock circuit configuration settings for lock windowsize
 372                 PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
 373
 374                 Helper data. Values are to be looked up in a table from Data Sheet
 375                 (OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
 376                 RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK |  0 );
 377
 378                 RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT
 379                         | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT
 380                         | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT
 381                         | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
 382                         | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
 383                         |  0 ) & RegMask); */
 384                 PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 385         /*############################################################################################################################ */
 386
 387                 // : UPDATE FB_DIV
 388                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 389
 390                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 391                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 392                 PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
 393
 394                 The integer portion of the feedback divider to the PLL
 395                 PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x42
 396
 397                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 398                 PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
 399
 400                 PLL Basic Control
 401                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014200U)
 402                 RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
 403
 404                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
 405                         | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT
 406                         | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
 407                         |  0 ) & RegMask); */
 408                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U);
 409         /*############################################################################################################################ */
 410
 411                 // : BY PASS PLL
 412                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 413
 414                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 415                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 416                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
 417
 418                 PLL Basic Control
 419                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)
 420                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 421
 422                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 423                         |  0 ) & RegMask); */
 424                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 425         /*############################################################################################################################ */
 426
 427                 // : ASSERT RESET
 428                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 429
 430                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 431                 PSU_CRF_APB_APLL_CTRL_RESET                                                     1
 432
 433                 PLL Basic Control
 434                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)
 435                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 436
 437                 RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
 438                         |  0 ) & RegMask); */
 439                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 440         /*############################################################################################################################ */
 441
 442                 // : DEASSERT RESET
 443                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 444
 445                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 446                 PSU_CRF_APB_APLL_CTRL_RESET                                                     0
 447
 448                 PLL Basic Control
 449                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)
 450                 RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
 451
 452                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
 453                         |  0 ) & RegMask); */
 454                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 455         /*############################################################################################################################ */
 456
 457                 // : CHECK PLL STATUS
 458                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 459
 460                 APLL is locked
 461                 PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
 462                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
 463                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U);
 464
 465         /*############################################################################################################################ */
 466
 467                 // : REMOVE PLL BY PASS
 468                 /*Register : APLL_CTRL @ 0XFD1A0020</p>
 469
 470                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 471                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 472                 PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
 473
 474                 PLL Basic Control
 475                 (OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)
 476                 RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
 477
 478                 RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
 479                         |  0 ) & RegMask); */
 480                 PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 481         /*############################################################################################################################ */
 482
 483                 /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
 484
 485                 Divisor value for this clock.
 486                 PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 487
 488                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 489                 (OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)
 490                 RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 491
 492                 RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 493                         |  0 ) & RegMask); */
 494                 PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 495         /*############################################################################################################################ */
 496
 497                 // : APLL FRAC CFG
 498                 /*Register : APLL_FRAC_CFG @ 0XFD1A0028</p>
 499
 500                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 501                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 502                 PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
 503
 504                 Fractional value for the Feedback value.
 505                 PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
 506
 507                 Fractional control for the PLL
 508                 (OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)
 509                 RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK |  0 );
 510
 511                 RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
 512                         | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
 513                         |  0 ) & RegMask); */
 514                 PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 515         /*############################################################################################################################ */
 516
 517                 // : DDR_PLL INIT
 518                 /*Register : DPLL_CFG @ 0XFD1A0030</p>
 519
 520                 PLL loop filter resistor control
 521                 PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
 522
 523                 PLL charge pump control
 524                 PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
 525
 526                 PLL loop filter high frequency capacitor control
 527                 PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
 528
 529                 Lock circuit counter setting
 530                 PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
 531
 532                 Lock circuit configuration settings for lock windowsize
 533                 PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
 534
 535                 Helper data. Values are to be looked up in a table from Data Sheet
 536                 (OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
 537                 RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK |  0 );
 538
 539                 RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT
 540                         | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT
 541                         | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT
 542                         | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
 543                         | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
 544                         |  0 ) & RegMask); */
 545                 PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
 546         /*############################################################################################################################ */
 547
 548                 // : UPDATE FB_DIV
 549                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 550
 551                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 552                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 553                 PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
 554
 555                 The integer portion of the feedback divider to the PLL
 556                 PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
 557
 558                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 559                 PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
 560
 561                 PLL Basic Control
 562                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)
 563                 RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
 564
 565                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
 566                         | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
 567                         | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
 568                         |  0 ) & RegMask); */
 569                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U);
 570         /*############################################################################################################################ */
 571
 572                 // : BY PASS PLL
 573                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 574
 575                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 576                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 577                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
 578
 579                 PLL Basic Control
 580                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)
 581                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 582
 583                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 584                         |  0 ) & RegMask); */
 585                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 586         /*############################################################################################################################ */
 587
 588                 // : ASSERT RESET
 589                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 590
 591                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 592                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
 593
 594                 PLL Basic Control
 595                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)
 596                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 597
 598                 RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 599                         |  0 ) & RegMask); */
 600                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 601         /*############################################################################################################################ */
 602
 603                 // : DEASSERT RESET
 604                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 605
 606                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 607                 PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
 608
 609                 PLL Basic Control
 610                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)
 611                 RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
 612
 613                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
 614                         |  0 ) & RegMask); */
 615                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 616         /*############################################################################################################################ */
 617
 618                 // : CHECK PLL STATUS
 619                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 620
 621                 DPLL is locked
 622                 PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
 623                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
 624                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U);
 625
 626         /*############################################################################################################################ */
 627
 628                 // : REMOVE PLL BY PASS
 629                 /*Register : DPLL_CTRL @ 0XFD1A002C</p>
 630
 631                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 632                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 633                 PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
 634
 635                 PLL Basic Control
 636                 (OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)
 637                 RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
 638
 639                 RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
 640                         |  0 ) & RegMask); */
 641                 PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 642         /*############################################################################################################################ */
 643
 644                 /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
 645
 646                 Divisor value for this clock.
 647                 PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 648
 649                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 650                 (OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)
 651                 RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 652
 653                 RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 654                         |  0 ) & RegMask); */
 655                 PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 656         /*############################################################################################################################ */
 657
 658                 // : DPLL FRAC CFG
 659                 /*Register : DPLL_FRAC_CFG @ 0XFD1A0034</p>
 660
 661                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 662                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 663                 PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
 664
 665                 Fractional value for the Feedback value.
 666                 PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
 667
 668                 Fractional control for the PLL
 669                 (OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)
 670                 RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK |  0 );
 671
 672                 RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
 673                         | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
 674                         |  0 ) & RegMask); */
 675                 PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
 676         /*############################################################################################################################ */
 677
 678                 // : VIDEO_PLL INIT
 679                 /*Register : VPLL_CFG @ 0XFD1A003C</p>
 680
 681                 PLL loop filter resistor control
 682                 PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
 683
 684                 PLL charge pump control
 685                 PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
 686
 687                 PLL loop filter high frequency capacitor control
 688                 PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
 689
 690                 Lock circuit counter setting
 691                 PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
 692
 693                 Lock circuit configuration settings for lock windowsize
 694                 PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
 695
 696                 Helper data. Values are to be looked up in a table from Data Sheet
 697                 (OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)
 698                 RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK |  0 );
 699
 700                 RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT
 701                         | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT
 702                         | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT
 703                         | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
 704                         | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
 705                         |  0 ) & RegMask); */
 706                 PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U);
 707         /*############################################################################################################################ */
 708
 709                 // : UPDATE FB_DIV
 710                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 711
 712                 Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
 713                 ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 714                 PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
 715
 716                 The integer portion of the feedback divider to the PLL
 717                 PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
 718
 719                 This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
 720                 PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
 721
 722                 PLL Basic Control
 723                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)
 724                 RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
 725
 726                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
 727                         | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
 728                         | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
 729                         |  0 ) & RegMask); */
 730                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U);
 731         /*############################################################################################################################ */
 732
 733                 // : BY PASS PLL
 734                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 735
 736                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 737                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 738                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
 739
 740                 PLL Basic Control
 741                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)
 742                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 743
 744                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 745                         |  0 ) & RegMask); */
 746                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
 747         /*############################################################################################################################ */
 748
 749                 // : ASSERT RESET
 750                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 751
 752                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 753                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
 754
 755                 PLL Basic Control
 756                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)
 757                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 758
 759                 RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 760                         |  0 ) & RegMask); */
 761                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
 762         /*############################################################################################################################ */
 763
 764                 // : DEASSERT RESET
 765                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 766
 767                 Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
 768                 PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
 769
 770                 PLL Basic Control
 771                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)
 772                 RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
 773
 774                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
 775                         |  0 ) & RegMask); */
 776                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
 777         /*############################################################################################################################ */
 778
 779                 // : CHECK PLL STATUS
 780                 /*Register : PLL_STATUS @ 0XFD1A0044</p>
 781
 782                 VPLL is locked
 783                 PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
 784                 (OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
 785                 mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U);
 786
 787         /*############################################################################################################################ */
 788
 789                 // : REMOVE PLL BY PASS
 790                 /*Register : VPLL_CTRL @ 0XFD1A0038</p>
 791
 792                 Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
 793                 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
 794                 PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
 795
 796                 PLL Basic Control
 797                 (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)
 798                 RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
 799
 800                 RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
 801                         |  0 ) & RegMask); */
 802                 PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
 803         /*############################################################################################################################ */
 804
 805                 /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
 806
 807                 Divisor value for this clock.
 808                 PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
 809
 810                 Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
 811                 (OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)
 812                 RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
 813
 814                 RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
 815                         |  0 ) & RegMask); */
 816                 PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
 817         /*############################################################################################################################ */
 818
 819                 // : VIDEO FRAC CFG
 820                 /*Register : VPLL_FRAC_CFG @ 0XFD1A0040</p>
 821
 822                 Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
 823                  mode and uses DATA of this register for the fractional portion of the feedback divider.
 824                 PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
 825
 826                 Fractional value for the Feedback value.
 827                 PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
 828
 829                 Fractional control for the PLL
 830                 (OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)
 831                 RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK |  0 );
 832
 833                 RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
 834                         | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
 835                         |  0 ) & RegMask); */
 836                 PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU);
 837         /*############################################################################################################################ */
 838
 839
 840   return 1;
 841 }
 842 unsigned long psu_clock_init_data() {
 843                 // : CLOCK CONTROL SLCR REGISTER
 844                 /*Register : GEM0_REF_CTRL @ 0XFF5E0050</p>
 845
 846                 Clock active for the RX channel
 847                 PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
 848
 849                 Clock active signal. Switch to 0 to disable the clock
 850                 PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
 851
 852                 6 bit divider
 853                 PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x1
 854
 855                 6 bit divider
 856                 PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x8
 857
 858                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 859                 clock. This is not usually an issue, but designers must be aware.)
 860                 PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
 861
 862                 This register controls this reference clock
 863                 (OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06010800U)
 864                 RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );
 865
 866                 RegVal = ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
 867                         | 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
 868                         | 0x00000001U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
 869                         | 0x00000008U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
 870                         | 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
 871                         |  0 ) & RegMask); */
 872                 PSU_Mask_Write (CRL_APB_GEM0_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
 873         /*############################################################################################################################ */
 874
 875                 /*Register : GEM1_REF_CTRL @ 0XFF5E0054</p>
 876
 877                 Clock active for the RX channel
 878                 PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
 879
 880                 Clock active signal. Switch to 0 to disable the clock
 881                 PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
 882
 883                 6 bit divider
 884                 PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x1
 885
 886                 6 bit divider
 887                 PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x8
 888
 889                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 890                 clock. This is not usually an issue, but designers must be aware.)
 891                 PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
 892
 893                 This register controls this reference clock
 894                 (OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06010800U)
 895                 RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );
 896
 897                 RegVal = ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
 898                         | 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
 899                         | 0x00000001U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
 900                         | 0x00000008U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
 901                         | 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
 902                         |  0 ) & RegMask); */
 903                 PSU_Mask_Write (CRL_APB_GEM1_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
 904         /*############################################################################################################################ */
 905
 906                 /*Register : GEM2_REF_CTRL @ 0XFF5E0058</p>
 907
 908                 Clock active for the RX channel
 909                 PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
 910
 911                 Clock active signal. Switch to 0 to disable the clock
 912                 PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
 913
 914                 6 bit divider
 915                 PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x1
 916
 917                 6 bit divider
 918                 PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x8
 919
 920                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 921                 clock. This is not usually an issue, but designers must be aware.)
 922                 PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
 923
 924                 This register controls this reference clock
 925                 (OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06010800U)
 926                 RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );
 927
 928                 RegVal = ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
 929                         | 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
 930                         | 0x00000001U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
 931                         | 0x00000008U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
 932                         | 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
 933                         |  0 ) & RegMask); */
 934                 PSU_Mask_Write (CRL_APB_GEM2_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
 935         /*############################################################################################################################ */
 936
 937                 /*Register : GEM3_REF_CTRL @ 0XFF5E005C</p>
 938
 939                 Clock active for the RX channel
 940                 PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
 941
 942                 Clock active signal. Switch to 0 to disable the clock
 943                 PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
 944
 945                 6 bit divider
 946                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
 947
 948                 6 bit divider
 949                 PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
 950
 951                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 952                 clock. This is not usually an issue, but designers must be aware.)
 953                 PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
 954
 955                 This register controls this reference clock
 956                 (OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
 957                 RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
 958
 959                 RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
 960                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
 961                         | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
 962                         | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
 963                         | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
 964                         |  0 ) & RegMask); */
 965                 PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
 966         /*############################################################################################################################ */
 967
 968                 /*Register : GEM_TSU_REF_CTRL @ 0XFF5E0100</p>
 969
 970                 6 bit divider
 971                 PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0                                           0x6
 972
 973                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
 974                 clock. This is not usually an issue, but designers must be aware.)
 975                 PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL                                             0x2
 976
 977                 6 bit divider
 978                 PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1                                           0x1
 979
 980                 Clock active signal. Switch to 0 to disable the clock
 981                 PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT                                             0x1
 982
 983                 This register controls this reference clock
 984                 (OFFSET, MASK, VALUE)      (0XFF5E0100, 0x013F3F07U ,0x01010602U)
 985                 RegMask = (CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK | CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK |  0 );
 986
 987                 RegVal = ((0x00000006U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
 988                         | 0x00000002U << CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
 989                         | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
 990                         | 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
 991                         |  0 ) & RegMask); */
 992                 PSU_Mask_Write (CRL_APB_GEM_TSU_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
 993         /*############################################################################################################################ */
 994
 995                 /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
 996
 997                 Clock active signal. Switch to 0 to disable the clock
 998                 PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
 999
1000                 6 bit divider
1001                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
1002
1003                 6 bit divider
1004                 PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
1005
1006                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1007                 clock. This is not usually an issue, but designers must be aware.)
1008                 PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
1009
1010                 This register controls this reference clock
1011                 (OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)
1012                 RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
1013
1014                 RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
1015                         | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
1016                         | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
1017                         | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
1018                         |  0 ) & RegMask); */
1019                 PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
1020         /*############################################################################################################################ */
1021
1022                 /*Register : USB1_BUS_REF_CTRL @ 0XFF5E0064</p>
1023
1024                 Clock active signal. Switch to 0 to disable the clock
1025                 PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT                                            0x1
1026
1027                 6 bit divider
1028                 PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1                                          0x1
1029
1030                 6 bit divider
1031                 PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0                                          0x4
1032
1033                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1034                 clock. This is not usually an issue, but designers must be aware.)
1035                 PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL                                            0x0
1036
1037                 This register controls this reference clock
1038                 (OFFSET, MASK, VALUE)      (0XFF5E0064, 0x023F3F07U ,0x02010400U)
1039                 RegMask = (CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK |  0 );
1040
1041                 RegVal = ((0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
1042                         | 0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
1043                         | 0x00000004U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
1044                         | 0x00000000U << CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
1045                         |  0 ) & RegMask); */
1046                 PSU_Mask_Write (CRL_APB_USB1_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010400U);
1047         /*############################################################################################################################ */
1048
1049                 /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
1050
1051                 Clock active signal. Switch to 0 to disable the clock
1052                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
1053
1054                 6 bit divider
1055                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
1056
1057                 6 bit divider
1058                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
1059
1060                 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1061                 clock. This is not usually an issue, but designers must be aware.)
1062                 PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
1063
1064                 This register controls this reference clock
1065                 (OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)
1066                 RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
1067
1068                 RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
1069                         | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
1070                         | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
1071                         | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
1072                         |  0 ) & RegMask); */
1073                 PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U);
1074         /*############################################################################################################################ */
1075
1076                 /*Register : QSPI_REF_CTRL @ 0XFF5E0068</p>
1077
1078                 Clock active signal. Switch to 0 to disable the clock
1079                 PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
1080
1081                 6 bit divider
1082                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
1083
1084                 6 bit divider
1085                 PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
1086
1087                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1088                 clock. This is not usually an issue, but designers must be aware.)
1089                 PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
1090
1091                 This register controls this reference clock
1092                 (OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
1093                 RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
1094
1095                 RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
1096                         | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
1097                         | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
1098                         | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
1099                         |  0 ) & RegMask); */
1100                 PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
1101         /*############################################################################################################################ */
1102
1103                 /*Register : SDIO0_REF_CTRL @ 0XFF5E006C</p>
1104
1105                 Clock active signal. Switch to 0 to disable the clock
1106                 PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
1107
1108                 6 bit divider
1109                 PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x1
1110
1111                 6 bit divider
1112                 PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x7
1113
1114                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1115                 clock. This is not usually an issue, but designers must be aware.)
1116                 PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x2
1117
1118                 This register controls this reference clock
1119                 (OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01010702U)
1120                 RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );
1121
1122                 RegVal = ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
1123                         | 0x00000001U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
1124                         | 0x00000007U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
1125                         | 0x00000002U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
1126                         |  0 ) & RegMask); */
1127                 PSU_Mask_Write (CRL_APB_SDIO0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
1128         /*############################################################################################################################ */
1129
1130                 /*Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
1131
1132                 Clock active signal. Switch to 0 to disable the clock
1133                 PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
1134
1135                 6 bit divider
1136                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
1137
1138                 6 bit divider
1139                 PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
1140
1141                 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1142                 clock. This is not usually an issue, but designers must be aware.)
1143                 PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
1144
1145                 This register controls this reference clock
1146                 (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)
1147                 RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
1148
1149                 RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
1150                         | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
1151                         | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
1152                         | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
1153                         |  0 ) & RegMask); */
1154                 PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
1155         /*############################################################################################################################ */
1156
1157                 /*Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
1158
1159                 MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
1160                 PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
1161
1162                 SoC Debug Clock Control
1163                 (OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)
1164                 RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK |  0 );
1165
1166                 RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
1167                         |  0 ) & RegMask); */
1168                 PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U);
1169         /*############################################################################################################################ */
1170
1171                 /*Register : UART0_REF_CTRL @ 0XFF5E0074</p>
1172
1173                 Clock active signal. Switch to 0 to disable the clock
1174                 PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
1175
1176                 6 bit divider
1177                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
1178
1179                 6 bit divider
1180                 PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
1181
1182                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1183                 clock. This is not usually an issue, but designers must be aware.)
1184                 PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
1185
1186                 This register controls this reference clock
1187                 (OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
1188                 RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
1189
1190                 RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
1191                         | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
1192                         | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
1193                         | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
1194                         |  0 ) & RegMask); */
1195                 PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1196         /*############################################################################################################################ */
1197
1198                 /*Register : UART1_REF_CTRL @ 0XFF5E0078</p>
1199
1200                 Clock active signal. Switch to 0 to disable the clock
1201                 PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
1202
1203                 6 bit divider
1204                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
1205
1206                 6 bit divider
1207                 PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
1208
1209                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1210                 clock. This is not usually an issue, but designers must be aware.)
1211                 PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
1212
1213                 This register controls this reference clock
1214                 (OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
1215                 RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
1216
1217                 RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
1218                         | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
1219                         | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
1220                         | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
1221                         |  0 ) & RegMask); */
1222                 PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1223         /*############################################################################################################################ */
1224
1225                 /*Register : I2C0_REF_CTRL @ 0XFF5E0120</p>
1226
1227                 Clock active signal. Switch to 0 to disable the clock
1228                 PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
1229
1230                 6 bit divider
1231                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
1232
1233                 6 bit divider
1234                 PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
1235
1236                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1237                 clock. This is not usually an issue, but designers must be aware.)
1238                 PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
1239
1240                 This register controls this reference clock
1241                 (OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
1242                 RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
1243
1244                 RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
1245                         | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
1246                         | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
1247                         | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
1248                         |  0 ) & RegMask); */
1249                 PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1250         /*############################################################################################################################ */
1251
1252                 /*Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
1253
1254                 Clock active signal. Switch to 0 to disable the clock
1255                 PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
1256
1257                 6 bit divider
1258                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
1259
1260                 6 bit divider
1261                 PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
1262
1263                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1264                 clock. This is not usually an issue, but designers must be aware.)
1265                 PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
1266
1267                 This register controls this reference clock
1268                 (OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
1269                 RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
1270
1271                 RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
1272                         | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
1273                         | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
1274                         | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
1275                         |  0 ) & RegMask); */
1276                 PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1277         /*############################################################################################################################ */
1278
1279                 /*Register : SPI0_REF_CTRL @ 0XFF5E007C</p>
1280
1281                 Clock active signal. Switch to 0 to disable the clock
1282                 PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
1283
1284                 6 bit divider
1285                 PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x1
1286
1287                 6 bit divider
1288                 PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x7
1289
1290                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1291                 clock. This is not usually an issue, but designers must be aware.)
1292                 PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x2
1293
1294                 This register controls this reference clock
1295                 (OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01010702U)
1296                 RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );
1297
1298                 RegVal = ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
1299                         | 0x00000001U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
1300                         | 0x00000007U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
1301                         | 0x00000002U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
1302                         |  0 ) & RegMask); */
1303                 PSU_Mask_Write (CRL_APB_SPI0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
1304         /*############################################################################################################################ */
1305
1306                 /*Register : SPI1_REF_CTRL @ 0XFF5E0080</p>
1307
1308                 Clock active signal. Switch to 0 to disable the clock
1309                 PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
1310
1311                 6 bit divider
1312                 PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0x1
1313
1314                 6 bit divider
1315                 PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x7
1316
1317                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1318                 clock. This is not usually an issue, but designers must be aware.)
1319                 PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x2
1320
1321                 This register controls this reference clock
1322                 (OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x01010702U)
1323                 RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );
1324
1325                 RegVal = ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
1326                         | 0x00000001U << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
1327                         | 0x00000007U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
1328                         | 0x00000002U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
1329                         |  0 ) & RegMask); */
1330                 PSU_Mask_Write (CRL_APB_SPI1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
1331         /*############################################################################################################################ */
1332
1333                 /*Register : CAN0_REF_CTRL @ 0XFF5E0084</p>
1334
1335                 Clock active signal. Switch to 0 to disable the clock
1336                 PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
1337
1338                 6 bit divider
1339                 PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x1
1340
1341                 6 bit divider
1342                 PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0xa
1343
1344                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1345                 clock. This is not usually an issue, but designers must be aware.)
1346                 PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
1347
1348                 This register controls this reference clock
1349                 (OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01010A00U)
1350                 RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );
1351
1352                 RegVal = ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
1353                         | 0x00000001U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
1354                         | 0x0000000AU << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
1355                         | 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
1356                         |  0 ) & RegMask); */
1357                 PSU_Mask_Write (CRL_APB_CAN0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
1358         /*############################################################################################################################ */
1359
1360                 /*Register : CAN1_REF_CTRL @ 0XFF5E0088</p>
1361
1362                 Clock active signal. Switch to 0 to disable the clock
1363                 PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
1364
1365                 6 bit divider
1366                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
1367
1368                 6 bit divider
1369                 PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
1370
1371                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1372                 clock. This is not usually an issue, but designers must be aware.)
1373                 PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
1374
1375                 This register controls this reference clock
1376                 (OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
1377                 RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
1378
1379                 RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
1380                         | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
1381                         | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
1382                         | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
1383                         |  0 ) & RegMask); */
1384                 PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1385         /*############################################################################################################################ */
1386
1387                 /*Register : CPU_R5_CTRL @ 0XFF5E0090</p>
1388
1389                 Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
1390                 d lead to system hang
1391                 PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
1392
1393                 6 bit divider
1394                 PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
1395
1396                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1397                 clock. This is not usually an issue, but designers must be aware.)
1398                 PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
1399
1400                 This register controls this reference clock
1401                 (OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)
1402                 RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
1403
1404                 RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
1405                         | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
1406                         | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
1407                         |  0 ) & RegMask); */
1408                 PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1409         /*############################################################################################################################ */
1410
1411                 /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
1412
1413                 Clock active signal. Switch to 0 to disable the clock
1414                 PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
1415
1416                 6 bit divider
1417                 PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
1418
1419                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1420                 clock. This is not usually an issue, but designers must be aware.)
1421                 PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
1422
1423                 This register controls this reference clock
1424                 (OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)
1425                 RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
1426
1427                 RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
1428                         | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
1429                         | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
1430                         |  0 ) & RegMask); */
1431                 PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1432         /*############################################################################################################################ */
1433
1434                 /*Register : CSU_PLL_CTRL @ 0XFF5E00A0</p>
1435
1436                 Clock active signal. Switch to 0 to disable the clock
1437                 PSU_CRL_APB_CSU_PLL_CTRL_CLKACT                                                 0x1
1438
1439                 6 bit divider
1440                 PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0                                               0x3
1441
1442                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1443                 clock. This is not usually an issue, but designers must be aware.)
1444                 PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL                                                 0x2
1445
1446                 This register controls this reference clock
1447                 (OFFSET, MASK, VALUE)      (0XFF5E00A0, 0x01003F07U ,0x01000302U)
1448                 RegMask = (CRL_APB_CSU_PLL_CTRL_CLKACT_MASK | CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK | CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK |  0 );
1449
1450                 RegVal = ((0x00000001U << CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
1451                         | 0x00000003U << CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
1452                         | 0x00000002U << CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
1453                         |  0 ) & RegMask); */
1454                 PSU_Mask_Write (CRL_APB_CSU_PLL_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1455         /*############################################################################################################################ */
1456
1457                 /*Register : PCAP_CTRL @ 0XFF5E00A4</p>
1458
1459                 Clock active signal. Switch to 0 to disable the clock
1460                 PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
1461
1462                 6 bit divider
1463                 PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
1464
1465                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1466                 clock. This is not usually an issue, but designers must be aware.)
1467                 PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
1468
1469                 This register controls this reference clock
1470                 (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)
1471                 RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
1472
1473                 RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
1474                         | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
1475                         | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
1476                         |  0 ) & RegMask); */
1477                 PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1478         /*############################################################################################################################ */
1479
1480                 /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
1481
1482                 Clock active signal. Switch to 0 to disable the clock
1483                 PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
1484
1485                 6 bit divider
1486                 PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
1487
1488                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1489                 clock. This is not usually an issue, but designers must be aware.)
1490                 PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
1491
1492                 This register controls this reference clock
1493                 (OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)
1494                 RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
1495
1496                 RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
1497                         | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
1498                         | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
1499                         |  0 ) & RegMask); */
1500                 PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1501         /*############################################################################################################################ */
1502
1503                 /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
1504
1505                 Clock active signal. Switch to 0 to disable the clock
1506                 PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
1507
1508                 6 bit divider
1509                 PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
1510
1511                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1512                 clock. This is not usually an issue, but designers must be aware.)
1513                 PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
1514
1515                 This register controls this reference clock
1516                 (OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
1517                 RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
1518
1519                 RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
1520                         | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
1521                         | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
1522                         |  0 ) & RegMask); */
1523                 PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U);
1524         /*############################################################################################################################ */
1525
1526                 /*Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
1527
1528                 Clock active signal. Switch to 0 to disable the clock
1529                 PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
1530
1531                 6 bit divider
1532                 PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
1533
1534                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1535                 clock. This is not usually an issue, but designers must be aware.)
1536                 PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
1537
1538                 This register controls this reference clock
1539                 (OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)
1540                 RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
1541
1542                 RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
1543                         | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
1544                         | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
1545                         |  0 ) & RegMask); */
1546                 PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
1547         /*############################################################################################################################ */
1548
1549                 /*Register : NAND_REF_CTRL @ 0XFF5E00B4</p>
1550
1551                 Clock active signal. Switch to 0 to disable the clock
1552                 PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
1553
1554                 6 bit divider
1555                 PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x1
1556
1557                 6 bit divider
1558                 PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0xa
1559
1560                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1561                 clock. This is not usually an issue, but designers must be aware.)
1562                 PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
1563
1564                 This register controls this reference clock
1565                 (OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)
1566                 RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );
1567
1568                 RegVal = ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
1569                         | 0x00000001U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
1570                         | 0x0000000AU << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
1571                         | 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
1572                         |  0 ) & RegMask); */
1573                 PSU_Mask_Write (CRL_APB_NAND_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
1574         /*############################################################################################################################ */
1575
1576                 /*Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
1577
1578                 Clock active signal. Switch to 0 to disable the clock
1579                 PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
1580
1581                 6 bit divider
1582                 PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
1583
1584                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1585                 clock. This is not usually an issue, but designers must be aware.)
1586                 PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
1587
1588                 This register controls this reference clock
1589                 (OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)
1590                 RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
1591
1592                 RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
1593                         | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
1594                         | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
1595                         |  0 ) & RegMask); */
1596                 PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
1597         /*############################################################################################################################ */
1598
1599                 /*Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
1600
1601                 Clock active signal. Switch to 0 to disable the clock
1602                 PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
1603
1604                 6 bit divider
1605                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
1606
1607                 6 bit divider
1608                 PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
1609
1610                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1611                 clock. This is not usually an issue, but designers must be aware.)
1612                 PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
1613
1614                 This register controls this reference clock
1615                 (OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
1616                 RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK |  0 );
1617
1618                 RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
1619                         | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
1620                         | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
1621                         | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
1622                         |  0 ) & RegMask); */
1623                 PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
1624         /*############################################################################################################################ */
1625
1626                 /*Register : PL1_REF_CTRL @ 0XFF5E00C4</p>
1627
1628                 Clock active signal. Switch to 0 to disable the clock
1629                 PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
1630
1631                 6 bit divider
1632                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
1633
1634                 6 bit divider
1635                 PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
1636
1637                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1638                 clock. This is not usually an issue, but designers must be aware.)
1639                 PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
1640
1641                 This register controls this reference clock
1642                 (OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)
1643                 RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK |  0 );
1644
1645                 RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
1646                         | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
1647                         | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
1648                         | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
1649                         |  0 ) & RegMask); */
1650                 PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U);
1651         /*############################################################################################################################ */
1652
1653                 /*Register : PL2_REF_CTRL @ 0XFF5E00C8</p>
1654
1655                 Clock active signal. Switch to 0 to disable the clock
1656                 PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
1657
1658                 6 bit divider
1659                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
1660
1661                 6 bit divider
1662                 PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
1663
1664                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1665                 clock. This is not usually an issue, but designers must be aware.)
1666                 PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
1667
1668                 This register controls this reference clock
1669                 (OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)
1670                 RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK |  0 );
1671
1672                 RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
1673                         | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
1674                         | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
1675                         | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
1676                         |  0 ) & RegMask); */
1677                 PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U);
1678         /*############################################################################################################################ */
1679
1680                 /*Register : PL3_REF_CTRL @ 0XFF5E00CC</p>
1681
1682                 Clock active signal. Switch to 0 to disable the clock
1683                 PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
1684
1685                 6 bit divider
1686                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
1687
1688                 6 bit divider
1689                 PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
1690
1691                 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1692                 clock. This is not usually an issue, but designers must be aware.)
1693                 PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
1694
1695                 This register controls this reference clock
1696                 (OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)
1697                 RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK |  0 );
1698
1699                 RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
1700                         | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
1701                         | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
1702                         | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
1703                         |  0 ) & RegMask); */
1704                 PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U);
1705         /*############################################################################################################################ */
1706
1707                 /*Register : AMS_REF_CTRL @ 0XFF5E0108</p>
1708
1709                 6 bit divider
1710                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
1711
1712                 6 bit divider
1713                 PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
1714
1715                 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1716                 clock. This is not usually an issue, but designers must be aware.)
1717                 PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
1718
1719                 Clock active signal. Switch to 0 to disable the clock
1720                 PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
1721
1722                 This register controls this reference clock
1723                 (OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)
1724                 RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
1725
1726                 RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
1727                         | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
1728                         | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
1729                         | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
1730                         |  0 ) & RegMask); */
1731                 PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U);
1732         /*############################################################################################################################ */
1733
1734                 /*Register : DLL_REF_CTRL @ 0XFF5E0104</p>
1735
1736                 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1737                 is not usually an issue, but designers must be aware.)
1738                 PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
1739
1740                 This register controls this reference clock
1741                 (OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)
1742                 RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
1743
1744                 RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
1745                         |  0 ) & RegMask); */
1746                 PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U);
1747         /*############################################################################################################################ */
1748
1749                 /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
1750
1751                 6 bit divider
1752                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
1753
1754                 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and
1755                  cycles of the new clock. This is not usually an issue, but designers must be aware.)
1756                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
1757
1758                 Clock active signal. Switch to 0 to disable the clock
1759                 PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
1760
1761                 This register controls this reference clock
1762                 (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)
1763                 RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
1764
1765                 RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
1766                         | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
1767                         | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
1768                         |  0 ) & RegMask); */
1769                 PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U);
1770         /*############################################################################################################################ */
1771
1772                 /*Register : SATA_REF_CTRL @ 0XFD1A00A0</p>
1773
1774                 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1775                 he new clock. This is not usually an issue, but designers must be aware.)
1776                 PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
1777
1778                 Clock active signal. Switch to 0 to disable the clock
1779                 PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
1780
1781                 6 bit divider
1782                 PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
1783
1784                 This register controls this reference clock
1785                 (OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)
1786                 RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK |  0 );
1787
1788                 RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
1789                         | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
1790                         | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
1791                         |  0 ) & RegMask); */
1792                 PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1793         /*############################################################################################################################ */
1794
1795                 /*Register : PCIE_REF_CTRL @ 0XFD1A00B4</p>
1796
1797                 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
1798                 es of the new clock. This is not usually an issue, but designers must be aware.)
1799                 PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
1800
1801                 Clock active signal. Switch to 0 to disable the clock
1802                 PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
1803
1804                 6 bit divider
1805                 PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x2
1806
1807                 This register controls this reference clock
1808                 (OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01000200U)
1809                 RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
1810
1811                 RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
1812                         | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
1813                         | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
1814                         |  0 ) & RegMask); */
1815                 PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1816         /*############################################################################################################################ */
1817
1818                 /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
1819
1820                 6 bit divider
1821                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
1822
1823                 6 bit divider
1824                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
1825
1826                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1827                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1828                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
1829
1830                 Clock active signal. Switch to 0 to disable the clock
1831                 PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
1832
1833                 This register controls this reference clock
1834                 (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)
1835                 RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
1836
1837                 RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
1838                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
1839                         | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
1840                         | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
1841                         |  0 ) & RegMask); */
1842                 PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U);
1843         /*############################################################################################################################ */
1844
1845                 /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
1846
1847                 6 bit divider
1848                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
1849
1850                 6 bit divider
1851                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
1852
1853                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the
1854                 ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
1855                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
1856
1857                 Clock active signal. Switch to 0 to disable the clock
1858                 PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
1859
1860                 This register controls this reference clock
1861                 (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)
1862                 RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
1863
1864                 RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
1865                         | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
1866                         | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
1867                         | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
1868                         |  0 ) & RegMask); */
1869                 PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U);
1870         /*############################################################################################################################ */
1871
1872                 /*Register : DP_STC_REF_CTRL @ 0XFD1A007C</p>
1873
1874                 6 bit divider
1875                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
1876
1877                 6 bit divider
1878                 PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
1879
1880                 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
1881                 e new clock. This is not usually an issue, but designers must be aware.)
1882                 PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
1883
1884                 Clock active signal. Switch to 0 to disable the clock
1885                 PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
1886
1887                 This register controls this reference clock
1888                 (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)
1889                 RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
1890
1891                 RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
1892                         | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
1893                         | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
1894                         | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
1895                         |  0 ) & RegMask); */
1896                 PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U);
1897         /*############################################################################################################################ */
1898
1899                 /*Register : ACPU_CTRL @ 0XFD1A0060</p>
1900
1901                 6 bit divider
1902                 PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
1903
1904                 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
1905                 lock. This is not usually an issue, but designers must be aware.)
1906                 PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
1907
1908                 Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
1909                 PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
1910
1911                 Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
1912                  to the entire APU
1913                 PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
1914
1915                 This register controls this reference clock
1916                 (OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)
1917                 RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
1918
1919                 RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
1920                         | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
1921                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
1922                         | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
1923                         |  0 ) & RegMask); */
1924                 PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U);
1925         /*############################################################################################################################ */
1926
1927                 /*Register : DBG_TRACE_CTRL @ 0XFD1A0064</p>
1928
1929                 6 bit divider
1930                 PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
1931
1932                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1933                 he new clock. This is not usually an issue, but designers must be aware.)
1934                 PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
1935
1936                 Clock active signal. Switch to 0 to disable the clock
1937                 PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
1938
1939                 This register controls this reference clock
1940                 (OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)
1941                 RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
1942
1943                 RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
1944                         | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
1945                         | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
1946                         |  0 ) & RegMask); */
1947                 PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1948         /*############################################################################################################################ */
1949
1950                 /*Register : DBG_FPD_CTRL @ 0XFD1A0068</p>
1951
1952                 6 bit divider
1953                 PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
1954
1955                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1956                 he new clock. This is not usually an issue, but designers must be aware.)
1957                 PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
1958
1959                 Clock active signal. Switch to 0 to disable the clock
1960                 PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
1961
1962                 This register controls this reference clock
1963                 (OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)
1964                 RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
1965
1966                 RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
1967                         | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
1968                         | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
1969                         |  0 ) & RegMask); */
1970                 PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
1971         /*############################################################################################################################ */
1972
1973                 /*Register : DDR_CTRL @ 0XFD1A0080</p>
1974
1975                 6 bit divider
1976                 PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
1977
1978                 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
1979                 s not usually an issue, but designers must be aware.)
1980                 PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
1981
1982                 This register controls this reference clock
1983                 (OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)
1984                 RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
1985
1986                 RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
1987                         | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
1988                         |  0 ) & RegMask); */
1989                 PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
1990         /*############################################################################################################################ */
1991
1992                 /*Register : GPU_REF_CTRL @ 0XFD1A0084</p>
1993
1994                 6 bit divider
1995                 PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
1996
1997                 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
1998                 he new clock. This is not usually an issue, but designers must be aware.)
1999                 PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
2000
2001                 Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
2002                 PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
2003
2004                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
2005                 PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
2006
2007                 Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
2008                 PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
2009
2010                 This register controls this reference clock
2011                 (OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)
2012                 RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
2013
2014                 RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
2015                         | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
2016                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
2017                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
2018                         | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
2019                         |  0 ) & RegMask); */
2020                 PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U);
2021         /*############################################################################################################################ */
2022
2023                 /*Register : GDMA_REF_CTRL @ 0XFD1A00B8</p>
2024
2025                 6 bit divider
2026                 PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
2027
2028                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2029                 lock. This is not usually an issue, but designers must be aware.)
2030                 PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
2031
2032                 Clock active signal. Switch to 0 to disable the clock
2033                 PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
2034
2035                 This register controls this reference clock
2036                 (OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)
2037                 RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
2038
2039                 RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
2040                         | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
2041                         | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
2042                         |  0 ) & RegMask); */
2043                 PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
2044         /*############################################################################################################################ */
2045
2046                 /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC</p>
2047
2048                 6 bit divider
2049                 PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
2050
2051                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2052                 lock. This is not usually an issue, but designers must be aware.)
2053                 PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
2054
2055                 Clock active signal. Switch to 0 to disable the clock
2056                 PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
2057
2058                 This register controls this reference clock
2059                 (OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)
2060                 RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
2061
2062                 RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
2063                         | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
2064                         | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
2065                         |  0 ) & RegMask); */
2066                 PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
2067         /*############################################################################################################################ */
2068
2069                 /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0</p>
2070
2071                 6 bit divider
2072                 PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
2073
2074                 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
2075                 lock. This is not usually an issue, but designers must be aware.)
2076                 PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
2077
2078                 Clock active signal. Switch to 0 to disable the clock
2079                 PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
2080
2081                 This register controls this reference clock
2082                 (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)
2083                 RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
2084
2085                 RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
2086                         | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
2087                         | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
2088                         |  0 ) & RegMask); */
2089                 PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U);
2090         /*############################################################################################################################ */
2091
2092                 /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4</p>
2093
2094                 6 bit divider
2095                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
2096
2097                 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2098                 he new clock. This is not usually an issue, but designers must be aware.)
2099                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
2100
2101                 Clock active signal. Switch to 0 to disable the clock
2102                 PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
2103
2104                 This register controls this reference clock
2105                 (OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)
2106                 RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
2107
2108                 RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
2109                         | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
2110                         | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
2111                         |  0 ) & RegMask); */
2112                 PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
2113         /*############################################################################################################################ */
2114
2115                 /*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8</p>
2116
2117                 6 bit divider
2118                 PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x4
2119
2120                 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2121                 he new clock. This is not usually an issue, but designers must be aware.)
2122                 PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x0
2123
2124                 Clock active signal. Switch to 0 to disable the clock
2125                 PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
2126
2127                 This register controls this reference clock
2128                 (OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01000400U)
2129                 RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );
2130
2131                 RegVal = ((0x00000004U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
2132                         | 0x00000000U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
2133                         | 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
2134                         |  0 ) & RegMask); */
2135                 PSU_Mask_Write (CRF_APB_GTGREF0_REF_CTRL_OFFSET ,0x01003F07U ,0x01000400U);
2136         /*############################################################################################################################ */
2137
2138                 /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8</p>
2139
2140                 6 bit divider
2141                 PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
2142
2143                 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of
2144                 he new clock. This is not usually an issue, but designers must be aware.)
2145                 PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
2146
2147                 This register controls this reference clock
2148                 (OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)
2149                 RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
2150
2151                 RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
2152                         | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
2153                         |  0 ) & RegMask); */
2154                 PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
2155         /*############################################################################################################################ */
2156
2157                 /*Register : IOU_TTC_APB_CLK @ 0XFF180380</p>
2158
2159                 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
2160                 0" = Select the R5 clock for the APB interface of TTC0
2161                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
2162
2163                 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
2164                 0" = Select the R5 clock for the APB interface of TTC1
2165                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
2166
2167                 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
2168                 0" = Select the R5 clock for the APB interface of TTC2
2169                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
2170
2171                 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
2172                 0" = Select the R5 clock for the APB interface of TTC3
2173                 PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
2174
2175                 TTC APB clock select
2176                 (OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)
2177                 RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK |  0 );
2178
2179                 RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
2180                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
2181                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
2182                         | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
2183                         |  0 ) & RegMask); */
2184                 PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U);
2185         /*############################################################################################################################ */
2186
2187                 /*Register : WDT_CLK_SEL @ 0XFD610100</p>
2188
2189                 System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
2190                 PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
2191
2192                 SWDT clock source select
2193                 (OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)
2194                 RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
2195
2196                 RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2197                         |  0 ) & RegMask); */
2198                 PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
2199         /*############################################################################################################################ */
2200
2201                 /*Register : WDT_CLK_SEL @ 0XFF180300</p>
2202
2203                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout
2204                 ia MIO
2205                 PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
2206
2207                 SWDT clock source select
2208                 (OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)
2209                 RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
2210
2211                 RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
2212                         |  0 ) & RegMask); */
2213                 PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
2214         /*############################################################################################################################ */
2215
2216                 /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050</p>
2217
2218                 System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
2219                 PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
2220
2221                 SWDT clock source select
2222                 (OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)
2223                 RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK |  0 );
2224
2225                 RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
2226                         |  0 ) & RegMask); */
2227                 PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
2228         /*############################################################################################################################ */
2229
2230
2231   return 1;
2232 }
2233 unsigned long psu_ddr_init_data() {
2234                 // : DDR INITIALIZATION
2235                 // : DDR CONTROLLER RESET
2236                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
2237
2238                 DDR block level reset inside of the DDR Sub System
2239                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
2240
2241                 DDR sub system block level reset
2242                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)
2243                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
2244
2245                 RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
2246                         |  0 ) & RegMask); */
2247                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U);
2248         /*############################################################################################################################ */
2249
2250                 /*Register : MSTR @ 0XFD070000</p>
2251
2252                 Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32
2253                 evice
2254                 PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
2255
2256                 Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
2257                 PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
2258
2259                 Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
2260                 esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 -
2261                 ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
2262                 ks - 1111 - Four ranks
2263                 PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
2264
2265                 SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
2266                  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls
2267                 he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
2268                 -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
2269                  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
2270                 PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
2271
2272                 Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM
2273                 n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
2274                 l_off_mode is not supported, and this bit must be set to '0'.
2275                 PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
2276
2277                 Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
2278                 AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
2279                 dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
2280                 figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
2281                 PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
2282
2283                 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
2284                  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode
2285                 s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
2286                 PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
2287
2288                 If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held
2289                 or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in
2290                 PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
2291                 ing is not supported in DDR4 geardown mode.
2292                 PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
2293
2294                 When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
2295                 t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
2296                  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
2297                 _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
2298                 PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
2299
2300                 Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
2301                 port LPDDR4.
2302                 PSU_DDRC_MSTR_LPDDR4                                                            0x0
2303
2304                 Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support
2305                 DR4.
2306                 PSU_DDRC_MSTR_DDR4                                                              0x1
2307
2308                 Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
2309                 port LPDDR3.
2310                 PSU_DDRC_MSTR_LPDDR3                                                            0x0
2311
2312                 Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
2313                 port LPDDR2.
2314                 PSU_DDRC_MSTR_LPDDR2                                                            0x0
2315
2316                 Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
2317
2318                 PSU_DDRC_MSTR_DDR3                                                              0x0
2319
2320                 Master Register
2321                 (OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)
2322                 RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK |  0 );
2323
2324                 RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT
2325                         | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT
2326                         | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT
2327                         | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT
2328                         | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT
2329                         | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
2330                         | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT
2331                         | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
2332                         | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT
2333                         | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT
2334                         | 0x00000001U << DDRC_MSTR_DDR4_SHIFT
2335                         | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT
2336                         | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT
2337                         | 0x00000000U << DDRC_MSTR_DDR3_SHIFT
2338                         |  0 ) & RegMask); */
2339                 PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U);
2340         /*############################################################################################################################ */
2341
2342                 /*Register : MRCTRL0 @ 0XFD070010</p>
2343
2344                 Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
2345                  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
2346                 re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
2347                 PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
2348
2349                 Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
2350                  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
2351                 R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
2352                 dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well
2353                 s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
2354                 put Inversion of RDIMMs.
2355                 PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
2356
2357                 Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
2358                  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
2359                 amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks
2360                  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
2361                 PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
2362
2363                 Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
2364                 or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
2365                  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared
2366                 o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
2367                 n is not allowed - 1 - Software intervention is allowed
2368                 PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
2369
2370                 Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
2371                 PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
2372
2373                 Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
2374                 PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
2375
2376                 Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
2377                 d
2378                 PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
2379
2380                 Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
2381                 it_int - pda_en - mpr_en
2382                 (OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)
2383                 RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK |  0 );
2384
2385                 RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT
2386                         | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT
2387                         | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT
2388                         | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT
2389                         | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT
2390                         | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT
2391                         | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT
2392                         |  0 ) & RegMask); */
2393                 PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U);
2394         /*############################################################################################################################ */
2395
2396                 /*Register : DERATEEN @ 0XFD070020</p>
2397
2398                 Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
2399                  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
2400                 g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
2401                 PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
2402
2403                 Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
2404                 r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
2405                 PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
2406
2407                 Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
2408                 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
2409                 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
2410                 PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
2411
2412                 Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
2413                 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
2414                 mode.
2415                 PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
2416
2417                 Temperature Derate Enable Register
2418                 (OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)
2419                 RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK |  0 );
2420
2421                 RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
2422                         | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT
2423                         | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT
2424                         | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT
2425                         |  0 ) & RegMask); */
2426                 PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U);
2427         /*############################################################################################################################ */
2428
2429                 /*Register : DERATEINT @ 0XFD070024</p>
2430
2431                 Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
2432                 DR3/LPDDR4. This register must not be set to zero
2433                 PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
2434
2435                 Temperature Derate Interval Register
2436                 (OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
2437                 RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK |  0 );
2438
2439                 RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
2440                         |  0 ) & RegMask); */
2441                 PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U);
2442         /*############################################################################################################################ */
2443
2444                 /*Register : PWRCTL @ 0XFD070030</p>
2445
2446                 Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
2447                 r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state -
2448                  - Allow transition from Self refresh state
2449                 PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
2450
2451                 A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
2452                 M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
2453                 are Exit from Self Refresh
2454                 PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
2455
2456                 When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
2457                 st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For
2458                 on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
2459                 DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
2460                 PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
2461
2462                 Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
2463                 is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
2464                 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in
2465                 ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
2466                 rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
2467                 PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
2468
2469                 When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
2470                 et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down
2471                 xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
2472                  should not be set to 1. FOR PERFORMANCE ONLY.
2473                 PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
2474
2475                 If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
2476                 RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
2477                 PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
2478
2479                 If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
2480                 f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
2481                 PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
2482
2483                 Low Power Control Register
2484                 (OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)
2485                 RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK |  0 );
2486
2487                 RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
2488                         | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT
2489                         | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT
2490                         | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
2491                         | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
2492                         | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT
2493                         | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT
2494                         |  0 ) & RegMask); */
2495                 PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U);
2496         /*############################################################################################################################ */
2497
2498                 /*Register : PWRTMG @ 0XFD070034</p>
2499
2500                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in
2501                 he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
2502                 PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
2503
2504                 Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
2505                 ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
2506                 iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
2507                 PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
2508
2509                 After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
2510                  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
2511                 PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
2512
2513                 Low Power Timing Register
2514                 (OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)
2515                 RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK |  0 );
2516
2517                 RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
2518                         | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT
2519                         | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
2520                         |  0 ) & RegMask); */
2521                 PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U);
2522         /*############################################################################################################################ */
2523
2524                 /*Register : RFSHCTL0 @ 0XFD070050</p>
2525
2526                 Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
2527                 d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
2528                  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
2529                 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
2530                 om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
2531                 PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
2532
2533                 If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
2534                 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
2535                  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
2536                 HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
2537                 formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
2538                 ued to the uMCTL2. FOR PERFORMANCE ONLY.
2539                 PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
2540
2541                 The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
2542                 reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
2543                 reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
2544                 RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
2545                 . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
2546                 tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
2547                 fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
2548                 ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
2549                 tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
2550                 d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
2551                 initiated update is complete.
2552                 PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
2553
2554                 - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
2555                 t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
2556                 support LPDDR2/LPDDR3/LPDDR4
2557                 PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
2558
2559                 Refresh Control Register 0
2560                 (OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)
2561                 RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK |  0 );
2562
2563                 RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
2564                         | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
2565                         | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
2566                         | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
2567                         |  0 ) & RegMask); */
2568                 PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U);
2569         /*############################################################################################################################ */
2570
2571                 /*Register : RFSHCTL3 @ 0XFD070060</p>
2572
2573                 Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
2574                 ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
2575                 orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
2576                 self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in
2577                 uture version of the uMCTL2.
2578                 PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
2579
2580                 Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value
2581                 s automatically updated when exiting reset, so it does not need to be toggled initially.
2582                 PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
2583
2584                 When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
2585                 ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
2586                 auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
2587                 is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'.
2588                 his register field is changeable on the fly.
2589                 PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
2590
2591                 Refresh Control Register 3
2592                 (OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)
2593                 RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK |  0 );
2594
2595                 RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
2596                         | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
2597                         | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
2598                         |  0 ) & RegMask); */
2599                 PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U);
2600         /*############################################################################################################################ */
2601
2602                 /*Register : RFSHTMG @ 0XFD070064</p>
2603
2604                 tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
2605                  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
2606                 , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should
2607                 e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
2608                 ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
2609                 programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
2610                 TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
2611                 PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
2612
2613                 Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the
2614                 REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
2615                  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
2616                 PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
2617
2618                 tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
2619                  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
2620                 DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
2621                  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
2622                 equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
2623                 opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
2624                 PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
2625
2626                 Refresh Timing Register
2627                 (OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)
2628                 RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK |  0 );
2629
2630                 RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
2631                         | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
2632                         | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT
2633                         |  0 ) & RegMask); */
2634                 PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU);
2635         /*############################################################################################################################ */
2636
2637                 /*Register : ECCCFG0 @ 0XFD070070</p>
2638
2639                 Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
2640                 PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
2641
2642                 ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
2643                  use
2644                 PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
2645
2646                 ECC Configuration Register 0
2647                 (OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)
2648                 RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK |  0 );
2649
2650                 RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT
2651                         | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT
2652                         |  0 ) & RegMask); */
2653                 PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U);
2654         /*############################################################################################################################ */
2655
2656                 /*Register : ECCCFG1 @ 0XFD070074</p>
2657
2658                 Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
2659                 ng, if ECCCFG1.data_poison_en=1
2660                 PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
2661
2662                 Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
2663                 PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
2664
2665                 ECC Configuration Register 1
2666                 (OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)
2667                 RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK |  0 );
2668
2669                 RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
2670                         | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
2671                         |  0 ) & RegMask); */
2672                 PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U);
2673         /*############################################################################################################################ */
2674
2675                 /*Register : CRCPARCTL1 @ 0XFD0700C4</p>
2676
2677                 The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
2678                 the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY
2679                 pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
2680                 L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
2681                 dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
2682                 e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
2683                 PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
2684
2685                 After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
2686                 M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
2687                 the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
2688                 the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
2689                 RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
2690                  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
2691                 rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
2692                 ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in
2693                 he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is
2694                 one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in
2695                 PR Page 1 should be treated as 'Don't care'.
2696                 PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
2697
2698                 - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
2699                  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
2700                  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
2701                 PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
2702
2703                 CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
2704                 d to support DDR4.
2705                 PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
2706
2707                 CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
2708                  CRC mode register setting in the DRAM.
2709                 PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
2710
2711                 C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of
2712                 /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
2713                 is register should be 1.
2714                 PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
2715
2716                 CRC Parity Control Register1
2717                 (OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)
2718                 RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK |  0 );
2719
2720                 RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
2721                         | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
2722                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
2723                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
2724                         | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
2725                         | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
2726                         |  0 ) & RegMask); */
2727                 PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U);
2728         /*############################################################################################################################ */
2729
2730                 /*Register : CRCPARCTL2 @ 0XFD0700C8</p>
2731
2732                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
2733                  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
2734                 er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
2735                 PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
2736
2737                 Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
2738                 tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
2739                 value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
2740                 PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
2741
2742                 Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
2743                 ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
2744                 er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
2745                 les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
2746                 or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
2747                 ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
2748                 max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
2749                 bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
2750                 + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
2751                 ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The
2752                 ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
2753                 to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
2754                  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
2755                 PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
2756                 _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
2757                 C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
2758                 e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
2759                  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
2760                 H-6 Values of 0, 1 and 2 are illegal.
2761                 PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
2762
2763                 CRC Parity Control Register2
2764                 (OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
2765                 RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK |  0 );
2766
2767                 RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
2768                         | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
2769                         | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
2770                         |  0 ) & RegMask); */
2771                 PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU);
2772         /*############################################################################################################################ */
2773
2774                 /*Register : INIT0 @ 0XFD0700D0</p>
2775
2776                 If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
2777                  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
2778                 ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
2779                 r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported
2780                 or LPDDR4 in this version of the uMCTL2.
2781                 PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
2782
2783                 Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires
2784                  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
2785                 grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
2786                 MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
2787                 PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
2788
2789                 Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2
2790                 pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
2791                 tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
2792                  to next integer value.
2793                 PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
2794
2795                 SDRAM Initialization Register 0
2796                 (OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
2797                 RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK |  0 );
2798
2799                 RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
2800                         | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT
2801                         | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT
2802                         |  0 ) & RegMask); */
2803                 PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U);
2804         /*############################################################################################################################ */
2805
2806                 /*Register : INIT1 @ 0XFD0700D4</p>
2807
2808                 Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
2809                 LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
2810                 PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
2811
2812                 Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
2813                 bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
2814                 PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
2815
2816                 Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
2817                 . There is no known specific requirement for this; it may be set to zero.
2818                 PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
2819
2820                 SDRAM Initialization Register 1
2821                 (OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
2822                 RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK |  0 );
2823
2824                 RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
2825                         | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT
2826                         | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT
2827                         |  0 ) & RegMask); */
2828                 PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U);
2829         /*############################################################################################################################ */
2830
2831                 /*Register : INIT2 @ 0XFD0700D8</p>
2832
2833                 Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
2834                 PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
2835
2836                 Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
2837                 e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
2838                 PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
2839
2840                 SDRAM Initialization Register 2
2841                 (OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
2842                 RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK |  0 );
2843
2844                 RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
2845                         | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
2846                         |  0 ) & RegMask); */
2847                 PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U);
2848         /*############################################################################################################################ */
2849
2850                 /*Register : INIT3 @ 0XFD0700DC</p>
2851
2852                 DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
2853                  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
2854                 register
2855                 PSU_DDRC_INIT3_MR                                                               0x930
2856
2857                 DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
2858                 bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
2859                  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
2860                 lue to write to MR2 register
2861                 PSU_DDRC_INIT3_EMR                                                              0x301
2862
2863                 SDRAM Initialization Register 3
2864                 (OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)
2865                 RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK |  0 );
2866
2867                 RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT
2868                         | 0x00000301U << DDRC_INIT3_EMR_SHIFT
2869                         |  0 ) & RegMask); */
2870                 PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U);
2871         /*############################################################################################################################ */
2872
2873                 /*Register : INIT4 @ 0XFD0700E0</p>
2874
2875                 DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3
2876                 egister mDDR: Unused
2877                 PSU_DDRC_INIT4_EMR2                                                             0x20
2878
2879                 DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to
2880                 rite to MR13 register
2881                 PSU_DDRC_INIT4_EMR3                                                             0x200
2882
2883                 SDRAM Initialization Register 4
2884                 (OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
2885                 RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK |  0 );
2886
2887                 RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT
2888                         | 0x00000200U << DDRC_INIT4_EMR3_SHIFT
2889                         |  0 ) & RegMask); */
2890                 PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U);
2891         /*############################################################################################################################ */
2892
2893                 /*Register : INIT5 @ 0XFD0700E4</p>
2894
2895                 ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock
2896                 ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
2897                 PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
2898
2899                 Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
2900                 3 typically requires 10 us.
2901                 PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
2902
2903                 SDRAM Initialization Register 5
2904                 (OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
2905                 RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK |  0 );
2906
2907                 RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
2908                         | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
2909                         |  0 ) & RegMask); */
2910                 PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U);
2911         /*############################################################################################################################ */
2912
2913                 /*Register : INIT6 @ 0XFD0700E8</p>
2914
2915                 DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
2916                 PSU_DDRC_INIT6_MR4                                                              0x0
2917
2918                 DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
2919                 PSU_DDRC_INIT6_MR5                                                              0x6c0
2920
2921                 SDRAM Initialization Register 6
2922                 (OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
2923                 RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK |  0 );
2924
2925                 RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT
2926                         | 0x000006C0U << DDRC_INIT6_MR5_SHIFT
2927                         |  0 ) & RegMask); */
2928                 PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
2929         /*############################################################################################################################ */
2930
2931                 /*Register : INIT7 @ 0XFD0700EC</p>
2932
2933                 DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
2934                 PSU_DDRC_INIT7_MR6                                                              0x819
2935
2936                 SDRAM Initialization Register 7
2937                 (OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
2938                 RegMask = (DDRC_INIT7_MR6_MASK |  0 );
2939
2940                 RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT
2941                         |  0 ) & RegMask); */
2942                 PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U);
2943         /*############################################################################################################################ */
2944
2945                 /*Register : DIMMCTL @ 0XFD0700F0</p>
2946
2947                 Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
2948                 ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
2949                  address mirroring is enabled.
2950                 PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
2951
2952                 Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2953                  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output
2954                 nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
2955                 effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
2956                 led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
2957                 PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
2958
2959                 Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
2960                  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled,
2961                 his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address
2962                 f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
2963                 PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
2964
2965                 Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
2966                 which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17,
2967                 A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
2968                 lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated.
2969                 or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
2970                  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
2971                 ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
2972                 PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
2973
2974                 Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
2975                 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits
2976                 re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
2977                 at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
2978                 sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
2979                  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
2980                 ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
2981                 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
2982                 hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
2983                 ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
2984                 not implement address mirroring
2985                 PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
2986
2987                 Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
2988                 R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
2989                 CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
2990                  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
2991                 PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
2992
2993                 DIMM Control Register
2994                 (OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)
2995                 RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK |  0 );
2996
2997                 RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
2998                         | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
2999                         | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT
3000                         | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
3001                         | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
3002                         | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
3003                         |  0 ) & RegMask); */
3004                 PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U);
3005         /*############################################################################################################################ */
3006
3007                 /*Register : RANKCTL @ 0XFD0700F4</p>
3008
3009                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3010                 e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
3011                 nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
3012                 ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
3013                 ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed
3014                 n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
3015                 ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
3016                 or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
3017                  to the next integer.
3018                 PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
3019
3020                 Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
3021                 e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
3022                 sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
3023                 p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
3024                 ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
3025                 requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
3026                 quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and
3027                 ound it up to the next integer.
3028                 PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
3029
3030                 Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
3031                 nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
3032                 on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
3033                 -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
3034                 _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
3035                 om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
3036                 ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to
3037                 llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
3038                 ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as
3039                 ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
3040                 . FOR PERFORMANCE ONLY.
3041                 PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
3042
3043                 Rank Control Register
3044                 (OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
3045                 RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK |  0 );
3046
3047                 RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
3048                         | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
3049                         | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT
3050                         |  0 ) & RegMask); */
3051                 PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU);
3052         /*############################################################################################################################ */
3053
3054                 /*Register : DRAMTMG0 @ 0XFD070100</p>
3055
3056                 Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles
3057                  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
3058                  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
3059                 Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this
3060                 arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
3061                 with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
3062                 PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
3063
3064                 tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
3065                 in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next
3066                 nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
3067                 PSU_DDRC_DRAMTMG0_T_FAW                                                         0xc
3068
3069                 tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
3070                 imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
3071                  No rounding up. Unit: Multiples of 1024 clocks.
3072                 PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
3073
3074                 tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode,
3075                 rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
3076                  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
3077                 PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
3078
3079                 SDRAM Timing Register 0
3080                 (OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)
3081                 RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK |  0 );
3082
3083                 RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
3084                         | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT
3085                         | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
3086                         | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
3087                         |  0 ) & RegMask); */
3088                 PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U);
3089         /*############################################################################################################################ */
3090
3091                 /*Register : DRAMTMG1 @ 0XFD070104</p>
3092
3093                 tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
3094                  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2,
3095                 rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
3096                 PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
3097
3098                 tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
3099                 R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
3100                 S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
3101                 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
3102                 gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
3103                 e. Unit: Clocks.
3104                 PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
3105
3106                 tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
3107                  up to next integer value. Unit: Clocks.
3108                 PSU_DDRC_DRAMTMG1_T_RC                                                          0x19
3109
3110                 SDRAM Timing Register 1
3111                 (OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x00040419U)
3112                 RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK |  0 );
3113
3114                 RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
3115                         | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
3116                         | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT
3117                         |  0 ) & RegMask); */
3118                 PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U);
3119         /*############################################################################################################################ */
3120
3121                 /*Register : DRAMTMG2 @ 0XFD070108</p>
3122
3123                 Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
3124                 t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
3125                 tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
3126                 equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
3127                  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
3128                 PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
3129
3130                 Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
3131                 using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For
3132                 onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
3133                 er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
3134                 s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
3135                 PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
3136
3137                 DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
3138                 PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
3139                 /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
3140                 time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL =
3141                 urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
3142                 tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
3143                 DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
3144                 gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
3145                 PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
3146
3147                 DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
3148                 k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
3149                  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
3150                  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
3151                 d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
3152                  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
3153                 ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
3154                 PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
3155
3156                 SDRAM Timing Register 2
3157                 (OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)
3158                 RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK |  0 );
3159
3160                 RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
3161                         | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT
3162                         | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT
3163                         | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT
3164                         |  0 ) & RegMask); */
3165                 PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU);
3166         /*############################################################################################################################ */
3167
3168                 /*Register : DRAMTMG3 @ 0XFD07010C</p>
3169
3170                 Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
3171                  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW
3172                 nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
3173                  used for the time from a MRW/MRR to a MRW/MRR.
3174                 PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
3175
3176                 tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time
3177                 rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
3178                 nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
3179                 4 is used, set to tMRD_PAR(tMOD+PL) instead.
3180                 PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
3181
3182                 tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
3183                 y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
3184                  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
3185                  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
3186                 PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
3187
3188                 SDRAM Timing Register 3
3189                 (OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
3190                 RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK |  0 );
3191
3192                 RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT
3193                         | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT
3194                         | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT
3195                         |  0 ) & RegMask); */
3196                 PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU);
3197         /*############################################################################################################################ */
3198
3199                 /*Register : DRAMTMG4 @ 0XFD070110</p>
3200
3201                 tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
3202                 am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
3203                 lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
3204                 PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
3205
3206                 DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
3207                 time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
3208                 d it up to the next integer value. Unit: clocks.
3209                 PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
3210
3211                 DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
3212                  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
3213                 it up to the next integer value. Unit: Clocks.
3214                 PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
3215
3216                 tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
3217                 (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
3218                 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
3219                 PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
3220
3221                 SDRAM Timing Register 4
3222                 (OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
3223                 RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK |  0 );
3224
3225                 RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT
3226                         | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT
3227                         | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT
3228                         | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT
3229                         |  0 ) & RegMask); */
3230                 PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U);
3231         /*############################################################################################################################ */
3232
3233                 /*Register : DRAMTMG5 @ 0XFD070114</p>
3234
3235                 This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
3236                 e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
3237                 tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
3238                 eger.
3239                 PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
3240
3241                 This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
3242                  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4:
3243                 ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
3244                 to next integer.
3245                 PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
3246
3247                 Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
3248                 tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE
3249                  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
3250                 .
3251                 PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
3252
3253                 Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of
3254                 CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set
3255                 his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
3256                  next integer value. Unit: Clocks.
3257                 PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
3258
3259                 SDRAM Timing Register 5
3260                 (OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
3261                 RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK |  0 );
3262
3263                 RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT
3264                         | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT
3265                         | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT
3266                         | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT
3267                         |  0 ) & RegMask); */
3268                 PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U);
3269         /*############################################################################################################################ */
3270
3271                 /*Register : DRAMTMG6 @ 0XFD070118</p>
3272
3273                 This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after
3274                 PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
3275                 ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
3276                 devices.
3277                 PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
3278
3279                 This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock
3280                 table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
3281                 gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
3282                 R or LPDDR2 devices.
3283                 PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
3284
3285                 This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the
3286                 lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
3287                 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it
3288                 p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
3289                 PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
3290
3291                 SDRAM Timing Register 6
3292                 (OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)
3293                 RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK |  0 );
3294
3295                 RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT
3296                         | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT
3297                         | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT
3298                         |  0 ) & RegMask); */
3299                 PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U);
3300         /*############################################################################################################################ */
3301
3302                 /*Register : DRAMTMG7 @ 0XFD07011C</p>
3303
3304                 This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
3305                 ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
3306                 is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
3307                 DDR2/LPDDR3/LPDDR4 devices.
3308                 PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x1
3309
3310                 This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
3311                 time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
3312                 , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
3313                 g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
3314                 PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x1
3315
3316                 SDRAM Timing Register 7
3317                 (OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000101U)
3318                 RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK |  0 );
3319
3320                 RegVal = ((0x00000001U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
3321                         | 0x00000001U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
3322                         |  0 ) & RegMask); */
3323                 PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000101U);
3324         /*############################################################################################################################ */
3325
3326                 /*Register : DRAMTMG8 @ 0XFD070120</p>
3327
3328                 tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
3329                 O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
3330                  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
3331                 PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
3332
3333                 tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
3334                 ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
3335                 nsure this is less than or equal to t_xs_x32.
3336                 PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
3337
3338                 tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3339                 bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3340                 DR4 SDRAMs.
3341                 PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
3342
3343                 tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
3344                 above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
3345                 DDR4 SDRAMs.
3346                 PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
3347
3348                 SDRAM Timing Register 8
3349                 (OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)
3350                 RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK |  0 );
3351
3352                 RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
3353                         | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
3354                         | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
3355                         | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT
3356                         |  0 ) & RegMask); */
3357                 PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U);
3358         /*############################################################################################################################ */
3359
3360                 /*Register : DRAMTMG9 @ 0XFD070124</p>
3361
3362                 DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
3363                 PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
3364
3365                 tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a'
3366                 o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
3367                 nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
3368                 PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
3369
3370                 tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
3371                 ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
3372                 R4. Unit: Clocks.
3373                 PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
3374
3375                 CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
3376                 round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
3377                  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
3378                 d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
3379                 is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using
3380                 he above equation by 2, and round it up to next integer.
3381                 PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
3382
3383                 SDRAM Timing Register 9
3384                 (OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)
3385                 RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK |  0 );
3386
3387                 RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
3388                         | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT
3389                         | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT
3390                         | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT
3391                         |  0 ) & RegMask); */
3392                 PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU);
3393         /*############################################################################################################################ */
3394
3395                 /*Register : DRAMTMG11 @ 0XFD07012C</p>
3396
3397                 tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
3398                 this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
3399                 ples of 32 clocks.
3400                 PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
3401
3402                 tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
3403                  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
3404                 PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
3405
3406                 tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
3407                 up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
3408                 PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
3409
3410                 tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
3411                 r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
3412                 teger.
3413                 PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
3414
3415                 SDRAM Timing Register 11
3416                 (OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)
3417                 RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK |  0 );
3418
3419                 RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
3420                         | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT
3421                         | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT
3422                         | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT
3423                         |  0 ) & RegMask); */
3424                 PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU);
3425         /*############################################################################################################################ */
3426
3427                 /*Register : DRAMTMG12 @ 0XFD070130</p>
3428
3429                 tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
3430                 REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
3431                 PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
3432
3433                 tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
3434                 /2) and round it up to next integer value.
3435                 PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
3436
3437                 tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
3438                 s to (tMRD_PDA/2) and round it up to next integer value.
3439                 PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
3440
3441                 SDRAM Timing Register 12
3442                 (OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)
3443                 RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK |  0 );
3444
3445                 RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT
3446                         | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
3447                         | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
3448                         |  0 ) & RegMask); */
3449                 PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U);
3450         /*############################################################################################################################ */
3451
3452                 /*Register : ZQCTL0 @ 0XFD070180</p>
3453
3454                 - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
3455                 ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
3456                 ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3457                 PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
3458
3459                 - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
3460                 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
3461                 own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
3462                 ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3463                 PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
3464
3465                 - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
3466                 nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
3467                 rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3468                 PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
3469
3470                 - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable
3471                 ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
3472                 gns supporting DDR4 devices.
3473                 PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
3474
3475                 tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
3476                 on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
3477                 er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
3478                 ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for
3479                 esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3480                 PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
3481
3482                 tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
3483                 ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
3484                 e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
3485                 s.
3486                 PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
3487
3488                 ZQ Control Register 0
3489                 (OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)
3490                 RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK |  0 );
3491
3492                 RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
3493                         | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
3494                         | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
3495                         | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
3496                         | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
3497                         | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
3498                         |  0 ) & RegMask); */
3499                 PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U);
3500         /*############################################################################################################################ */
3501
3502                 /*Register : ZQCTL1 @ 0XFD070184</p>
3503
3504                 tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
3505                 ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is
3506                 nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
3507                 PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
3508
3509                 Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
3510                 PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs
3511                 upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
3512                 PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
3513
3514                 ZQ Control Register 1
3515                 (OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)
3516                 RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK |  0 );
3517
3518                 RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
3519                         | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
3520                         |  0 ) & RegMask); */
3521                 PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U);
3522         /*############################################################################################################################ */
3523
3524                 /*Register : DFITMG0 @ 0XFD070190</p>
3525
3526                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
3527                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
3528                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
3529                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
3530                 PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
3531
3532                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
3533                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
3534                 fer to PHY specification for correct value.
3535                 PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
3536
3537                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
3538                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
3539                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
3540                  latency through the RDIMM. Unit: Clocks
3541                 PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
3542
3543                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
3544                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
3545                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
3546                 e.
3547                 PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
3548
3549                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
3550                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
3551                 te, max supported value is 8. Unit: Clocks
3552                 PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
3553
3554                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
3555                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
3556                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
3557                 rough the RDIMM.
3558                 PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
3559
3560                 DFI Timing Register 0
3561                 (OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
3562                 RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK |  0 );
3563
3564                 RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
3565                         | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
3566                         | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
3567                         | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
3568                         | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
3569                         | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
3570                         |  0 ) & RegMask); */
3571                 PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU);
3572         /*############################################################################################################################ */
3573
3574                 /*Register : DFITMG1 @ 0XFD070194</p>
3575
3576                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven.
3577                 his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
3578                 the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
3579                 PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
3580
3581                 Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
3582                  is driven.
3583                 PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
3584
3585                 Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
3586                 nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
3587                  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to
3588                 phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
3589                 RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
3590                 : Clocks
3591                 PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
3592
3593                 Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to
3594                 he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase
3595                 ligned, this timing parameter should be rounded up to the next integer value.
3596                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
3597
3598                 Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first
3599                 alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
3600                 not phase aligned, this timing parameter should be rounded up to the next integer value.
3601                 PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
3602
3603                 DFI Timing Register 1
3604                 (OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)
3605                 RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK |  0 );
3606
3607                 RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
3608                         | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
3609                         | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
3610                         | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
3611                         | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
3612                         |  0 ) & RegMask); */
3613                 PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U);
3614         /*############################################################################################################################ */
3615
3616                 /*Register : DFILPCFG0 @ 0XFD070198</p>
3617
3618                 Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
3619                 g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
3620                 PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
3621
3622                 Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
3623                 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
3624                 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD -
3625                 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
3626                 .
3627                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
3628
3629                 Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
3630                 nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
3631                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
3632
3633                 Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
3634                 les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 -
3635                 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
3636                 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
3637                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
3638
3639                 Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
3640                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
3641
3642                 Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
3643                 s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
3644                 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
3645                  cycles - 0xE - 262144 cycles - 0xF - Unlimited
3646                 PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x4
3647
3648                 Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
3649                 PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
3650
3651                 DFI Low Power Configuration Register 0
3652                 (OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000141U)
3653                 RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK |  0 );
3654
3655                 RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
3656                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
3657                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
3658                         | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
3659                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
3660                         | 0x00000004U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
3661                         | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
3662                         |  0 ) & RegMask); */
3663                 PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000141U);
3664         /*############################################################################################################################ */
3665
3666                 /*Register : DFILPCFG1 @ 0XFD07019C</p>
3667
3668                 Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
3669                 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles
3670                  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
3671                 D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
3672                 PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
3673
3674                 Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
3675                 only present for designs supporting DDR4 devices.
3676                 PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
3677
3678                 DFI Low Power Configuration Register 1
3679                 (OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)
3680                 RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK |  0 );
3681
3682                 RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
3683                         | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
3684                         |  0 ) & RegMask); */
3685                 PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U);
3686         /*############################################################################################################################ */
3687
3688                 /*Register : DFIUPD1 @ 0XFD0701A4</p>
3689
3690                 This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
3691                 ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
3692                 t read request when the uMCTL2 is idle. Unit: 1024 clocks
3693                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
3694
3695                 This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request;
3696                 hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
3697                 idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
3698                 e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
3699                 Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
3700                 024. Unit: 1024 clocks
3701                 PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
3702
3703                 DFI Update Register 1
3704                 (OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)
3705                 RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK |  0 );
3706
3707                 RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
3708                         | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
3709                         |  0 ) & RegMask); */
3710                 PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U);
3711         /*############################################################################################################################ */
3712
3713                 /*Register : DFIMISC @ 0XFD0701B0</p>
3714
3715                 Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
3716                 PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
3717
3718                 DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
3719                 in designs configured to support DDR4 and LPDDR4.
3720                 PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
3721
3722                 PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
3723                 ion
3724                 PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
3725
3726                 DFI Miscellaneous Control Register
3727                 (OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)
3728                 RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK |  0 );
3729
3730                 RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
3731                         | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
3732                         | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
3733                         |  0 ) & RegMask); */
3734                 PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U);
3735         /*############################################################################################################################ */
3736
3737                 /*Register : DFITMG2 @ 0XFD0701B4</p>
3738
3739                 >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
3740                 l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
3741                 PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
3742
3743                 Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
3744                 l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
3745                 PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
3746
3747                 DFI Timing Register 2
3748                 (OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)
3749                 RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK |  0 );
3750
3751                 RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
3752                         | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
3753                         |  0 ) & RegMask); */
3754                 PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U);
3755         /*############################################################################################################################ */
3756
3757                 /*Register : DBICTL @ 0XFD0701C0</p>
3758
3759                 Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
3760                 as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
3761                 PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
3762
3763                 Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
3764                 ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
3765                 PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
3766
3767                 DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
3768                 mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
3769                 : Set this to inverted value of MR13[5] which is opposite polarity from this signal
3770                 PSU_DDRC_DBICTL_DM_EN                                                           0x1
3771
3772                 DM/DBI Control Register
3773                 (OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)
3774                 RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK |  0 );
3775
3776                 RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT
3777                         | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT
3778                         | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT
3779                         |  0 ) & RegMask); */
3780                 PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U);
3781         /*############################################################################################################################ */
3782
3783                 /*Register : ADDRMAP0 @ 0XFD070200</p>
3784
3785                 Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
3786                  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
3787                 PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
3788
3789                 Address Map Register 0
3790                 (OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)
3791                 RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK |  0 );
3792
3793                 RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
3794                         |  0 ) & RegMask); */
3795                 PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU);
3796         /*############################################################################################################################ */
3797
3798                 /*Register : ADDRMAP1 @ 0XFD070204</p>
3799
3800                 Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
3801                 bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
3802                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
3803
3804                 Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
3805                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3806                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
3807
3808                 Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
3809                 r each of the bank address bits is determined by adding the internal base to the value of this field.
3810                 PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
3811
3812                 Address Map Register 1
3813                 (OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
3814                 RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK |  0 );
3815
3816                 RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
3817                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
3818                         | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
3819                         |  0 ) & RegMask); */
3820                 PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU);
3821         /*############################################################################################################################ */
3822
3823                 /*Register : ADDRMAP2 @ 0XFD070208</p>
3824
3825                 - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
3826                 s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
3827                  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
3828                  this field. If set to 15, this column address bit is set to 0.
3829                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
3830
3831                 - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
3832                 s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
3833                 Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
3834                 this field. If set to 15, this column address bit is set to 0.
3835                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
3836
3837                 - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
3838                 s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
3839                 Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
3840                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
3841                  this case.
3842                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
3843
3844                 - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
3845                 s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
3846                 Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
3847                 ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
3848                 PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
3849
3850                 Address Map Register 2
3851                 (OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
3852                 RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK |  0 );
3853
3854                 RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
3855                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
3856                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
3857                         | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
3858                         |  0 ) & RegMask); */
3859                 PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3860         /*############################################################################################################################ */
3861
3862                 /*Register : ADDRMAP3 @ 0XFD07020C</p>
3863
3864                 - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
3865                 s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
3866                 column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
3867                  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note:
3868                 er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
3869                 ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
3870                  hence column bit 10 is used.
3871                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
3872
3873                 - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
3874                 s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
3875                  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
3876                 ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
3877                 cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
3878                 mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
3879                 .
3880                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
3881
3882                 - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
3883                 s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
3884                 Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
3885                 this field. If set to 15, this column address bit is set to 0.
3886                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
3887
3888                 - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
3889                 s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
3890                 Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
3891                 this field. If set to 15, this column address bit is set to 0.
3892                 PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
3893
3894                 Address Map Register 3
3895                 (OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
3896                 RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK |  0 );
3897
3898                 RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
3899                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
3900                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
3901                         | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
3902                         |  0 ) & RegMask); */
3903                 PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U);
3904         /*############################################################################################################################ */
3905
3906                 /*Register : ADDRMAP4 @ 0XFD070210</p>
3907
3908                 - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
3909                 mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must
3910                 e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
3911                 l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
3912                 n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
3913                 dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
3914                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
3915
3916                 - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
3917                 mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
3918                 To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
3919                 termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
3920                 JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
3921                 bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
3922                 nce column bit 10 is used.
3923                 PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
3924
3925                 Address Map Register 4
3926                 (OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)
3927                 RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK |  0 );
3928
3929                 RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
3930                         | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
3931                         |  0 ) & RegMask); */
3932                 PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU);
3933         /*############################################################################################################################ */
3934
3935                 /*Register : ADDRMAP5 @ 0XFD070214</p>
3936
3937                 Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
3938                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
3939                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
3940
3941                 Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
3942                 bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF
3943                 ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value
3944                 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
3945                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
3946
3947                 Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
3948                  each of the row address bits is determined by adding the internal base to the value of this field.
3949                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
3950
3951                 Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
3952                  each of the row address bits is determined by adding the internal base to the value of this field.
3953                 PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
3954
3955                 Address Map Register 5
3956                 (OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
3957                 RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK |  0 );
3958
3959                 RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
3960                         | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
3961                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
3962                         | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
3963                         |  0 ) & RegMask); */
3964                 PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U);
3965         /*############################################################################################################################ */
3966
3967                 /*Register : ADDRMAP6 @ 0XFD070218</p>
3968
3969                 Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
3970                 having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
3971                 y in designs configured to support LPDDR3.
3972                 PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
3973
3974                 Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
3975                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
3976                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
3977
3978                 Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
3979                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
3980                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
3981
3982                 Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
3983                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
3984                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
3985
3986                 Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
3987                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
3988                 PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
3989
3990                 Address Map Register 6
3991                 (OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
3992                 RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK |  0 );
3993
3994                 RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
3995                         | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
3996                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
3997                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
3998                         | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
3999                         |  0 ) & RegMask); */
4000                 PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U);
4001         /*############################################################################################################################ */
4002
4003                 /*Register : ADDRMAP7 @ 0XFD07021C</p>
4004
4005                 Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
4006                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
4007                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
4008
4009                 Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
4010                 s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
4011                 PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
4012
4013                 Address Map Register 7
4014                 (OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
4015                 RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK |  0 );
4016
4017                 RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
4018                         | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
4019                         |  0 ) & RegMask); */
4020                 PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU);
4021         /*############################################################################################################################ */
4022
4023                 /*Register : ADDRMAP8 @ 0XFD070220</p>
4024
4025                 Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
4026                 address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If
4027                 et to 31, bank group address bit 1 is set to 0.
4028                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
4029
4030                 Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
4031                 bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
4032                 PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
4033
4034                 Address Map Register 8
4035                 (OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)
4036                 RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK |  0 );
4037
4038                 RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
4039                         | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
4040                         |  0 ) & RegMask); */
4041                 PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U);
4042         /*############################################################################################################################ */
4043
4044                 /*Register : ADDRMAP9 @ 0XFD070224</p>
4045
4046                 Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
4047                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4048                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4049                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
4050
4051                 Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
4052                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4053                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4054                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
4055
4056                 Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
4057                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4058                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4059                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
4060
4061                 Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
4062                  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
4063                 d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4064                 PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
4065
4066                 Address Map Register 9
4067                 (OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
4068                 RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK |  0 );
4069
4070                 RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
4071                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
4072                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
4073                         | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
4074                         |  0 ) & RegMask); */
4075                 PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U);
4076         /*############################################################################################################################ */
4077
4078                 /*Register : ADDRMAP10 @ 0XFD070228</p>
4079
4080                 Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
4081                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4082                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4083                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
4084
4085                 Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
4086                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4087                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4088                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
4089
4090                 Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
4091                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4092                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4093                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
4094
4095                 Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
4096                 r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
4097                 ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4098                 PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
4099
4100                 Address Map Register 10
4101                 (OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
4102                 RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK |  0 );
4103
4104                 RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
4105                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
4106                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
4107                         | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
4108                         |  0 ) & RegMask); */
4109                 PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U);
4110         /*############################################################################################################################ */
4111
4112                 /*Register : ADDRMAP11 @ 0XFD07022C</p>
4113
4114                 Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit
4115                 or each of the row address bits is determined by adding the internal base to the value of this field. This register field is
4116                 sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
4117                 PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
4118
4119                 Address Map Register 11
4120                 (OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)
4121                 RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK |  0 );
4122
4123                 RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
4124                         |  0 ) & RegMask); */
4125                 PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U);
4126         /*############################################################################################################################ */
4127
4128                 /*Register : ODTCFG @ 0XFD070240</p>
4129
4130                 Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
4131                 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: -
4132                 L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1
4133                 CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
4134                 PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
4135
4136                 The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
4137                 remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
4138                 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
4139                  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
4140                 PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
4141
4142                 Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
4143                  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
4144                 tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
4145                 )
4146                 PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
4147
4148                 The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must
4149                 emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
4150                 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
4151                 L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
4152                 write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
4153                 uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
4154                 PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
4155
4156                 ODT Configuration Register
4157                 (OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
4158                 RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK |  0 );
4159
4160                 RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
4161                         | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
4162                         | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
4163                         | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
4164                         |  0 ) & RegMask); */
4165                 PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U);
4166         /*############################################################################################################################ */
4167
4168                 /*Register : ODTMAP @ 0XFD070244</p>
4169
4170                 Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can
4171                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4172                  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
4173                 PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
4174
4175                 Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
4176                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4177                 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
4178                 PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
4179
4180                 Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can
4181                 e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
4182                  etc. For each rank, set its bit to 1 to enable its ODT.
4183                 PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
4184
4185                 Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
4186                  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
4187                 etc. For each rank, set its bit to 1 to enable its ODT.
4188                 PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
4189
4190                 ODT/Rank Map Register
4191                 (OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)
4192                 RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK |  0 );
4193
4194                 RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
4195                         | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
4196                         | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
4197                         | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
4198                         |  0 ) & RegMask); */
4199                 PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U);
4200         /*############################################################################################################################ */
4201
4202                 /*Register : SCHED @ 0XFD070250</p>
4203
4204                 When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
4205                 non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
4206                 ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this
4207                 egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
4208                 OR PERFORMANCE ONLY
4209                 PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
4210
4211                 UNUSED
4212                 PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
4213
4214                 Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
4215                  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
4216                 to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
4217                 priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
4218                  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
4219                 sing out of single bit error correction RMW operation.
4220                 PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
4221
4222                 If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
4223                 e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this
4224                 egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
4225                 es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed
4226                 s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
4227                 ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open
4228                 age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
4229                 ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
4230                 PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
4231
4232                 If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
4233                 PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
4234
4235                 Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
4236                 ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
4237                 e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
4238                 ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
4239                 PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
4240
4241                 Scheduler Control Register
4242                 (OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)
4243                 RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK |  0 );
4244
4245                 RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
4246                         | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
4247                         | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
4248                         | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT
4249                         | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT
4250                         | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
4251                         |  0 ) & RegMask); */
4252                 PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U);
4253         /*############################################################################################################################ */
4254
4255                 /*Register : PERFLPR1 @ 0XFD070264</p>
4256
4257                 Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
4258                  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
4259                 PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
4260
4261                 Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
4262                 er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4263                 be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4264                 PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
4265
4266                 Low Priority Read CAM Register 1
4267                 (OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)
4268                 RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK |  0 );
4269
4270                 RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
4271                         | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
4272                         |  0 ) & RegMask); */
4273                 PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
4274         /*############################################################################################################################ */
4275
4276                 /*Register : PERFWR1 @ 0XFD07026C</p>
4277
4278                 Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
4279                 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
4280                 PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
4281
4282                 Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
4283                 r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
4284                 e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
4285                 PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
4286
4287                 Write CAM Register 1
4288                 (OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)
4289                 RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK |  0 );
4290
4291                 RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
4292                         | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT
4293                         |  0 ) & RegMask); */
4294                 PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
4295         /*############################################################################################################################ */
4296
4297                 /*Register : DQMAP5 @ 0XFD070294</p>
4298
4299                 All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
4300                 all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and
4301                 wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
4302                 port DDR4.
4303                 PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
4304
4305                 DQ Map Register 5
4306                 (OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)
4307                 RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK |  0 );
4308
4309                 RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
4310                         |  0 ) & RegMask); */
4311                 PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U);
4312         /*############################################################################################################################ */
4313
4314                 /*Register : DBG0 @ 0XFD070300</p>
4315
4316                 When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
4317                 lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
4318                 s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
4319                 PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
4320
4321                 When 1, disable write combine. FOR DEBUG ONLY
4322                 PSU_DDRC_DBG0_DIS_WC                                                            0x0
4323
4324                 Debug Register 0
4325                 (OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)
4326                 RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK |  0 );
4327
4328                 RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
4329                         | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT
4330                         |  0 ) & RegMask); */
4331                 PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U);
4332         /*############################################################################################################################ */
4333
4334                 /*Register : DBGCMD @ 0XFD07030C</p>
4335
4336                 Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
4337                 the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
4338                 register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
4339                 _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
4340                  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
4341                 PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
4342
4343                 Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in
4344                 he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
4345                 PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
4346
4347                 Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to
4348                 he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
4349                 en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
4350                 d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
4351                 de.
4352                 PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
4353
4354                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
4355                 refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4356                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4357                 wn operating modes or Maximum Power Saving Mode.
4358                 PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
4359
4360                 Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
4361                 refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
4362                 be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
4363                 wn operating modes or Maximum Power Saving Mode.
4364                 PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
4365
4366                 Command Debug Register
4367                 (OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)
4368                 RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK |  0 );
4369
4370                 RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
4371                         | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT
4372                         | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
4373                         | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT
4374                         | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT
4375                         |  0 ) & RegMask); */
4376                 PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U);
4377         /*############################################################################################################################ */
4378
4379                 /*Register : SWCTL @ 0XFD070320</p>
4380
4381                 Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back
4382                 egister to 1 once programming is done.
4383                 PSU_DDRC_SWCTL_SW_DONE                                                          0x0
4384
4385                 Software register programming control enable
4386                 (OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)
4387                 RegMask = (DDRC_SWCTL_SW_DONE_MASK |  0 );
4388
4389                 RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT
4390                         |  0 ) & RegMask); */
4391                 PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U);
4392         /*############################################################################################################################ */
4393
4394                 /*Register : PCCFG @ 0XFD070400</p>
4395
4396                 Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
4397                 e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
4398                 h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
4399                 ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
4400                 _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
4401                 ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
4402                 DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
4403                 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
4404                 -AC is enabled
4405                 PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
4406
4407                 Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
4408                 rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
4409                 ge DDRC transactions.
4410                 PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
4411
4412                 If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based
4413                 n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
4414                 _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
4415                 PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
4416
4417                 Port Common Configuration Register
4418                 (OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)
4419                 RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK |  0 );
4420
4421                 RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT
4422                         | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
4423                         | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
4424                         |  0 ) & RegMask); */
4425                 PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U);
4426         /*############################################################################################################################ */
4427
4428                 /*Register : PCFGR_0 @ 0XFD070404</p>
4429
4430                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4431                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4432                 imit register.
4433                 PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
4434
4435                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4436                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4437                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4438                 ess handshaking (it is not associated with any particular command).
4439                 PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
4440
4441                 If set to 1, enables aging function for the read channel of the port.
4442                 PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
4443
4444                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4445                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4446                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4447                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4448                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4449                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4450                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4451                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4452                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4453                 he two LSBs of this register field are tied internally to 2'b00.
4454                 PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
4455
4456                 Port n Configuration Read Register
4457                 (OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)
4458                 RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK |  0 );
4459
4460                 RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
4461                         | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
4462                         | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
4463                         | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
4464                         |  0 ) & RegMask); */
4465                 PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU);
4466         /*############################################################################################################################ */
4467
4468                 /*Register : PCFGW_0 @ 0XFD070408</p>
4469
4470                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4471                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4472                 imit register.
4473                 PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
4474
4475                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4476                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4477                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4478                 not associated with any particular command).
4479                 PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
4480
4481                 If set to 1, enables aging function for the write channel of the port.
4482                 PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
4483
4484                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4485                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4486                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4487                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4488                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4489                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4490                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4491                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4492                 PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
4493
4494                 Port n Configuration Write Register
4495                 (OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)
4496                 RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK |  0 );
4497
4498                 RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
4499                         | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
4500                         | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
4501                         | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
4502                         |  0 ) & RegMask); */
4503                 PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU);
4504         /*############################################################################################################################ */
4505
4506                 /*Register : PCTRL_0 @ 0XFD070490</p>
4507
4508                 Enables port n.
4509                 PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
4510
4511                 Port n Control Register
4512                 (OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)
4513                 RegMask = (DDRC_PCTRL_0_PORT_EN_MASK |  0 );
4514
4515                 RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT
4516                         |  0 ) & RegMask); */
4517                 PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U);
4518         /*############################################################################################################################ */
4519
4520                 /*Register : PCFGQOS0_0 @ 0XFD070494</p>
4521
4522                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4523                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4524                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4525                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
4526
4527                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4528                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4529                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4530                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
4531
4532                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4533                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4534                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4535                  values.
4536                 PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
4537
4538                 Port n Read QoS Configuration Register 0
4539                 (OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)
4540                 RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK |  0 );
4541
4542                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
4543                         | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
4544                         | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
4545                         |  0 ) & RegMask); */
4546                 PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU);
4547         /*############################################################################################################################ */
4548
4549                 /*Register : PCFGQOS1_0 @ 0XFD070498</p>
4550
4551                 Specifies the timeout value for transactions mapped to the red address queue.
4552                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
4553
4554                 Specifies the timeout value for transactions mapped to the blue address queue.
4555                 PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
4556
4557                 Port n Read QoS Configuration Register 1
4558                 (OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)
4559                 RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK |  0 );
4560
4561                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
4562                         | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
4563                         |  0 ) & RegMask); */
4564                 PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U);
4565         /*############################################################################################################################ */
4566
4567                 /*Register : PCFGR_1 @ 0XFD0704B4</p>
4568
4569                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4570                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4571                 imit register.
4572                 PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
4573
4574                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4575                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4576                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4577                 ess handshaking (it is not associated with any particular command).
4578                 PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
4579
4580                 If set to 1, enables aging function for the read channel of the port.
4581                 PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
4582
4583                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4584                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4585                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4586                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4587                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4588                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4589                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4590                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4591                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4592                 he two LSBs of this register field are tied internally to 2'b00.
4593                 PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
4594
4595                 Port n Configuration Read Register
4596                 (OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)
4597                 RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK |  0 );
4598
4599                 RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
4600                         | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
4601                         | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
4602                         | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
4603                         |  0 ) & RegMask); */
4604                 PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU);
4605         /*############################################################################################################################ */
4606
4607                 /*Register : PCFGW_1 @ 0XFD0704B8</p>
4608
4609                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4610                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4611                 imit register.
4612                 PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
4613
4614                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4615                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4616                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4617                 not associated with any particular command).
4618                 PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
4619
4620                 If set to 1, enables aging function for the write channel of the port.
4621                 PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
4622
4623                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4624                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4625                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4626                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4627                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4628                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4629                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4630                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4631                 PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
4632
4633                 Port n Configuration Write Register
4634                 (OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)
4635                 RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK |  0 );
4636
4637                 RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
4638                         | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
4639                         | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
4640                         | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
4641                         |  0 ) & RegMask); */
4642                 PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU);
4643         /*############################################################################################################################ */
4644
4645                 /*Register : PCTRL_1 @ 0XFD070540</p>
4646
4647                 Enables port n.
4648                 PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
4649
4650                 Port n Control Register
4651                 (OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)
4652                 RegMask = (DDRC_PCTRL_1_PORT_EN_MASK |  0 );
4653
4654                 RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT
4655                         |  0 ) & RegMask); */
4656                 PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U);
4657         /*############################################################################################################################ */
4658
4659                 /*Register : PCFGQOS0_1 @ 0XFD070544</p>
4660
4661                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4662                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4663                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4664                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
4665
4666                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4667                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4668                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4669                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
4670
4671                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4672                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4673                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4674                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
4675
4676                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4677                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4678                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4679                 ust be set to distinct values.
4680                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
4681
4682                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4683                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4684                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4685                  values.
4686                 PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
4687
4688                 Port n Read QoS Configuration Register 0
4689                 (OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)
4690                 RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK |  0 );
4691
4692                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
4693                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
4694                         | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
4695                         | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
4696                         | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
4697                         |  0 ) & RegMask); */
4698                 PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U);
4699         /*############################################################################################################################ */
4700
4701                 /*Register : PCFGQOS1_1 @ 0XFD070548</p>
4702
4703                 Specifies the timeout value for transactions mapped to the red address queue.
4704                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
4705
4706                 Specifies the timeout value for transactions mapped to the blue address queue.
4707                 PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
4708
4709                 Port n Read QoS Configuration Register 1
4710                 (OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)
4711                 RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK |  0 );
4712
4713                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
4714                         | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
4715                         |  0 ) & RegMask); */
4716                 PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U);
4717         /*############################################################################################################################ */
4718
4719                 /*Register : PCFGR_2 @ 0XFD070564</p>
4720
4721                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4722                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4723                 imit register.
4724                 PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
4725
4726                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4727                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4728                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4729                 ess handshaking (it is not associated with any particular command).
4730                 PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
4731
4732                 If set to 1, enables aging function for the read channel of the port.
4733                 PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
4734
4735                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4736                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4737                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4738                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4739                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4740                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4741                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4742                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4743                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4744                 he two LSBs of this register field are tied internally to 2'b00.
4745                 PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
4746
4747                 Port n Configuration Read Register
4748                 (OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)
4749                 RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK |  0 );
4750
4751                 RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
4752                         | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
4753                         | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
4754                         | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
4755                         |  0 ) & RegMask); */
4756                 PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU);
4757         /*############################################################################################################################ */
4758
4759                 /*Register : PCFGW_2 @ 0XFD070568</p>
4760
4761                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4762                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4763                 imit register.
4764                 PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
4765
4766                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4767                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4768                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4769                 not associated with any particular command).
4770                 PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
4771
4772                 If set to 1, enables aging function for the write channel of the port.
4773                 PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
4774
4775                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4776                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4777                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4778                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4779                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4780                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4781                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4782                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4783                 PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
4784
4785                 Port n Configuration Write Register
4786                 (OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)
4787                 RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK |  0 );
4788
4789                 RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
4790                         | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
4791                         | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
4792                         | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
4793                         |  0 ) & RegMask); */
4794                 PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU);
4795         /*############################################################################################################################ */
4796
4797                 /*Register : PCTRL_2 @ 0XFD0705F0</p>
4798
4799                 Enables port n.
4800                 PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
4801
4802                 Port n Control Register
4803                 (OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)
4804                 RegMask = (DDRC_PCTRL_2_PORT_EN_MASK |  0 );
4805
4806                 RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT
4807                         |  0 ) & RegMask); */
4808                 PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U);
4809         /*############################################################################################################################ */
4810
4811                 /*Register : PCFGQOS0_2 @ 0XFD0705F4</p>
4812
4813                 This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address
4814                 ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2
4815                 s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4816                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
4817
4818                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4819                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4820                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4821                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
4822
4823                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4824                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4825                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4826                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
4827
4828                 Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
4829                 el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
4830                 directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers
4831                 ust be set to distinct values.
4832                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
4833
4834                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4835                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4836                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4837                  values.
4838                 PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
4839
4840                 Port n Read QoS Configuration Register 0
4841                 (OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)
4842                 RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK |  0 );
4843
4844                 RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
4845                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
4846                         | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
4847                         | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
4848                         | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
4849                         |  0 ) & RegMask); */
4850                 PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U);
4851         /*############################################################################################################################ */
4852
4853                 /*Register : PCFGQOS1_2 @ 0XFD0705F8</p>
4854
4855                 Specifies the timeout value for transactions mapped to the red address queue.
4856                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
4857
4858                 Specifies the timeout value for transactions mapped to the blue address queue.
4859                 PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
4860
4861                 Port n Read QoS Configuration Register 1
4862                 (OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)
4863                 RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK |  0 );
4864
4865                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
4866                         | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
4867                         |  0 ) & RegMask); */
4868                 PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U);
4869         /*############################################################################################################################ */
4870
4871                 /*Register : PCFGR_3 @ 0XFD070614</p>
4872
4873                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4874                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4875                 imit register.
4876                 PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
4877
4878                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
4879                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
4880                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
4881                 ess handshaking (it is not associated with any particular command).
4882                 PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
4883
4884                 If set to 1, enables aging function for the read channel of the port.
4885                 PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
4886
4887                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
4888                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4889                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
4890                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
4891                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
4892                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
4893                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
4894                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
4895                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
4896                 he two LSBs of this register field are tied internally to 2'b00.
4897                 PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
4898
4899                 Port n Configuration Read Register
4900                 (OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)
4901                 RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK |  0 );
4902
4903                 RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
4904                         | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
4905                         | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
4906                         | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
4907                         |  0 ) & RegMask); */
4908                 PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU);
4909         /*############################################################################################################################ */
4910
4911                 /*Register : PCFGW_3 @ 0XFD070618</p>
4912
4913                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
4914                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
4915                 imit register.
4916                 PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
4917
4918                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
4919                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
4920                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
4921                 not associated with any particular command).
4922                 PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
4923
4924                 If set to 1, enables aging function for the write channel of the port.
4925                 PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
4926
4927                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
4928                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
4929                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
4930                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
4931                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
4932                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
4933                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
4934                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
4935                 PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
4936
4937                 Port n Configuration Write Register
4938                 (OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)
4939                 RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK |  0 );
4940
4941                 RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
4942                         | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
4943                         | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
4944                         | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
4945                         |  0 ) & RegMask); */
4946                 PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU);
4947         /*############################################################################################################################ */
4948
4949                 /*Register : PCTRL_3 @ 0XFD0706A0</p>
4950
4951                 Enables port n.
4952                 PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
4953
4954                 Port n Control Register
4955                 (OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)
4956                 RegMask = (DDRC_PCTRL_3_PORT_EN_MASK |  0 );
4957
4958                 RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT
4959                         |  0 ) & RegMask); */
4960                 PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U);
4961         /*############################################################################################################################ */
4962
4963                 /*Register : PCFGQOS0_3 @ 0XFD0706A4</p>
4964
4965                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
4966                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
4967                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4968                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
4969
4970                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
4971                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
4972                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
4973                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
4974
4975                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
4976                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
4977                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
4978                  values.
4979                 PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
4980
4981                 Port n Read QoS Configuration Register 0
4982                 (OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)
4983                 RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK |  0 );
4984
4985                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
4986                         | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
4987                         | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
4988                         |  0 ) & RegMask); */
4989                 PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
4990         /*############################################################################################################################ */
4991
4992                 /*Register : PCFGQOS1_3 @ 0XFD0706A8</p>
4993
4994                 Specifies the timeout value for transactions mapped to the red address queue.
4995                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
4996
4997                 Specifies the timeout value for transactions mapped to the blue address queue.
4998                 PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
4999
5000                 Port n Read QoS Configuration Register 1
5001                 (OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)
5002                 RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK |  0 );
5003
5004                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
5005                         | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
5006                         |  0 ) & RegMask); */
5007                 PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU);
5008         /*############################################################################################################################ */
5009
5010                 /*Register : PCFGWQOS0_3 @ 0XFD0706AC</p>
5011
5012                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5013                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
5014                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
5015
5016                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5017                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
5018                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
5019
5020                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5021                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5022                 s to higher port priority.
5023                 PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
5024
5025                 Port n Write QoS Configuration Register 0
5026                 (OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)
5027                 RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK |  0 );
5028
5029                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
5030                         | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
5031                         | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
5032                         |  0 ) & RegMask); */
5033                 PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
5034         /*############################################################################################################################ */
5035
5036                 /*Register : PCFGWQOS1_3 @ 0XFD0706B0</p>
5037
5038                 Specifies the timeout value for write transactions.
5039                 PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
5040
5041                 Port n Write QoS Configuration Register 1
5042                 (OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)
5043                 RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK |  0 );
5044
5045                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
5046                         |  0 ) & RegMask); */
5047                 PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU);
5048         /*############################################################################################################################ */
5049
5050                 /*Register : PCFGR_4 @ 0XFD0706C4</p>
5051
5052                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5053                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5054                 imit register.
5055                 PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
5056
5057                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5058                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5059                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5060                 ess handshaking (it is not associated with any particular command).
5061                 PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
5062
5063                 If set to 1, enables aging function for the read channel of the port.
5064                 PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
5065
5066                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5067                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5068                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5069                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5070                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5071                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5072                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5073                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5074                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5075                 he two LSBs of this register field are tied internally to 2'b00.
5076                 PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
5077
5078                 Port n Configuration Read Register
5079                 (OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)
5080                 RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK |  0 );
5081
5082                 RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
5083                         | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
5084                         | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
5085                         | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
5086                         |  0 ) & RegMask); */
5087                 PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU);
5088         /*############################################################################################################################ */
5089
5090                 /*Register : PCFGW_4 @ 0XFD0706C8</p>
5091
5092                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5093                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5094                 imit register.
5095                 PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
5096
5097                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5098                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5099                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5100                 not associated with any particular command).
5101                 PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
5102
5103                 If set to 1, enables aging function for the write channel of the port.
5104                 PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
5105
5106                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5107                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5108                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5109                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5110                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5111                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5112                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5113                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
5114                 PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
5115
5116                 Port n Configuration Write Register
5117                 (OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)
5118                 RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK |  0 );
5119
5120                 RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
5121                         | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
5122                         | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
5123                         | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
5124                         |  0 ) & RegMask); */
5125                 PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU);
5126         /*############################################################################################################################ */
5127
5128                 /*Register : PCTRL_4 @ 0XFD070750</p>
5129
5130                 Enables port n.
5131                 PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
5132
5133                 Port n Control Register
5134                 (OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)
5135                 RegMask = (DDRC_PCTRL_4_PORT_EN_MASK |  0 );
5136
5137                 RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT
5138                         |  0 ) & RegMask); */
5139                 PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U);
5140         /*############################################################################################################################ */
5141
5142                 /*Register : PCFGQOS0_4 @ 0XFD070754</p>
5143
5144                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5145                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5146                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5147                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
5148
5149                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5150                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5151                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5152                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
5153
5154                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5155                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5156                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5157                  values.
5158                 PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
5159
5160                 Port n Read QoS Configuration Register 0
5161                 (OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)
5162                 RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK |  0 );
5163
5164                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
5165                         | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
5166                         | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
5167                         |  0 ) & RegMask); */
5168                 PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
5169         /*############################################################################################################################ */
5170
5171                 /*Register : PCFGQOS1_4 @ 0XFD070758</p>
5172
5173                 Specifies the timeout value for transactions mapped to the red address queue.
5174                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
5175
5176                 Specifies the timeout value for transactions mapped to the blue address queue.
5177                 PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
5178
5179                 Port n Read QoS Configuration Register 1
5180                 (OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)
5181                 RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK |  0 );
5182
5183                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
5184                         | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
5185                         |  0 ) & RegMask); */
5186                 PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU);
5187         /*############################################################################################################################ */
5188
5189                 /*Register : PCFGWQOS0_4 @ 0XFD07075C</p>
5190
5191                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5192                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
5193                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
5194
5195                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5196                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
5197                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
5198
5199                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5200                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5201                 s to higher port priority.
5202                 PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
5203
5204                 Port n Write QoS Configuration Register 0
5205                 (OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)
5206                 RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK |  0 );
5207
5208                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
5209                         | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
5210                         | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
5211                         |  0 ) & RegMask); */
5212                 PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
5213         /*############################################################################################################################ */
5214
5215                 /*Register : PCFGWQOS1_4 @ 0XFD070760</p>
5216
5217                 Specifies the timeout value for write transactions.
5218                 PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
5219
5220                 Port n Write QoS Configuration Register 1
5221                 (OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)
5222                 RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK |  0 );
5223
5224                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
5225                         |  0 ) & RegMask); */
5226                 PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU);
5227         /*############################################################################################################################ */
5228
5229                 /*Register : PCFGR_5 @ 0XFD070774</p>
5230
5231                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5232                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5233                 imit register.
5234                 PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
5235
5236                 If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
5237                  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
5238                 o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
5239                 ess handshaking (it is not associated with any particular command).
5240                 PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
5241
5242                 If set to 1, enables aging function for the read channel of the port.
5243                 PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
5244
5245                 Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
5246                 ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5247                 he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
5248                 will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
5249                 ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
5250                 aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
5251                 ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
5252                 ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
5253                 RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note:
5254                 he two LSBs of this register field are tied internally to 2'b00.
5255                 PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
5256
5257                 Port n Configuration Read Register
5258                 (OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)
5259                 RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK |  0 );
5260
5261                 RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
5262                         | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
5263                         | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
5264                         | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
5265                         |  0 ) & RegMask); */
5266                 PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU);
5267         /*############################################################################################################################ */
5268
5269                 /*Register : PCFGW_5 @ 0XFD070778</p>
5270
5271                 If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
5272                 d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
5273                 imit register.
5274                 PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
5275
5276                 If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
5277                  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
5278                  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
5279                 not associated with any particular command).
5280                 PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
5281
5282                 If set to 1, enables aging function for the write channel of the port.
5283                 PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
5284
5285                 Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each
5286                 rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
5287                 The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
5288                 s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
5289                  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
5290                  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For
5291                 ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
5292                 ng. Note: The two LSBs of this register field are tied internally to 2'b00.
5293                 PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
5294
5295                 Port n Configuration Write Register
5296                 (OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)
5297                 RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK |  0 );
5298
5299                 RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
5300                         | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
5301                         | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
5302                         | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
5303                         |  0 ) & RegMask); */
5304                 PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU);
5305         /*############################################################################################################################ */
5306
5307                 /*Register : PCTRL_5 @ 0XFD070800</p>
5308
5309                 Enables port n.
5310                 PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
5311
5312                 Port n Control Register
5313                 (OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)
5314                 RegMask = (DDRC_PCTRL_5_PORT_EN_MASK |  0 );
5315
5316                 RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT
5317                         |  0 ) & RegMask); */
5318                 PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U);
5319         /*############################################################################################################################ */
5320
5321                 /*Register : PCFGQOS0_5 @ 0XFD070804</p>
5322
5323                 This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
5324                 gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
5325                 disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5326                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
5327
5328                 This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
5329                 urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
5330                  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
5331                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
5332
5333                 Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
5334                 al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
5335                 ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
5336                  values.
5337                 PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
5338
5339                 Port n Read QoS Configuration Register 0
5340                 (OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)
5341                 RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK |  0 );
5342
5343                 RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
5344                         | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
5345                         | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
5346                         |  0 ) & RegMask); */
5347                 PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5348         /*############################################################################################################################ */
5349
5350                 /*Register : PCFGQOS1_5 @ 0XFD070808</p>
5351
5352                 Specifies the timeout value for transactions mapped to the red address queue.
5353                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
5354
5355                 Specifies the timeout value for transactions mapped to the blue address queue.
5356                 PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
5357
5358                 Port n Read QoS Configuration Register 1
5359                 (OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)
5360                 RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK |  0 );
5361
5362                 RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
5363                         | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
5364                         |  0 ) & RegMask); */
5365                 PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU);
5366         /*############################################################################################################################ */
5367
5368                 /*Register : PCFGWQOS0_5 @ 0XFD07080C</p>
5369
5370                 This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5371                 VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
5372                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
5373
5374                 This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
5375                 VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
5376                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
5377
5378                 Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
5379                 rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
5380                 s to higher port priority.
5381                 PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
5382
5383                 Port n Write QoS Configuration Register 0
5384                 (OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)
5385                 RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK |  0 );
5386
5387                 RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
5388                         | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
5389                         | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
5390                         |  0 ) & RegMask); */
5391                 PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
5392         /*############################################################################################################################ */
5393
5394                 /*Register : PCFGWQOS1_5 @ 0XFD070810</p>
5395
5396                 Specifies the timeout value for write transactions.
5397                 PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
5398
5399                 Port n Write QoS Configuration Register 1
5400                 (OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)
5401                 RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK |  0 );
5402
5403                 RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
5404                         |  0 ) & RegMask); */
5405                 PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU);
5406         /*############################################################################################################################ */
5407
5408                 /*Register : SARBASE0 @ 0XFD070F04</p>
5409
5410                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5411                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5412                 PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
5413
5414                 SAR Base Address Register n
5415                 (OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)
5416                 RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK |  0 );
5417
5418                 RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT
5419                         |  0 ) & RegMask); */
5420                 PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U);
5421         /*############################################################################################################################ */
5422
5423                 /*Register : SARSIZE0 @ 0XFD070F08</p>
5424
5425                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5426                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5427                 or example, if register is programmed to 0, region will have 1 block.
5428                 PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
5429
5430                 SAR Size Register n
5431                 (OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)
5432                 RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK |  0 );
5433
5434                 RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT
5435                         |  0 ) & RegMask); */
5436                 PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U);
5437         /*############################################################################################################################ */
5438
5439                 /*Register : SARBASE1 @ 0XFD070F0C</p>
5440
5441                 Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
5442                  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
5443                 PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
5444
5445                 SAR Base Address Register n
5446                 (OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)
5447                 RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK |  0 );
5448
5449                 RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT
5450                         |  0 ) & RegMask); */
5451                 PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U);
5452         /*############################################################################################################################ */
5453
5454                 /*Register : SARSIZE1 @ 0XFD070F10</p>
5455
5456                 Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
5457                 e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1.
5458                 or example, if register is programmed to 0, region will have 1 block.
5459                 PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
5460
5461                 SAR Size Register n
5462                 (OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)
5463                 RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK |  0 );
5464
5465                 RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT
5466                         |  0 ) & RegMask); */
5467                 PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU);
5468         /*############################################################################################################################ */
5469
5470                 /*Register : DFITMG0_SHADOW @ 0XFD072190</p>
5471
5472                 Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
5473                 s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
5474                 , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
5475                  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
5476                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
5477
5478                 Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
5479                 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
5480                 fer to PHY specification for correct value.
5481                 PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
5482
5483                 Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
5484                 ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
5485                 , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
5486                  latency through the RDIMM. Unit: Clocks
5487                 PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
5488
5489                 Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
5490                 .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
5491                 HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
5492                 e.
5493                 PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
5494
5495                 Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
5496                  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
5497                 te, max supported value is 8. Unit: Clocks
5498                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
5499
5500                 Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
5501                  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
5502                  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
5503                 rough the RDIMM.
5504                 PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
5505
5506                 DFI Timing Shadow Register 0
5507                 (OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)
5508                 RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK |  0 );
5509
5510                 RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
5511                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
5512                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
5513                         | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
5514                         | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
5515                         | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
5516                         |  0 ) & RegMask); */
5517                 PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U);
5518         /*############################################################################################################################ */
5519
5520                 // : DDR CONTROLLER RESET
5521                 /*Register : RST_DDR_SS @ 0XFD1A0108</p>
5522
5523                 DDR block level reset inside of the DDR Sub System
5524                 PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
5525
5526                 DDR sub system block level reset
5527                 (OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)
5528                 RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
5529
5530                 RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
5531                         |  0 ) & RegMask); */
5532                 PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U);
5533         /*############################################################################################################################ */
5534
5535                 // : DDR PHY
5536                 /*Register : PGCR0 @ 0XFD080010</p>
5537
5538                 Address Copy
5539                 PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
5540
5541                 Reserved. Returns zeroes on reads.
5542                 PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
5543
5544                 PHY FIFO Reset
5545                 PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
5546
5547                 Oscillator Mode Address/Command Delay Line Select
5548                 PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
5549
5550                 Reserved. Returns zeroes on reads.
5551                 PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
5552
5553                 Digital Test Output Select
5554                 PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
5555
5556                 Reserved. Returns zeroes on reads.
5557                 PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
5558
5559                 Oscillator Mode Division
5560                 PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
5561
5562                 Oscillator Enable
5563                 PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
5564
5565                 Reserved. Returns zeroes on reads.
5566                 PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
5567
5568                 PHY General Configuration Register 0
5569                 (OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)
5570                 RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK |  0 );
5571
5572                 RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT
5573                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
5574                         | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT
5575                         | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT
5576                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
5577                         | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT
5578                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT
5579                         | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT
5580                         | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT
5581                         | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
5582                         |  0 ) & RegMask); */
5583                 PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U);
5584         /*############################################################################################################################ */
5585
5586                 /*Register : PGCR2 @ 0XFD080018</p>
5587
5588                 Clear Training Status Registers
5589                 PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
5590
5591                 Clear Impedance Calibration
5592                 PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
5593
5594                 Clear Parity Error
5595                 PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
5596
5597                 Initialization Complete Pin Configuration
5598                 PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
5599
5600                 Data Training PUB Mode Exit Timer
5601                 PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
5602
5603                 Initialization Bypass
5604                 PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
5605
5606                 PLL FSM Bypass
5607                 PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
5608
5609                 Refresh Period
5610                 PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x12302
5611
5612                 PHY General Configuration Register 2
5613                 (OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)
5614                 RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK |  0 );
5615
5616                 RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
5617                         | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT
5618                         | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT
5619                         | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT
5620                         | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
5621                         | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
5622                         | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
5623                         | 0x00012302U << DDR_PHY_PGCR2_TREFPRD_SHIFT
5624                         |  0 ) & RegMask); */
5625                 PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F12302U);
5626         /*############################################################################################################################ */
5627
5628                 /*Register : PGCR5 @ 0XFD080024</p>
5629
5630                 Frequency B Ratio Term
5631                 PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
5632
5633                 Frequency A Ratio Term
5634                 PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
5635
5636                 DFI Disconnect Time Period
5637                 PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
5638
5639                 Receiver bias core side control
5640                 PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
5641
5642                 Reserved. Return zeroes on reads.
5643                 PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
5644
5645                 Internal VREF generator REFSEL ragne select
5646                 PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
5647
5648                 DDL Page Read Write select
5649                 PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
5650
5651                 DDL Page Read Write select
5652                 PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
5653
5654                 PHY General Configuration Register 5
5655                 (OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)
5656                 RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK |  0 );
5657
5658                 RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT
5659                         | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT
5660                         | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
5661                         | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
5662                         | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT
5663                         | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
5664                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT
5665                         | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT
5666                         |  0 ) & RegMask); */
5667                 PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U);
5668         /*############################################################################################################################ */
5669
5670                 /*Register : PTR0 @ 0XFD080040</p>
5671
5672                 PLL Power-Down Time
5673                 PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
5674
5675                 PLL Gear Shift Time
5676                 PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
5677
5678                 PHY Reset Time
5679                 PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
5680
5681                 PHY Timing Register 0
5682                 (OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)
5683                 RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK |  0 );
5684
5685                 RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT
5686                         | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT
5687                         | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT
5688                         |  0 ) & RegMask); */
5689                 PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U);
5690         /*############################################################################################################################ */
5691
5692                 /*Register : PTR1 @ 0XFD080044</p>
5693
5694                 PLL Lock Time
5695                 PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
5696
5697                 Reserved. Returns zeroes on reads.
5698                 PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
5699
5700                 PLL Reset Time
5701                 PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
5702
5703                 PHY Timing Register 1
5704                 (OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)
5705                 RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK |  0 );
5706
5707                 RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT
5708                         | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT
5709                         | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT
5710                         |  0 ) & RegMask); */
5711                 PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U);
5712         /*############################################################################################################################ */
5713
5714                 /*Register : DSGCR @ 0XFD080090</p>
5715
5716                 Reserved. Return zeroes on reads.
5717                 PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
5718
5719                 When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
5720                 fault calculation.
5721                 PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
5722
5723                 When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
5724                 PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
5725
5726                 PHY Impedance Update Enable
5727                 PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
5728
5729                 Reserved. Return zeroes on reads.
5730                 PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
5731
5732                 SDRAM Reset Output Enable
5733                 PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
5734
5735                 Single Data Rate Mode
5736                 PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
5737
5738                 Reserved. Return zeroes on reads.
5739                 PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
5740
5741                 ATO Analog Test Enable
5742                 PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
5743
5744                 DTO Output Enable
5745                 PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
5746
5747                 DTO I/O Mode
5748                 PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
5749
5750                 DTO Power Down Receiver
5751                 PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
5752
5753                 Reserved. Return zeroes on reads
5754                 PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
5755
5756                 DTO On-Die Termination
5757                 PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
5758
5759                 PHY Update Acknowledge Delay
5760                 PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
5761
5762                 Controller Update Acknowledge Enable
5763                 PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
5764
5765                 Reserved. Return zeroes on reads
5766                 PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
5767
5768                 Controller Impedance Update Enable
5769                 PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
5770
5771                 Reserved. Return zeroes on reads
5772                 PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
5773
5774                 PHY Update Request Enable
5775                 PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
5776
5777                 DDR System General Configuration Register
5778                 (OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)
5779                 RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK |  0 );
5780
5781                 RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
5782                         | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT
5783                         | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT
5784                         | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT
5785                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT
5786                         | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT
5787                         | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT
5788                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT
5789                         | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT
5790                         | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT
5791                         | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT
5792                         | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT
5793                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT
5794                         | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT
5795                         | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT
5796                         | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT
5797                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
5798                         | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT
5799                         | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT
5800                         | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT
5801                         |  0 ) & RegMask); */
5802                 PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U);
5803         /*############################################################################################################################ */
5804
5805                 /*Register : DCR @ 0XFD080100</p>
5806
5807                 DDR4 Gear Down Timing.
5808                 PSU_DDR_PHY_DCR_GEARDN                                                          0x0
5809
5810                 Un-used Bank Group
5811                 PSU_DDR_PHY_DCR_UBG                                                             0x0
5812
5813                 Un-buffered DIMM Address Mirroring
5814                 PSU_DDR_PHY_DCR_UDIMM                                                           0x0
5815
5816                 DDR 2T Timing
5817                 PSU_DDR_PHY_DCR_DDR2T                                                           0x0
5818
5819                 No Simultaneous Rank Access
5820                 PSU_DDR_PHY_DCR_NOSRA                                                           0x1
5821
5822                 Reserved. Return zeroes on reads.
5823                 PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
5824
5825                 Byte Mask
5826                 PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
5827
5828                 DDR Type
5829                 PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
5830
5831                 Multi-Purpose Register (MPR) DQ (DDR3 Only)
5832                 PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
5833
5834                 Primary DQ (DDR3 Only)
5835                 PSU_DDR_PHY_DCR_PDQ                                                             0x0
5836
5837                 DDR 8-Bank
5838                 PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
5839
5840                 DDR Mode
5841                 PSU_DDR_PHY_DCR_DDRMD                                                           0x4
5842
5843                 DRAM Configuration Register
5844                 (OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)
5845                 RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK |  0 );
5846
5847                 RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT
5848                         | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT
5849                         | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT
5850                         | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT
5851                         | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT
5852                         | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT
5853                         | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT
5854                         | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT
5855                         | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT
5856                         | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT
5857                         | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT
5858                         | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT
5859                         |  0 ) & RegMask); */
5860                 PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU);
5861         /*############################################################################################################################ */
5862
5863                 /*Register : DTPR0 @ 0XFD080110</p>
5864
5865                 Reserved. Return zeroes on reads.
5866                 PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
5867
5868                 Activate to activate command delay (different banks)
5869                 PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
5870
5871                 Reserved. Return zeroes on reads.
5872                 PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
5873
5874                 Activate to precharge command delay
5875                 PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
5876
5877                 Reserved. Return zeroes on reads.
5878                 PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
5879
5880                 Precharge command period
5881                 PSU_DDR_PHY_DTPR0_TRP                                                           0x12
5882
5883                 Reserved. Return zeroes on reads.
5884                 PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
5885
5886                 Internal read to precharge command delay
5887                 PSU_DDR_PHY_DTPR0_TRTP                                                          0x8
5888
5889                 DRAM Timing Parameters Register 0
5890                 (OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06241208U)
5891                 RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK |  0 );
5892
5893                 RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
5894                         | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT
5895                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
5896                         | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
5897                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
5898                         | 0x00000012U << DDR_PHY_DTPR0_TRP_SHIFT
5899                         | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
5900                         | 0x00000008U << DDR_PHY_DTPR0_TRTP_SHIFT
5901                         |  0 ) & RegMask); */
5902                 PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06241208U);
5903         /*############################################################################################################################ */
5904
5905                 /*Register : DTPR1 @ 0XFD080114</p>
5906
5907                 Reserved. Return zeroes on reads.
5908                 PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
5909
5910                 Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
5911                 PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
5912
5913                 Reserved. Return zeroes on reads.
5914                 PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
5915
5916                 4-bank activate period
5917                 PSU_DDR_PHY_DTPR1_TFAW                                                          0x18
5918
5919                 Reserved. Return zeroes on reads.
5920                 PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
5921
5922                 Load mode update delay (DDR4 and DDR3 only)
5923                 PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
5924
5925                 Reserved. Return zeroes on reads.
5926                 PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
5927
5928                 Load mode cycle time
5929                 PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
5930
5931                 DRAM Timing Parameters Register 1
5932                 (OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28180708U)
5933                 RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK |  0 );
5934
5935                 RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
5936                         | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
5937                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
5938                         | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT
5939                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
5940                         | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
5941                         | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
5942                         | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
5943                         |  0 ) & RegMask); */
5944                 PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U);
5945         /*############################################################################################################################ */
5946
5947                 /*Register : DTPR2 @ 0XFD080118</p>
5948
5949                 Reserved. Return zeroes on reads.
5950                 PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
5951
5952                 Read to Write command delay. Valid values are
5953                 PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
5954
5955                 Reserved. Return zeroes on reads.
5956                 PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
5957
5958                 Read to ODT delay (DDR3 only)
5959                 PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
5960
5961                 Reserved. Return zeroes on reads.
5962                 PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
5963
5964                 CKE minimum pulse width
5965                 PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
5966
5967                 Reserved. Return zeroes on reads.
5968                 PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
5969
5970                 Self refresh exit delay
5971                 PSU_DDR_PHY_DTPR2_TXS                                                           0x200
5972
5973                 DRAM Timing Parameters Register 2
5974                 (OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)
5975                 RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK |  0 );
5976
5977                 RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
5978                         | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT
5979                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
5980                         | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT
5981                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
5982                         | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT
5983                         | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
5984                         | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT
5985                         |  0 ) & RegMask); */
5986                 PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U);
5987         /*############################################################################################################################ */
5988
5989                 /*Register : DTPR3 @ 0XFD08011C</p>
5990
5991                 ODT turn-off delay extension
5992                 PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
5993
5994                 Read to read and write to write command delay
5995                 PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
5996
5997                 DLL locking time
5998                 PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
5999
6000                 Reserved. Return zeroes on reads.
6001                 PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
6002
6003                 Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
6004                 PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
6005
6006                 Reserved. Return zeroes on reads.
6007                 PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
6008
6009                 DQS output access time from CK/CK# (LPDDR2/3 only)
6010                 PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x4
6011
6012                 DRAM Timing Parameters Register 3
6013                 (OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)
6014                 RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK |  0 );
6015
6016                 RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
6017                         | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT
6018                         | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT
6019                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
6020                         | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
6021                         | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
6022                         | 0x00000004U << DDR_PHY_DTPR3_TDQSCK_SHIFT
6023                         |  0 ) & RegMask); */
6024                 PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000804U);
6025         /*############################################################################################################################ */
6026
6027                 /*Register : DTPR4 @ 0XFD080120</p>
6028
6029                 Reserved. Return zeroes on reads.
6030                 PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
6031
6032                 ODT turn-on/turn-off delays (DDR2 only)
6033                 PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
6034
6035                 Reserved. Return zeroes on reads.
6036                 PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
6037
6038                 Refresh-to-Refresh
6039                 PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
6040
6041                 Reserved. Return zeroes on reads.
6042                 PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
6043
6044                 Write leveling output delay
6045                 PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
6046
6047                 Reserved. Return zeroes on reads.
6048                 PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
6049
6050                 Power down exit delay
6051                 PSU_DDR_PHY_DTPR4_TXP                                                           0x8
6052
6053                 DRAM Timing Parameters Register 4
6054                 (OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)
6055                 RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK |  0 );
6056
6057                 RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
6058                         | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
6059                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
6060                         | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT
6061                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
6062                         | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT
6063                         | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
6064                         | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT
6065                         |  0 ) & RegMask); */
6066                 PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U);
6067         /*############################################################################################################################ */
6068
6069                 /*Register : DTPR5 @ 0XFD080124</p>
6070
6071                 Reserved. Return zeroes on reads.
6072                 PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
6073
6074                 Activate to activate command delay (same bank)
6075                 PSU_DDR_PHY_DTPR5_TRC                                                           0x32
6076
6077                 Reserved. Return zeroes on reads.
6078                 PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
6079
6080                 Activate to read or write delay
6081                 PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
6082
6083                 Reserved. Return zeroes on reads.
6084                 PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
6085
6086                 Internal write to read command delay
6087                 PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
6088
6089                 DRAM Timing Parameters Register 5
6090                 (OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)
6091                 RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK |  0 );
6092
6093                 RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
6094                         | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT
6095                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
6096                         | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
6097                         | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
6098                         | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
6099                         |  0 ) & RegMask); */
6100                 PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U);
6101         /*############################################################################################################################ */
6102
6103                 /*Register : DTPR6 @ 0XFD080128</p>
6104
6105                 PUB Write Latency Enable
6106                 PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
6107
6108                 PUB Read Latency Enable
6109                 PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
6110
6111                 Reserved. Return zeroes on reads.
6112                 PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
6113
6114                 Write Latency
6115                 PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
6116
6117                 Reserved. Return zeroes on reads.
6118                 PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
6119
6120                 Read Latency
6121                 PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
6122
6123                 DRAM Timing Parameters Register 6
6124                 (OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)
6125                 RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK |  0 );
6126
6127                 RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT
6128                         | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT
6129                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
6130                         | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT
6131                         | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
6132                         | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT
6133                         |  0 ) & RegMask); */
6134                 PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU);
6135         /*############################################################################################################################ */
6136
6137                 /*Register : RDIMMGCR0 @ 0XFD080140</p>
6138
6139                 Reserved. Return zeroes on reads.
6140                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
6141
6142                 RDMIMM Quad CS Enable
6143                 PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
6144
6145                 Reserved. Return zeroes on reads.
6146                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
6147
6148                 RDIMM Outputs I/O Mode
6149                 PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
6150
6151                 Reserved. Return zeroes on reads.
6152                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
6153
6154                 ERROUT# Output Enable
6155                 PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
6156
6157                 ERROUT# I/O Mode
6158                 PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
6159
6160                 ERROUT# Power Down Receiver
6161                 PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
6162
6163                 Reserved. Return zeroes on reads.
6164                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
6165
6166                 ERROUT# On-Die Termination
6167                 PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
6168
6169                 Load Reduced DIMM
6170                 PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
6171
6172                 PAR_IN I/O Mode
6173                 PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
6174
6175                 Reserved. Return zeroes on reads.
6176                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
6177
6178                 Reserved. Return zeroes on reads.
6179                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
6180
6181                 Rank Mirror Enable.
6182                 PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
6183
6184                 Reserved. Return zeroes on reads.
6185                 PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
6186
6187                 Stop on Parity Error
6188                 PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
6189
6190                 Parity Error No Registering
6191                 PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
6192
6193                 Registered DIMM
6194                 PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
6195
6196                 RDIMM General Configuration Register 0
6197                 (OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)
6198                 RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK |  0 );
6199
6200                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
6201                         | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
6202                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
6203                         | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
6204                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
6205                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
6206                         | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
6207                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
6208                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
6209                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
6210                         | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
6211                         | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
6212                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
6213                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
6214                         | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
6215                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
6216                         | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
6217                         | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
6218                         | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
6219                         |  0 ) & RegMask); */
6220                 PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U);
6221         /*############################################################################################################################ */
6222
6223                 /*Register : RDIMMGCR1 @ 0XFD080144</p>
6224
6225                 Reserved. Return zeroes on reads.
6226                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
6227
6228                 Address [17] B-side Inversion Disable
6229                 PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
6230
6231                 Reserved. Return zeroes on reads.
6232                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
6233
6234                 Command word to command word programming delay
6235                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
6236
6237                 Reserved. Return zeroes on reads.
6238                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
6239
6240                 Command word to command word programming delay
6241                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
6242
6243                 Reserved. Return zeroes on reads.
6244                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
6245
6246                 Command word to command word programming delay
6247                 PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
6248
6249                 Reserved. Return zeroes on reads.
6250                 PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
6251
6252                 Stabilization time
6253                 PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
6254
6255                 RDIMM General Configuration Register 1
6256                 (OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)
6257                 RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK |  0 );
6258
6259                 RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
6260                         | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT
6261                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
6262                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
6263                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
6264                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
6265                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
6266                         | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
6267                         | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
6268                         | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
6269                         |  0 ) & RegMask); */
6270                 PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
6271         /*############################################################################################################################ */
6272
6273                 /*Register : RDIMMCR1 @ 0XFD080154</p>
6274
6275                 Control Word 15
6276                 PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
6277
6278                 DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
6279                 PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
6280
6281                 DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
6282                 PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
6283
6284                 DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
6285                 PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
6286
6287                 DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
6288                 rol Word)
6289                 PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
6290
6291                 DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
6292                 PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
6293
6294                 DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
6295                 PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
6296
6297                 DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
6298                 Control Word)
6299                 PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
6300
6301                 RDIMM Control Register 1
6302                 (OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)
6303                 RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK |  0 );
6304
6305                 RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT
6306                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT
6307                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT
6308                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT
6309                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT
6310                         | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT
6311                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT
6312                         | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT
6313                         |  0 ) & RegMask); */
6314                 PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6315         /*############################################################################################################################ */
6316
6317                 /*Register : MR0 @ 0XFD080180</p>
6318
6319                 Reserved. Return zeroes on reads.
6320                 PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
6321
6322                 CA Terminating Rank
6323                 PSU_DDR_PHY_MR0_CATR                                                            0x0
6324
6325                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6326                 PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
6327
6328                 Built-in Self-Test for RZQ
6329                 PSU_DDR_PHY_MR0_RZQI                                                            0x2
6330
6331                 Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6332                 PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
6333
6334                 LPDDR4 Mode Register 0
6335                 (OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)
6336                 RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK |  0 );
6337
6338                 RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT
6339                         | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT
6340                         | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT
6341                         | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT
6342                         | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT
6343                         |  0 ) & RegMask); */
6344                 PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U);
6345         /*############################################################################################################################ */
6346
6347                 /*Register : MR1 @ 0XFD080184</p>
6348
6349                 Reserved. Return zeroes on reads.
6350                 PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
6351
6352                 Read Postamble Length
6353                 PSU_DDR_PHY_MR1_RDPST                                                           0x0
6354
6355                 Write-recovery for auto-precharge command
6356                 PSU_DDR_PHY_MR1_NWR                                                             0x0
6357
6358                 Read Preamble Length
6359                 PSU_DDR_PHY_MR1_RDPRE                                                           0x0
6360
6361                 Write Preamble Length
6362                 PSU_DDR_PHY_MR1_WRPRE                                                           0x0
6363
6364                 Burst Length
6365                 PSU_DDR_PHY_MR1_BL                                                              0x1
6366
6367                 LPDDR4 Mode Register 1
6368                 (OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)
6369                 RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK |  0 );
6370
6371                 RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT
6372                         | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT
6373                         | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT
6374                         | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT
6375                         | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT
6376                         | 0x00000001U << DDR_PHY_MR1_BL_SHIFT
6377                         |  0 ) & RegMask); */
6378                 PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U);
6379         /*############################################################################################################################ */
6380
6381                 /*Register : MR2 @ 0XFD080188</p>
6382
6383                 Reserved. Return zeroes on reads.
6384                 PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
6385
6386                 Write Leveling
6387                 PSU_DDR_PHY_MR2_WRL                                                             0x0
6388
6389                 Write Latency Set
6390                 PSU_DDR_PHY_MR2_WLS                                                             0x0
6391
6392                 Write Latency
6393                 PSU_DDR_PHY_MR2_WL                                                              0x4
6394
6395                 Read Latency
6396                 PSU_DDR_PHY_MR2_RL                                                              0x0
6397
6398                 LPDDR4 Mode Register 2
6399                 (OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)
6400                 RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK |  0 );
6401
6402                 RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT
6403                         | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT
6404                         | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT
6405                         | 0x00000004U << DDR_PHY_MR2_WL_SHIFT
6406                         | 0x00000000U << DDR_PHY_MR2_RL_SHIFT
6407                         |  0 ) & RegMask); */
6408                 PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U);
6409         /*############################################################################################################################ */
6410
6411                 /*Register : MR3 @ 0XFD08018C</p>
6412
6413                 Reserved. Return zeroes on reads.
6414                 PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
6415
6416                 DBI-Write Enable
6417                 PSU_DDR_PHY_MR3_DBIWR                                                           0x0
6418
6419                 DBI-Read Enable
6420                 PSU_DDR_PHY_MR3_DBIRD                                                           0x0
6421
6422                 Pull-down Drive Strength
6423                 PSU_DDR_PHY_MR3_PDDS                                                            0x0
6424
6425                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6426                 PSU_DDR_PHY_MR3_RSVD                                                            0x0
6427
6428                 Write Postamble Length
6429                 PSU_DDR_PHY_MR3_WRPST                                                           0x0
6430
6431                 Pull-up Calibration Point
6432                 PSU_DDR_PHY_MR3_PUCAL                                                           0x0
6433
6434                 LPDDR4 Mode Register 3
6435                 (OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)
6436                 RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK |  0 );
6437
6438                 RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT
6439                         | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT
6440                         | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT
6441                         | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT
6442                         | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT
6443                         | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT
6444                         | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT
6445                         |  0 ) & RegMask); */
6446                 PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U);
6447         /*############################################################################################################################ */
6448
6449                 /*Register : MR4 @ 0XFD080190</p>
6450
6451                 Reserved. Return zeroes on reads.
6452                 PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
6453
6454                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6455                 PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
6456
6457                 Write Preamble
6458                 PSU_DDR_PHY_MR4_WRP                                                             0x0
6459
6460                 Read Preamble
6461                 PSU_DDR_PHY_MR4_RDP                                                             0x0
6462
6463                 Read Preamble Training Mode
6464                 PSU_DDR_PHY_MR4_RPTM                                                            0x0
6465
6466                 Self Refresh Abort
6467                 PSU_DDR_PHY_MR4_SRA                                                             0x0
6468
6469                 CS to Command Latency Mode
6470                 PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
6471
6472                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6473                 PSU_DDR_PHY_MR4_RSVD1                                                           0x0
6474
6475                 Internal VREF Monitor
6476                 PSU_DDR_PHY_MR4_IVM                                                             0x0
6477
6478                 Temperature Controlled Refresh Mode
6479                 PSU_DDR_PHY_MR4_TCRM                                                            0x0
6480
6481                 Temperature Controlled Refresh Range
6482                 PSU_DDR_PHY_MR4_TCRR                                                            0x0
6483
6484                 Maximum Power Down Mode
6485                 PSU_DDR_PHY_MR4_MPDM                                                            0x0
6486
6487                 This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
6488                 PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
6489
6490                 DDR4 Mode Register 4
6491                 (OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)
6492                 RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK |  0 );
6493
6494                 RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT
6495                         | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT
6496                         | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT
6497                         | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT
6498                         | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT
6499                         | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT
6500                         | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT
6501                         | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT
6502                         | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT
6503                         | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT
6504                         | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT
6505                         | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT
6506                         | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT
6507                         |  0 ) & RegMask); */
6508                 PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6509         /*############################################################################################################################ */
6510
6511                 /*Register : MR5 @ 0XFD080194</p>
6512
6513                 Reserved. Return zeroes on reads.
6514                 PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
6515
6516                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6517                 PSU_DDR_PHY_MR5_RSVD                                                            0x0
6518
6519                 Read DBI
6520                 PSU_DDR_PHY_MR5_RDBI                                                            0x0
6521
6522                 Write DBI
6523                 PSU_DDR_PHY_MR5_WDBI                                                            0x0
6524
6525                 Data Mask
6526                 PSU_DDR_PHY_MR5_DM                                                              0x1
6527
6528                 CA Parity Persistent Error
6529                 PSU_DDR_PHY_MR5_CAPPE                                                           0x1
6530
6531                 RTT_PARK
6532                 PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
6533
6534                 ODT Input Buffer during Power Down mode
6535                 PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
6536
6537                 C/A Parity Error Status
6538                 PSU_DDR_PHY_MR5_CAPES                                                           0x0
6539
6540                 CRC Error Clear
6541                 PSU_DDR_PHY_MR5_CRCEC                                                           0x0
6542
6543                 C/A Parity Latency Mode
6544                 PSU_DDR_PHY_MR5_CAPM                                                            0x0
6545
6546                 DDR4 Mode Register 5
6547                 (OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)
6548                 RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK |  0 );
6549
6550                 RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT
6551                         | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT
6552                         | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT
6553                         | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT
6554                         | 0x00000001U << DDR_PHY_MR5_DM_SHIFT
6555                         | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT
6556                         | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT
6557                         | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT
6558                         | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT
6559                         | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT
6560                         | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT
6561                         |  0 ) & RegMask); */
6562                 PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
6563         /*############################################################################################################################ */
6564
6565                 /*Register : MR6 @ 0XFD080198</p>
6566
6567                 Reserved. Return zeroes on reads.
6568                 PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
6569
6570                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6571                 PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
6572
6573                 CAS_n to CAS_n command delay for same bank group (tCCD_L)
6574                 PSU_DDR_PHY_MR6_TCCDL                                                           0x2
6575
6576                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6577                 PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
6578
6579                 VrefDQ Training Enable
6580                 PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
6581
6582                 VrefDQ Training Range
6583                 PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
6584
6585                 VrefDQ Training Values
6586                 PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
6587
6588                 DDR4 Mode Register 6
6589                 (OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)
6590                 RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK |  0 );
6591
6592                 RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT
6593                         | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT
6594                         | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT
6595                         | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT
6596                         | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT
6597                         | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT
6598                         | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT
6599                         |  0 ) & RegMask); */
6600                 PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U);
6601         /*############################################################################################################################ */
6602
6603                 /*Register : MR11 @ 0XFD0801AC</p>
6604
6605                 Reserved. Return zeroes on reads.
6606                 PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
6607
6608                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6609                 PSU_DDR_PHY_MR11_RSVD                                                           0x0
6610
6611                 Power Down Control
6612                 PSU_DDR_PHY_MR11_PDCTL                                                          0x0
6613
6614                 DQ Bus Receiver On-Die-Termination
6615                 PSU_DDR_PHY_MR11_DQODT                                                          0x0
6616
6617                 LPDDR4 Mode Register 11
6618                 (OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)
6619                 RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK |  0 );
6620
6621                 RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT
6622                         | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT
6623                         | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT
6624                         | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT
6625                         |  0 ) & RegMask); */
6626                 PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6627         /*############################################################################################################################ */
6628
6629                 /*Register : MR12 @ 0XFD0801B0</p>
6630
6631                 Reserved. Return zeroes on reads.
6632                 PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
6633
6634                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6635                 PSU_DDR_PHY_MR12_RSVD                                                           0x0
6636
6637                 VREF_CA Range Select.
6638                 PSU_DDR_PHY_MR12_VR_CA                                                          0x1
6639
6640                 Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
6641                 PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
6642
6643                 LPDDR4 Mode Register 12
6644                 (OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)
6645                 RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK |  0 );
6646
6647                 RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT
6648                         | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT
6649                         | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT
6650                         | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT
6651                         |  0 ) & RegMask); */
6652                 PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6653         /*############################################################################################################################ */
6654
6655                 /*Register : MR13 @ 0XFD0801B4</p>
6656
6657                 Reserved. Return zeroes on reads.
6658                 PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
6659
6660                 Frequency Set Point Operation Mode
6661                 PSU_DDR_PHY_MR13_FSPOP                                                          0x0
6662
6663                 Frequency Set Point Write Enable
6664                 PSU_DDR_PHY_MR13_FSPWR                                                          0x0
6665
6666                 Data Mask Enable
6667                 PSU_DDR_PHY_MR13_DMD                                                            0x0
6668
6669                 Refresh Rate Option
6670                 PSU_DDR_PHY_MR13_RRO                                                            0x0
6671
6672                 VREF Current Generator
6673                 PSU_DDR_PHY_MR13_VRCG                                                           0x1
6674
6675                 VREF Output
6676                 PSU_DDR_PHY_MR13_VRO                                                            0x0
6677
6678                 Read Preamble Training Mode
6679                 PSU_DDR_PHY_MR13_RPT                                                            0x0
6680
6681                 Command Bus Training
6682                 PSU_DDR_PHY_MR13_CBT                                                            0x0
6683
6684                 LPDDR4 Mode Register 13
6685                 (OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)
6686                 RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK |  0 );
6687
6688                 RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT
6689                         | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT
6690                         | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT
6691                         | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT
6692                         | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT
6693                         | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT
6694                         | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT
6695                         | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT
6696                         | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT
6697                         |  0 ) & RegMask); */
6698                 PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U);
6699         /*############################################################################################################################ */
6700
6701                 /*Register : MR14 @ 0XFD0801B8</p>
6702
6703                 Reserved. Return zeroes on reads.
6704                 PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
6705
6706                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6707                 PSU_DDR_PHY_MR14_RSVD                                                           0x0
6708
6709                 VREFDQ Range Selects.
6710                 PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
6711
6712                 Reserved. Return zeroes on reads.
6713                 PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
6714
6715                 LPDDR4 Mode Register 14
6716                 (OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)
6717                 RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK |  0 );
6718
6719                 RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT
6720                         | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT
6721                         | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT
6722                         | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT
6723                         |  0 ) & RegMask); */
6724                 PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
6725         /*############################################################################################################################ */
6726
6727                 /*Register : MR22 @ 0XFD0801D8</p>
6728
6729                 Reserved. Return zeroes on reads.
6730                 PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
6731
6732                 These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
6733                 PSU_DDR_PHY_MR22_RSVD                                                           0x0
6734
6735                 CA ODT termination disable.
6736                 PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
6737
6738                 ODT CS override.
6739                 PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
6740
6741                 ODT CK override.
6742                 PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
6743
6744                 Controller ODT value for VOH calibration.
6745                 PSU_DDR_PHY_MR22_CODT                                                           0x0
6746
6747                 LPDDR4 Mode Register 22
6748                 (OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)
6749                 RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK |  0 );
6750
6751                 RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT
6752                         | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT
6753                         | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT
6754                         | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT
6755                         | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT
6756                         | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT
6757                         |  0 ) & RegMask); */
6758                 PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U);
6759         /*############################################################################################################################ */
6760
6761                 /*Register : DTCR0 @ 0XFD080200</p>
6762
6763                 Refresh During Training
6764                 PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
6765
6766                 Reserved. Return zeroes on reads.
6767                 PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
6768
6769                 Data Training Debug Rank Select
6770                 PSU_DDR_PHY_DTCR0_DTDRS                                                         0x1
6771
6772                 Data Training with Early/Extended Gate
6773                 PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
6774
6775                 Data Training Extended Write DQS
6776                 PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
6777
6778                 Data Training Debug Step
6779                 PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
6780
6781                 Data Training Debug Enable
6782                 PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
6783
6784                 Data Training Debug Byte Select
6785                 PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
6786
6787                 Data Training read DBI deskewing configuration
6788                 PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x0
6789
6790                 Reserved. Return zeroes on reads.
6791                 PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
6792
6793                 Data Training Write Bit Deskew Data Mask
6794                 PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
6795
6796                 Refreshes Issued During Entry to Training
6797                 PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
6798
6799                 Data Training Compare Data
6800                 PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
6801
6802                 Data Training Using MPR
6803                 PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
6804
6805                 Reserved. Return zeroes on reads.
6806                 PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
6807
6808                 Data Training Repeat Number
6809                 PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
6810
6811                 Data Training Configuration Register 0
6812                 (OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)
6813                 RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK |  0 );
6814
6815                 RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
6816                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
6817                         | 0x00000001U << DDR_PHY_DTCR0_DTDRS_SHIFT
6818                         | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
6819                         | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
6820                         | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
6821                         | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
6822                         | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
6823                         | 0x00000000U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
6824                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
6825                         | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
6826                         | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
6827                         | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT
6828                         | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT
6829                         | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
6830                         | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
6831                         |  0 ) & RegMask); */
6832                 PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x810011C7U);
6833         /*############################################################################################################################ */
6834
6835                 /*Register : DTCR1 @ 0XFD080204</p>
6836
6837                 Rank Enable.
6838                 PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
6839
6840                 Rank Enable.
6841                 PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
6842
6843                 Reserved. Return zeroes on reads.
6844                 PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
6845
6846                 Data Training Rank
6847                 PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
6848
6849                 Reserved. Return zeroes on reads.
6850                 PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
6851
6852                 Read Leveling Gate Sampling Difference
6853                 PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
6854
6855                 Reserved. Return zeroes on reads.
6856                 PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
6857
6858                 Read Leveling Gate Shift
6859                 PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
6860
6861                 Reserved. Return zeroes on reads.
6862                 PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
6863
6864                 Read Preamble Training enable
6865                 PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
6866
6867                 Read Leveling Enable
6868                 PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
6869
6870                 Basic Gate Training Enable
6871                 PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
6872
6873                 Data Training Configuration Register 1
6874                 (OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)
6875                 RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK |  0 );
6876
6877                 RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
6878                         | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT
6879                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
6880                         | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT
6881                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT
6882                         | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
6883                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT
6884                         | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT
6885                         | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT
6886                         | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
6887                         | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT
6888                         | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT
6889                         |  0 ) & RegMask); */
6890                 PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U);
6891         /*############################################################################################################################ */
6892
6893                 /*Register : CATR0 @ 0XFD080240</p>
6894
6895                 Reserved. Return zeroes on reads.
6896                 PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
6897
6898                 Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
6899                 PSU_DDR_PHY_CATR0_CACD                                                          0x14
6900
6901                 Reserved. Return zeroes on reads.
6902                 PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
6903
6904                 Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
6905                  been sent to the memory
6906                 PSU_DDR_PHY_CATR0_CAADR                                                         0x10
6907
6908                 CA_1 Response Byte Lane 1
6909                 PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
6910
6911                 CA_1 Response Byte Lane 0
6912                 PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
6913
6914                 CA Training Register 0
6915                 (OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)
6916                 RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK |  0 );
6917
6918                 RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT
6919                         | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT
6920                         | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT
6921                         | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT
6922                         | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT
6923                         | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT
6924                         |  0 ) & RegMask); */
6925                 PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
6926         /*############################################################################################################################ */
6927
6928                 /*Register : RIOCR5 @ 0XFD0804F4</p>
6929
6930                 Reserved. Return zeroes on reads.
6931                 PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
6932
6933                 Reserved. Return zeros on reads.
6934                 PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
6935
6936                 SDRAM On-die Termination Output Enable (OE) Mode Selection.
6937                 PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
6938
6939                 Rank I/O Configuration Register 5
6940                 (OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)
6941                 RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK |  0 );
6942
6943                 RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
6944                         | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
6945                         | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
6946                         |  0 ) & RegMask); */
6947                 PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U);
6948         /*############################################################################################################################ */
6949
6950                 /*Register : ACIOCR0 @ 0XFD080500</p>
6951
6952                 Address/Command Slew Rate (D3F I/O Only)
6953                 PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
6954
6955                 SDRAM Reset I/O Mode
6956                 PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
6957
6958                 SDRAM Reset Power Down Receiver
6959                 PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
6960
6961                 Reserved. Return zeroes on reads.
6962                 PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
6963
6964                 SDRAM Reset On-Die Termination
6965                 PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
6966
6967                 Reserved. Return zeroes on reads.
6968                 PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
6969
6970                 CK Duty Cycle Correction
6971                 PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
6972
6973                 AC Power Down Receiver Mode
6974                 PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
6975
6976                 AC On-die Termination Mode
6977                 PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
6978
6979                 Reserved. Return zeroes on reads.
6980                 PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
6981
6982                 Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
6983                 PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
6984
6985                 AC I/O Configuration Register 0
6986                 (OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)
6987                 RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK |  0 );
6988
6989                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT
6990                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT
6991                         | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT
6992                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
6993                         | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT
6994                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
6995                         | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT
6996                         | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
6997                         | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
6998                         | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
6999                         | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
7000                         |  0 ) & RegMask); */
7001                 PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U);
7002         /*############################################################################################################################ */
7003
7004                 /*Register : ACIOCR2 @ 0XFD080508</p>
7005
7006                 Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
7007                 PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
7008
7009                 Clock gating for Output Enable D slices [0]
7010                 PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
7011
7012                 Clock gating for Power Down Receiver D slices [0]
7013                 PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
7014
7015                 Clock gating for Termination Enable D slices [0]
7016                 PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
7017
7018                 Clock gating for CK# D slices [1:0]
7019                 PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
7020
7021                 Clock gating for CK D slices [1:0]
7022                 PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
7023
7024                 Clock gating for AC D slices [23:0]
7025                 PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
7026
7027                 AC I/O Configuration Register 2
7028                 (OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)
7029                 RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK |  0 );
7030
7031                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
7032                         | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
7033                         | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
7034                         | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
7035                         | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
7036                         | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
7037                         | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
7038                         |  0 ) & RegMask); */
7039                 PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
7040         /*############################################################################################################################ */
7041
7042                 /*Register : ACIOCR3 @ 0XFD08050C</p>
7043
7044                 SDRAM Parity Output Enable (OE) Mode Selection
7045                 PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
7046
7047                 SDRAM Bank Group Output Enable (OE) Mode Selection
7048                 PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
7049
7050                 SDRAM Bank Address Output Enable (OE) Mode Selection
7051                 PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
7052
7053                 SDRAM A[17] Output Enable (OE) Mode Selection
7054                 PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
7055
7056                 SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
7057                 PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
7058
7059                 SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
7060                 PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
7061
7062                 Reserved. Return zeroes on reads.
7063                 PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
7064
7065                 Reserved. Return zeros on reads.
7066                 PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
7067
7068                 SDRAM CK Output Enable (OE) Mode Selection.
7069                 PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
7070
7071                 AC I/O Configuration Register 3
7072                 (OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)
7073                 RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK |  0 );
7074
7075                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
7076                         | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
7077                         | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
7078                         | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
7079                         | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
7080                         | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
7081                         | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
7082                         | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
7083                         | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
7084                         |  0 ) & RegMask); */
7085                 PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U);
7086         /*############################################################################################################################ */
7087
7088                 /*Register : ACIOCR4 @ 0XFD080510</p>
7089
7090                 Clock gating for AC LB slices and loopback read valid slices
7091                 PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
7092
7093                 Clock gating for Output Enable D slices [1]
7094                 PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
7095
7096                 Clock gating for Power Down Receiver D slices [1]
7097                 PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
7098
7099                 Clock gating for Termination Enable D slices [1]
7100                 PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
7101
7102                 Clock gating for CK# D slices [3:2]
7103                 PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
7104
7105                 Clock gating for CK D slices [3:2]
7106                 PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
7107
7108                 Clock gating for AC D slices [47:24]
7109                 PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
7110
7111                 AC I/O Configuration Register 4
7112                 (OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)
7113                 RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK |  0 );
7114
7115                 RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
7116                         | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
7117                         | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
7118                         | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
7119                         | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
7120                         | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
7121                         | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
7122                         |  0 ) & RegMask); */
7123                 PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
7124         /*############################################################################################################################ */
7125
7126                 /*Register : IOVCR0 @ 0XFD080520</p>
7127
7128                 Reserved. Return zeroes on reads.
7129                 PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
7130
7131                 Address/command lane VREF Pad Enable
7132                 PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
7133
7134                 Address/command lane Internal VREF Enable
7135                 PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
7136
7137                 Address/command lane Single-End VREF Enable
7138                 PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
7139
7140                 Address/command lane Internal VREF Enable
7141                 PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
7142
7143                 External VREF generato REFSEL range select
7144                 PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
7145
7146                 Address/command lane External VREF Select
7147                 PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
7148
7149                 Single ended VREF generator REFSEL range select
7150                 PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
7151
7152                 Address/command lane Single-End VREF Select
7153                 PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
7154
7155                 Internal VREF generator REFSEL ragne select
7156                 PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
7157
7158                 REFSEL Control for internal AC IOs
7159                 PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
7160
7161                 IO VREF Control Register 0
7162                 (OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)
7163                 RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK |  0 );
7164
7165                 RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
7166                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT
7167                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT
7168                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT
7169                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT
7170                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
7171                         | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT
7172                         | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
7173                         | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
7174                         | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
7175                         | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
7176                         |  0 ) & RegMask); */
7177                 PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U);
7178         /*############################################################################################################################ */
7179
7180                 /*Register : VTCR0 @ 0XFD080528</p>
7181
7182                 Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
7183                 PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
7184
7185                 DRM DQ VREF training Enable
7186                 PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
7187
7188                 Per Device Addressability Enable
7189                 PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
7190
7191                 Reserved. Returns zeroes on reads.
7192                 PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
7193
7194                 VREF Word Count
7195                 PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
7196
7197                 DRAM DQ VREF step size used during DRAM VREF training
7198                 PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
7199
7200                 Maximum VREF limit value used during DRAM VREF training
7201                 PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
7202
7203                 Minimum VREF limit value used during DRAM VREF training
7204                 PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
7205
7206                 Initial DRAM DQ VREF value used during DRAM VREF training
7207                 PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
7208
7209                 VREF Training Control Register 0
7210                 (OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)
7211                 RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK |  0 );
7212
7213                 RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT
7214                         | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT
7215                         | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT
7216                         | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT
7217                         | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT
7218                         | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT
7219                         | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT
7220                         | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT
7221                         | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT
7222                         |  0 ) & RegMask); */
7223                 PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U);
7224         /*############################################################################################################################ */
7225
7226                 /*Register : VTCR1 @ 0XFD08052C</p>
7227
7228                 Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
7229                 PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
7230
7231                 Reserved. Returns zeroes on reads.
7232                 PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
7233
7234                 Maximum VREF limit value used during DRAM VREF training.
7235                 PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
7236
7237                 Reserved. Returns zeroes on reads.
7238                 PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
7239
7240                 Minimum VREF limit value used during DRAM VREF training.
7241                 PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
7242
7243                 Reserved. Returns zeroes on reads.
7244                 PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
7245
7246                 Static Host Vref Rank Value
7247                 PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
7248
7249                 Static Host Vref Rank Enable
7250                 PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
7251
7252                 Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
7253                 PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x4
7254
7255                 Eye LCDL Offset value for VREF training
7256                 PSU_DDR_PHY_VTCR1_EOFF                                                          0x1
7257
7258                 Number of LCDL Eye points for which VREF training is repeated
7259                 PSU_DDR_PHY_VTCR1_ENUM                                                          0x1
7260
7261                 HOST (IO) internal VREF training Enable
7262                 PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
7263
7264                 Host IO Type Control
7265                 PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
7266
7267                 VREF Training Control Register 1
7268                 (OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)
7269                 RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK |  0 );
7270
7271                 RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
7272                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT
7273                         | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT
7274                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT
7275                         | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT
7276                         | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
7277                         | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
7278                         | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
7279                         | 0x00000004U << DDR_PHY_VTCR1_TVREFIO_SHIFT
7280                         | 0x00000001U << DDR_PHY_VTCR1_EOFF_SHIFT
7281                         | 0x00000001U << DDR_PHY_VTCR1_ENUM_SHIFT
7282                         | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
7283                         | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
7284                         |  0 ) & RegMask); */
7285                 PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F0018FU);
7286         /*############################################################################################################################ */
7287
7288                 /*Register : ACBDLR6 @ 0XFD080558</p>
7289
7290                 Reserved. Return zeroes on reads.
7291                 PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
7292
7293                 Delay select for the BDL on Address A[3].
7294                 PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
7295
7296                 Reserved. Return zeroes on reads.
7297                 PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
7298
7299                 Delay select for the BDL on Address A[2].
7300                 PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
7301
7302                 Reserved. Return zeroes on reads.
7303                 PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
7304
7305                 Delay select for the BDL on Address A[1].
7306                 PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
7307
7308                 Reserved. Return zeroes on reads.
7309                 PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
7310
7311                 Delay select for the BDL on Address A[0].
7312                 PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
7313
7314                 AC Bit Delay Line Register 6
7315                 (OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)
7316                 RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK |  0 );
7317
7318                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
7319                         | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
7320                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
7321                         | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
7322                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
7323                         | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
7324                         | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
7325                         | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
7326                         |  0 ) & RegMask); */
7327                 PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7328         /*############################################################################################################################ */
7329
7330                 /*Register : ACBDLR7 @ 0XFD08055C</p>
7331
7332                 Reserved. Return zeroes on reads.
7333                 PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
7334
7335                 Delay select for the BDL on Address A[7].
7336                 PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
7337
7338                 Reserved. Return zeroes on reads.
7339                 PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
7340
7341                 Delay select for the BDL on Address A[6].
7342                 PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
7343
7344                 Reserved. Return zeroes on reads.
7345                 PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
7346
7347                 Delay select for the BDL on Address A[5].
7348                 PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
7349
7350                 Reserved. Return zeroes on reads.
7351                 PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
7352
7353                 Delay select for the BDL on Address A[4].
7354                 PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
7355
7356                 AC Bit Delay Line Register 7
7357                 (OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)
7358                 RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK |  0 );
7359
7360                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
7361                         | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT
7362                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
7363                         | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT
7364                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
7365                         | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT
7366                         | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
7367                         | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT
7368                         |  0 ) & RegMask); */
7369                 PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7370         /*############################################################################################################################ */
7371
7372                 /*Register : ACBDLR8 @ 0XFD080560</p>
7373
7374                 Reserved. Return zeroes on reads.
7375                 PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
7376
7377                 Delay select for the BDL on Address A[11].
7378                 PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
7379
7380                 Reserved. Return zeroes on reads.
7381                 PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
7382
7383                 Delay select for the BDL on Address A[10].
7384                 PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
7385
7386                 Reserved. Return zeroes on reads.
7387                 PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
7388
7389                 Delay select for the BDL on Address A[9].
7390                 PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
7391
7392                 Reserved. Return zeroes on reads.
7393                 PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
7394
7395                 Delay select for the BDL on Address A[8].
7396                 PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
7397
7398                 AC Bit Delay Line Register 8
7399                 (OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)
7400                 RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK |  0 );
7401
7402                 RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
7403                         | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT
7404                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
7405                         | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT
7406                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
7407                         | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT
7408                         | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
7409                         | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT
7410                         |  0 ) & RegMask); */
7411                 PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7412         /*############################################################################################################################ */
7413
7414                 /*Register : ZQCR @ 0XFD080680</p>
7415
7416                 Reserved. Return zeroes on reads.
7417                 PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
7418
7419                 ZQ VREF Range
7420                 PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
7421
7422                 Programmable Wait for Frequency B
7423                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
7424
7425                 Programmable Wait for Frequency A
7426                 PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
7427
7428                 ZQ VREF Pad Enable
7429                 PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
7430
7431                 ZQ Internal VREF Enable
7432                 PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
7433
7434                 Choice of termination mode
7435                 PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
7436
7437                 Force ZCAL VT update
7438                 PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
7439
7440                 IO VT Drift Limit
7441                 PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
7442
7443                 Averaging algorithm enable, if set, enables averaging algorithm
7444                 PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
7445
7446                 Maximum number of averaging rounds to be used by averaging algorithm
7447                 PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
7448
7449                 ZQ Calibration Type
7450                 PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
7451
7452                 ZQ Power Down
7453                 PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
7454
7455                 ZQ Impedance Control Register
7456                 (OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)
7457                 RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK |  0 );
7458
7459                 RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
7460                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
7461                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
7462                         | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
7463                         | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT
7464                         | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT
7465                         | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT
7466                         | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
7467                         | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT
7468                         | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT
7469                         | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT
7470                         | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT
7471                         | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT
7472                         |  0 ) & RegMask); */
7473                 PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U);
7474         /*############################################################################################################################ */
7475
7476                 /*Register : ZQ0PR0 @ 0XFD080684</p>
7477
7478                 Pull-down drive strength ZCTRL over-ride enable
7479                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
7480
7481                 Pull-up drive strength ZCTRL over-ride enable
7482                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
7483
7484                 Pull-down termination ZCTRL over-ride enable
7485                 PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
7486
7487                 Pull-up termination ZCTRL over-ride enable
7488                 PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
7489
7490                 Calibration segment bypass
7491                 PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
7492
7493                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7494                 PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
7495
7496                 Termination adjustment
7497                 PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
7498
7499                 Pulldown drive strength adjustment
7500                 PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
7501
7502                 Pullup drive strength adjustment
7503                 PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
7504
7505                 DRAM Impedance Divide Ratio
7506                 PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
7507
7508                 HOST Impedance Divide Ratio
7509                 PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
7510
7511                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7512                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
7513
7514                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7515                 PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
7516
7517                 ZQ n Impedance Control Program Register 0
7518                 (OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)
7519                 RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7520
7521                 RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
7522                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
7523                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
7524                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
7525                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
7526                         | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
7527                         | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
7528                         | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
7529                         | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
7530                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
7531                         | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
7532                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
7533                         | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
7534                         |  0 ) & RegMask); */
7535                 PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU);
7536         /*############################################################################################################################ */
7537
7538                 /*Register : ZQ0OR0 @ 0XFD080694</p>
7539
7540                 Reserved. Return zeros on reads.
7541                 PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
7542
7543                 Override value for the pull-up output impedance
7544                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
7545
7546                 Reserved. Return zeros on reads.
7547                 PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
7548
7549                 Override value for the pull-down output impedance
7550                 PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
7551
7552                 ZQ n Impedance Control Override Data Register 0
7553                 (OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)
7554                 RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK |  0 );
7555
7556                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
7557                         | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
7558                         | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
7559                         | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
7560                         |  0 ) & RegMask); */
7561                 PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U);
7562         /*############################################################################################################################ */
7563
7564                 /*Register : ZQ0OR1 @ 0XFD080698</p>
7565
7566                 Reserved. Return zeros on reads.
7567                 PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
7568
7569                 Override value for the pull-up termination
7570                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
7571
7572                 Reserved. Return zeros on reads.
7573                 PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
7574
7575                 Override value for the pull-down termination
7576                 PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
7577
7578                 ZQ n Impedance Control Override Data Register 1
7579                 (OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)
7580                 RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK |  0 );
7581
7582                 RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
7583                         | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
7584                         | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
7585                         | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
7586                         |  0 ) & RegMask); */
7587                 PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U);
7588         /*############################################################################################################################ */
7589
7590                 /*Register : ZQ1PR0 @ 0XFD0806A4</p>
7591
7592                 Pull-down drive strength ZCTRL over-ride enable
7593                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
7594
7595                 Pull-up drive strength ZCTRL over-ride enable
7596                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
7597
7598                 Pull-down termination ZCTRL over-ride enable
7599                 PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
7600
7601                 Pull-up termination ZCTRL over-ride enable
7602                 PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
7603
7604                 Calibration segment bypass
7605                 PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
7606
7607                 VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
7608                 PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
7609
7610                 Termination adjustment
7611                 PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
7612
7613                 Pulldown drive strength adjustment
7614                 PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
7615
7616                 Pullup drive strength adjustment
7617                 PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
7618
7619                 DRAM Impedance Divide Ratio
7620                 PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
7621
7622                 HOST Impedance Divide Ratio
7623                 PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
7624
7625                 Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
7626                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
7627
7628                 Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
7629                 PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
7630
7631                 ZQ n Impedance Control Program Register 0
7632                 (OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)
7633                 RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
7634
7635                 RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
7636                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
7637                         | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
7638                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
7639                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
7640                         | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
7641                         | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
7642                         | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
7643                         | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
7644                         | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
7645                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
7646                         | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
7647                         | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
7648                         |  0 ) & RegMask); */
7649                 PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU);
7650         /*############################################################################################################################ */
7651
7652                 /*Register : DX0GCR0 @ 0XFD080700</p>
7653
7654                 Calibration Bypass
7655                 PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
7656
7657                 Master Delay Line Enable
7658                 PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
7659
7660                 Configurable ODT(TE) Phase Shift
7661                 PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
7662
7663                 DQS Duty Cycle Correction
7664                 PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
7665
7666                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7667                 PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
7668
7669                 Reserved. Return zeroes on reads.
7670                 PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
7671
7672                 DQSNSE Power Down Receiver
7673                 PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
7674
7675                 DQSSE Power Down Receiver
7676                 PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
7677
7678                 RTT On Additive Latency
7679                 PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
7680
7681                 RTT Output Hold
7682                 PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
7683
7684                 Configurable PDR Phase Shift
7685                 PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
7686
7687                 DQSR Power Down
7688                 PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
7689
7690                 DQSG Power Down Receiver
7691                 PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
7692
7693                 Reserved. Return zeroes on reads.
7694                 PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
7695
7696                 DQSG On-Die Termination
7697                 PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
7698
7699                 DQSG Output Enable
7700                 PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
7701
7702                 Reserved. Return zeroes on reads.
7703                 PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
7704
7705                 DATX8 n General Configuration Register 0
7706                 (OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)
7707                 RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK |  0 );
7708
7709                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT
7710                         | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT
7711                         | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
7712                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT
7713                         | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT
7714                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
7715                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
7716                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
7717                         | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT
7718                         | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT
7719                         | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
7720                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT
7721                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
7722                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
7723                         | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT
7724                         | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT
7725                         | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
7726                         |  0 ) & RegMask); */
7727                 PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
7728         /*############################################################################################################################ */
7729
7730                 /*Register : DX0GCR4 @ 0XFD080710</p>
7731
7732                 Byte lane VREF IOM (Used only by D4MU IOs)
7733                 PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
7734
7735                 Byte Lane VREF Pad Enable
7736                 PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
7737
7738                 Byte Lane Internal VREF Enable
7739                 PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
7740
7741                 Byte Lane Single-End VREF Enable
7742                 PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
7743
7744                 Reserved. Returns zeros on reads.
7745                 PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
7746
7747                 External VREF generator REFSEL range select
7748                 PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
7749
7750                 Byte Lane External VREF Select
7751                 PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
7752
7753                 Single ended VREF generator REFSEL range select
7754                 PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
7755
7756                 Byte Lane Single-End VREF Select
7757                 PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
7758
7759                 Reserved. Returns zeros on reads.
7760                 PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
7761
7762                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
7763                 PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
7764
7765                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
7766                 PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
7767
7768                 DATX8 n General Configuration Register 4
7769                 (OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)
7770                 RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK |  0 );
7771
7772                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
7773                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
7774                         | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
7775                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
7776                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
7777                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
7778                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
7779                         | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
7780                         | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
7781                         | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
7782                         | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
7783                         | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
7784                         |  0 ) & RegMask); */
7785                 PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
7786         /*############################################################################################################################ */
7787
7788                 /*Register : DX0GCR5 @ 0XFD080714</p>
7789
7790                 Reserved. Returns zeros on reads.
7791                 PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
7792
7793                 Byte Lane internal VREF Select for Rank 3
7794                 PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
7795
7796                 Reserved. Returns zeros on reads.
7797                 PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
7798
7799                 Byte Lane internal VREF Select for Rank 2
7800                 PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
7801
7802                 Reserved. Returns zeros on reads.
7803                 PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
7804
7805                 Byte Lane internal VREF Select for Rank 1
7806                 PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x55
7807
7808                 Reserved. Returns zeros on reads.
7809                 PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
7810
7811                 Byte Lane internal VREF Select for Rank 0
7812                 PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x55
7813
7814                 DATX8 n General Configuration Register 5
7815                 (OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09095555U)
7816                 RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK |  0 );
7817
7818                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
7819                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
7820                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
7821                         | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
7822                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
7823                         | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
7824                         | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
7825                         | 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
7826                         |  0 ) & RegMask); */
7827                 PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
7828         /*############################################################################################################################ */
7829
7830                 /*Register : DX0GCR6 @ 0XFD080718</p>
7831
7832                 Reserved. Returns zeros on reads.
7833                 PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
7834
7835                 DRAM DQ VREF Select for Rank3
7836                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
7837
7838                 Reserved. Returns zeros on reads.
7839                 PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
7840
7841                 DRAM DQ VREF Select for Rank2
7842                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
7843
7844                 Reserved. Returns zeros on reads.
7845                 PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
7846
7847                 DRAM DQ VREF Select for Rank1
7848                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
7849
7850                 Reserved. Returns zeros on reads.
7851                 PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
7852
7853                 DRAM DQ VREF Select for Rank0
7854                 PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
7855
7856                 DATX8 n General Configuration Register 6
7857                 (OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)
7858                 RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK |  0 );
7859
7860                 RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
7861                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
7862                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
7863                         | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
7864                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
7865                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
7866                         | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
7867                         | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
7868                         |  0 ) & RegMask); */
7869                 PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
7870         /*############################################################################################################################ */
7871
7872                 /*Register : DX0LCDLR2 @ 0XFD080788</p>
7873
7874                 Reserved. Return zeroes on reads.
7875                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
7876
7877                 Reserved. Caution, do not write to this register field.
7878                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
7879
7880                 Reserved. Return zeroes on reads.
7881                 PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
7882
7883                 Read DQS Gating Delay
7884                 PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
7885
7886                 DATX8 n Local Calibrated Delay Line Register 2
7887                 (OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)
7888                 RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK |  0 );
7889
7890                 RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
7891                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
7892                         | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
7893                         | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
7894                         |  0 ) & RegMask); */
7895                 PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
7896         /*############################################################################################################################ */
7897
7898                 /*Register : DX0GTR0 @ 0XFD0807C0</p>
7899
7900                 Reserved. Return zeroes on reads.
7901                 PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
7902
7903                 DQ Write Path Latency Pipeline
7904                 PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
7905
7906                 Reserved. Caution, do not write to this register field.
7907                 PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
7908
7909                 Write Leveling System Latency
7910                 PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
7911
7912                 Reserved. Return zeroes on reads.
7913                 PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
7914
7915                 Reserved. Caution, do not write to this register field.
7916                 PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
7917
7918                 Reserved. Return zeroes on reads.
7919                 PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
7920
7921                 DQS Gating System Latency
7922                 PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
7923
7924                 DATX8 n General Timing Register 0
7925                 (OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)
7926                 RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK |  0 );
7927
7928                 RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
7929                         | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT
7930                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
7931                         | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT
7932                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
7933                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
7934                         | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
7935                         | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT
7936                         |  0 ) & RegMask); */
7937                 PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
7938         /*############################################################################################################################ */
7939
7940                 /*Register : DX1GCR0 @ 0XFD080800</p>
7941
7942                 Calibration Bypass
7943                 PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
7944
7945                 Master Delay Line Enable
7946                 PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
7947
7948                 Configurable ODT(TE) Phase Shift
7949                 PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
7950
7951                 DQS Duty Cycle Correction
7952                 PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
7953
7954                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
7955                 PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
7956
7957                 Reserved. Return zeroes on reads.
7958                 PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
7959
7960                 DQSNSE Power Down Receiver
7961                 PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
7962
7963                 DQSSE Power Down Receiver
7964                 PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
7965
7966                 RTT On Additive Latency
7967                 PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
7968
7969                 RTT Output Hold
7970                 PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
7971
7972                 Configurable PDR Phase Shift
7973                 PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
7974
7975                 DQSR Power Down
7976                 PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
7977
7978                 DQSG Power Down Receiver
7979                 PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
7980
7981                 Reserved. Return zeroes on reads.
7982                 PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
7983
7984                 DQSG On-Die Termination
7985                 PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
7986
7987                 DQSG Output Enable
7988                 PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
7989
7990                 Reserved. Return zeroes on reads.
7991                 PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
7992
7993                 DATX8 n General Configuration Register 0
7994                 (OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)
7995                 RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK |  0 );
7996
7997                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT
7998                         | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT
7999                         | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
8000                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT
8001                         | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT
8002                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
8003                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
8004                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
8005                         | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT
8006                         | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT
8007                         | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
8008                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT
8009                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
8010                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
8011                         | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT
8012                         | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT
8013                         | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
8014                         |  0 ) & RegMask); */
8015                 PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8016         /*############################################################################################################################ */
8017
8018                 /*Register : DX1GCR4 @ 0XFD080810</p>
8019
8020                 Byte lane VREF IOM (Used only by D4MU IOs)
8021                 PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
8022
8023                 Byte Lane VREF Pad Enable
8024                 PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
8025
8026                 Byte Lane Internal VREF Enable
8027                 PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
8028
8029                 Byte Lane Single-End VREF Enable
8030                 PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
8031
8032                 Reserved. Returns zeros on reads.
8033                 PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
8034
8035                 External VREF generator REFSEL range select
8036                 PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
8037
8038                 Byte Lane External VREF Select
8039                 PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
8040
8041                 Single ended VREF generator REFSEL range select
8042                 PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
8043
8044                 Byte Lane Single-End VREF Select
8045                 PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
8046
8047                 Reserved. Returns zeros on reads.
8048                 PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
8049
8050                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8051                 PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
8052
8053                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8054                 PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
8055
8056                 DATX8 n General Configuration Register 4
8057                 (OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)
8058                 RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK |  0 );
8059
8060                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
8061                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
8062                         | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
8063                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
8064                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
8065                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
8066                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
8067                         | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
8068                         | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
8069                         | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
8070                         | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
8071                         | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
8072                         |  0 ) & RegMask); */
8073                 PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8074         /*############################################################################################################################ */
8075
8076                 /*Register : DX1GCR5 @ 0XFD080814</p>
8077
8078                 Reserved. Returns zeros on reads.
8079                 PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
8080
8081                 Byte Lane internal VREF Select for Rank 3
8082                 PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
8083
8084                 Reserved. Returns zeros on reads.
8085                 PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
8086
8087                 Byte Lane internal VREF Select for Rank 2
8088                 PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
8089
8090                 Reserved. Returns zeros on reads.
8091                 PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
8092
8093                 Byte Lane internal VREF Select for Rank 1
8094                 PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x55
8095
8096                 Reserved. Returns zeros on reads.
8097                 PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
8098
8099                 Byte Lane internal VREF Select for Rank 0
8100                 PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x55
8101
8102                 DATX8 n General Configuration Register 5
8103                 (OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09095555U)
8104                 RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK |  0 );
8105
8106                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
8107                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
8108                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
8109                         | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
8110                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
8111                         | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
8112                         | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
8113                         | 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
8114                         |  0 ) & RegMask); */
8115                 PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
8116         /*############################################################################################################################ */
8117
8118                 /*Register : DX1GCR6 @ 0XFD080818</p>
8119
8120                 Reserved. Returns zeros on reads.
8121                 PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
8122
8123                 DRAM DQ VREF Select for Rank3
8124                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
8125
8126                 Reserved. Returns zeros on reads.
8127                 PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
8128
8129                 DRAM DQ VREF Select for Rank2
8130                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
8131
8132                 Reserved. Returns zeros on reads.
8133                 PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
8134
8135                 DRAM DQ VREF Select for Rank1
8136                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
8137
8138                 Reserved. Returns zeros on reads.
8139                 PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
8140
8141                 DRAM DQ VREF Select for Rank0
8142                 PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
8143
8144                 DATX8 n General Configuration Register 6
8145                 (OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)
8146                 RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK |  0 );
8147
8148                 RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
8149                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
8150                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
8151                         | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
8152                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
8153                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
8154                         | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
8155                         | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
8156                         |  0 ) & RegMask); */
8157                 PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8158         /*############################################################################################################################ */
8159
8160                 /*Register : DX1LCDLR2 @ 0XFD080888</p>
8161
8162                 Reserved. Return zeroes on reads.
8163                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
8164
8165                 Reserved. Caution, do not write to this register field.
8166                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
8167
8168                 Reserved. Return zeroes on reads.
8169                 PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
8170
8171                 Read DQS Gating Delay
8172                 PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
8173
8174                 DATX8 n Local Calibrated Delay Line Register 2
8175                 (OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)
8176                 RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK |  0 );
8177
8178                 RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
8179                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
8180                         | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
8181                         | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
8182                         |  0 ) & RegMask); */
8183                 PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8184         /*############################################################################################################################ */
8185
8186                 /*Register : DX1GTR0 @ 0XFD0808C0</p>
8187
8188                 Reserved. Return zeroes on reads.
8189                 PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
8190
8191                 DQ Write Path Latency Pipeline
8192                 PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
8193
8194                 Reserved. Caution, do not write to this register field.
8195                 PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
8196
8197                 Write Leveling System Latency
8198                 PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
8199
8200                 Reserved. Return zeroes on reads.
8201                 PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
8202
8203                 Reserved. Caution, do not write to this register field.
8204                 PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
8205
8206                 Reserved. Return zeroes on reads.
8207                 PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
8208
8209                 DQS Gating System Latency
8210                 PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
8211
8212                 DATX8 n General Timing Register 0
8213                 (OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)
8214                 RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK |  0 );
8215
8216                 RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
8217                         | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT
8218                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
8219                         | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT
8220                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
8221                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
8222                         | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
8223                         | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT
8224                         |  0 ) & RegMask); */
8225                 PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8226         /*############################################################################################################################ */
8227
8228                 /*Register : DX2GCR0 @ 0XFD080900</p>
8229
8230                 Calibration Bypass
8231                 PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
8232
8233                 Master Delay Line Enable
8234                 PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
8235
8236                 Configurable ODT(TE) Phase Shift
8237                 PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
8238
8239                 DQS Duty Cycle Correction
8240                 PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
8241
8242                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8243                 PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
8244
8245                 Reserved. Return zeroes on reads.
8246                 PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
8247
8248                 DQSNSE Power Down Receiver
8249                 PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
8250
8251                 DQSSE Power Down Receiver
8252                 PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
8253
8254                 RTT On Additive Latency
8255                 PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
8256
8257                 RTT Output Hold
8258                 PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
8259
8260                 Configurable PDR Phase Shift
8261                 PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
8262
8263                 DQSR Power Down
8264                 PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
8265
8266                 DQSG Power Down Receiver
8267                 PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
8268
8269                 Reserved. Return zeroes on reads.
8270                 PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
8271
8272                 DQSG On-Die Termination
8273                 PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
8274
8275                 DQSG Output Enable
8276                 PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
8277
8278                 Reserved. Return zeroes on reads.
8279                 PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
8280
8281                 DATX8 n General Configuration Register 0
8282                 (OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)
8283                 RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK |  0 );
8284
8285                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT
8286                         | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT
8287                         | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
8288                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT
8289                         | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT
8290                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
8291                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
8292                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
8293                         | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT
8294                         | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT
8295                         | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
8296                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT
8297                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
8298                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
8299                         | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT
8300                         | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT
8301                         | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
8302                         |  0 ) & RegMask); */
8303                 PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8304         /*############################################################################################################################ */
8305
8306                 /*Register : DX2GCR1 @ 0XFD080904</p>
8307
8308                 Enables the PDR mode for DQ[7:0]
8309                 PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
8310
8311                 Reserved. Returns zeroes on reads.
8312                 PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
8313
8314                 Select the delayed or non-delayed read data strobe #
8315                 PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
8316
8317                 Select the delayed or non-delayed read data strobe
8318                 PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
8319
8320                 Enables Read Data Strobe in a byte lane
8321                 PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
8322
8323                 Enables PDR in a byte lane
8324                 PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
8325
8326                 Enables ODT/TE in a byte lane
8327                 PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
8328
8329                 Enables Write Data strobe in a byte lane
8330                 PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
8331
8332                 Enables DM pin in a byte lane
8333                 PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
8334
8335                 Enables DQ corresponding to each bit in a byte
8336                 PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
8337
8338                 DATX8 n General Configuration Register 1
8339                 (OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)
8340                 RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK |  0 );
8341
8342                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
8343                         | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
8344                         | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT
8345                         | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT
8346                         | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT
8347                         | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT
8348                         | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT
8349                         | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT
8350                         | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT
8351                         | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT
8352                         |  0 ) & RegMask); */
8353                 PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8354         /*############################################################################################################################ */
8355
8356                 /*Register : DX2GCR4 @ 0XFD080910</p>
8357
8358                 Byte lane VREF IOM (Used only by D4MU IOs)
8359                 PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
8360
8361                 Byte Lane VREF Pad Enable
8362                 PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
8363
8364                 Byte Lane Internal VREF Enable
8365                 PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
8366
8367                 Byte Lane Single-End VREF Enable
8368                 PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
8369
8370                 Reserved. Returns zeros on reads.
8371                 PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
8372
8373                 External VREF generator REFSEL range select
8374                 PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
8375
8376                 Byte Lane External VREF Select
8377                 PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
8378
8379                 Single ended VREF generator REFSEL range select
8380                 PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
8381
8382                 Byte Lane Single-End VREF Select
8383                 PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
8384
8385                 Reserved. Returns zeros on reads.
8386                 PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
8387
8388                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8389                 PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
8390
8391                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8392                 PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
8393
8394                 DATX8 n General Configuration Register 4
8395                 (OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)
8396                 RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK |  0 );
8397
8398                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
8399                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
8400                         | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
8401                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
8402                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
8403                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
8404                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
8405                         | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
8406                         | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
8407                         | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
8408                         | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
8409                         | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
8410                         |  0 ) & RegMask); */
8411                 PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8412         /*############################################################################################################################ */
8413
8414                 /*Register : DX2GCR5 @ 0XFD080914</p>
8415
8416                 Reserved. Returns zeros on reads.
8417                 PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
8418
8419                 Byte Lane internal VREF Select for Rank 3
8420                 PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
8421
8422                 Reserved. Returns zeros on reads.
8423                 PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
8424
8425                 Byte Lane internal VREF Select for Rank 2
8426                 PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
8427
8428                 Reserved. Returns zeros on reads.
8429                 PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
8430
8431                 Byte Lane internal VREF Select for Rank 1
8432                 PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x55
8433
8434                 Reserved. Returns zeros on reads.
8435                 PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
8436
8437                 Byte Lane internal VREF Select for Rank 0
8438                 PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x55
8439
8440                 DATX8 n General Configuration Register 5
8441                 (OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09095555U)
8442                 RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK |  0 );
8443
8444                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
8445                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
8446                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
8447                         | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
8448                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
8449                         | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
8450                         | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
8451                         | 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
8452                         |  0 ) & RegMask); */
8453                 PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
8454         /*############################################################################################################################ */
8455
8456                 /*Register : DX2GCR6 @ 0XFD080918</p>
8457
8458                 Reserved. Returns zeros on reads.
8459                 PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
8460
8461                 DRAM DQ VREF Select for Rank3
8462                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
8463
8464                 Reserved. Returns zeros on reads.
8465                 PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
8466
8467                 DRAM DQ VREF Select for Rank2
8468                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
8469
8470                 Reserved. Returns zeros on reads.
8471                 PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
8472
8473                 DRAM DQ VREF Select for Rank1
8474                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
8475
8476                 Reserved. Returns zeros on reads.
8477                 PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
8478
8479                 DRAM DQ VREF Select for Rank0
8480                 PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
8481
8482                 DATX8 n General Configuration Register 6
8483                 (OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)
8484                 RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK |  0 );
8485
8486                 RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
8487                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
8488                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
8489                         | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
8490                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
8491                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
8492                         | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
8493                         | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
8494                         |  0 ) & RegMask); */
8495                 PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8496         /*############################################################################################################################ */
8497
8498                 /*Register : DX2LCDLR2 @ 0XFD080988</p>
8499
8500                 Reserved. Return zeroes on reads.
8501                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
8502
8503                 Reserved. Caution, do not write to this register field.
8504                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
8505
8506                 Reserved. Return zeroes on reads.
8507                 PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
8508
8509                 Read DQS Gating Delay
8510                 PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
8511
8512                 DATX8 n Local Calibrated Delay Line Register 2
8513                 (OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)
8514                 RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK |  0 );
8515
8516                 RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
8517                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
8518                         | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
8519                         | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
8520                         |  0 ) & RegMask); */
8521                 PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8522         /*############################################################################################################################ */
8523
8524                 /*Register : DX2GTR0 @ 0XFD0809C0</p>
8525
8526                 Reserved. Return zeroes on reads.
8527                 PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
8528
8529                 DQ Write Path Latency Pipeline
8530                 PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
8531
8532                 Reserved. Caution, do not write to this register field.
8533                 PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
8534
8535                 Write Leveling System Latency
8536                 PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
8537
8538                 Reserved. Return zeroes on reads.
8539                 PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
8540
8541                 Reserved. Caution, do not write to this register field.
8542                 PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
8543
8544                 Reserved. Return zeroes on reads.
8545                 PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
8546
8547                 DQS Gating System Latency
8548                 PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
8549
8550                 DATX8 n General Timing Register 0
8551                 (OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)
8552                 RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK |  0 );
8553
8554                 RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
8555                         | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT
8556                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
8557                         | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT
8558                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
8559                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
8560                         | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
8561                         | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT
8562                         |  0 ) & RegMask); */
8563                 PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8564         /*############################################################################################################################ */
8565
8566                 /*Register : DX3GCR0 @ 0XFD080A00</p>
8567
8568                 Calibration Bypass
8569                 PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
8570
8571                 Master Delay Line Enable
8572                 PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
8573
8574                 Configurable ODT(TE) Phase Shift
8575                 PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
8576
8577                 DQS Duty Cycle Correction
8578                 PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
8579
8580                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8581                 PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
8582
8583                 Reserved. Return zeroes on reads.
8584                 PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
8585
8586                 DQSNSE Power Down Receiver
8587                 PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
8588
8589                 DQSSE Power Down Receiver
8590                 PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
8591
8592                 RTT On Additive Latency
8593                 PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
8594
8595                 RTT Output Hold
8596                 PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
8597
8598                 Configurable PDR Phase Shift
8599                 PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
8600
8601                 DQSR Power Down
8602                 PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
8603
8604                 DQSG Power Down Receiver
8605                 PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
8606
8607                 Reserved. Return zeroes on reads.
8608                 PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
8609
8610                 DQSG On-Die Termination
8611                 PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
8612
8613                 DQSG Output Enable
8614                 PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
8615
8616                 Reserved. Return zeroes on reads.
8617                 PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
8618
8619                 DATX8 n General Configuration Register 0
8620                 (OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)
8621                 RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK |  0 );
8622
8623                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT
8624                         | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT
8625                         | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
8626                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT
8627                         | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT
8628                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
8629                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
8630                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
8631                         | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT
8632                         | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT
8633                         | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
8634                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT
8635                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
8636                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
8637                         | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT
8638                         | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT
8639                         | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
8640                         |  0 ) & RegMask); */
8641                 PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8642         /*############################################################################################################################ */
8643
8644                 /*Register : DX3GCR1 @ 0XFD080A04</p>
8645
8646                 Enables the PDR mode for DQ[7:0]
8647                 PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
8648
8649                 Reserved. Returns zeroes on reads.
8650                 PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
8651
8652                 Select the delayed or non-delayed read data strobe #
8653                 PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
8654
8655                 Select the delayed or non-delayed read data strobe
8656                 PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
8657
8658                 Enables Read Data Strobe in a byte lane
8659                 PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
8660
8661                 Enables PDR in a byte lane
8662                 PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
8663
8664                 Enables ODT/TE in a byte lane
8665                 PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
8666
8667                 Enables Write Data strobe in a byte lane
8668                 PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
8669
8670                 Enables DM pin in a byte lane
8671                 PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
8672
8673                 Enables DQ corresponding to each bit in a byte
8674                 PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
8675
8676                 DATX8 n General Configuration Register 1
8677                 (OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)
8678                 RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK |  0 );
8679
8680                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
8681                         | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
8682                         | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT
8683                         | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT
8684                         | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT
8685                         | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT
8686                         | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT
8687                         | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT
8688                         | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT
8689                         | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT
8690                         |  0 ) & RegMask); */
8691                 PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
8692         /*############################################################################################################################ */
8693
8694                 /*Register : DX3GCR4 @ 0XFD080A10</p>
8695
8696                 Byte lane VREF IOM (Used only by D4MU IOs)
8697                 PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
8698
8699                 Byte Lane VREF Pad Enable
8700                 PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
8701
8702                 Byte Lane Internal VREF Enable
8703                 PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
8704
8705                 Byte Lane Single-End VREF Enable
8706                 PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
8707
8708                 Reserved. Returns zeros on reads.
8709                 PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
8710
8711                 External VREF generator REFSEL range select
8712                 PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
8713
8714                 Byte Lane External VREF Select
8715                 PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
8716
8717                 Single ended VREF generator REFSEL range select
8718                 PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
8719
8720                 Byte Lane Single-End VREF Select
8721                 PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
8722
8723                 Reserved. Returns zeros on reads.
8724                 PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
8725
8726                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
8727                 PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
8728
8729                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
8730                 PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
8731
8732                 DATX8 n General Configuration Register 4
8733                 (OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)
8734                 RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK |  0 );
8735
8736                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
8737                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
8738                         | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
8739                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
8740                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
8741                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
8742                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
8743                         | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
8744                         | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
8745                         | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
8746                         | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
8747                         | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
8748                         |  0 ) & RegMask); */
8749                 PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
8750         /*############################################################################################################################ */
8751
8752                 /*Register : DX3GCR5 @ 0XFD080A14</p>
8753
8754                 Reserved. Returns zeros on reads.
8755                 PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
8756
8757                 Byte Lane internal VREF Select for Rank 3
8758                 PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
8759
8760                 Reserved. Returns zeros on reads.
8761                 PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
8762
8763                 Byte Lane internal VREF Select for Rank 2
8764                 PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
8765
8766                 Reserved. Returns zeros on reads.
8767                 PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
8768
8769                 Byte Lane internal VREF Select for Rank 1
8770                 PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x55
8771
8772                 Reserved. Returns zeros on reads.
8773                 PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
8774
8775                 Byte Lane internal VREF Select for Rank 0
8776                 PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x55
8777
8778                 DATX8 n General Configuration Register 5
8779                 (OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)
8780                 RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK |  0 );
8781
8782                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
8783                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
8784                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
8785                         | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
8786                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
8787                         | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
8788                         | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
8789                         | 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
8790                         |  0 ) & RegMask); */
8791                 PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
8792         /*############################################################################################################################ */
8793
8794                 /*Register : DX3GCR6 @ 0XFD080A18</p>
8795
8796                 Reserved. Returns zeros on reads.
8797                 PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
8798
8799                 DRAM DQ VREF Select for Rank3
8800                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
8801
8802                 Reserved. Returns zeros on reads.
8803                 PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
8804
8805                 DRAM DQ VREF Select for Rank2
8806                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
8807
8808                 Reserved. Returns zeros on reads.
8809                 PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
8810
8811                 DRAM DQ VREF Select for Rank1
8812                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
8813
8814                 Reserved. Returns zeros on reads.
8815                 PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
8816
8817                 DRAM DQ VREF Select for Rank0
8818                 PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
8819
8820                 DATX8 n General Configuration Register 6
8821                 (OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)
8822                 RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK |  0 );
8823
8824                 RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
8825                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
8826                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
8827                         | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
8828                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
8829                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
8830                         | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
8831                         | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
8832                         |  0 ) & RegMask); */
8833                 PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
8834         /*############################################################################################################################ */
8835
8836                 /*Register : DX3LCDLR2 @ 0XFD080A88</p>
8837
8838                 Reserved. Return zeroes on reads.
8839                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
8840
8841                 Reserved. Caution, do not write to this register field.
8842                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
8843
8844                 Reserved. Return zeroes on reads.
8845                 PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
8846
8847                 Read DQS Gating Delay
8848                 PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
8849
8850                 DATX8 n Local Calibrated Delay Line Register 2
8851                 (OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)
8852                 RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK |  0 );
8853
8854                 RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
8855                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
8856                         | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
8857                         | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
8858                         |  0 ) & RegMask); */
8859                 PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
8860         /*############################################################################################################################ */
8861
8862                 /*Register : DX3GTR0 @ 0XFD080AC0</p>
8863
8864                 Reserved. Return zeroes on reads.
8865                 PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
8866
8867                 DQ Write Path Latency Pipeline
8868                 PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
8869
8870                 Reserved. Caution, do not write to this register field.
8871                 PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
8872
8873                 Write Leveling System Latency
8874                 PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
8875
8876                 Reserved. Return zeroes on reads.
8877                 PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
8878
8879                 Reserved. Caution, do not write to this register field.
8880                 PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
8881
8882                 Reserved. Return zeroes on reads.
8883                 PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
8884
8885                 DQS Gating System Latency
8886                 PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
8887
8888                 DATX8 n General Timing Register 0
8889                 (OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)
8890                 RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK |  0 );
8891
8892                 RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
8893                         | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT
8894                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
8895                         | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT
8896                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
8897                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
8898                         | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
8899                         | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT
8900                         |  0 ) & RegMask); */
8901                 PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
8902         /*############################################################################################################################ */
8903
8904                 /*Register : DX4GCR0 @ 0XFD080B00</p>
8905
8906                 Calibration Bypass
8907                 PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
8908
8909                 Master Delay Line Enable
8910                 PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
8911
8912                 Configurable ODT(TE) Phase Shift
8913                 PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
8914
8915                 DQS Duty Cycle Correction
8916                 PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
8917
8918                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
8919                 PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
8920
8921                 Reserved. Return zeroes on reads.
8922                 PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
8923
8924                 DQSNSE Power Down Receiver
8925                 PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
8926
8927                 DQSSE Power Down Receiver
8928                 PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
8929
8930                 RTT On Additive Latency
8931                 PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
8932
8933                 RTT Output Hold
8934                 PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
8935
8936                 Configurable PDR Phase Shift
8937                 PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
8938
8939                 DQSR Power Down
8940                 PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
8941
8942                 DQSG Power Down Receiver
8943                 PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
8944
8945                 Reserved. Return zeroes on reads.
8946                 PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
8947
8948                 DQSG On-Die Termination
8949                 PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
8950
8951                 DQSG Output Enable
8952                 PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
8953
8954                 Reserved. Return zeroes on reads.
8955                 PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
8956
8957                 DATX8 n General Configuration Register 0
8958                 (OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)
8959                 RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK |  0 );
8960
8961                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT
8962                         | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT
8963                         | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
8964                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT
8965                         | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT
8966                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
8967                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
8968                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
8969                         | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT
8970                         | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT
8971                         | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
8972                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT
8973                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
8974                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
8975                         | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT
8976                         | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT
8977                         | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
8978                         |  0 ) & RegMask); */
8979                 PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
8980         /*############################################################################################################################ */
8981
8982                 /*Register : DX4GCR1 @ 0XFD080B04</p>
8983
8984                 Enables the PDR mode for DQ[7:0]
8985                 PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
8986
8987                 Reserved. Returns zeroes on reads.
8988                 PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
8989
8990                 Select the delayed or non-delayed read data strobe #
8991                 PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
8992
8993                 Select the delayed or non-delayed read data strobe
8994                 PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
8995
8996                 Enables Read Data Strobe in a byte lane
8997                 PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
8998
8999                 Enables PDR in a byte lane
9000                 PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
9001
9002                 Enables ODT/TE in a byte lane
9003                 PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
9004
9005                 Enables Write Data strobe in a byte lane
9006                 PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
9007
9008                 Enables DM pin in a byte lane
9009                 PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
9010
9011                 Enables DQ corresponding to each bit in a byte
9012                 PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
9013
9014                 DATX8 n General Configuration Register 1
9015                 (OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)
9016                 RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK |  0 );
9017
9018                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
9019                         | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
9020                         | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT
9021                         | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT
9022                         | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT
9023                         | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT
9024                         | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT
9025                         | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT
9026                         | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT
9027                         | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT
9028                         |  0 ) & RegMask); */
9029                 PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9030         /*############################################################################################################################ */
9031
9032                 /*Register : DX4GCR4 @ 0XFD080B10</p>
9033
9034                 Byte lane VREF IOM (Used only by D4MU IOs)
9035                 PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
9036
9037                 Byte Lane VREF Pad Enable
9038                 PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
9039
9040                 Byte Lane Internal VREF Enable
9041                 PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
9042
9043                 Byte Lane Single-End VREF Enable
9044                 PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
9045
9046                 Reserved. Returns zeros on reads.
9047                 PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
9048
9049                 External VREF generator REFSEL range select
9050                 PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
9051
9052                 Byte Lane External VREF Select
9053                 PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
9054
9055                 Single ended VREF generator REFSEL range select
9056                 PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
9057
9058                 Byte Lane Single-End VREF Select
9059                 PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
9060
9061                 Reserved. Returns zeros on reads.
9062                 PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
9063
9064                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9065                 PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
9066
9067                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9068                 PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
9069
9070                 DATX8 n General Configuration Register 4
9071                 (OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)
9072                 RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK |  0 );
9073
9074                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
9075                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
9076                         | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
9077                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
9078                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
9079                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
9080                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
9081                         | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
9082                         | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
9083                         | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
9084                         | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
9085                         | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
9086                         |  0 ) & RegMask); */
9087                 PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9088         /*############################################################################################################################ */
9089
9090                 /*Register : DX4GCR5 @ 0XFD080B14</p>
9091
9092                 Reserved. Returns zeros on reads.
9093                 PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
9094
9095                 Byte Lane internal VREF Select for Rank 3
9096                 PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
9097
9098                 Reserved. Returns zeros on reads.
9099                 PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
9100
9101                 Byte Lane internal VREF Select for Rank 2
9102                 PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
9103
9104                 Reserved. Returns zeros on reads.
9105                 PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
9106
9107                 Byte Lane internal VREF Select for Rank 1
9108                 PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x55
9109
9110                 Reserved. Returns zeros on reads.
9111                 PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
9112
9113                 Byte Lane internal VREF Select for Rank 0
9114                 PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x55
9115
9116                 DATX8 n General Configuration Register 5
9117                 (OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)
9118                 RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK |  0 );
9119
9120                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
9121                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
9122                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
9123                         | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
9124                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
9125                         | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
9126                         | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
9127                         | 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
9128                         |  0 ) & RegMask); */
9129                 PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
9130         /*############################################################################################################################ */
9131
9132                 /*Register : DX4GCR6 @ 0XFD080B18</p>
9133
9134                 Reserved. Returns zeros on reads.
9135                 PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
9136
9137                 DRAM DQ VREF Select for Rank3
9138                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
9139
9140                 Reserved. Returns zeros on reads.
9141                 PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
9142
9143                 DRAM DQ VREF Select for Rank2
9144                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
9145
9146                 Reserved. Returns zeros on reads.
9147                 PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
9148
9149                 DRAM DQ VREF Select for Rank1
9150                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
9151
9152                 Reserved. Returns zeros on reads.
9153                 PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
9154
9155                 DRAM DQ VREF Select for Rank0
9156                 PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
9157
9158                 DATX8 n General Configuration Register 6
9159                 (OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)
9160                 RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK |  0 );
9161
9162                 RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
9163                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
9164                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
9165                         | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
9166                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
9167                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
9168                         | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
9169                         | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
9170                         |  0 ) & RegMask); */
9171                 PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9172         /*############################################################################################################################ */
9173
9174                 /*Register : DX4LCDLR2 @ 0XFD080B88</p>
9175
9176                 Reserved. Return zeroes on reads.
9177                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
9178
9179                 Reserved. Caution, do not write to this register field.
9180                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
9181
9182                 Reserved. Return zeroes on reads.
9183                 PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
9184
9185                 Read DQS Gating Delay
9186                 PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
9187
9188                 DATX8 n Local Calibrated Delay Line Register 2
9189                 (OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)
9190                 RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK |  0 );
9191
9192                 RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
9193                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
9194                         | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
9195                         | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
9196                         |  0 ) & RegMask); */
9197                 PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9198         /*############################################################################################################################ */
9199
9200                 /*Register : DX4GTR0 @ 0XFD080BC0</p>
9201
9202                 Reserved. Return zeroes on reads.
9203                 PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
9204
9205                 DQ Write Path Latency Pipeline
9206                 PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
9207
9208                 Reserved. Caution, do not write to this register field.
9209                 PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
9210
9211                 Write Leveling System Latency
9212                 PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
9213
9214                 Reserved. Return zeroes on reads.
9215                 PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
9216
9217                 Reserved. Caution, do not write to this register field.
9218                 PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
9219
9220                 Reserved. Return zeroes on reads.
9221                 PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
9222
9223                 DQS Gating System Latency
9224                 PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
9225
9226                 DATX8 n General Timing Register 0
9227                 (OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)
9228                 RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK |  0 );
9229
9230                 RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
9231                         | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT
9232                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
9233                         | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT
9234                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
9235                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
9236                         | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
9237                         | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT
9238                         |  0 ) & RegMask); */
9239                 PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9240         /*############################################################################################################################ */
9241
9242                 /*Register : DX5GCR0 @ 0XFD080C00</p>
9243
9244                 Calibration Bypass
9245                 PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
9246
9247                 Master Delay Line Enable
9248                 PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
9249
9250                 Configurable ODT(TE) Phase Shift
9251                 PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
9252
9253                 DQS Duty Cycle Correction
9254                 PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
9255
9256                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9257                 PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
9258
9259                 Reserved. Return zeroes on reads.
9260                 PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
9261
9262                 DQSNSE Power Down Receiver
9263                 PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
9264
9265                 DQSSE Power Down Receiver
9266                 PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
9267
9268                 RTT On Additive Latency
9269                 PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
9270
9271                 RTT Output Hold
9272                 PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
9273
9274                 Configurable PDR Phase Shift
9275                 PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
9276
9277                 DQSR Power Down
9278                 PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
9279
9280                 DQSG Power Down Receiver
9281                 PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
9282
9283                 Reserved. Return zeroes on reads.
9284                 PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
9285
9286                 DQSG On-Die Termination
9287                 PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
9288
9289                 DQSG Output Enable
9290                 PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
9291
9292                 Reserved. Return zeroes on reads.
9293                 PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
9294
9295                 DATX8 n General Configuration Register 0
9296                 (OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)
9297                 RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK |  0 );
9298
9299                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT
9300                         | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT
9301                         | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
9302                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT
9303                         | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT
9304                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
9305                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
9306                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
9307                         | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT
9308                         | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT
9309                         | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
9310                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT
9311                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
9312                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
9313                         | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT
9314                         | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT
9315                         | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
9316                         |  0 ) & RegMask); */
9317                 PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9318         /*############################################################################################################################ */
9319
9320                 /*Register : DX5GCR1 @ 0XFD080C04</p>
9321
9322                 Enables the PDR mode for DQ[7:0]
9323                 PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
9324
9325                 Reserved. Returns zeroes on reads.
9326                 PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
9327
9328                 Select the delayed or non-delayed read data strobe #
9329                 PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
9330
9331                 Select the delayed or non-delayed read data strobe
9332                 PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
9333
9334                 Enables Read Data Strobe in a byte lane
9335                 PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
9336
9337                 Enables PDR in a byte lane
9338                 PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
9339
9340                 Enables ODT/TE in a byte lane
9341                 PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
9342
9343                 Enables Write Data strobe in a byte lane
9344                 PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
9345
9346                 Enables DM pin in a byte lane
9347                 PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
9348
9349                 Enables DQ corresponding to each bit in a byte
9350                 PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
9351
9352                 DATX8 n General Configuration Register 1
9353                 (OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)
9354                 RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK |  0 );
9355
9356                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
9357                         | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
9358                         | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT
9359                         | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT
9360                         | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT
9361                         | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT
9362                         | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT
9363                         | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT
9364                         | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT
9365                         | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT
9366                         |  0 ) & RegMask); */
9367                 PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9368         /*############################################################################################################################ */
9369
9370                 /*Register : DX5GCR4 @ 0XFD080C10</p>
9371
9372                 Byte lane VREF IOM (Used only by D4MU IOs)
9373                 PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
9374
9375                 Byte Lane VREF Pad Enable
9376                 PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
9377
9378                 Byte Lane Internal VREF Enable
9379                 PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
9380
9381                 Byte Lane Single-End VREF Enable
9382                 PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
9383
9384                 Reserved. Returns zeros on reads.
9385                 PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
9386
9387                 External VREF generator REFSEL range select
9388                 PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
9389
9390                 Byte Lane External VREF Select
9391                 PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
9392
9393                 Single ended VREF generator REFSEL range select
9394                 PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
9395
9396                 Byte Lane Single-End VREF Select
9397                 PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
9398
9399                 Reserved. Returns zeros on reads.
9400                 PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
9401
9402                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9403                 PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
9404
9405                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9406                 PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
9407
9408                 DATX8 n General Configuration Register 4
9409                 (OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)
9410                 RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK |  0 );
9411
9412                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
9413                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
9414                         | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
9415                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
9416                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
9417                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
9418                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
9419                         | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
9420                         | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
9421                         | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
9422                         | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
9423                         | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
9424                         |  0 ) & RegMask); */
9425                 PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9426         /*############################################################################################################################ */
9427
9428                 /*Register : DX5GCR5 @ 0XFD080C14</p>
9429
9430                 Reserved. Returns zeros on reads.
9431                 PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
9432
9433                 Byte Lane internal VREF Select for Rank 3
9434                 PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
9435
9436                 Reserved. Returns zeros on reads.
9437                 PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
9438
9439                 Byte Lane internal VREF Select for Rank 2
9440                 PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
9441
9442                 Reserved. Returns zeros on reads.
9443                 PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
9444
9445                 Byte Lane internal VREF Select for Rank 1
9446                 PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x55
9447
9448                 Reserved. Returns zeros on reads.
9449                 PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
9450
9451                 Byte Lane internal VREF Select for Rank 0
9452                 PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x55
9453
9454                 DATX8 n General Configuration Register 5
9455                 (OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)
9456                 RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK |  0 );
9457
9458                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
9459                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
9460                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
9461                         | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
9462                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
9463                         | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
9464                         | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
9465                         | 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
9466                         |  0 ) & RegMask); */
9467                 PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
9468         /*############################################################################################################################ */
9469
9470                 /*Register : DX5GCR6 @ 0XFD080C18</p>
9471
9472                 Reserved. Returns zeros on reads.
9473                 PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
9474
9475                 DRAM DQ VREF Select for Rank3
9476                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
9477
9478                 Reserved. Returns zeros on reads.
9479                 PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
9480
9481                 DRAM DQ VREF Select for Rank2
9482                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
9483
9484                 Reserved. Returns zeros on reads.
9485                 PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
9486
9487                 DRAM DQ VREF Select for Rank1
9488                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
9489
9490                 Reserved. Returns zeros on reads.
9491                 PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
9492
9493                 DRAM DQ VREF Select for Rank0
9494                 PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
9495
9496                 DATX8 n General Configuration Register 6
9497                 (OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)
9498                 RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK |  0 );
9499
9500                 RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
9501                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
9502                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
9503                         | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
9504                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
9505                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
9506                         | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
9507                         | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
9508                         |  0 ) & RegMask); */
9509                 PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9510         /*############################################################################################################################ */
9511
9512                 /*Register : DX5LCDLR2 @ 0XFD080C88</p>
9513
9514                 Reserved. Return zeroes on reads.
9515                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
9516
9517                 Reserved. Caution, do not write to this register field.
9518                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
9519
9520                 Reserved. Return zeroes on reads.
9521                 PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
9522
9523                 Read DQS Gating Delay
9524                 PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
9525
9526                 DATX8 n Local Calibrated Delay Line Register 2
9527                 (OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)
9528                 RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK |  0 );
9529
9530                 RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
9531                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
9532                         | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
9533                         | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
9534                         |  0 ) & RegMask); */
9535                 PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9536         /*############################################################################################################################ */
9537
9538                 /*Register : DX5GTR0 @ 0XFD080CC0</p>
9539
9540                 Reserved. Return zeroes on reads.
9541                 PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
9542
9543                 DQ Write Path Latency Pipeline
9544                 PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
9545
9546                 Reserved. Caution, do not write to this register field.
9547                 PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
9548
9549                 Write Leveling System Latency
9550                 PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
9551
9552                 Reserved. Return zeroes on reads.
9553                 PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
9554
9555                 Reserved. Caution, do not write to this register field.
9556                 PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
9557
9558                 Reserved. Return zeroes on reads.
9559                 PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
9560
9561                 DQS Gating System Latency
9562                 PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
9563
9564                 DATX8 n General Timing Register 0
9565                 (OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)
9566                 RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK |  0 );
9567
9568                 RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
9569                         | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT
9570                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
9571                         | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT
9572                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
9573                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
9574                         | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
9575                         | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT
9576                         |  0 ) & RegMask); */
9577                 PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9578         /*############################################################################################################################ */
9579
9580                 /*Register : DX6GCR0 @ 0XFD080D00</p>
9581
9582                 Calibration Bypass
9583                 PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
9584
9585                 Master Delay Line Enable
9586                 PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
9587
9588                 Configurable ODT(TE) Phase Shift
9589                 PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
9590
9591                 DQS Duty Cycle Correction
9592                 PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
9593
9594                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9595                 PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
9596
9597                 Reserved. Return zeroes on reads.
9598                 PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
9599
9600                 DQSNSE Power Down Receiver
9601                 PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
9602
9603                 DQSSE Power Down Receiver
9604                 PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
9605
9606                 RTT On Additive Latency
9607                 PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
9608
9609                 RTT Output Hold
9610                 PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
9611
9612                 Configurable PDR Phase Shift
9613                 PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
9614
9615                 DQSR Power Down
9616                 PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
9617
9618                 DQSG Power Down Receiver
9619                 PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
9620
9621                 Reserved. Return zeroes on reads.
9622                 PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
9623
9624                 DQSG On-Die Termination
9625                 PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
9626
9627                 DQSG Output Enable
9628                 PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
9629
9630                 Reserved. Return zeroes on reads.
9631                 PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
9632
9633                 DATX8 n General Configuration Register 0
9634                 (OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)
9635                 RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK |  0 );
9636
9637                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT
9638                         | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT
9639                         | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
9640                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT
9641                         | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT
9642                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
9643                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
9644                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
9645                         | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT
9646                         | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT
9647                         | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
9648                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT
9649                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
9650                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
9651                         | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT
9652                         | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT
9653                         | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
9654                         |  0 ) & RegMask); */
9655                 PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9656         /*############################################################################################################################ */
9657
9658                 /*Register : DX6GCR1 @ 0XFD080D04</p>
9659
9660                 Enables the PDR mode for DQ[7:0]
9661                 PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
9662
9663                 Reserved. Returns zeroes on reads.
9664                 PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
9665
9666                 Select the delayed or non-delayed read data strobe #
9667                 PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
9668
9669                 Select the delayed or non-delayed read data strobe
9670                 PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
9671
9672                 Enables Read Data Strobe in a byte lane
9673                 PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
9674
9675                 Enables PDR in a byte lane
9676                 PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
9677
9678                 Enables ODT/TE in a byte lane
9679                 PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
9680
9681                 Enables Write Data strobe in a byte lane
9682                 PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
9683
9684                 Enables DM pin in a byte lane
9685                 PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
9686
9687                 Enables DQ corresponding to each bit in a byte
9688                 PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
9689
9690                 DATX8 n General Configuration Register 1
9691                 (OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)
9692                 RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK |  0 );
9693
9694                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
9695                         | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
9696                         | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT
9697                         | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT
9698                         | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT
9699                         | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT
9700                         | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT
9701                         | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT
9702                         | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT
9703                         | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT
9704                         |  0 ) & RegMask); */
9705                 PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
9706         /*############################################################################################################################ */
9707
9708                 /*Register : DX6GCR4 @ 0XFD080D10</p>
9709
9710                 Byte lane VREF IOM (Used only by D4MU IOs)
9711                 PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
9712
9713                 Byte Lane VREF Pad Enable
9714                 PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
9715
9716                 Byte Lane Internal VREF Enable
9717                 PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
9718
9719                 Byte Lane Single-End VREF Enable
9720                 PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
9721
9722                 Reserved. Returns zeros on reads.
9723                 PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
9724
9725                 External VREF generator REFSEL range select
9726                 PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
9727
9728                 Byte Lane External VREF Select
9729                 PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
9730
9731                 Single ended VREF generator REFSEL range select
9732                 PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
9733
9734                 Byte Lane Single-End VREF Select
9735                 PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
9736
9737                 Reserved. Returns zeros on reads.
9738                 PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
9739
9740                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
9741                 PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
9742
9743                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
9744                 PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
9745
9746                 DATX8 n General Configuration Register 4
9747                 (OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)
9748                 RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK |  0 );
9749
9750                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
9751                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
9752                         | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
9753                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
9754                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
9755                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
9756                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
9757                         | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
9758                         | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
9759                         | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
9760                         | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
9761                         | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
9762                         |  0 ) & RegMask); */
9763                 PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
9764         /*############################################################################################################################ */
9765
9766                 /*Register : DX6GCR5 @ 0XFD080D14</p>
9767
9768                 Reserved. Returns zeros on reads.
9769                 PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
9770
9771                 Byte Lane internal VREF Select for Rank 3
9772                 PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
9773
9774                 Reserved. Returns zeros on reads.
9775                 PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
9776
9777                 Byte Lane internal VREF Select for Rank 2
9778                 PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
9779
9780                 Reserved. Returns zeros on reads.
9781                 PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
9782
9783                 Byte Lane internal VREF Select for Rank 1
9784                 PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x55
9785
9786                 Reserved. Returns zeros on reads.
9787                 PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
9788
9789                 Byte Lane internal VREF Select for Rank 0
9790                 PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x55
9791
9792                 DATX8 n General Configuration Register 5
9793                 (OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)
9794                 RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK |  0 );
9795
9796                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
9797                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
9798                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
9799                         | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
9800                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
9801                         | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
9802                         | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
9803                         | 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
9804                         |  0 ) & RegMask); */
9805                 PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
9806         /*############################################################################################################################ */
9807
9808                 /*Register : DX6GCR6 @ 0XFD080D18</p>
9809
9810                 Reserved. Returns zeros on reads.
9811                 PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
9812
9813                 DRAM DQ VREF Select for Rank3
9814                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
9815
9816                 Reserved. Returns zeros on reads.
9817                 PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
9818
9819                 DRAM DQ VREF Select for Rank2
9820                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
9821
9822                 Reserved. Returns zeros on reads.
9823                 PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
9824
9825                 DRAM DQ VREF Select for Rank1
9826                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
9827
9828                 Reserved. Returns zeros on reads.
9829                 PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
9830
9831                 DRAM DQ VREF Select for Rank0
9832                 PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
9833
9834                 DATX8 n General Configuration Register 6
9835                 (OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)
9836                 RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK |  0 );
9837
9838                 RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
9839                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
9840                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
9841                         | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
9842                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
9843                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
9844                         | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
9845                         | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
9846                         |  0 ) & RegMask); */
9847                 PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
9848         /*############################################################################################################################ */
9849
9850                 /*Register : DX6LCDLR2 @ 0XFD080D88</p>
9851
9852                 Reserved. Return zeroes on reads.
9853                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
9854
9855                 Reserved. Caution, do not write to this register field.
9856                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
9857
9858                 Reserved. Return zeroes on reads.
9859                 PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
9860
9861                 Read DQS Gating Delay
9862                 PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
9863
9864                 DATX8 n Local Calibrated Delay Line Register 2
9865                 (OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)
9866                 RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK |  0 );
9867
9868                 RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
9869                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
9870                         | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
9871                         | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
9872                         |  0 ) & RegMask); */
9873                 PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
9874         /*############################################################################################################################ */
9875
9876                 /*Register : DX6GTR0 @ 0XFD080DC0</p>
9877
9878                 Reserved. Return zeroes on reads.
9879                 PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
9880
9881                 DQ Write Path Latency Pipeline
9882                 PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
9883
9884                 Reserved. Caution, do not write to this register field.
9885                 PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
9886
9887                 Write Leveling System Latency
9888                 PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
9889
9890                 Reserved. Return zeroes on reads.
9891                 PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
9892
9893                 Reserved. Caution, do not write to this register field.
9894                 PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
9895
9896                 Reserved. Return zeroes on reads.
9897                 PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
9898
9899                 DQS Gating System Latency
9900                 PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
9901
9902                 DATX8 n General Timing Register 0
9903                 (OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)
9904                 RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK |  0 );
9905
9906                 RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
9907                         | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT
9908                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
9909                         | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT
9910                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
9911                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
9912                         | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
9913                         | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT
9914                         |  0 ) & RegMask); */
9915                 PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
9916         /*############################################################################################################################ */
9917
9918                 /*Register : DX7GCR0 @ 0XFD080E00</p>
9919
9920                 Calibration Bypass
9921                 PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
9922
9923                 Master Delay Line Enable
9924                 PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
9925
9926                 Configurable ODT(TE) Phase Shift
9927                 PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
9928
9929                 DQS Duty Cycle Correction
9930                 PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
9931
9932                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
9933                 PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
9934
9935                 Reserved. Return zeroes on reads.
9936                 PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
9937
9938                 DQSNSE Power Down Receiver
9939                 PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
9940
9941                 DQSSE Power Down Receiver
9942                 PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
9943
9944                 RTT On Additive Latency
9945                 PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
9946
9947                 RTT Output Hold
9948                 PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
9949
9950                 Configurable PDR Phase Shift
9951                 PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
9952
9953                 DQSR Power Down
9954                 PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
9955
9956                 DQSG Power Down Receiver
9957                 PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
9958
9959                 Reserved. Return zeroes on reads.
9960                 PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
9961
9962                 DQSG On-Die Termination
9963                 PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
9964
9965                 DQSG Output Enable
9966                 PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
9967
9968                 Reserved. Return zeroes on reads.
9969                 PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
9970
9971                 DATX8 n General Configuration Register 0
9972                 (OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)
9973                 RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK |  0 );
9974
9975                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT
9976                         | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT
9977                         | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
9978                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT
9979                         | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT
9980                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
9981                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
9982                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
9983                         | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT
9984                         | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT
9985                         | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
9986                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT
9987                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
9988                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
9989                         | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT
9990                         | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT
9991                         | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
9992                         |  0 ) & RegMask); */
9993                 PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
9994         /*############################################################################################################################ */
9995
9996                 /*Register : DX7GCR1 @ 0XFD080E04</p>
9997
9998                 Enables the PDR mode for DQ[7:0]
9999                 PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
10000
10001                 Reserved. Returns zeroes on reads.
10002                 PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
10003
10004                 Select the delayed or non-delayed read data strobe #
10005                 PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
10006
10007                 Select the delayed or non-delayed read data strobe
10008                 PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
10009
10010                 Enables Read Data Strobe in a byte lane
10011                 PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
10012
10013                 Enables PDR in a byte lane
10014                 PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
10015
10016                 Enables ODT/TE in a byte lane
10017                 PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
10018
10019                 Enables Write Data strobe in a byte lane
10020                 PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
10021
10022                 Enables DM pin in a byte lane
10023                 PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
10024
10025                 Enables DQ corresponding to each bit in a byte
10026                 PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
10027
10028                 DATX8 n General Configuration Register 1
10029                 (OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)
10030                 RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK |  0 );
10031
10032                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
10033                         | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
10034                         | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT
10035                         | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT
10036                         | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT
10037                         | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT
10038                         | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT
10039                         | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT
10040                         | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT
10041                         | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT
10042                         |  0 ) & RegMask); */
10043                 PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
10044         /*############################################################################################################################ */
10045
10046                 /*Register : DX7GCR4 @ 0XFD080E10</p>
10047
10048                 Byte lane VREF IOM (Used only by D4MU IOs)
10049                 PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
10050
10051                 Byte Lane VREF Pad Enable
10052                 PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
10053
10054                 Byte Lane Internal VREF Enable
10055                 PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
10056
10057                 Byte Lane Single-End VREF Enable
10058                 PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
10059
10060                 Reserved. Returns zeros on reads.
10061                 PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
10062
10063                 External VREF generator REFSEL range select
10064                 PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
10065
10066                 Byte Lane External VREF Select
10067                 PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
10068
10069                 Single ended VREF generator REFSEL range select
10070                 PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
10071
10072                 Byte Lane Single-End VREF Select
10073                 PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
10074
10075                 Reserved. Returns zeros on reads.
10076                 PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
10077
10078                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
10079                 PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
10080
10081                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
10082                 PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
10083
10084                 DATX8 n General Configuration Register 4
10085                 (OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)
10086                 RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK |  0 );
10087
10088                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
10089                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
10090                         | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
10091                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
10092                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
10093                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
10094                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
10095                         | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
10096                         | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
10097                         | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
10098                         | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
10099                         | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
10100                         |  0 ) & RegMask); */
10101                 PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10102         /*############################################################################################################################ */
10103
10104                 /*Register : DX7GCR5 @ 0XFD080E14</p>
10105
10106                 Reserved. Returns zeros on reads.
10107                 PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
10108
10109                 Byte Lane internal VREF Select for Rank 3
10110                 PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
10111
10112                 Reserved. Returns zeros on reads.
10113                 PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
10114
10115                 Byte Lane internal VREF Select for Rank 2
10116                 PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
10117
10118                 Reserved. Returns zeros on reads.
10119                 PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
10120
10121                 Byte Lane internal VREF Select for Rank 1
10122                 PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x55
10123
10124                 Reserved. Returns zeros on reads.
10125                 PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
10126
10127                 Byte Lane internal VREF Select for Rank 0
10128                 PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x55
10129
10130                 DATX8 n General Configuration Register 5
10131                 (OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)
10132                 RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK |  0 );
10133
10134                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
10135                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
10136                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
10137                         | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
10138                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
10139                         | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
10140                         | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
10141                         | 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
10142                         |  0 ) & RegMask); */
10143                 PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
10144         /*############################################################################################################################ */
10145
10146                 /*Register : DX7GCR6 @ 0XFD080E18</p>
10147
10148                 Reserved. Returns zeros on reads.
10149                 PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
10150
10151                 DRAM DQ VREF Select for Rank3
10152                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
10153
10154                 Reserved. Returns zeros on reads.
10155                 PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
10156
10157                 DRAM DQ VREF Select for Rank2
10158                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
10159
10160                 Reserved. Returns zeros on reads.
10161                 PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
10162
10163                 DRAM DQ VREF Select for Rank1
10164                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
10165
10166                 Reserved. Returns zeros on reads.
10167                 PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
10168
10169                 DRAM DQ VREF Select for Rank0
10170                 PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
10171
10172                 DATX8 n General Configuration Register 6
10173                 (OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)
10174                 RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK |  0 );
10175
10176                 RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
10177                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
10178                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
10179                         | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
10180                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
10181                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
10182                         | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
10183                         | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
10184                         |  0 ) & RegMask); */
10185                 PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10186         /*############################################################################################################################ */
10187
10188                 /*Register : DX7LCDLR2 @ 0XFD080E88</p>
10189
10190                 Reserved. Return zeroes on reads.
10191                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
10192
10193                 Reserved. Caution, do not write to this register field.
10194                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
10195
10196                 Reserved. Return zeroes on reads.
10197                 PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
10198
10199                 Read DQS Gating Delay
10200                 PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
10201
10202                 DATX8 n Local Calibrated Delay Line Register 2
10203                 (OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)
10204                 RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK |  0 );
10205
10206                 RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
10207                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
10208                         | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
10209                         | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
10210                         |  0 ) & RegMask); */
10211                 PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU);
10212         /*############################################################################################################################ */
10213
10214                 /*Register : DX7GTR0 @ 0XFD080EC0</p>
10215
10216                 Reserved. Return zeroes on reads.
10217                 PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
10218
10219                 DQ Write Path Latency Pipeline
10220                 PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
10221
10222                 Reserved. Caution, do not write to this register field.
10223                 PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
10224
10225                 Write Leveling System Latency
10226                 PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
10227
10228                 Reserved. Return zeroes on reads.
10229                 PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
10230
10231                 Reserved. Caution, do not write to this register field.
10232                 PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
10233
10234                 Reserved. Return zeroes on reads.
10235                 PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
10236
10237                 DQS Gating System Latency
10238                 PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
10239
10240                 DATX8 n General Timing Register 0
10241                 (OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)
10242                 RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK |  0 );
10243
10244                 RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
10245                         | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT
10246                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
10247                         | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT
10248                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
10249                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
10250                         | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
10251                         | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT
10252                         |  0 ) & RegMask); */
10253                 PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10254         /*############################################################################################################################ */
10255
10256                 /*Register : DX8GCR0 @ 0XFD080F00</p>
10257
10258                 Calibration Bypass
10259                 PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
10260
10261                 Master Delay Line Enable
10262                 PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
10263
10264                 Configurable ODT(TE) Phase Shift
10265                 PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
10266
10267                 DQS Duty Cycle Correction
10268                 PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
10269
10270                 Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
10271                 PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
10272
10273                 Reserved. Return zeroes on reads.
10274                 PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
10275
10276                 DQSNSE Power Down Receiver
10277                 PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
10278
10279                 DQSSE Power Down Receiver
10280                 PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
10281
10282                 RTT On Additive Latency
10283                 PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
10284
10285                 RTT Output Hold
10286                 PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
10287
10288                 Configurable PDR Phase Shift
10289                 PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
10290
10291                 DQSR Power Down
10292                 PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
10293
10294                 DQSG Power Down Receiver
10295                 PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
10296
10297                 Reserved. Return zeroes on reads.
10298                 PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
10299
10300                 DQSG On-Die Termination
10301                 PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
10302
10303                 DQSG Output Enable
10304                 PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
10305
10306                 Reserved. Return zeroes on reads.
10307                 PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
10308
10309                 DATX8 n General Configuration Register 0
10310                 (OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)
10311                 RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK |  0 );
10312
10313                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT
10314                         | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT
10315                         | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
10316                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT
10317                         | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT
10318                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
10319                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
10320                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
10321                         | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT
10322                         | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT
10323                         | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
10324                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT
10325                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
10326                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
10327                         | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT
10328                         | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT
10329                         | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
10330                         |  0 ) & RegMask); */
10331                 PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U);
10332         /*############################################################################################################################ */
10333
10334                 /*Register : DX8GCR1 @ 0XFD080F04</p>
10335
10336                 Enables the PDR mode for DQ[7:0]
10337                 PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
10338
10339                 Reserved. Returns zeroes on reads.
10340                 PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
10341
10342                 Select the delayed or non-delayed read data strobe #
10343                 PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
10344
10345                 Select the delayed or non-delayed read data strobe
10346                 PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
10347
10348                 Enables Read Data Strobe in a byte lane
10349                 PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
10350
10351                 Enables PDR in a byte lane
10352                 PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
10353
10354                 Enables ODT/TE in a byte lane
10355                 PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
10356
10357                 Enables Write Data strobe in a byte lane
10358                 PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
10359
10360                 Enables DM pin in a byte lane
10361                 PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
10362
10363                 Enables DQ corresponding to each bit in a byte
10364                 PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
10365
10366                 DATX8 n General Configuration Register 1
10367                 (OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)
10368                 RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK |  0 );
10369
10370                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
10371                         | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
10372                         | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT
10373                         | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT
10374                         | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT
10375                         | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT
10376                         | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT
10377                         | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT
10378                         | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT
10379                         | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT
10380                         |  0 ) & RegMask); */
10381                 PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U);
10382         /*############################################################################################################################ */
10383
10384                 /*Register : DX8GCR4 @ 0XFD080F10</p>
10385
10386                 Byte lane VREF IOM (Used only by D4MU IOs)
10387                 PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
10388
10389                 Byte Lane VREF Pad Enable
10390                 PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
10391
10392                 Byte Lane Internal VREF Enable
10393                 PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
10394
10395                 Byte Lane Single-End VREF Enable
10396                 PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
10397
10398                 Reserved. Returns zeros on reads.
10399                 PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
10400
10401                 External VREF generator REFSEL range select
10402                 PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
10403
10404                 Byte Lane External VREF Select
10405                 PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
10406
10407                 Single ended VREF generator REFSEL range select
10408                 PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
10409
10410                 Byte Lane Single-End VREF Select
10411                 PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
10412
10413                 Reserved. Returns zeros on reads.
10414                 PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
10415
10416                 VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
10417                 PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
10418
10419                 VRMON control for DQ IO (Single Ended) buffers of a byte lane.
10420                 PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
10421
10422                 DATX8 n General Configuration Register 4
10423                 (OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)
10424                 RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK |  0 );
10425
10426                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
10427                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
10428                         | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
10429                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
10430                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
10431                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
10432                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
10433                         | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
10434                         | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
10435                         | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
10436                         | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
10437                         | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
10438                         |  0 ) & RegMask); */
10439                 PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
10440         /*############################################################################################################################ */
10441
10442                 /*Register : DX8GCR5 @ 0XFD080F14</p>
10443
10444                 Reserved. Returns zeros on reads.
10445                 PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
10446
10447                 Byte Lane internal VREF Select for Rank 3
10448                 PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
10449
10450                 Reserved. Returns zeros on reads.
10451                 PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
10452
10453                 Byte Lane internal VREF Select for Rank 2
10454                 PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
10455
10456                 Reserved. Returns zeros on reads.
10457                 PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
10458
10459                 Byte Lane internal VREF Select for Rank 1
10460                 PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x55
10461
10462                 Reserved. Returns zeros on reads.
10463                 PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
10464
10465                 Byte Lane internal VREF Select for Rank 0
10466                 PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x55
10467
10468                 DATX8 n General Configuration Register 5
10469                 (OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)
10470                 RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK |  0 );
10471
10472                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
10473                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
10474                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
10475                         | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
10476                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
10477                         | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
10478                         | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
10479                         | 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
10480                         |  0 ) & RegMask); */
10481                 PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
10482         /*############################################################################################################################ */
10483
10484                 /*Register : DX8GCR6 @ 0XFD080F18</p>
10485
10486                 Reserved. Returns zeros on reads.
10487                 PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
10488
10489                 DRAM DQ VREF Select for Rank3
10490                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
10491
10492                 Reserved. Returns zeros on reads.
10493                 PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
10494
10495                 DRAM DQ VREF Select for Rank2
10496                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
10497
10498                 Reserved. Returns zeros on reads.
10499                 PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
10500
10501                 DRAM DQ VREF Select for Rank1
10502                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
10503
10504                 Reserved. Returns zeros on reads.
10505                 PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
10506
10507                 DRAM DQ VREF Select for Rank0
10508                 PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
10509
10510                 DATX8 n General Configuration Register 6
10511                 (OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)
10512                 RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK |  0 );
10513
10514                 RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
10515                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
10516                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
10517                         | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
10518                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
10519                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
10520                         | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
10521                         | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
10522                         |  0 ) & RegMask); */
10523                 PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
10524         /*############################################################################################################################ */
10525
10526                 /*Register : DX8LCDLR2 @ 0XFD080F88</p>
10527
10528                 Reserved. Return zeroes on reads.
10529                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
10530
10531                 Reserved. Caution, do not write to this register field.
10532                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
10533
10534                 Reserved. Return zeroes on reads.
10535                 PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
10536
10537                 Read DQS Gating Delay
10538                 PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
10539
10540                 DATX8 n Local Calibrated Delay Line Register 2
10541                 (OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)
10542                 RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK |  0 );
10543
10544                 RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
10545                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
10546                         | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
10547                         | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
10548                         |  0 ) & RegMask); */
10549                 PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
10550         /*############################################################################################################################ */
10551
10552                 /*Register : DX8GTR0 @ 0XFD080FC0</p>
10553
10554                 Reserved. Return zeroes on reads.
10555                 PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
10556
10557                 DQ Write Path Latency Pipeline
10558                 PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
10559
10560                 Reserved. Caution, do not write to this register field.
10561                 PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
10562
10563                 Write Leveling System Latency
10564                 PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
10565
10566                 Reserved. Return zeroes on reads.
10567                 PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
10568
10569                 Reserved. Caution, do not write to this register field.
10570                 PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
10571
10572                 Reserved. Return zeroes on reads.
10573                 PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
10574
10575                 DQS Gating System Latency
10576                 PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
10577
10578                 DATX8 n General Timing Register 0
10579                 (OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)
10580                 RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK |  0 );
10581
10582                 RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
10583                         | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT
10584                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
10585                         | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT
10586                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
10587                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
10588                         | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
10589                         | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT
10590                         |  0 ) & RegMask); */
10591                 PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
10592         /*############################################################################################################################ */
10593
10594                 /*Register : DX8SL0DQSCTL @ 0XFD08141C</p>
10595
10596                 Reserved. Return zeroes on reads.
10597                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
10598
10599                 Read Path Rise-to-Rise Mode
10600                 PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
10601
10602                 Reserved. Return zeroes on reads.
10603                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
10604
10605                 Write Path Rise-to-Rise Mode
10606                 PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
10607
10608                 DQS Gate Extension
10609                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
10610
10611                 Low Power PLL Power Down
10612                 PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
10613
10614                 Low Power I/O Power Down
10615                 PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
10616
10617                 Reserved. Return zeroes on reads.
10618                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
10619
10620                 QS Counter Enable
10621                 PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
10622
10623                 Unused DQ I/O Mode
10624                 PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
10625
10626                 Reserved. Return zeroes on reads.
10627                 PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
10628
10629                 Data Slew Rate
10630                 PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
10631
10632                 DQS_N Resistor
10633                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0xc
10634
10635                 DQS Resistor
10636                 PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x4
10637
10638                 DATX8 0-1 DQS Control Register
10639                 (OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)
10640                 RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK |  0 );
10641
10642                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
10643                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
10644                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
10645                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
10646                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
10647                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
10648                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
10649                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
10650                         | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
10651                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
10652                         | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
10653                         | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
10654                         | 0x0000000CU << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
10655                         | 0x00000004U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
10656                         |  0 ) & RegMask); */
10657                 PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
10658         /*############################################################################################################################ */
10659
10660                 /*Register : DX8SL0DXCTL2 @ 0XFD08142C</p>
10661
10662                 Reserved. Return zeroes on reads.
10663                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
10664
10665                 Configurable Read Data Enable
10666                 PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
10667
10668                 OX Extension during Post-amble
10669                 PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
10670
10671                 OE Extension during Pre-amble
10672                 PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x0
10673
10674                 Reserved. Return zeroes on reads.
10675                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
10676
10677                 I/O Assisted Gate Select
10678                 PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
10679
10680                 I/O Loopback Select
10681                 PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
10682
10683                 Reserved. Return zeroes on reads.
10684                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
10685
10686                 Low Power Wakeup Threshold
10687                 PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
10688
10689                 Read Data Bus Inversion Enable
10690                 PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
10691
10692                 Write Data Bus Inversion Enable
10693                 PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
10694
10695                 PUB Read FIFO Bypass
10696                 PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
10697
10698                 DATX8 Receive FIFO Read Mode
10699                 PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
10700
10701                 Disables the Read FIFO Reset
10702                 PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
10703
10704                 Read DQS Gate I/O Loopback
10705                 PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
10706
10707                 Reserved. Return zeroes on reads.
10708                 PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
10709
10710                 DATX8 0-1 DX Control Register 2
10711                 (OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)
10712                 RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK |  0 );
10713
10714                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
10715                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
10716                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
10717                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
10718                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
10719                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
10720                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
10721                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
10722                         | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
10723                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
10724                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
10725                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
10726                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
10727                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
10728                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
10729                         | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
10730                         |  0 ) & RegMask); */
10731                 PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
10732         /*############################################################################################################################ */
10733
10734                 /*Register : DX8SL0IOCR @ 0XFD081430</p>
10735
10736                 Reserved. Return zeroes on reads.
10737                 PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
10738
10739                 PVREF_DAC REFSEL range select
10740                 PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
10741
10742                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10743                 PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
10744
10745                 DX IO Mode
10746                 PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
10747
10748                 DX IO Transmitter Mode
10749                 PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
10750
10751                 DX IO Receiver Mode
10752                 PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
10753
10754                 DATX8 0-1 I/O Configuration Register
10755                 (OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)
10756                 RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK |  0 );
10757
10758                 RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
10759                         | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
10760                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
10761                         | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
10762                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
10763                         | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
10764                         |  0 ) & RegMask); */
10765                 PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
10766         /*############################################################################################################################ */
10767
10768                 /*Register : DX8SL1DQSCTL @ 0XFD08145C</p>
10769
10770                 Reserved. Return zeroes on reads.
10771                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
10772
10773                 Read Path Rise-to-Rise Mode
10774                 PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
10775
10776                 Reserved. Return zeroes on reads.
10777                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
10778
10779                 Write Path Rise-to-Rise Mode
10780                 PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
10781
10782                 DQS Gate Extension
10783                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
10784
10785                 Low Power PLL Power Down
10786                 PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
10787
10788                 Low Power I/O Power Down
10789                 PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
10790
10791                 Reserved. Return zeroes on reads.
10792                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
10793
10794                 QS Counter Enable
10795                 PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
10796
10797                 Unused DQ I/O Mode
10798                 PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
10799
10800                 Reserved. Return zeroes on reads.
10801                 PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
10802
10803                 Data Slew Rate
10804                 PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
10805
10806                 DQS_N Resistor
10807                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0xc
10808
10809                 DQS Resistor
10810                 PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x4
10811
10812                 DATX8 0-1 DQS Control Register
10813                 (OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)
10814                 RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK |  0 );
10815
10816                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
10817                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
10818                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
10819                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
10820                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
10821                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
10822                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
10823                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
10824                         | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
10825                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
10826                         | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
10827                         | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
10828                         | 0x0000000CU << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
10829                         | 0x00000004U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
10830                         |  0 ) & RegMask); */
10831                 PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
10832         /*############################################################################################################################ */
10833
10834                 /*Register : DX8SL1DXCTL2 @ 0XFD08146C</p>
10835
10836                 Reserved. Return zeroes on reads.
10837                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
10838
10839                 Configurable Read Data Enable
10840                 PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
10841
10842                 OX Extension during Post-amble
10843                 PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
10844
10845                 OE Extension during Pre-amble
10846                 PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x0
10847
10848                 Reserved. Return zeroes on reads.
10849                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
10850
10851                 I/O Assisted Gate Select
10852                 PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
10853
10854                 I/O Loopback Select
10855                 PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
10856
10857                 Reserved. Return zeroes on reads.
10858                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
10859
10860                 Low Power Wakeup Threshold
10861                 PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
10862
10863                 Read Data Bus Inversion Enable
10864                 PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
10865
10866                 Write Data Bus Inversion Enable
10867                 PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
10868
10869                 PUB Read FIFO Bypass
10870                 PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
10871
10872                 DATX8 Receive FIFO Read Mode
10873                 PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
10874
10875                 Disables the Read FIFO Reset
10876                 PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
10877
10878                 Read DQS Gate I/O Loopback
10879                 PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
10880
10881                 Reserved. Return zeroes on reads.
10882                 PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
10883
10884                 DATX8 0-1 DX Control Register 2
10885                 (OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)
10886                 RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK |  0 );
10887
10888                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
10889                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
10890                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
10891                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
10892                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
10893                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
10894                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
10895                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
10896                         | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
10897                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
10898                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
10899                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
10900                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
10901                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
10902                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
10903                         | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
10904                         |  0 ) & RegMask); */
10905                 PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
10906         /*############################################################################################################################ */
10907
10908                 /*Register : DX8SL1IOCR @ 0XFD081470</p>
10909
10910                 Reserved. Return zeroes on reads.
10911                 PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
10912
10913                 PVREF_DAC REFSEL range select
10914                 PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
10915
10916                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
10917                 PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
10918
10919                 DX IO Mode
10920                 PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
10921
10922                 DX IO Transmitter Mode
10923                 PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
10924
10925                 DX IO Receiver Mode
10926                 PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
10927
10928                 DATX8 0-1 I/O Configuration Register
10929                 (OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)
10930                 RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK |  0 );
10931
10932                 RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
10933                         | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
10934                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
10935                         | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
10936                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
10937                         | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
10938                         |  0 ) & RegMask); */
10939                 PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
10940         /*############################################################################################################################ */
10941
10942                 /*Register : DX8SL2DQSCTL @ 0XFD08149C</p>
10943
10944                 Reserved. Return zeroes on reads.
10945                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
10946
10947                 Read Path Rise-to-Rise Mode
10948                 PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
10949
10950                 Reserved. Return zeroes on reads.
10951                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
10952
10953                 Write Path Rise-to-Rise Mode
10954                 PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
10955
10956                 DQS Gate Extension
10957                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
10958
10959                 Low Power PLL Power Down
10960                 PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
10961
10962                 Low Power I/O Power Down
10963                 PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
10964
10965                 Reserved. Return zeroes on reads.
10966                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
10967
10968                 QS Counter Enable
10969                 PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
10970
10971                 Unused DQ I/O Mode
10972                 PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
10973
10974                 Reserved. Return zeroes on reads.
10975                 PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
10976
10977                 Data Slew Rate
10978                 PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
10979
10980                 DQS_N Resistor
10981                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0xc
10982
10983                 DQS Resistor
10984                 PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x4
10985
10986                 DATX8 0-1 DQS Control Register
10987                 (OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)
10988                 RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK |  0 );
10989
10990                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
10991                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
10992                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
10993                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
10994                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
10995                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
10996                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
10997                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
10998                         | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
10999                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
11000                         | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
11001                         | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
11002                         | 0x0000000CU << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
11003                         | 0x00000004U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
11004                         |  0 ) & RegMask); */
11005                 PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11006         /*############################################################################################################################ */
11007
11008                 /*Register : DX8SL2DXCTL2 @ 0XFD0814AC</p>
11009
11010                 Reserved. Return zeroes on reads.
11011                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
11012
11013                 Configurable Read Data Enable
11014                 PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
11015
11016                 OX Extension during Post-amble
11017                 PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
11018
11019                 OE Extension during Pre-amble
11020                 PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x0
11021
11022                 Reserved. Return zeroes on reads.
11023                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
11024
11025                 I/O Assisted Gate Select
11026                 PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
11027
11028                 I/O Loopback Select
11029                 PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
11030
11031                 Reserved. Return zeroes on reads.
11032                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
11033
11034                 Low Power Wakeup Threshold
11035                 PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
11036
11037                 Read Data Bus Inversion Enable
11038                 PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
11039
11040                 Write Data Bus Inversion Enable
11041                 PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
11042
11043                 PUB Read FIFO Bypass
11044                 PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
11045
11046                 DATX8 Receive FIFO Read Mode
11047                 PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
11048
11049                 Disables the Read FIFO Reset
11050                 PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
11051
11052                 Read DQS Gate I/O Loopback
11053                 PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
11054
11055                 Reserved. Return zeroes on reads.
11056                 PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
11057
11058                 DATX8 0-1 DX Control Register 2
11059                 (OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)
11060                 RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK |  0 );
11061
11062                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
11063                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
11064                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
11065                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
11066                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
11067                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
11068                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
11069                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
11070                         | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
11071                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
11072                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
11073                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
11074                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
11075                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
11076                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
11077                         | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
11078                         |  0 ) & RegMask); */
11079                 PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
11080         /*############################################################################################################################ */
11081
11082                 /*Register : DX8SL2IOCR @ 0XFD0814B0</p>
11083
11084                 Reserved. Return zeroes on reads.
11085                 PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
11086
11087                 PVREF_DAC REFSEL range select
11088                 PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
11089
11090                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11091                 PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
11092
11093                 DX IO Mode
11094                 PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
11095
11096                 DX IO Transmitter Mode
11097                 PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
11098
11099                 DX IO Receiver Mode
11100                 PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
11101
11102                 DATX8 0-1 I/O Configuration Register
11103                 (OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)
11104                 RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK |  0 );
11105
11106                 RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
11107                         | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
11108                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
11109                         | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
11110                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
11111                         | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
11112                         |  0 ) & RegMask); */
11113                 PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11114         /*############################################################################################################################ */
11115
11116                 /*Register : DX8SL3DQSCTL @ 0XFD0814DC</p>
11117
11118                 Reserved. Return zeroes on reads.
11119                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
11120
11121                 Read Path Rise-to-Rise Mode
11122                 PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
11123
11124                 Reserved. Return zeroes on reads.
11125                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
11126
11127                 Write Path Rise-to-Rise Mode
11128                 PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
11129
11130                 DQS Gate Extension
11131                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
11132
11133                 Low Power PLL Power Down
11134                 PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
11135
11136                 Low Power I/O Power Down
11137                 PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
11138
11139                 Reserved. Return zeroes on reads.
11140                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
11141
11142                 QS Counter Enable
11143                 PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
11144
11145                 Unused DQ I/O Mode
11146                 PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
11147
11148                 Reserved. Return zeroes on reads.
11149                 PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
11150
11151                 Data Slew Rate
11152                 PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
11153
11154                 DQS_N Resistor
11155                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0xc
11156
11157                 DQS Resistor
11158                 PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x4
11159
11160                 DATX8 0-1 DQS Control Register
11161                 (OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)
11162                 RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK |  0 );
11163
11164                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
11165                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
11166                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
11167                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
11168                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
11169                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
11170                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
11171                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
11172                         | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
11173                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
11174                         | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
11175                         | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
11176                         | 0x0000000CU << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
11177                         | 0x00000004U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
11178                         |  0 ) & RegMask); */
11179                 PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11180         /*############################################################################################################################ */
11181
11182                 /*Register : DX8SL3DXCTL2 @ 0XFD0814EC</p>
11183
11184                 Reserved. Return zeroes on reads.
11185                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
11186
11187                 Configurable Read Data Enable
11188                 PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
11189
11190                 OX Extension during Post-amble
11191                 PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
11192
11193                 OE Extension during Pre-amble
11194                 PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x0
11195
11196                 Reserved. Return zeroes on reads.
11197                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
11198
11199                 I/O Assisted Gate Select
11200                 PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
11201
11202                 I/O Loopback Select
11203                 PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
11204
11205                 Reserved. Return zeroes on reads.
11206                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
11207
11208                 Low Power Wakeup Threshold
11209                 PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
11210
11211                 Read Data Bus Inversion Enable
11212                 PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
11213
11214                 Write Data Bus Inversion Enable
11215                 PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
11216
11217                 PUB Read FIFO Bypass
11218                 PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
11219
11220                 DATX8 Receive FIFO Read Mode
11221                 PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
11222
11223                 Disables the Read FIFO Reset
11224                 PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
11225
11226                 Read DQS Gate I/O Loopback
11227                 PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
11228
11229                 Reserved. Return zeroes on reads.
11230                 PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
11231
11232                 DATX8 0-1 DX Control Register 2
11233                 (OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)
11234                 RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK |  0 );
11235
11236                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
11237                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
11238                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
11239                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
11240                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
11241                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
11242                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
11243                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
11244                         | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
11245                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
11246                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
11247                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
11248                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
11249                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
11250                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
11251                         | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
11252                         |  0 ) & RegMask); */
11253                 PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
11254         /*############################################################################################################################ */
11255
11256                 /*Register : DX8SL3IOCR @ 0XFD0814F0</p>
11257
11258                 Reserved. Return zeroes on reads.
11259                 PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
11260
11261                 PVREF_DAC REFSEL range select
11262                 PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
11263
11264                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11265                 PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
11266
11267                 DX IO Mode
11268                 PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
11269
11270                 DX IO Transmitter Mode
11271                 PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
11272
11273                 DX IO Receiver Mode
11274                 PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
11275
11276                 DATX8 0-1 I/O Configuration Register
11277                 (OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)
11278                 RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK |  0 );
11279
11280                 RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
11281                         | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
11282                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
11283                         | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
11284                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
11285                         | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
11286                         |  0 ) & RegMask); */
11287                 PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11288         /*############################################################################################################################ */
11289
11290                 /*Register : DX8SL4DQSCTL @ 0XFD08151C</p>
11291
11292                 Reserved. Return zeroes on reads.
11293                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
11294
11295                 Read Path Rise-to-Rise Mode
11296                 PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
11297
11298                 Reserved. Return zeroes on reads.
11299                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
11300
11301                 Write Path Rise-to-Rise Mode
11302                 PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
11303
11304                 DQS Gate Extension
11305                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
11306
11307                 Low Power PLL Power Down
11308                 PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
11309
11310                 Low Power I/O Power Down
11311                 PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
11312
11313                 Reserved. Return zeroes on reads.
11314                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
11315
11316                 QS Counter Enable
11317                 PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
11318
11319                 Unused DQ I/O Mode
11320                 PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
11321
11322                 Reserved. Return zeroes on reads.
11323                 PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
11324
11325                 Data Slew Rate
11326                 PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
11327
11328                 DQS_N Resistor
11329                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0xc
11330
11331                 DQS Resistor
11332                 PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x4
11333
11334                 DATX8 0-1 DQS Control Register
11335                 (OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)
11336                 RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK |  0 );
11337
11338                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
11339                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
11340                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
11341                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
11342                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
11343                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
11344                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
11345                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
11346                         | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
11347                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
11348                         | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
11349                         | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
11350                         | 0x0000000CU << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
11351                         | 0x00000004U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
11352                         |  0 ) & RegMask); */
11353                 PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11354         /*############################################################################################################################ */
11355
11356                 /*Register : DX8SL4DXCTL2 @ 0XFD08152C</p>
11357
11358                 Reserved. Return zeroes on reads.
11359                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
11360
11361                 Configurable Read Data Enable
11362                 PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
11363
11364                 OX Extension during Post-amble
11365                 PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
11366
11367                 OE Extension during Pre-amble
11368                 PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x0
11369
11370                 Reserved. Return zeroes on reads.
11371                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
11372
11373                 I/O Assisted Gate Select
11374                 PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
11375
11376                 I/O Loopback Select
11377                 PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
11378
11379                 Reserved. Return zeroes on reads.
11380                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
11381
11382                 Low Power Wakeup Threshold
11383                 PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
11384
11385                 Read Data Bus Inversion Enable
11386                 PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
11387
11388                 Write Data Bus Inversion Enable
11389                 PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
11390
11391                 PUB Read FIFO Bypass
11392                 PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
11393
11394                 DATX8 Receive FIFO Read Mode
11395                 PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
11396
11397                 Disables the Read FIFO Reset
11398                 PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
11399
11400                 Read DQS Gate I/O Loopback
11401                 PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
11402
11403                 Reserved. Return zeroes on reads.
11404                 PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
11405
11406                 DATX8 0-1 DX Control Register 2
11407                 (OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)
11408                 RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK |  0 );
11409
11410                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
11411                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
11412                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
11413                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
11414                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
11415                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
11416                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
11417                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
11418                         | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
11419                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
11420                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
11421                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
11422                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
11423                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
11424                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
11425                         | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
11426                         |  0 ) & RegMask); */
11427                 PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
11428         /*############################################################################################################################ */
11429
11430                 /*Register : DX8SL4IOCR @ 0XFD081530</p>
11431
11432                 Reserved. Return zeroes on reads.
11433                 PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
11434
11435                 PVREF_DAC REFSEL range select
11436                 PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
11437
11438                 IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
11439                 PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
11440
11441                 DX IO Mode
11442                 PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
11443
11444                 DX IO Transmitter Mode
11445                 PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
11446
11447                 DX IO Receiver Mode
11448                 PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
11449
11450                 DATX8 0-1 I/O Configuration Register
11451                 (OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)
11452                 RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK |  0 );
11453
11454                 RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
11455                         | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
11456                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
11457                         | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
11458                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
11459                         | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
11460                         |  0 ) & RegMask); */
11461                 PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
11462         /*############################################################################################################################ */
11463
11464                 /*Register : DX8SLbDQSCTL @ 0XFD0817DC</p>
11465
11466                 Reserved. Return zeroes on reads.
11467                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
11468
11469                 Read Path Rise-to-Rise Mode
11470                 PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
11471
11472                 Reserved. Return zeroes on reads.
11473                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
11474
11475                 Write Path Rise-to-Rise Mode
11476                 PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
11477
11478                 DQS Gate Extension
11479                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
11480
11481                 Low Power PLL Power Down
11482                 PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
11483
11484                 Low Power I/O Power Down
11485                 PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
11486
11487                 Reserved. Return zeroes on reads.
11488                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
11489
11490                 QS Counter Enable
11491                 PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
11492
11493                 Unused DQ I/O Mode
11494                 PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
11495
11496                 Reserved. Return zeroes on reads.
11497                 PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
11498
11499                 Data Slew Rate
11500                 PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
11501
11502                 DQS# Resistor
11503                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
11504
11505                 DQS Resistor
11506                 PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
11507
11508                 DATX8 0-8 DQS Control Register
11509                 (OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)
11510                 RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK |  0 );
11511
11512                 RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
11513                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
11514                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
11515                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
11516                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
11517                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
11518                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
11519                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
11520                         | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
11521                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
11522                         | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
11523                         | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
11524                         | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
11525                         | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
11526                         |  0 ) & RegMask); */
11527                 PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
11528         /*############################################################################################################################ */
11529
11530                 /*Register : PIR @ 0XFD080004</p>
11531
11532                 Reserved. Return zeroes on reads.
11533                 PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
11534
11535                 Impedance Calibration Bypass
11536                 PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
11537
11538                 Digital Delay Line (DDL) Calibration Pause
11539                 PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
11540
11541                 Reserved. Return zeroes on reads.
11542                 PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
11543
11544                 Write DQS2DQ Training
11545                 PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
11546
11547                 RDIMM Initialization
11548                 PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
11549
11550                 Controller DRAM Initialization
11551                 PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
11552
11553                 VREF Training
11554                 PSU_DDR_PHY_PIR_VREF                                                            0x0
11555
11556                 Static Read Training
11557                 PSU_DDR_PHY_PIR_SRD                                                             0x0
11558
11559                 Write Data Eye Training
11560                 PSU_DDR_PHY_PIR_WREYE                                                           0x0
11561
11562                 Read Data Eye Training
11563                 PSU_DDR_PHY_PIR_RDEYE                                                           0x0
11564
11565                 Write Data Bit Deskew
11566                 PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
11567
11568                 Read Data Bit Deskew
11569                 PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
11570
11571                 Write Leveling Adjust
11572                 PSU_DDR_PHY_PIR_WLADJ                                                           0x0
11573
11574                 Read DQS Gate Training
11575                 PSU_DDR_PHY_PIR_QSGATE                                                          0x0
11576
11577                 Write Leveling
11578                 PSU_DDR_PHY_PIR_WL                                                              0x0
11579
11580                 DRAM Initialization
11581                 PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
11582
11583                 DRAM Reset (DDR3/DDR4/LPDDR4 Only)
11584                 PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
11585
11586                 PHY Reset
11587                 PSU_DDR_PHY_PIR_PHYRST                                                          0x1
11588
11589                 Digital Delay Line (DDL) Calibration
11590                 PSU_DDR_PHY_PIR_DCAL                                                            0x1
11591
11592                 PLL Initialiazation
11593                 PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
11594
11595                 Reserved. Return zeroes on reads.
11596                 PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
11597
11598                 CA Training
11599                 PSU_DDR_PHY_PIR_CA                                                              0x0
11600
11601                 Impedance Calibration
11602                 PSU_DDR_PHY_PIR_ZCAL                                                            0x1
11603
11604                 Initialization Trigger
11605                 PSU_DDR_PHY_PIR_INIT                                                            0x1
11606
11607                 PHY Initialization Register
11608                 (OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)
11609                 RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK |  0 );
11610
11611                 RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT
11612                         | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT
11613                         | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT
11614                         | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT
11615                         | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT
11616                         | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT
11617                         | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT
11618                         | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT
11619                         | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT
11620                         | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT
11621                         | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT
11622                         | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT
11623                         | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT
11624                         | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT
11625                         | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT
11626                         | 0x00000000U << DDR_PHY_PIR_WL_SHIFT
11627                         | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT
11628                         | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT
11629                         | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT
11630                         | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT
11631                         | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT
11632                         | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT
11633                         | 0x00000000U << DDR_PHY_PIR_CA_SHIFT
11634                         | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT
11635                         | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT
11636                         |  0 ) & RegMask); */
11637                 PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U);
11638         /*############################################################################################################################ */
11639
11640
11641   return 1;
11642 }
11643 unsigned long psu_mio_init_data() {
11644                 // : MIO PROGRAMMING
11645                 /*Register : MIO_PIN_0 @ 0XFF180000</p>
11646
11647                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
11648                 PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
11649
11650                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11651                 PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
11652
11653                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
11654                 t, test_scan_out[0]- (Test Scan Port) 3= Not Used
11655                 PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
11656
11657                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
11658                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
11659                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
11660                 ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
11661                 lk- (Trace Port Clock)
11662                 PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
11663
11664                 Configures MIO Pin 0 peripheral interface mapping. S
11665                 (OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)
11666                 RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
11667
11668                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
11669                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
11670                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
11671                         | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
11672                         |  0 ) & RegMask); */
11673                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U);
11674         /*############################################################################################################################ */
11675
11676                 /*Register : MIO_PIN_1 @ 0XFF180004</p>
11677
11678                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
11679                 us)
11680                 PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
11681
11682                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11683                 PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
11684
11685                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
11686                 t, test_scan_out[1]- (Test Scan Port) 3= Not Used
11687                 PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
11688
11689                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
11690                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
11691                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
11692                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
11693                 Signal)
11694                 PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
11695
11696                 Configures MIO Pin 1 peripheral interface mapping
11697                 (OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)
11698                 RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
11699
11700                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
11701                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
11702                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
11703                         | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
11704                         |  0 ) & RegMask); */
11705                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U);
11706         /*############################################################################################################################ */
11707
11708                 /*Register : MIO_PIN_2 @ 0XFF180008</p>
11709
11710                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
11711                 PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
11712
11713                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11714                 PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
11715
11716                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
11717                 t, test_scan_out[2]- (Test Scan Port) 3= Not Used
11718                 PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
11719
11720                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
11721                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
11722                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
11723                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
11724                 PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
11725
11726                 Configures MIO Pin 2 peripheral interface mapping
11727                 (OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)
11728                 RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
11729
11730                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
11731                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
11732                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
11733                         | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
11734                         |  0 ) & RegMask); */
11735                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U);
11736         /*############################################################################################################################ */
11737
11738                 /*Register : MIO_PIN_3 @ 0XFF18000C</p>
11739
11740                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
11741                 PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
11742
11743                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11744                 PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
11745
11746                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
11747                 t, test_scan_out[3]- (Test Scan Port) 3= Not Used
11748                 PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
11749
11750                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
11751                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
11752                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
11753                 - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
11754                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
11755                 PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
11756
11757                 Configures MIO Pin 3 peripheral interface mapping
11758                 (OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)
11759                 RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
11760
11761                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
11762                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
11763                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
11764                         | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
11765                         |  0 ) & RegMask); */
11766                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U);
11767         /*############################################################################################################################ */
11768
11769                 /*Register : MIO_PIN_4 @ 0XFF180010</p>
11770
11771                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
11772                 us)
11773                 PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
11774
11775                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11776                 PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
11777
11778                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
11779                 t, test_scan_out[4]- (Test Scan Port) 3= Not Used
11780                 PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
11781
11782                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
11783                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
11784                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
11785                 - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
11786                 utput, tracedq[2]- (Trace Port Databus)
11787                 PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
11788
11789                 Configures MIO Pin 4 peripheral interface mapping
11790                 (OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)
11791                 RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
11792
11793                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
11794                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
11795                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
11796                         | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
11797                         |  0 ) & RegMask); */
11798                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U);
11799         /*############################################################################################################################ */
11800
11801                 /*Register : MIO_PIN_5 @ 0XFF180014</p>
11802
11803                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
11804                 PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
11805
11806                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11807                 PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
11808
11809                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
11810                 t, test_scan_out[5]- (Test Scan Port) 3= Not Used
11811                 PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
11812
11813                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
11814                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
11815                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
11816                 si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
11817                  trace, Output, tracedq[3]- (Trace Port Databus)
11818                 PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
11819
11820                 Configures MIO Pin 5 peripheral interface mapping
11821                 (OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)
11822                 RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
11823
11824                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
11825                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
11826                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
11827                         | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
11828                         |  0 ) & RegMask); */
11829                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U);
11830         /*############################################################################################################################ */
11831
11832                 /*Register : MIO_PIN_6 @ 0XFF180018</p>
11833
11834                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
11835                 PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
11836
11837                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11838                 PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
11839
11840                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
11841                 t, test_scan_out[6]- (Test Scan Port) 3= Not Used
11842                 PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
11843
11844                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
11845                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
11846                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
11847                 sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
11848                 Output, tracedq[4]- (Trace Port Databus)
11849                 PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
11850
11851                 Configures MIO Pin 6 peripheral interface mapping
11852                 (OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)
11853                 RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
11854
11855                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
11856                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
11857                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
11858                         | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
11859                         |  0 ) & RegMask); */
11860                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U);
11861         /*############################################################################################################################ */
11862
11863                 /*Register : MIO_PIN_7 @ 0XFF18001C</p>
11864
11865                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
11866                 PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
11867
11868                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11869                 PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
11870
11871                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
11872                 t, test_scan_out[7]- (Test Scan Port) 3= Not Used
11873                 PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
11874
11875                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
11876                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
11877                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
11878                 tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output,
11879                 racedq[5]- (Trace Port Databus)
11880                 PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
11881
11882                 Configures MIO Pin 7 peripheral interface mapping
11883                 (OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)
11884                 RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
11885
11886                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
11887                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
11888                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
11889                         | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
11890                         |  0 ) & RegMask); */
11891                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U);
11892         /*############################################################################################################################ */
11893
11894                 /*Register : MIO_PIN_8 @ 0XFF180020</p>
11895
11896                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
11897                 [0]- (QSPI Upper Databus)
11898                 PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
11899
11900                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
11901                 PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
11902
11903                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
11904                 t, test_scan_out[8]- (Test Scan Port) 3= Not Used
11905                 PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
11906
11907                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
11908                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
11909                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
11910                 , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
11911                 ce Port Databus)
11912                 PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
11913
11914                 Configures MIO Pin 8 peripheral interface mapping
11915                 (OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)
11916                 RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
11917
11918                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
11919                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
11920                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
11921                         | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
11922                         |  0 ) & RegMask); */
11923                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U);
11924         /*############################################################################################################################ */
11925
11926                 /*Register : MIO_PIN_9 @ 0XFF180024</p>
11927
11928                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
11929                 [1]- (QSPI Upper Databus)
11930                 PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
11931
11932                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
11933                 PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
11934
11935                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
11936                 t, test_scan_out[9]- (Test Scan Port) 3= Not Used
11937                 PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
11938
11939                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
11940                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
11941                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
11942                 utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
11943                 RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
11944                 PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
11945
11946                 Configures MIO Pin 9 peripheral interface mapping
11947                 (OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)
11948                 RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
11949
11950                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
11951                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
11952                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
11953                         | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
11954                         |  0 ) & RegMask); */
11955                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U);
11956         /*############################################################################################################################ */
11957
11958                 /*Register : MIO_PIN_10 @ 0XFF180028</p>
11959
11960                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
11961                 [2]- (QSPI Upper Databus)
11962                 PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
11963
11964                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
11965                 PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
11966
11967                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
11968                 ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
11969                 PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
11970
11971                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
11972                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
11973                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
11974                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
11975                 t, tracedq[8]- (Trace Port Databus)
11976                 PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
11977
11978                 Configures MIO Pin 10 peripheral interface mapping
11979                 (OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)
11980                 RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
11981
11982                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
11983                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
11984                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
11985                         | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
11986                         |  0 ) & RegMask); */
11987                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U);
11988         /*############################################################################################################################ */
11989
11990                 /*Register : MIO_PIN_11 @ 0XFF18002C</p>
11991
11992                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
11993                 [3]- (QSPI Upper Databus)
11994                 PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
11995
11996                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
11997                 PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
11998
11999                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
12000                 ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
12001                 PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
12002
12003                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
12004                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12005                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12006                 i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12007                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12008                 PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
12009
12010                 Configures MIO Pin 11 peripheral interface mapping
12011                 (OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)
12012                 RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
12013
12014                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
12015                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
12016                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
12017                         | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
12018                         |  0 ) & RegMask); */
12019                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U);
12020         /*############################################################################################################################ */
12021
12022                 /*Register : MIO_PIN_12 @ 0XFF180030</p>
12023
12024                 Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
12025                 PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
12026
12027                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
12028
12029                 PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
12030
12031                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
12032                 ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
12033                 PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
12034
12035                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
12036                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12037                 al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
12038                 ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
12039                 dq[10]- (Trace Port Databus)
12040                 PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
12041
12042                 Configures MIO Pin 12 peripheral interface mapping
12043                 (OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)
12044                 RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
12045
12046                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
12047                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
12048                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
12049                         | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
12050                         |  0 ) & RegMask); */
12051                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U);
12052         /*############################################################################################################################ */
12053
12054                 /*Register : MIO_PIN_13 @ 0XFF180034</p>
12055
12056                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12057                 PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
12058
12059                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
12060                 PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
12061
12062                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
12063                 bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
12064                  3= Not Used
12065                 PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
12066
12067                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
12068                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12069                 l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
12070                 out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
12071                 bus)
12072                 PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
12073
12074                 Configures MIO Pin 13 peripheral interface mapping
12075                 (OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)
12076                 RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
12077
12078                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
12079                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
12080                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
12081                         | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
12082                         |  0 ) & RegMask); */
12083                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U);
12084         /*############################################################################################################################ */
12085
12086                 /*Register : MIO_PIN_14 @ 0XFF180038</p>
12087
12088                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12089                 PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
12090
12091                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
12092                 PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
12093
12094                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
12095                 bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
12096                  3= Not Used
12097                 PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
12098
12099                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
12100                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12101                 l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
12102                 n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
12103                 PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
12104
12105                 Configures MIO Pin 14 peripheral interface mapping
12106                 (OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)
12107                 RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
12108
12109                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
12110                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
12111                         | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
12112                         | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
12113                         |  0 ) & RegMask); */
12114                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U);
12115         /*############################################################################################################################ */
12116
12117                 /*Register : MIO_PIN_15 @ 0XFF18003C</p>
12118
12119                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12120                 PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
12121
12122                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
12123                 PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
12124
12125                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
12126                 bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
12127                  3= Not Used
12128                 PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
12129
12130                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
12131                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12132                 al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
12133                 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
12134                 l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
12135                 PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
12136
12137                 Configures MIO Pin 15 peripheral interface mapping
12138                 (OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)
12139                 RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
12140
12141                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
12142                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
12143                         | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
12144                         | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
12145                         |  0 ) & RegMask); */
12146                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U);
12147         /*############################################################################################################################ */
12148
12149                 /*Register : MIO_PIN_16 @ 0XFF180040</p>
12150
12151                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12152                 PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
12153
12154                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND
12155                 ata Bus)
12156                 PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
12157
12158                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
12159                 bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
12160                  3= Not Used
12161                 PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
12162
12163                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
12164                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12165                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
12166                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
12167                  Output, tracedq[14]- (Trace Port Databus)
12168                 PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
12169
12170                 Configures MIO Pin 16 peripheral interface mapping
12171                 (OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)
12172                 RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
12173
12174                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
12175                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
12176                         | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
12177                         | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
12178                         |  0 ) & RegMask); */
12179                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U);
12180         /*############################################################################################################################ */
12181
12182                 /*Register : MIO_PIN_17 @ 0XFF180044</p>
12183
12184                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12185                 PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
12186
12187                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND
12188                 ata Bus)
12189                 PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
12190
12191                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
12192                 bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
12193                  3= Not Used
12194                 PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
12195
12196                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
12197                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12198                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
12199                 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12200                 7= trace, Output, tracedq[15]- (Trace Port Databus)
12201                 PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
12202
12203                 Configures MIO Pin 17 peripheral interface mapping
12204                 (OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)
12205                 RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
12206
12207                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
12208                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
12209                         | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
12210                         | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
12211                         |  0 ) & RegMask); */
12212                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U);
12213         /*############################################################################################################################ */
12214
12215                 /*Register : MIO_PIN_18 @ 0XFF180048</p>
12216
12217                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12218                 PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
12219
12220                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND
12221                 ata Bus)
12222                 PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
12223
12224                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
12225                 bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
12226                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12227                 PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
12228
12229                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
12230                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12231                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
12232                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
12233                 PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
12234
12235                 Configures MIO Pin 18 peripheral interface mapping
12236                 (OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)
12237                 RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
12238
12239                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
12240                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
12241                         | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
12242                         | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
12243                         |  0 ) & RegMask); */
12244                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U);
12245         /*############################################################################################################################ */
12246
12247                 /*Register : MIO_PIN_19 @ 0XFF18004C</p>
12248
12249                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12250                 PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
12251
12252                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND
12253                 ata Bus)
12254                 PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
12255
12256                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
12257                 bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
12258                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12259                 PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
12260
12261                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
12262                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12263                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
12264                  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
12265                 PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
12266
12267                 Configures MIO Pin 19 peripheral interface mapping
12268                 (OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)
12269                 RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
12270
12271                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
12272                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
12273                         | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
12274                         | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
12275                         |  0 ) & RegMask); */
12276                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U);
12277         /*############################################################################################################################ */
12278
12279                 /*Register : MIO_PIN_20 @ 0XFF180050</p>
12280
12281                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12282                 PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
12283
12284                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND
12285                 ata Bus)
12286                 PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
12287
12288                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
12289                 bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
12290                  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12291                 PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
12292
12293                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
12294                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12295                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
12296                 c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12297                 PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
12298
12299                 Configures MIO Pin 20 peripheral interface mapping
12300                 (OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)
12301                 RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
12302
12303                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
12304                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
12305                         | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
12306                         | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
12307                         |  0 ) & RegMask); */
12308                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U);
12309         /*############################################################################################################################ */
12310
12311                 /*Register : MIO_PIN_21 @ 0XFF180054</p>
12312
12313                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12314                 PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
12315
12316                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND
12317                 ata Bus)
12318                 PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
12319
12320                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
12321                  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port)
12322                 = csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12323                 PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
12324
12325                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
12326                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12327                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
12328                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd-
12329                 UART receiver serial input) 7= Not Used
12330                 PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
12331
12332                 Configures MIO Pin 21 peripheral interface mapping
12333                 (OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)
12334                 RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
12335
12336                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
12337                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
12338                         | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
12339                         | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
12340                         |  0 ) & RegMask); */
12341                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U);
12342         /*############################################################################################################################ */
12343
12344                 /*Register : MIO_PIN_22 @ 0XFF180058</p>
12345
12346                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12347                 PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
12348
12349                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
12350                 PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
12351
12352                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
12353                 (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12354                 PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
12355
12356                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
12357                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12358                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
12359                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
12360                 sed
12361                 PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
12362
12363                 Configures MIO Pin 22 peripheral interface mapping
12364                 (OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)
12365                 RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
12366
12367                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
12368                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
12369                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
12370                         | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
12371                         |  0 ) & RegMask); */
12372                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U);
12373         /*############################################################################################################################ */
12374
12375                 /*Register : MIO_PIN_23 @ 0XFF18005C</p>
12376
12377                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12378                 PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
12379
12380                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND
12381                 ata Bus)
12382                 PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
12383
12384                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
12385                 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
12386
12387                 PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
12388
12389                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
12390                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12391                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
12392                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
12393                 tput) 7= Not Used
12394                 PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
12395
12396                 Configures MIO Pin 23 peripheral interface mapping
12397                 (OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)
12398                 RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
12399
12400                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
12401                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
12402                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
12403                         | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
12404                         |  0 ) & RegMask); */
12405                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U);
12406         /*############################################################################################################################ */
12407
12408                 /*Register : MIO_PIN_24 @ 0XFF180060</p>
12409
12410                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12411                 PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
12412
12413                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND
12414                 ata Bus)
12415                 PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
12416
12417                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
12418                 scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
12419                  Tamper)
12420                 PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
12421
12422                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
12423                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12424                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
12425                 Output, ua1_txd- (UART transmitter serial output) 7= Not Used
12426                 PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
12427
12428                 Configures MIO Pin 24 peripheral interface mapping
12429                 (OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)
12430                 RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
12431
12432                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
12433                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
12434                         | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
12435                         | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
12436                         |  0 ) & RegMask); */
12437                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U);
12438         /*############################################################################################################################ */
12439
12440                 /*Register : MIO_PIN_25 @ 0XFF180064</p>
12441
12442                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
12443                 PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
12444
12445                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
12446                 PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
12447
12448                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
12449                 test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
12450                 U Ext Tamper)
12451                 PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
12452
12453                 Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
12454                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12455                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform
12456                 lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
12457                 PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
12458
12459                 Configures MIO Pin 25 peripheral interface mapping
12460                 (OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)
12461                 RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
12462
12463                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
12464                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
12465                         | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
12466                         | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
12467                         |  0 ) & RegMask); */
12468                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U);
12469         /*############################################################################################################################ */
12470
12471                 /*Register : MIO_PIN_26 @ 0XFF180068</p>
12472
12473                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
12474                 PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
12475
12476                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
12477                 PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
12478
12479                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
12480                 n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12481                 PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  1
12482
12483                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
12484                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12485                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
12486                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
12487                 Trace Port Databus)
12488                 PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
12489
12490                 Configures MIO Pin 26 peripheral interface mapping
12491                 (OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000008U)
12492                 RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
12493
12494                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
12495                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
12496                         | 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
12497                         | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
12498                         |  0 ) & RegMask); */
12499                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
12500         /*############################################################################################################################ */
12501
12502                 /*Register : MIO_PIN_27 @ 0XFF18006C</p>
12503
12504                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
12505                 PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
12506
12507                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
12508                 PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
12509
12510                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
12511                 n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12512                 t, dp_aux_data_out- (Dp Aux Data)
12513                 PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
12514
12515                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
12516                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12517                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
12518                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
12519                 atabus)
12520                 PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
12521
12522                 Configures MIO Pin 27 peripheral interface mapping
12523                 (OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)
12524                 RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
12525
12526                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
12527                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
12528                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
12529                         | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
12530                         |  0 ) & RegMask); */
12531                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000000U);
12532         /*############################################################################################################################ */
12533
12534                 /*Register : MIO_PIN_28 @ 0XFF180070</p>
12535
12536                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
12537                 PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
12538
12539                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
12540                 PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
12541
12542                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
12543                 n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12544                 PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
12545
12546                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
12547                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12548                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
12549                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
12550                 PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
12551
12552                 Configures MIO Pin 28 peripheral interface mapping
12553                 (OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)
12554                 RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
12555
12556                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
12557                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
12558                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
12559                         | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
12560                         |  0 ) & RegMask); */
12561                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000000U);
12562         /*############################################################################################################################ */
12563
12564                 /*Register : MIO_PIN_29 @ 0XFF180074</p>
12565
12566                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
12567                 PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
12568
12569                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12570                 PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
12571
12572                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
12573                 n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
12574                 t, dp_aux_data_out- (Dp Aux Data)
12575                 PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
12576
12577                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
12578                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12579                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
12580                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
12581                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
12582                 PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
12583
12584                 Configures MIO Pin 29 peripheral interface mapping
12585                 (OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000000U)
12586                 RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
12587
12588                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
12589                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
12590                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
12591                         | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
12592                         |  0 ) & RegMask); */
12593                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000000U);
12594         /*############################################################################################################################ */
12595
12596                 /*Register : MIO_PIN_30 @ 0XFF180078</p>
12597
12598                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
12599                 PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
12600
12601                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12602                 PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
12603
12604                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
12605                 n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12606                 PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
12607
12608                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
12609                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12610                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
12611                  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
12612                  tracedq[8]- (Trace Port Databus)
12613                 PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
12614
12615                 Configures MIO Pin 30 peripheral interface mapping
12616                 (OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)
12617                 RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
12618
12619                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
12620                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
12621                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
12622                         | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
12623                         |  0 ) & RegMask); */
12624                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000000U);
12625         /*############################################################################################################################ */
12626
12627                 /*Register : MIO_PIN_31 @ 0XFF18007C</p>
12628
12629                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
12630                 PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
12631
12632                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12633                 PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
12634
12635                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
12636                 n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12637                 PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
12638
12639                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
12640                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12641                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
12642                 _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
12643                 ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
12644                 PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
12645
12646                 Configures MIO Pin 31 peripheral interface mapping
12647                 (OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)
12648                 RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
12649
12650                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
12651                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
12652                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
12653                         | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
12654                         |  0 ) & RegMask); */
12655                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U);
12656         /*############################################################################################################################ */
12657
12658                 /*Register : MIO_PIN_32 @ 0XFF180080</p>
12659
12660                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
12661                 PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
12662
12663                 Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
12664
12665                 PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
12666
12667                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
12668                 an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12669                 PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
12670
12671                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
12672                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
12673                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
12674                 _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
12675                 race, Output, tracedq[10]- (Trace Port Databus)
12676                 PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
12677
12678                 Configures MIO Pin 32 peripheral interface mapping
12679                 (OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)
12680                 RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
12681
12682                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
12683                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
12684                         | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
12685                         | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
12686                         |  0 ) & RegMask); */
12687                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U);
12688         /*############################################################################################################################ */
12689
12690                 /*Register : MIO_PIN_33 @ 0XFF180084</p>
12691
12692                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
12693                 PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
12694
12695                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12696                 PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
12697
12698                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
12699                 an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
12700                 PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
12701
12702                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
12703                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
12704                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
12705                 c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
12706                 [11]- (Trace Port Databus)
12707                 PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
12708
12709                 Configures MIO Pin 33 peripheral interface mapping
12710                 (OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)
12711                 RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
12712
12713                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
12714                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
12715                         | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
12716                         | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
12717                         |  0 ) & RegMask); */
12718                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U);
12719         /*############################################################################################################################ */
12720
12721                 /*Register : MIO_PIN_34 @ 0XFF180088</p>
12722
12723                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
12724                 PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
12725
12726                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12727                 PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
12728
12729                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
12730                 an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
12731                 ut, dp_aux_data_out- (Dp Aux Data)
12732                 PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
12733
12734                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
12735                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
12736                  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
12737                  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
12738                 rt Databus)
12739                 PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
12740
12741                 Configures MIO Pin 34 peripheral interface mapping
12742                 (OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)
12743                 RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
12744
12745                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
12746                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
12747                         | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
12748                         | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
12749                         |  0 ) & RegMask); */
12750                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U);
12751         /*############################################################################################################################ */
12752
12753                 /*Register : MIO_PIN_35 @ 0XFF18008C</p>
12754
12755                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
12756                 PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
12757
12758                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12759                 PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
12760
12761                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
12762                 an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12763                 PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
12764
12765                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
12766                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
12767                 ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
12768                 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
12769                 UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
12770                 PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
12771
12772                 Configures MIO Pin 35 peripheral interface mapping
12773                 (OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)
12774                 RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
12775
12776                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
12777                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
12778                         | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
12779                         | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
12780                         |  0 ) & RegMask); */
12781                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U);
12782         /*############################################################################################################################ */
12783
12784                 /*Register : MIO_PIN_36 @ 0XFF180090</p>
12785
12786                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
12787                 PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
12788
12789                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12790                 PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
12791
12792                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
12793                 an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
12794                 ut, dp_aux_data_out- (Dp Aux Data)
12795                 PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
12796
12797                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
12798                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12799                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
12800                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
12801                  Output, tracedq[14]- (Trace Port Databus)
12802                 PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
12803
12804                 Configures MIO Pin 36 peripheral interface mapping
12805                 (OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)
12806                 RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
12807
12808                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
12809                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
12810                         | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
12811                         | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
12812                         |  0 ) & RegMask); */
12813                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U);
12814         /*############################################################################################################################ */
12815
12816                 /*Register : MIO_PIN_37 @ 0XFF180094</p>
12817
12818                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
12819                 PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
12820
12821                 Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
12822                 PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
12823
12824                 Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
12825                 an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
12826                 PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
12827
12828                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
12829                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12830                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
12831                 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
12832                 7= trace, Output, tracedq[15]- (Trace Port Databus)
12833                 PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
12834
12835                 Configures MIO Pin 37 peripheral interface mapping
12836                 (OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)
12837                 RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
12838
12839                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
12840                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
12841                         | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
12842                         | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
12843                         |  0 ) & RegMask); */
12844                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U);
12845         /*############################################################################################################################ */
12846
12847                 /*Register : MIO_PIN_38 @ 0XFF180098</p>
12848
12849                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
12850                 PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
12851
12852                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12853                 PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
12854
12855                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
12856                 PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
12857
12858                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
12859                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12860                 l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
12861                 k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
12862                 (Trace Port Clock)
12863                 PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
12864
12865                 Configures MIO Pin 38 peripheral interface mapping
12866                 (OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)
12867                 RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
12868
12869                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
12870                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
12871                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
12872                         | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
12873                         |  0 ) & RegMask); */
12874                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U);
12875         /*############################################################################################################################ */
12876
12877                 /*Register : MIO_PIN_39 @ 0XFF18009C</p>
12878
12879                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
12880                 PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
12881
12882                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12883                 PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
12884
12885                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
12886                 [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
12887                 PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
12888
12889                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
12890                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
12891                 al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
12892                 _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
12893                 Control Signal)
12894                 PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
12895
12896                 Configures MIO Pin 39 peripheral interface mapping
12897                 (OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)
12898                 RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
12899
12900                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
12901                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
12902                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
12903                         | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
12904                         |  0 ) & RegMask); */
12905                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U);
12906         /*############################################################################################################################ */
12907
12908                 /*Register : MIO_PIN_40 @ 0XFF1800A0</p>
12909
12910                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
12911                 PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
12912
12913                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12914                 PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
12915
12916                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
12917                  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
12918                 PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
12919
12920                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
12921                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
12922                 al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
12923                 in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
12924                 PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
12925
12926                 Configures MIO Pin 40 peripheral interface mapping
12927                 (OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)
12928                 RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
12929
12930                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
12931                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
12932                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
12933                         | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
12934                         |  0 ) & RegMask); */
12935                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U);
12936         /*############################################################################################################################ */
12937
12938                 /*Register : MIO_PIN_41 @ 0XFF1800A4</p>
12939
12940                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
12941                 PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
12942
12943                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12944                 PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
12945
12946                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
12947                 bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
12948                 PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
12949
12950                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
12951                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
12952                 l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
12953                 ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
12954                 ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
12955                 PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
12956
12957                 Configures MIO Pin 41 peripheral interface mapping
12958                 (OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)
12959                 RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
12960
12961                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
12962                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
12963                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
12964                         | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
12965                         |  0 ) & RegMask); */
12966                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U);
12967         /*############################################################################################################################ */
12968
12969                 /*Register : MIO_PIN_42 @ 0XFF1800A8</p>
12970
12971                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
12972                 PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
12973
12974                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
12975                 PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
12976
12977                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
12978                 bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
12979                 PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
12980
12981                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
12982                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
12983                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
12984                 o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
12985                 t, tracedq[2]- (Trace Port Databus)
12986                 PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
12987
12988                 Configures MIO Pin 42 peripheral interface mapping
12989                 (OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)
12990                 RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
12991
12992                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
12993                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
12994                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
12995                         | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
12996                         |  0 ) & RegMask); */
12997                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U);
12998         /*############################################################################################################################ */
12999
13000                 /*Register : MIO_PIN_43 @ 0XFF1800AC</p>
13001
13002                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
13003                 PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
13004
13005                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13006                 PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
13007
13008                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
13009                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
13010                 PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
13011
13012                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
13013                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13014                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
13015                 i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13016                 tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
13017                 PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
13018
13019                 Configures MIO Pin 43 peripheral interface mapping
13020                 (OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)
13021                 RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
13022
13023                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
13024                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
13025                         | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
13026                         | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
13027                         |  0 ) & RegMask); */
13028                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U);
13029         /*############################################################################################################################ */
13030
13031                 /*Register : MIO_PIN_44 @ 0XFF1800B0</p>
13032
13033                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
13034                 PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
13035
13036                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13037                 PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
13038
13039                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
13040                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
13041                 PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
13042
13043                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
13044                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13045                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
13046                 i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
13047                  Not Used
13048                 PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
13049
13050                 Configures MIO Pin 44 peripheral interface mapping
13051                 (OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)
13052                 RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
13053
13054                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
13055                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
13056                         | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
13057                         | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
13058                         |  0 ) & RegMask); */
13059                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U);
13060         /*############################################################################################################################ */
13061
13062                 /*Register : MIO_PIN_45 @ 0XFF1800B4</p>
13063
13064                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
13065                 PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
13066
13067                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13068                 PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
13069
13070                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
13071                 bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
13072                 PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
13073
13074                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
13075                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13076                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
13077                 ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13078                 PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
13079
13080                 Configures MIO Pin 45 peripheral interface mapping
13081                 (OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)
13082                 RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
13083
13084                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
13085                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
13086                         | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
13087                         | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
13088                         |  0 ) & RegMask); */
13089                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U);
13090         /*############################################################################################################################ */
13091
13092                 /*Register : MIO_PIN_46 @ 0XFF1800B8</p>
13093
13094                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
13095                 PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
13096
13097                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13098                 PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
13099
13100                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
13101                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
13102                 PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
13103
13104                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
13105                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13106                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
13107                 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13108                 PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
13109
13110                 Configures MIO Pin 46 peripheral interface mapping
13111                 (OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)
13112                 RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
13113
13114                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
13115                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
13116                         | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
13117                         | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
13118                         |  0 ) & RegMask); */
13119                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U);
13120         /*############################################################################################################################ */
13121
13122                 /*Register : MIO_PIN_47 @ 0XFF1800BC</p>
13123
13124                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
13125                 PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
13126
13127                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13128                 PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
13129
13130                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
13131                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
13132                 PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
13133
13134                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
13135                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13136                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
13137                 , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
13138                  (UART transmitter serial output) 7= Not Used
13139                 PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
13140
13141                 Configures MIO Pin 47 peripheral interface mapping
13142                 (OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)
13143                 RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
13144
13145                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
13146                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
13147                         | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
13148                         | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
13149                         |  0 ) & RegMask); */
13150                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U);
13151         /*############################################################################################################################ */
13152
13153                 /*Register : MIO_PIN_48 @ 0XFF1800C0</p>
13154
13155                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
13156                 PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
13157
13158                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13159                 PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
13160
13161                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
13162                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
13163                 PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
13164
13165                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
13166                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13167                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
13168                 so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
13169                 ed
13170                 PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
13171
13172                 Configures MIO Pin 48 peripheral interface mapping
13173                 (OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)
13174                 RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
13175
13176                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
13177                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
13178                         | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
13179                         | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
13180                         |  0 ) & RegMask); */
13181                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U);
13182         /*############################################################################################################################ */
13183
13184                 /*Register : MIO_PIN_49 @ 0XFF1800C4</p>
13185
13186                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
13187                 PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
13188
13189                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13190                 PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
13191
13192                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
13193                 bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
13194                 PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
13195
13196                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
13197                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13198                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
13199                 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13200                 7= Not Used
13201                 PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
13202
13203                 Configures MIO Pin 49 peripheral interface mapping
13204                 (OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)
13205                 RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
13206
13207                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
13208                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
13209                         | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
13210                         | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
13211                         |  0 ) & RegMask); */
13212                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U);
13213         /*############################################################################################################################ */
13214
13215                 /*Register : MIO_PIN_50 @ 0XFF1800C8</p>
13216
13217                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13218                 PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
13219
13220                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13221                 PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
13222
13223                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
13224                 d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13225                 PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
13226
13227                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
13228                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13229                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
13230                 clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13231                 PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
13232
13233                 Configures MIO Pin 50 peripheral interface mapping
13234                 (OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)
13235                 RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
13236
13237                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
13238                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
13239                         | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
13240                         | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
13241                         |  0 ) & RegMask); */
13242                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U);
13243         /*############################################################################################################################ */
13244
13245                 /*Register : MIO_PIN_51 @ 0XFF1800CC</p>
13246
13247                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
13248                 PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
13249
13250                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
13251                 PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
13252
13253                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
13254                 PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
13255
13256                 Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
13257                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13258                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
13259                 t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
13260                 serial output) 7= Not Used
13261                 PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
13262
13263                 Configures MIO Pin 51 peripheral interface mapping
13264                 (OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)
13265                 RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
13266
13267                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
13268                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
13269                         | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
13270                         | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
13271                         |  0 ) & RegMask); */
13272                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U);
13273         /*############################################################################################################################ */
13274
13275                 /*Register : MIO_PIN_52 @ 0XFF1800D0</p>
13276
13277                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
13278                 PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
13279
13280                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
13281                 PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
13282
13283                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13284                 PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
13285
13286                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
13287                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13288                 ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
13289                 ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
13290                 lk- (Trace Port Clock)
13291                 PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
13292
13293                 Configures MIO Pin 52 peripheral interface mapping
13294                 (OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)
13295                 RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
13296
13297                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
13298                         | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
13299                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
13300                         | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
13301                         |  0 ) & RegMask); */
13302                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U);
13303         /*############################################################################################################################ */
13304
13305                 /*Register : MIO_PIN_53 @ 0XFF1800D4</p>
13306
13307                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
13308                 PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
13309
13310                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
13311                 PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
13312
13313                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13314                 PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
13315
13316                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
13317                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13318                  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
13319                 t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
13320                 Signal)
13321                 PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
13322
13323                 Configures MIO Pin 53 peripheral interface mapping
13324                 (OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)
13325                 RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
13326
13327                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
13328                         | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
13329                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
13330                         | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
13331                         |  0 ) & RegMask); */
13332                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U);
13333         /*############################################################################################################################ */
13334
13335                 /*Register : MIO_PIN_54 @ 0XFF1800D8</p>
13336
13337                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
13338                 PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
13339
13340                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13341                 ata[2]- (ULPI data bus)
13342                 PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
13343
13344                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13345                 PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
13346
13347                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
13348                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13349                  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
13350                  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
13351                 PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
13352
13353                 Configures MIO Pin 54 peripheral interface mapping
13354                 (OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)
13355                 RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
13356
13357                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
13358                         | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
13359                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
13360                         | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
13361                         |  0 ) & RegMask); */
13362                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U);
13363         /*############################################################################################################################ */
13364
13365                 /*Register : MIO_PIN_55 @ 0XFF1800DC</p>
13366
13367                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
13368                 PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
13369
13370                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
13371                 PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
13372
13373                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13374                 PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
13375
13376                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
13377                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13378                 ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
13379                 - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
13380                 output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
13381                 PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
13382
13383                 Configures MIO Pin 55 peripheral interface mapping
13384                 (OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)
13385                 RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
13386
13387                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
13388                         | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
13389                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
13390                         | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
13391                         |  0 ) & RegMask); */
13392                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U);
13393         /*############################################################################################################################ */
13394
13395                 /*Register : MIO_PIN_56 @ 0XFF1800E0</p>
13396
13397                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
13398                 PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
13399
13400                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13401                 ata[0]- (ULPI data bus)
13402                 PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
13403
13404                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13405                 PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
13406
13407                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
13408                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13409                 ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
13410                 - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
13411                 utput, tracedq[2]- (Trace Port Databus)
13412                 PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
13413
13414                 Configures MIO Pin 56 peripheral interface mapping
13415                 (OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)
13416                 RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
13417
13418                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
13419                         | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
13420                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
13421                         | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
13422                         |  0 ) & RegMask); */
13423                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U);
13424         /*############################################################################################################################ */
13425
13426                 /*Register : MIO_PIN_57 @ 0XFF1800E4</p>
13427
13428                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
13429                 PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
13430
13431                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13432                 ata[1]- (ULPI data bus)
13433                 PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
13434
13435                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13436                 PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
13437
13438                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
13439                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13440                  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
13441                 si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
13442                  trace, Output, tracedq[3]- (Trace Port Databus)
13443                 PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
13444
13445                 Configures MIO Pin 57 peripheral interface mapping
13446                 (OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)
13447                 RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
13448
13449                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
13450                         | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
13451                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
13452                         | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
13453                         |  0 ) & RegMask); */
13454                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U);
13455         /*############################################################################################################################ */
13456
13457                 /*Register : MIO_PIN_58 @ 0XFF1800E8</p>
13458
13459                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
13460                 PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
13461
13462                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
13463                 PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
13464
13465                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13466                 PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
13467
13468                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
13469                 , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
13470                  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
13471                  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]-
13472                 Trace Port Databus)
13473                 PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
13474
13475                 Configures MIO Pin 58 peripheral interface mapping
13476                 (OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)
13477                 RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
13478
13479                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
13480                         | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
13481                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
13482                         | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
13483                         |  0 ) & RegMask); */
13484                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U);
13485         /*############################################################################################################################ */
13486
13487                 /*Register : MIO_PIN_59 @ 0XFF1800EC</p>
13488
13489                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
13490                 PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
13491
13492                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13493                 ata[3]- (ULPI data bus)
13494                 PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
13495
13496                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13497                 PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
13498
13499                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
13500                 , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
13501                 ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
13502                 ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port
13503                 atabus)
13504                 PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
13505
13506                 Configures MIO Pin 59 peripheral interface mapping
13507                 (OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)
13508                 RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
13509
13510                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
13511                         | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
13512                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
13513                         | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
13514                         |  0 ) & RegMask); */
13515                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U);
13516         /*############################################################################################################################ */
13517
13518                 /*Register : MIO_PIN_60 @ 0XFF1800F0</p>
13519
13520                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
13521                 PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
13522
13523                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13524                 ata[4]- (ULPI data bus)
13525                 PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
13526
13527                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13528                 PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
13529
13530                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
13531                 , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
13532                 ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
13533                 - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
13534                 PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
13535
13536                 Configures MIO Pin 60 peripheral interface mapping
13537                 (OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)
13538                 RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
13539
13540                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
13541                         | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
13542                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
13543                         | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
13544                         |  0 ) & RegMask); */
13545                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U);
13546         /*############################################################################################################################ */
13547
13548                 /*Register : MIO_PIN_61 @ 0XFF1800F4</p>
13549
13550                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
13551                 PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
13552
13553                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13554                 ata[5]- (ULPI data bus)
13555                 PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
13556
13557                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13558                 PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
13559
13560                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
13561                 , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
13562                  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
13563                  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
13564                 ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
13565                 PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
13566
13567                 Configures MIO Pin 61 peripheral interface mapping
13568                 (OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)
13569                 RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
13570
13571                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
13572                         | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
13573                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
13574                         | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
13575                         |  0 ) & RegMask); */
13576                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U);
13577         /*############################################################################################################################ */
13578
13579                 /*Register : MIO_PIN_62 @ 0XFF1800F8</p>
13580
13581                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
13582                 PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
13583
13584                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13585                 ata[6]- (ULPI data bus)
13586                 PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
13587
13588                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13589                 PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
13590
13591                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
13592                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13593                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
13594                 o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
13595                 t, tracedq[8]- (Trace Port Databus)
13596                 PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
13597
13598                 Configures MIO Pin 62 peripheral interface mapping
13599                 (OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)
13600                 RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
13601
13602                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
13603                         | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
13604                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
13605                         | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
13606                         |  0 ) & RegMask); */
13607                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U);
13608         /*############################################################################################################################ */
13609
13610                 /*Register : MIO_PIN_63 @ 0XFF1800FC</p>
13611
13612                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
13613                 PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
13614
13615                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
13616                 ata[7]- (ULPI data bus)
13617                 PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
13618
13619                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
13620                 PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
13621
13622                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
13623                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13624                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
13625                 i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
13626                 tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
13627                 PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
13628
13629                 Configures MIO Pin 63 peripheral interface mapping
13630                 (OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)
13631                 RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
13632
13633                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
13634                         | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
13635                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
13636                         | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
13637                         |  0 ) & RegMask); */
13638                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U);
13639         /*############################################################################################################################ */
13640
13641                 /*Register : MIO_PIN_64 @ 0XFF180100</p>
13642
13643                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
13644                 PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
13645
13646                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
13647                 PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
13648
13649                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
13650                 PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
13651
13652                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
13653                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13654                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
13655                 i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
13656                  trace, Output, tracedq[10]- (Trace Port Databus)
13657                 PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
13658
13659                 Configures MIO Pin 64 peripheral interface mapping
13660                 (OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)
13661                 RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
13662
13663                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
13664                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
13665                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
13666                         | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
13667                         |  0 ) & RegMask); */
13668                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U);
13669         /*############################################################################################################################ */
13670
13671                 /*Register : MIO_PIN_65 @ 0XFF180104</p>
13672
13673                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
13674                 PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
13675
13676                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
13677                 PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
13678
13679                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
13680                 PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
13681
13682                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
13683                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13684                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
13685                 ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
13686                 dq[11]- (Trace Port Databus)
13687                 PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
13688
13689                 Configures MIO Pin 65 peripheral interface mapping
13690                 (OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)
13691                 RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
13692
13693                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
13694                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
13695                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
13696                         | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
13697                         |  0 ) & RegMask); */
13698                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U);
13699         /*############################################################################################################################ */
13700
13701                 /*Register : MIO_PIN_66 @ 0XFF180108</p>
13702
13703                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
13704                 PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
13705
13706                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13707                 ata[2]- (ULPI data bus)
13708                 PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
13709
13710                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
13711                  Indicator) 2= Not Used 3= Not Used
13712                 PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
13713
13714                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
13715                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13716                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
13717                 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
13718                 Port Databus)
13719                 PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
13720
13721                 Configures MIO Pin 66 peripheral interface mapping
13722                 (OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)
13723                 RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
13724
13725                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
13726                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
13727                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
13728                         | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
13729                         |  0 ) & RegMask); */
13730                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U);
13731         /*############################################################################################################################ */
13732
13733                 /*Register : MIO_PIN_67 @ 0XFF18010C</p>
13734
13735                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
13736                 PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
13737
13738                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
13739                 PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
13740
13741                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
13742                 bit Data bus) 2= Not Used 3= Not Used
13743                 PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
13744
13745                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
13746                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13747                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
13748                 , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
13749                  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
13750                 PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
13751
13752                 Configures MIO Pin 67 peripheral interface mapping
13753                 (OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)
13754                 RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
13755
13756                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
13757                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
13758                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
13759                         | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
13760                         |  0 ) & RegMask); */
13761                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U);
13762         /*############################################################################################################################ */
13763
13764                 /*Register : MIO_PIN_68 @ 0XFF180110</p>
13765
13766                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
13767                 PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
13768
13769                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13770                 ata[0]- (ULPI data bus)
13771                 PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
13772
13773                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
13774                 bit Data bus) 2= Not Used 3= Not Used
13775                 PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
13776
13777                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
13778                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13779                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
13780                 so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
13781                  Output, tracedq[14]- (Trace Port Databus)
13782                 PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
13783
13784                 Configures MIO Pin 68 peripheral interface mapping
13785                 (OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)
13786                 RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
13787
13788                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
13789                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
13790                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
13791                         | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
13792                         |  0 ) & RegMask); */
13793                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U);
13794         /*############################################################################################################################ */
13795
13796                 /*Register : MIO_PIN_69 @ 0XFF180114</p>
13797
13798                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
13799                 PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
13800
13801                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13802                 ata[1]- (ULPI data bus)
13803                 PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
13804
13805                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
13806                 bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
13807                 PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
13808
13809                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
13810                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13811                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
13812                 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
13813                 7= trace, Output, tracedq[15]- (Trace Port Databus)
13814                 PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
13815
13816                 Configures MIO Pin 69 peripheral interface mapping
13817                 (OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)
13818                 RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
13819
13820                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
13821                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
13822                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
13823                         | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
13824                         |  0 ) & RegMask); */
13825                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U);
13826         /*############################################################################################################################ */
13827
13828                 /*Register : MIO_PIN_70 @ 0XFF180118</p>
13829
13830                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
13831                 PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
13832
13833                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
13834                 PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
13835
13836                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
13837                 bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
13838                 PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
13839
13840                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
13841                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13842                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
13843                 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not
13844                 sed
13845                 PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
13846
13847                 Configures MIO Pin 70 peripheral interface mapping
13848                 (OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)
13849                 RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
13850
13851                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
13852                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
13853                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
13854                         | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
13855                         |  0 ) & RegMask); */
13856                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U);
13857         /*############################################################################################################################ */
13858
13859                 /*Register : MIO_PIN_71 @ 0XFF18011C</p>
13860
13861                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
13862                 PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
13863
13864                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13865                 ata[3]- (ULPI data bus)
13866                 PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
13867
13868                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
13869                 bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
13870                 PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
13871
13872                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
13873                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13874                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
13875                  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
13876                 PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
13877
13878                 Configures MIO Pin 71 peripheral interface mapping
13879                 (OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)
13880                 RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
13881
13882                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
13883                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
13884                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
13885                         | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
13886                         |  0 ) & RegMask); */
13887                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U);
13888         /*############################################################################################################################ */
13889
13890                 /*Register : MIO_PIN_72 @ 0XFF180120</p>
13891
13892                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
13893                 PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
13894
13895                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13896                 ata[4]- (ULPI data bus)
13897                 PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
13898
13899                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
13900                 bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
13901                 PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
13902
13903                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
13904                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
13905                 al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
13906                 t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
13907                 PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
13908
13909                 Configures MIO Pin 72 peripheral interface mapping
13910                 (OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)
13911                 RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
13912
13913                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
13914                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
13915                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
13916                         | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
13917                         |  0 ) & RegMask); */
13918                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U);
13919         /*############################################################################################################################ */
13920
13921                 /*Register : MIO_PIN_73 @ 0XFF180124</p>
13922
13923                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
13924                 PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
13925
13926                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13927                 ata[5]- (ULPI data bus)
13928                 PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
13929
13930                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
13931                 bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
13932                 PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
13933
13934                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
13935                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
13936                 l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
13937                  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
13938                 PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
13939
13940                 Configures MIO Pin 73 peripheral interface mapping
13941                 (OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)
13942                 RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
13943
13944                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
13945                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
13946                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
13947                         | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
13948                         |  0 ) & RegMask); */
13949                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U);
13950         /*############################################################################################################################ */
13951
13952                 /*Register : MIO_PIN_74 @ 0XFF180128</p>
13953
13954                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
13955                 PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
13956
13957                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13958                 ata[6]- (ULPI data bus)
13959                 PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
13960
13961                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
13962                 bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
13963                 PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
13964
13965                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
13966                 n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
13967                 l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
13968                 o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
13969                 PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
13970
13971                 Configures MIO Pin 74 peripheral interface mapping
13972                 (OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)
13973                 RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
13974
13975                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
13976                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
13977                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
13978                         | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
13979                         |  0 ) & RegMask); */
13980                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U);
13981         /*############################################################################################################################ */
13982
13983                 /*Register : MIO_PIN_75 @ 0XFF18012C</p>
13984
13985                 Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
13986                 PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
13987
13988                 Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
13989                 ata[7]- (ULPI data bus)
13990                 PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
13991
13992                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
13993                 d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
13994                 PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
13995
13996                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
13997                 n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
13998                 al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
13999                 i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
14000                 PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
14001
14002                 Configures MIO Pin 75 peripheral interface mapping
14003                 (OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)
14004                 RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
14005
14006                 RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
14007                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
14008                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
14009                         | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
14010                         |  0 ) & RegMask); */
14011                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U);
14012         /*############################################################################################################################ */
14013
14014                 /*Register : MIO_PIN_76 @ 0XFF180130</p>
14015
14016                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14017                 PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
14018
14019                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14020                 PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
14021
14022                 Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
14023                 _clk_out- (SDSDIO clock) 3= Not Used
14024                 PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
14025
14026                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
14027                 n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
14028                 al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
14029                  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
14030                 PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
14031
14032                 Configures MIO Pin 76 peripheral interface mapping
14033                 (OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)
14034                 RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
14035
14036                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
14037                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
14038                         | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
14039                         | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
14040                         |  0 ) & RegMask); */
14041                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U);
14042         /*############################################################################################################################ */
14043
14044                 /*Register : MIO_PIN_77 @ 0XFF180134</p>
14045
14046                 Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
14047                 PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
14048
14049                 Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
14050                 PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
14051
14052                 Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
14053                 PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
14054
14055                 Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
14056                 n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
14057                 l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
14058                 O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
14059                 t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
14060                 PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
14061
14062                 Configures MIO Pin 77 peripheral interface mapping
14063                 (OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)
14064                 RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
14065
14066                 RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
14067                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
14068                         | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
14069                         | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
14070                         |  0 ) & RegMask); */
14071                 PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U);
14072         /*############################################################################################################################ */
14073
14074                 /*Register : MIO_MST_TRI0 @ 0XFF180204</p>
14075
14076                 Master Tri-state Enable for pin 0, active high
14077                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
14078
14079                 Master Tri-state Enable for pin 1, active high
14080                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
14081
14082                 Master Tri-state Enable for pin 2, active high
14083                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
14084
14085                 Master Tri-state Enable for pin 3, active high
14086                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
14087
14088                 Master Tri-state Enable for pin 4, active high
14089                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
14090
14091                 Master Tri-state Enable for pin 5, active high
14092                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
14093
14094                 Master Tri-state Enable for pin 6, active high
14095                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
14096
14097                 Master Tri-state Enable for pin 7, active high
14098                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
14099
14100                 Master Tri-state Enable for pin 8, active high
14101                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
14102
14103                 Master Tri-state Enable for pin 9, active high
14104                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
14105
14106                 Master Tri-state Enable for pin 10, active high
14107                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
14108
14109                 Master Tri-state Enable for pin 11, active high
14110                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
14111
14112                 Master Tri-state Enable for pin 12, active high
14113                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
14114
14115                 Master Tri-state Enable for pin 13, active high
14116                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
14117
14118                 Master Tri-state Enable for pin 14, active high
14119                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
14120
14121                 Master Tri-state Enable for pin 15, active high
14122                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
14123
14124                 Master Tri-state Enable for pin 16, active high
14125                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
14126
14127                 Master Tri-state Enable for pin 17, active high
14128                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
14129
14130                 Master Tri-state Enable for pin 18, active high
14131                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
14132
14133                 Master Tri-state Enable for pin 19, active high
14134                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
14135
14136                 Master Tri-state Enable for pin 20, active high
14137                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
14138
14139                 Master Tri-state Enable for pin 21, active high
14140                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
14141
14142                 Master Tri-state Enable for pin 22, active high
14143                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
14144
14145                 Master Tri-state Enable for pin 23, active high
14146                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
14147
14148                 Master Tri-state Enable for pin 24, active high
14149                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
14150
14151                 Master Tri-state Enable for pin 25, active high
14152                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
14153
14154                 Master Tri-state Enable for pin 26, active high
14155                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            1
14156
14157                 Master Tri-state Enable for pin 27, active high
14158                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
14159
14160                 Master Tri-state Enable for pin 28, active high
14161                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
14162
14163                 Master Tri-state Enable for pin 29, active high
14164                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
14165
14166                 Master Tri-state Enable for pin 30, active high
14167                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
14168
14169                 Master Tri-state Enable for pin 31, active high
14170                 PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
14171
14172                 MIO pin Tri-state Enables, 31:0
14173                 (OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x06240000U)
14174                 RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
14175
14176                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
14177                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
14178                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
14179                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
14180                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
14181                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
14182                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
14183                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
14184                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
14185                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
14186                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
14187                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
14188                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
14189                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
14190                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
14191                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
14192                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
14193                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
14194                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
14195                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
14196                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
14197                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
14198                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
14199                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
14200                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
14201                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
14202                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
14203                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
14204                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
14205                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
14206                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
14207                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
14208                         |  0 ) & RegMask); */
14209                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x06240000U);
14210         /*############################################################################################################################ */
14211
14212                 /*Register : MIO_MST_TRI1 @ 0XFF180208</p>
14213
14214                 Master Tri-state Enable for pin 32, active high
14215                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
14216
14217                 Master Tri-state Enable for pin 33, active high
14218                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
14219
14220                 Master Tri-state Enable for pin 34, active high
14221                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
14222
14223                 Master Tri-state Enable for pin 35, active high
14224                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
14225
14226                 Master Tri-state Enable for pin 36, active high
14227                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
14228
14229                 Master Tri-state Enable for pin 37, active high
14230                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
14231
14232                 Master Tri-state Enable for pin 38, active high
14233                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
14234
14235                 Master Tri-state Enable for pin 39, active high
14236                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
14237
14238                 Master Tri-state Enable for pin 40, active high
14239                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
14240
14241                 Master Tri-state Enable for pin 41, active high
14242                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
14243
14244                 Master Tri-state Enable for pin 42, active high
14245                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
14246
14247                 Master Tri-state Enable for pin 43, active high
14248                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
14249
14250                 Master Tri-state Enable for pin 44, active high
14251                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
14252
14253                 Master Tri-state Enable for pin 45, active high
14254                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
14255
14256                 Master Tri-state Enable for pin 46, active high
14257                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
14258
14259                 Master Tri-state Enable for pin 47, active high
14260                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
14261
14262                 Master Tri-state Enable for pin 48, active high
14263                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
14264
14265                 Master Tri-state Enable for pin 49, active high
14266                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
14267
14268                 Master Tri-state Enable for pin 50, active high
14269                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
14270
14271                 Master Tri-state Enable for pin 51, active high
14272                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
14273
14274                 Master Tri-state Enable for pin 52, active high
14275                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
14276
14277                 Master Tri-state Enable for pin 53, active high
14278                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
14279
14280                 Master Tri-state Enable for pin 54, active high
14281                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
14282
14283                 Master Tri-state Enable for pin 55, active high
14284                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
14285
14286                 Master Tri-state Enable for pin 56, active high
14287                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
14288
14289                 Master Tri-state Enable for pin 57, active high
14290                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
14291
14292                 Master Tri-state Enable for pin 58, active high
14293                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
14294
14295                 Master Tri-state Enable for pin 59, active high
14296                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
14297
14298                 Master Tri-state Enable for pin 60, active high
14299                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
14300
14301                 Master Tri-state Enable for pin 61, active high
14302                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
14303
14304                 Master Tri-state Enable for pin 62, active high
14305                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
14306
14307                 Master Tri-state Enable for pin 63, active high
14308                 PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
14309
14310                 MIO pin Tri-state Enables, 63:32
14311                 (OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)
14312                 RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
14313
14314                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
14315                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
14316                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
14317                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
14318                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
14319                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
14320                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
14321                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
14322                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
14323                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
14324                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
14325                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
14326                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
14327                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
14328                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
14329                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
14330                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
14331                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
14332                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
14333                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
14334                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
14335                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
14336                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
14337                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
14338                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
14339                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
14340                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
14341                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
14342                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
14343                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
14344                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
14345                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
14346                         |  0 ) & RegMask); */
14347                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U);
14348         /*############################################################################################################################ */
14349
14350                 /*Register : MIO_MST_TRI2 @ 0XFF18020C</p>
14351
14352                 Master Tri-state Enable for pin 64, active high
14353                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
14354
14355                 Master Tri-state Enable for pin 65, active high
14356                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
14357
14358                 Master Tri-state Enable for pin 66, active high
14359                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
14360
14361                 Master Tri-state Enable for pin 67, active high
14362                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
14363
14364                 Master Tri-state Enable for pin 68, active high
14365                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
14366
14367                 Master Tri-state Enable for pin 69, active high
14368                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
14369
14370                 Master Tri-state Enable for pin 70, active high
14371                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
14372
14373                 Master Tri-state Enable for pin 71, active high
14374                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
14375
14376                 Master Tri-state Enable for pin 72, active high
14377                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
14378
14379                 Master Tri-state Enable for pin 73, active high
14380                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
14381
14382                 Master Tri-state Enable for pin 74, active high
14383                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
14384
14385                 Master Tri-state Enable for pin 75, active high
14386                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
14387
14388                 Master Tri-state Enable for pin 76, active high
14389                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
14390
14391                 Master Tri-state Enable for pin 77, active high
14392                 PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
14393
14394                 MIO pin Tri-state Enables, 77:64
14395                 (OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)
14396                 RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
14397
14398                 RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
14399                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
14400                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
14401                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
14402                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
14403                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
14404                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
14405                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
14406                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
14407                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
14408                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
14409                         | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
14410                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
14411                         | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
14412                         |  0 ) & RegMask); */
14413                 PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U);
14414         /*############################################################################################################################ */
14415
14416                 /*Register : bank0_ctrl0 @ 0XFF180138</p>
14417
14418                 Each bit applies to a single IO. Bit 0 for MIO[0].
14419                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
14420
14421                 Each bit applies to a single IO. Bit 0 for MIO[0].
14422                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
14423
14424                 Each bit applies to a single IO. Bit 0 for MIO[0].
14425                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
14426
14427                 Each bit applies to a single IO. Bit 0 for MIO[0].
14428                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
14429
14430                 Each bit applies to a single IO. Bit 0 for MIO[0].
14431                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
14432
14433                 Each bit applies to a single IO. Bit 0 for MIO[0].
14434                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
14435
14436                 Each bit applies to a single IO. Bit 0 for MIO[0].
14437                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
14438
14439                 Each bit applies to a single IO. Bit 0 for MIO[0].
14440                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
14441
14442                 Each bit applies to a single IO. Bit 0 for MIO[0].
14443                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
14444
14445                 Each bit applies to a single IO. Bit 0 for MIO[0].
14446                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
14447
14448                 Each bit applies to a single IO. Bit 0 for MIO[0].
14449                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
14450
14451                 Each bit applies to a single IO. Bit 0 for MIO[0].
14452                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
14453
14454                 Each bit applies to a single IO. Bit 0 for MIO[0].
14455                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
14456
14457                 Each bit applies to a single IO. Bit 0 for MIO[0].
14458                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
14459
14460                 Each bit applies to a single IO. Bit 0 for MIO[0].
14461                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
14462
14463                 Each bit applies to a single IO. Bit 0 for MIO[0].
14464                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
14465
14466                 Each bit applies to a single IO. Bit 0 for MIO[0].
14467                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
14468
14469                 Each bit applies to a single IO. Bit 0 for MIO[0].
14470                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
14471
14472                 Each bit applies to a single IO. Bit 0 for MIO[0].
14473                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
14474
14475                 Each bit applies to a single IO. Bit 0 for MIO[0].
14476                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
14477
14478                 Each bit applies to a single IO. Bit 0 for MIO[0].
14479                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
14480
14481                 Each bit applies to a single IO. Bit 0 for MIO[0].
14482                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
14483
14484                 Each bit applies to a single IO. Bit 0 for MIO[0].
14485                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
14486
14487                 Each bit applies to a single IO. Bit 0 for MIO[0].
14488                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
14489
14490                 Each bit applies to a single IO. Bit 0 for MIO[0].
14491                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
14492
14493                 Each bit applies to a single IO. Bit 0 for MIO[0].
14494                 PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
14495
14496                 Drive0 control to MIO Bank 0 - control MIO[25:0]
14497                 (OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)
14498                 RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK |  0 );
14499
14500                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
14501                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
14502                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
14503                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
14504                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
14505                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
14506                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
14507                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
14508                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
14509                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
14510                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
14511                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
14512                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
14513                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
14514                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
14515                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
14516                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
14517                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
14518                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
14519                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
14520                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
14521                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
14522                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
14523                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
14524                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
14525                         | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
14526                         |  0 ) & RegMask); */
14527                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14528         /*############################################################################################################################ */
14529
14530                 /*Register : bank0_ctrl1 @ 0XFF18013C</p>
14531
14532                 Each bit applies to a single IO. Bit 0 for MIO[0].
14533                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
14534
14535                 Each bit applies to a single IO. Bit 0 for MIO[0].
14536                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
14537
14538                 Each bit applies to a single IO. Bit 0 for MIO[0].
14539                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
14540
14541                 Each bit applies to a single IO. Bit 0 for MIO[0].
14542                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
14543
14544                 Each bit applies to a single IO. Bit 0 for MIO[0].
14545                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
14546
14547                 Each bit applies to a single IO. Bit 0 for MIO[0].
14548                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
14549
14550                 Each bit applies to a single IO. Bit 0 for MIO[0].
14551                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
14552
14553                 Each bit applies to a single IO. Bit 0 for MIO[0].
14554                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
14555
14556                 Each bit applies to a single IO. Bit 0 for MIO[0].
14557                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
14558
14559                 Each bit applies to a single IO. Bit 0 for MIO[0].
14560                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
14561
14562                 Each bit applies to a single IO. Bit 0 for MIO[0].
14563                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
14564
14565                 Each bit applies to a single IO. Bit 0 for MIO[0].
14566                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
14567
14568                 Each bit applies to a single IO. Bit 0 for MIO[0].
14569                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
14570
14571                 Each bit applies to a single IO. Bit 0 for MIO[0].
14572                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
14573
14574                 Each bit applies to a single IO. Bit 0 for MIO[0].
14575                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
14576
14577                 Each bit applies to a single IO. Bit 0 for MIO[0].
14578                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
14579
14580                 Each bit applies to a single IO. Bit 0 for MIO[0].
14581                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
14582
14583                 Each bit applies to a single IO. Bit 0 for MIO[0].
14584                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
14585
14586                 Each bit applies to a single IO. Bit 0 for MIO[0].
14587                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
14588
14589                 Each bit applies to a single IO. Bit 0 for MIO[0].
14590                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
14591
14592                 Each bit applies to a single IO. Bit 0 for MIO[0].
14593                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
14594
14595                 Each bit applies to a single IO. Bit 0 for MIO[0].
14596                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
14597
14598                 Each bit applies to a single IO. Bit 0 for MIO[0].
14599                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
14600
14601                 Each bit applies to a single IO. Bit 0 for MIO[0].
14602                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
14603
14604                 Each bit applies to a single IO. Bit 0 for MIO[0].
14605                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
14606
14607                 Each bit applies to a single IO. Bit 0 for MIO[0].
14608                 PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
14609
14610                 Drive1 control to MIO Bank 0 - control MIO[25:0]
14611                 (OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)
14612                 RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK |  0 );
14613
14614                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
14615                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
14616                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
14617                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
14618                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
14619                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
14620                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
14621                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
14622                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
14623                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
14624                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
14625                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
14626                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
14627                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
14628                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
14629                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
14630                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
14631                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
14632                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
14633                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
14634                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
14635                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
14636                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
14637                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
14638                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
14639                         | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
14640                         |  0 ) & RegMask); */
14641                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14642         /*############################################################################################################################ */
14643
14644                 /*Register : bank0_ctrl3 @ 0XFF180140</p>
14645
14646                 Each bit applies to a single IO. Bit 0 for MIO[0].
14647                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
14648
14649                 Each bit applies to a single IO. Bit 0 for MIO[0].
14650                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
14651
14652                 Each bit applies to a single IO. Bit 0 for MIO[0].
14653                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
14654
14655                 Each bit applies to a single IO. Bit 0 for MIO[0].
14656                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
14657
14658                 Each bit applies to a single IO. Bit 0 for MIO[0].
14659                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
14660
14661                 Each bit applies to a single IO. Bit 0 for MIO[0].
14662                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
14663
14664                 Each bit applies to a single IO. Bit 0 for MIO[0].
14665                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
14666
14667                 Each bit applies to a single IO. Bit 0 for MIO[0].
14668                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
14669
14670                 Each bit applies to a single IO. Bit 0 for MIO[0].
14671                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
14672
14673                 Each bit applies to a single IO. Bit 0 for MIO[0].
14674                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
14675
14676                 Each bit applies to a single IO. Bit 0 for MIO[0].
14677                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
14678
14679                 Each bit applies to a single IO. Bit 0 for MIO[0].
14680                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
14681
14682                 Each bit applies to a single IO. Bit 0 for MIO[0].
14683                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
14684
14685                 Each bit applies to a single IO. Bit 0 for MIO[0].
14686                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
14687
14688                 Each bit applies to a single IO. Bit 0 for MIO[0].
14689                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
14690
14691                 Each bit applies to a single IO. Bit 0 for MIO[0].
14692                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
14693
14694                 Each bit applies to a single IO. Bit 0 for MIO[0].
14695                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
14696
14697                 Each bit applies to a single IO. Bit 0 for MIO[0].
14698                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
14699
14700                 Each bit applies to a single IO. Bit 0 for MIO[0].
14701                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
14702
14703                 Each bit applies to a single IO. Bit 0 for MIO[0].
14704                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
14705
14706                 Each bit applies to a single IO. Bit 0 for MIO[0].
14707                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
14708
14709                 Each bit applies to a single IO. Bit 0 for MIO[0].
14710                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
14711
14712                 Each bit applies to a single IO. Bit 0 for MIO[0].
14713                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
14714
14715                 Each bit applies to a single IO. Bit 0 for MIO[0].
14716                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
14717
14718                 Each bit applies to a single IO. Bit 0 for MIO[0].
14719                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
14720
14721                 Each bit applies to a single IO. Bit 0 for MIO[0].
14722                 PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
14723
14724                 Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
14725                 (OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)
14726                 RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
14727
14728                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
14729                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
14730                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
14731                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
14732                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
14733                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
14734                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
14735                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
14736                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
14737                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
14738                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
14739                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
14740                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
14741                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
14742                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
14743                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
14744                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
14745                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
14746                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
14747                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
14748                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
14749                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
14750                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
14751                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
14752                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
14753                         | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
14754                         |  0 ) & RegMask); */
14755                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
14756         /*############################################################################################################################ */
14757
14758                 /*Register : bank0_ctrl4 @ 0XFF180144</p>
14759
14760                 Each bit applies to a single IO. Bit 0 for MIO[0].
14761                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
14762
14763                 Each bit applies to a single IO. Bit 0 for MIO[0].
14764                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
14765
14766                 Each bit applies to a single IO. Bit 0 for MIO[0].
14767                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
14768
14769                 Each bit applies to a single IO. Bit 0 for MIO[0].
14770                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
14771
14772                 Each bit applies to a single IO. Bit 0 for MIO[0].
14773                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
14774
14775                 Each bit applies to a single IO. Bit 0 for MIO[0].
14776                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
14777
14778                 Each bit applies to a single IO. Bit 0 for MIO[0].
14779                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
14780
14781                 Each bit applies to a single IO. Bit 0 for MIO[0].
14782                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
14783
14784                 Each bit applies to a single IO. Bit 0 for MIO[0].
14785                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
14786
14787                 Each bit applies to a single IO. Bit 0 for MIO[0].
14788                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
14789
14790                 Each bit applies to a single IO. Bit 0 for MIO[0].
14791                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
14792
14793                 Each bit applies to a single IO. Bit 0 for MIO[0].
14794                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
14795
14796                 Each bit applies to a single IO. Bit 0 for MIO[0].
14797                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
14798
14799                 Each bit applies to a single IO. Bit 0 for MIO[0].
14800                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
14801
14802                 Each bit applies to a single IO. Bit 0 for MIO[0].
14803                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
14804
14805                 Each bit applies to a single IO. Bit 0 for MIO[0].
14806                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
14807
14808                 Each bit applies to a single IO. Bit 0 for MIO[0].
14809                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
14810
14811                 Each bit applies to a single IO. Bit 0 for MIO[0].
14812                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
14813
14814                 Each bit applies to a single IO. Bit 0 for MIO[0].
14815                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
14816
14817                 Each bit applies to a single IO. Bit 0 for MIO[0].
14818                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
14819
14820                 Each bit applies to a single IO. Bit 0 for MIO[0].
14821                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
14822
14823                 Each bit applies to a single IO. Bit 0 for MIO[0].
14824                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
14825
14826                 Each bit applies to a single IO. Bit 0 for MIO[0].
14827                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
14828
14829                 Each bit applies to a single IO. Bit 0 for MIO[0].
14830                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
14831
14832                 Each bit applies to a single IO. Bit 0 for MIO[0].
14833                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
14834
14835                 Each bit applies to a single IO. Bit 0 for MIO[0].
14836                 PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
14837
14838                 When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
14839                 (OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)
14840                 RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
14841
14842                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
14843                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
14844                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
14845                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
14846                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
14847                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
14848                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
14849                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
14850                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
14851                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
14852                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
14853                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
14854                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
14855                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
14856                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
14857                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
14858                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
14859                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
14860                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
14861                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
14862                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
14863                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
14864                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
14865                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
14866                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
14867                         | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
14868                         |  0 ) & RegMask); */
14869                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14870         /*############################################################################################################################ */
14871
14872                 /*Register : bank0_ctrl5 @ 0XFF180148</p>
14873
14874                 Each bit applies to a single IO. Bit 0 for MIO[0].
14875                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
14876
14877                 Each bit applies to a single IO. Bit 0 for MIO[0].
14878                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
14879
14880                 Each bit applies to a single IO. Bit 0 for MIO[0].
14881                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
14882
14883                 Each bit applies to a single IO. Bit 0 for MIO[0].
14884                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
14885
14886                 Each bit applies to a single IO. Bit 0 for MIO[0].
14887                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
14888
14889                 Each bit applies to a single IO. Bit 0 for MIO[0].
14890                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
14891
14892                 Each bit applies to a single IO. Bit 0 for MIO[0].
14893                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
14894
14895                 Each bit applies to a single IO. Bit 0 for MIO[0].
14896                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
14897
14898                 Each bit applies to a single IO. Bit 0 for MIO[0].
14899                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
14900
14901                 Each bit applies to a single IO. Bit 0 for MIO[0].
14902                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
14903
14904                 Each bit applies to a single IO. Bit 0 for MIO[0].
14905                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
14906
14907                 Each bit applies to a single IO. Bit 0 for MIO[0].
14908                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
14909
14910                 Each bit applies to a single IO. Bit 0 for MIO[0].
14911                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
14912
14913                 Each bit applies to a single IO. Bit 0 for MIO[0].
14914                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
14915
14916                 Each bit applies to a single IO. Bit 0 for MIO[0].
14917                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
14918
14919                 Each bit applies to a single IO. Bit 0 for MIO[0].
14920                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
14921
14922                 Each bit applies to a single IO. Bit 0 for MIO[0].
14923                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
14924
14925                 Each bit applies to a single IO. Bit 0 for MIO[0].
14926                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
14927
14928                 Each bit applies to a single IO. Bit 0 for MIO[0].
14929                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
14930
14931                 Each bit applies to a single IO. Bit 0 for MIO[0].
14932                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
14933
14934                 Each bit applies to a single IO. Bit 0 for MIO[0].
14935                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
14936
14937                 Each bit applies to a single IO. Bit 0 for MIO[0].
14938                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
14939
14940                 Each bit applies to a single IO. Bit 0 for MIO[0].
14941                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
14942
14943                 Each bit applies to a single IO. Bit 0 for MIO[0].
14944                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
14945
14946                 Each bit applies to a single IO. Bit 0 for MIO[0].
14947                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
14948
14949                 Each bit applies to a single IO. Bit 0 for MIO[0].
14950                 PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
14951
14952                 When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
14953                 (OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)
14954                 RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
14955
14956                 RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
14957                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
14958                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
14959                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
14960                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
14961                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
14962                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
14963                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
14964                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
14965                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
14966                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
14967                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
14968                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
14969                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
14970                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
14971                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
14972                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
14973                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
14974                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
14975                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
14976                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
14977                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
14978                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
14979                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
14980                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
14981                         | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
14982                         |  0 ) & RegMask); */
14983                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
14984         /*############################################################################################################################ */
14985
14986                 /*Register : bank0_ctrl6 @ 0XFF18014C</p>
14987
14988                 Each bit applies to a single IO. Bit 0 for MIO[0].
14989                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
14990
14991                 Each bit applies to a single IO. Bit 0 for MIO[0].
14992                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
14993
14994                 Each bit applies to a single IO. Bit 0 for MIO[0].
14995                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
14996
14997                 Each bit applies to a single IO. Bit 0 for MIO[0].
14998                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
14999
15000                 Each bit applies to a single IO. Bit 0 for MIO[0].
15001                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
15002
15003                 Each bit applies to a single IO. Bit 0 for MIO[0].
15004                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
15005
15006                 Each bit applies to a single IO. Bit 0 for MIO[0].
15007                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
15008
15009                 Each bit applies to a single IO. Bit 0 for MIO[0].
15010                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
15011
15012                 Each bit applies to a single IO. Bit 0 for MIO[0].
15013                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
15014
15015                 Each bit applies to a single IO. Bit 0 for MIO[0].
15016                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
15017
15018                 Each bit applies to a single IO. Bit 0 for MIO[0].
15019                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
15020
15021                 Each bit applies to a single IO. Bit 0 for MIO[0].
15022                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
15023
15024                 Each bit applies to a single IO. Bit 0 for MIO[0].
15025                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
15026
15027                 Each bit applies to a single IO. Bit 0 for MIO[0].
15028                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
15029
15030                 Each bit applies to a single IO. Bit 0 for MIO[0].
15031                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
15032
15033                 Each bit applies to a single IO. Bit 0 for MIO[0].
15034                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
15035
15036                 Each bit applies to a single IO. Bit 0 for MIO[0].
15037                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
15038
15039                 Each bit applies to a single IO. Bit 0 for MIO[0].
15040                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
15041
15042                 Each bit applies to a single IO. Bit 0 for MIO[0].
15043                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
15044
15045                 Each bit applies to a single IO. Bit 0 for MIO[0].
15046                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
15047
15048                 Each bit applies to a single IO. Bit 0 for MIO[0].
15049                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
15050
15051                 Each bit applies to a single IO. Bit 0 for MIO[0].
15052                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
15053
15054                 Each bit applies to a single IO. Bit 0 for MIO[0].
15055                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
15056
15057                 Each bit applies to a single IO. Bit 0 for MIO[0].
15058                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
15059
15060                 Each bit applies to a single IO. Bit 0 for MIO[0].
15061                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
15062
15063                 Each bit applies to a single IO. Bit 0 for MIO[0].
15064                 PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
15065
15066                 Slew rate control to MIO Bank 0 - control MIO[25:0]
15067                 (OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)
15068                 RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
15069
15070                 RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
15071                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
15072                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
15073                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
15074                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
15075                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
15076                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
15077                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
15078                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
15079                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
15080                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
15081                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
15082                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
15083                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
15084                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
15085                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
15086                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
15087                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
15088                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
15089                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
15090                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
15091                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
15092                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
15093                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
15094                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
15095                         | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
15096                         |  0 ) & RegMask); */
15097                 PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
15098         /*############################################################################################################################ */
15099
15100                 /*Register : bank1_ctrl0 @ 0XFF180154</p>
15101
15102                 Each bit applies to a single IO. Bit 0 for MIO[26].
15103                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
15104
15105                 Each bit applies to a single IO. Bit 0 for MIO[26].
15106                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
15107
15108                 Each bit applies to a single IO. Bit 0 for MIO[26].
15109                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
15110
15111                 Each bit applies to a single IO. Bit 0 for MIO[26].
15112                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
15113
15114                 Each bit applies to a single IO. Bit 0 for MIO[26].
15115                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
15116
15117                 Each bit applies to a single IO. Bit 0 for MIO[26].
15118                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
15119
15120                 Each bit applies to a single IO. Bit 0 for MIO[26].
15121                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
15122
15123                 Each bit applies to a single IO. Bit 0 for MIO[26].
15124                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
15125
15126                 Each bit applies to a single IO. Bit 0 for MIO[26].
15127                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
15128
15129                 Each bit applies to a single IO. Bit 0 for MIO[26].
15130                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
15131
15132                 Each bit applies to a single IO. Bit 0 for MIO[26].
15133                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
15134
15135                 Each bit applies to a single IO. Bit 0 for MIO[26].
15136                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
15137
15138                 Each bit applies to a single IO. Bit 0 for MIO[26].
15139                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
15140
15141                 Each bit applies to a single IO. Bit 0 for MIO[26].
15142                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
15143
15144                 Each bit applies to a single IO. Bit 0 for MIO[26].
15145                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
15146
15147                 Each bit applies to a single IO. Bit 0 for MIO[26].
15148                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
15149
15150                 Each bit applies to a single IO. Bit 0 for MIO[26].
15151                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
15152
15153                 Each bit applies to a single IO. Bit 0 for MIO[26].
15154                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
15155
15156                 Each bit applies to a single IO. Bit 0 for MIO[26].
15157                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
15158
15159                 Each bit applies to a single IO. Bit 0 for MIO[26].
15160                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
15161
15162                 Each bit applies to a single IO. Bit 0 for MIO[26].
15163                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
15164
15165                 Each bit applies to a single IO. Bit 0 for MIO[26].
15166                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
15167
15168                 Each bit applies to a single IO. Bit 0 for MIO[26].
15169                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
15170
15171                 Each bit applies to a single IO. Bit 0 for MIO[26].
15172                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
15173
15174                 Each bit applies to a single IO. Bit 0 for MIO[26].
15175                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
15176
15177                 Each bit applies to a single IO. Bit 0 for MIO[26].
15178                 PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
15179
15180                 Drive0 control to MIO Bank 1 - control MIO[51:26]
15181                 (OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)
15182                 RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK |  0 );
15183
15184                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
15185                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
15186                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
15187                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
15188                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
15189                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
15190                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
15191                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
15192                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
15193                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
15194                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
15195                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
15196                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
15197                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
15198                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
15199                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
15200                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
15201                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
15202                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
15203                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
15204                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
15205                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
15206                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
15207                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
15208                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
15209                         | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
15210                         |  0 ) & RegMask); */
15211                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15212         /*############################################################################################################################ */
15213
15214                 /*Register : bank1_ctrl1 @ 0XFF180158</p>
15215
15216                 Each bit applies to a single IO. Bit 0 for MIO[26].
15217                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
15218
15219                 Each bit applies to a single IO. Bit 0 for MIO[26].
15220                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
15221
15222                 Each bit applies to a single IO. Bit 0 for MIO[26].
15223                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
15224
15225                 Each bit applies to a single IO. Bit 0 for MIO[26].
15226                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
15227
15228                 Each bit applies to a single IO. Bit 0 for MIO[26].
15229                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
15230
15231                 Each bit applies to a single IO. Bit 0 for MIO[26].
15232                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
15233
15234                 Each bit applies to a single IO. Bit 0 for MIO[26].
15235                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
15236
15237                 Each bit applies to a single IO. Bit 0 for MIO[26].
15238                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
15239
15240                 Each bit applies to a single IO. Bit 0 for MIO[26].
15241                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
15242
15243                 Each bit applies to a single IO. Bit 0 for MIO[26].
15244                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
15245
15246                 Each bit applies to a single IO. Bit 0 for MIO[26].
15247                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
15248
15249                 Each bit applies to a single IO. Bit 0 for MIO[26].
15250                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
15251
15252                 Each bit applies to a single IO. Bit 0 for MIO[26].
15253                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
15254
15255                 Each bit applies to a single IO. Bit 0 for MIO[26].
15256                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
15257
15258                 Each bit applies to a single IO. Bit 0 for MIO[26].
15259                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
15260
15261                 Each bit applies to a single IO. Bit 0 for MIO[26].
15262                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
15263
15264                 Each bit applies to a single IO. Bit 0 for MIO[26].
15265                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
15266
15267                 Each bit applies to a single IO. Bit 0 for MIO[26].
15268                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
15269
15270                 Each bit applies to a single IO. Bit 0 for MIO[26].
15271                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
15272
15273                 Each bit applies to a single IO. Bit 0 for MIO[26].
15274                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
15275
15276                 Each bit applies to a single IO. Bit 0 for MIO[26].
15277                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
15278
15279                 Each bit applies to a single IO. Bit 0 for MIO[26].
15280                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
15281
15282                 Each bit applies to a single IO. Bit 0 for MIO[26].
15283                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
15284
15285                 Each bit applies to a single IO. Bit 0 for MIO[26].
15286                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
15287
15288                 Each bit applies to a single IO. Bit 0 for MIO[26].
15289                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
15290
15291                 Each bit applies to a single IO. Bit 0 for MIO[26].
15292                 PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
15293
15294                 Drive1 control to MIO Bank 1 - control MIO[51:26]
15295                 (OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)
15296                 RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK |  0 );
15297
15298                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
15299                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
15300                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
15301                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
15302                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
15303                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
15304                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
15305                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
15306                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
15307                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
15308                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
15309                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
15310                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
15311                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
15312                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
15313                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
15314                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
15315                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
15316                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
15317                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
15318                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
15319                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
15320                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
15321                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
15322                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
15323                         | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
15324                         |  0 ) & RegMask); */
15325                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15326         /*############################################################################################################################ */
15327
15328                 /*Register : bank1_ctrl3 @ 0XFF18015C</p>
15329
15330                 Each bit applies to a single IO. Bit 0 for MIO[26].
15331                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
15332
15333                 Each bit applies to a single IO. Bit 0 for MIO[26].
15334                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
15335
15336                 Each bit applies to a single IO. Bit 0 for MIO[26].
15337                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
15338
15339                 Each bit applies to a single IO. Bit 0 for MIO[26].
15340                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
15341
15342                 Each bit applies to a single IO. Bit 0 for MIO[26].
15343                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
15344
15345                 Each bit applies to a single IO. Bit 0 for MIO[26].
15346                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
15347
15348                 Each bit applies to a single IO. Bit 0 for MIO[26].
15349                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
15350
15351                 Each bit applies to a single IO. Bit 0 for MIO[26].
15352                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
15353
15354                 Each bit applies to a single IO. Bit 0 for MIO[26].
15355                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
15356
15357                 Each bit applies to a single IO. Bit 0 for MIO[26].
15358                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
15359
15360                 Each bit applies to a single IO. Bit 0 for MIO[26].
15361                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
15362
15363                 Each bit applies to a single IO. Bit 0 for MIO[26].
15364                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
15365
15366                 Each bit applies to a single IO. Bit 0 for MIO[26].
15367                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
15368
15369                 Each bit applies to a single IO. Bit 0 for MIO[26].
15370                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
15371
15372                 Each bit applies to a single IO. Bit 0 for MIO[26].
15373                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
15374
15375                 Each bit applies to a single IO. Bit 0 for MIO[26].
15376                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
15377
15378                 Each bit applies to a single IO. Bit 0 for MIO[26].
15379                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
15380
15381                 Each bit applies to a single IO. Bit 0 for MIO[26].
15382                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
15383
15384                 Each bit applies to a single IO. Bit 0 for MIO[26].
15385                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
15386
15387                 Each bit applies to a single IO. Bit 0 for MIO[26].
15388                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
15389
15390                 Each bit applies to a single IO. Bit 0 for MIO[26].
15391                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
15392
15393                 Each bit applies to a single IO. Bit 0 for MIO[26].
15394                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
15395
15396                 Each bit applies to a single IO. Bit 0 for MIO[26].
15397                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
15398
15399                 Each bit applies to a single IO. Bit 0 for MIO[26].
15400                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
15401
15402                 Each bit applies to a single IO. Bit 0 for MIO[26].
15403                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
15404
15405                 Each bit applies to a single IO. Bit 0 for MIO[26].
15406                 PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
15407
15408                 Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
15409                 (OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)
15410                 RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
15411
15412                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
15413                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
15414                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
15415                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
15416                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
15417                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
15418                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
15419                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
15420                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
15421                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
15422                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
15423                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
15424                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
15425                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
15426                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
15427                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
15428                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
15429                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
15430                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
15431                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
15432                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
15433                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
15434                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
15435                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
15436                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
15437                         | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
15438                         |  0 ) & RegMask); */
15439                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
15440         /*############################################################################################################################ */
15441
15442                 /*Register : bank1_ctrl4 @ 0XFF180160</p>
15443
15444                 Each bit applies to a single IO. Bit 0 for MIO[26].
15445                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
15446
15447                 Each bit applies to a single IO. Bit 0 for MIO[26].
15448                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
15449
15450                 Each bit applies to a single IO. Bit 0 for MIO[26].
15451                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
15452
15453                 Each bit applies to a single IO. Bit 0 for MIO[26].
15454                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
15455
15456                 Each bit applies to a single IO. Bit 0 for MIO[26].
15457                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
15458
15459                 Each bit applies to a single IO. Bit 0 for MIO[26].
15460                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
15461
15462                 Each bit applies to a single IO. Bit 0 for MIO[26].
15463                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
15464
15465                 Each bit applies to a single IO. Bit 0 for MIO[26].
15466                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
15467
15468                 Each bit applies to a single IO. Bit 0 for MIO[26].
15469                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
15470
15471                 Each bit applies to a single IO. Bit 0 for MIO[26].
15472                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
15473
15474                 Each bit applies to a single IO. Bit 0 for MIO[26].
15475                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
15476
15477                 Each bit applies to a single IO. Bit 0 for MIO[26].
15478                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
15479
15480                 Each bit applies to a single IO. Bit 0 for MIO[26].
15481                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
15482
15483                 Each bit applies to a single IO. Bit 0 for MIO[26].
15484                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
15485
15486                 Each bit applies to a single IO. Bit 0 for MIO[26].
15487                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
15488
15489                 Each bit applies to a single IO. Bit 0 for MIO[26].
15490                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
15491
15492                 Each bit applies to a single IO. Bit 0 for MIO[26].
15493                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
15494
15495                 Each bit applies to a single IO. Bit 0 for MIO[26].
15496                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
15497
15498                 Each bit applies to a single IO. Bit 0 for MIO[26].
15499                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
15500
15501                 Each bit applies to a single IO. Bit 0 for MIO[26].
15502                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
15503
15504                 Each bit applies to a single IO. Bit 0 for MIO[26].
15505                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
15506
15507                 Each bit applies to a single IO. Bit 0 for MIO[26].
15508                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
15509
15510                 Each bit applies to a single IO. Bit 0 for MIO[26].
15511                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
15512
15513                 Each bit applies to a single IO. Bit 0 for MIO[26].
15514                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
15515
15516                 Each bit applies to a single IO. Bit 0 for MIO[26].
15517                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
15518
15519                 Each bit applies to a single IO. Bit 0 for MIO[26].
15520                 PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
15521
15522                 When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15523                 (OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)
15524                 RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
15525
15526                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
15527                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
15528                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
15529                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
15530                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
15531                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
15532                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
15533                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
15534                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
15535                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
15536                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
15537                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
15538                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
15539                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
15540                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
15541                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
15542                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
15543                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
15544                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
15545                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
15546                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
15547                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
15548                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
15549                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
15550                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
15551                         | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
15552                         |  0 ) & RegMask); */
15553                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15554         /*############################################################################################################################ */
15555
15556                 /*Register : bank1_ctrl5 @ 0XFF180164</p>
15557
15558                 Each bit applies to a single IO. Bit 0 for MIO[26].
15559                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
15560
15561                 Each bit applies to a single IO. Bit 0 for MIO[26].
15562                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
15563
15564                 Each bit applies to a single IO. Bit 0 for MIO[26].
15565                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
15566
15567                 Each bit applies to a single IO. Bit 0 for MIO[26].
15568                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
15569
15570                 Each bit applies to a single IO. Bit 0 for MIO[26].
15571                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
15572
15573                 Each bit applies to a single IO. Bit 0 for MIO[26].
15574                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
15575
15576                 Each bit applies to a single IO. Bit 0 for MIO[26].
15577                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
15578
15579                 Each bit applies to a single IO. Bit 0 for MIO[26].
15580                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
15581
15582                 Each bit applies to a single IO. Bit 0 for MIO[26].
15583                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
15584
15585                 Each bit applies to a single IO. Bit 0 for MIO[26].
15586                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
15587
15588                 Each bit applies to a single IO. Bit 0 for MIO[26].
15589                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
15590
15591                 Each bit applies to a single IO. Bit 0 for MIO[26].
15592                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
15593
15594                 Each bit applies to a single IO. Bit 0 for MIO[26].
15595                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
15596
15597                 Each bit applies to a single IO. Bit 0 for MIO[26].
15598                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
15599
15600                 Each bit applies to a single IO. Bit 0 for MIO[26].
15601                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
15602
15603                 Each bit applies to a single IO. Bit 0 for MIO[26].
15604                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
15605
15606                 Each bit applies to a single IO. Bit 0 for MIO[26].
15607                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
15608
15609                 Each bit applies to a single IO. Bit 0 for MIO[26].
15610                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
15611
15612                 Each bit applies to a single IO. Bit 0 for MIO[26].
15613                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
15614
15615                 Each bit applies to a single IO. Bit 0 for MIO[26].
15616                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
15617
15618                 Each bit applies to a single IO. Bit 0 for MIO[26].
15619                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
15620
15621                 Each bit applies to a single IO. Bit 0 for MIO[26].
15622                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
15623
15624                 Each bit applies to a single IO. Bit 0 for MIO[26].
15625                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
15626
15627                 Each bit applies to a single IO. Bit 0 for MIO[26].
15628                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
15629
15630                 Each bit applies to a single IO. Bit 0 for MIO[26].
15631                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
15632
15633                 Each bit applies to a single IO. Bit 0 for MIO[26].
15634                 PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
15635
15636                 When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
15637                 (OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)
15638                 RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
15639
15640                 RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
15641                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
15642                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
15643                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
15644                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
15645                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
15646                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
15647                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
15648                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
15649                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
15650                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
15651                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
15652                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
15653                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
15654                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
15655                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
15656                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
15657                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
15658                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
15659                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
15660                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
15661                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
15662                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
15663                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
15664                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
15665                         | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
15666                         |  0 ) & RegMask); */
15667                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15668         /*############################################################################################################################ */
15669
15670                 /*Register : bank1_ctrl6 @ 0XFF180168</p>
15671
15672                 Each bit applies to a single IO. Bit 0 for MIO[26].
15673                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
15674
15675                 Each bit applies to a single IO. Bit 0 for MIO[26].
15676                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
15677
15678                 Each bit applies to a single IO. Bit 0 for MIO[26].
15679                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
15680
15681                 Each bit applies to a single IO. Bit 0 for MIO[26].
15682                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
15683
15684                 Each bit applies to a single IO. Bit 0 for MIO[26].
15685                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
15686
15687                 Each bit applies to a single IO. Bit 0 for MIO[26].
15688                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
15689
15690                 Each bit applies to a single IO. Bit 0 for MIO[26].
15691                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
15692
15693                 Each bit applies to a single IO. Bit 0 for MIO[26].
15694                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
15695
15696                 Each bit applies to a single IO. Bit 0 for MIO[26].
15697                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
15698
15699                 Each bit applies to a single IO. Bit 0 for MIO[26].
15700                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
15701
15702                 Each bit applies to a single IO. Bit 0 for MIO[26].
15703                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
15704
15705                 Each bit applies to a single IO. Bit 0 for MIO[26].
15706                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
15707
15708                 Each bit applies to a single IO. Bit 0 for MIO[26].
15709                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
15710
15711                 Each bit applies to a single IO. Bit 0 for MIO[26].
15712                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
15713
15714                 Each bit applies to a single IO. Bit 0 for MIO[26].
15715                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
15716
15717                 Each bit applies to a single IO. Bit 0 for MIO[26].
15718                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
15719
15720                 Each bit applies to a single IO. Bit 0 for MIO[26].
15721                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
15722
15723                 Each bit applies to a single IO. Bit 0 for MIO[26].
15724                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
15725
15726                 Each bit applies to a single IO. Bit 0 for MIO[26].
15727                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
15728
15729                 Each bit applies to a single IO. Bit 0 for MIO[26].
15730                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
15731
15732                 Each bit applies to a single IO. Bit 0 for MIO[26].
15733                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
15734
15735                 Each bit applies to a single IO. Bit 0 for MIO[26].
15736                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
15737
15738                 Each bit applies to a single IO. Bit 0 for MIO[26].
15739                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
15740
15741                 Each bit applies to a single IO. Bit 0 for MIO[26].
15742                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
15743
15744                 Each bit applies to a single IO. Bit 0 for MIO[26].
15745                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
15746
15747                 Each bit applies to a single IO. Bit 0 for MIO[26].
15748                 PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
15749
15750                 Slew rate control to MIO Bank 1 - control MIO[51:26]
15751                 (OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)
15752                 RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
15753
15754                 RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
15755                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
15756                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
15757                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
15758                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
15759                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
15760                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
15761                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
15762                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
15763                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
15764                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
15765                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
15766                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
15767                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
15768                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
15769                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
15770                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
15771                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
15772                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
15773                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
15774                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
15775                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
15776                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
15777                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
15778                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
15779                         | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
15780                         |  0 ) & RegMask); */
15781                 PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
15782         /*############################################################################################################################ */
15783
15784                 /*Register : bank2_ctrl0 @ 0XFF180170</p>
15785
15786                 Each bit applies to a single IO. Bit 0 for MIO[52].
15787                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
15788
15789                 Each bit applies to a single IO. Bit 0 for MIO[52].
15790                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
15791
15792                 Each bit applies to a single IO. Bit 0 for MIO[52].
15793                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
15794
15795                 Each bit applies to a single IO. Bit 0 for MIO[52].
15796                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
15797
15798                 Each bit applies to a single IO. Bit 0 for MIO[52].
15799                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
15800
15801                 Each bit applies to a single IO. Bit 0 for MIO[52].
15802                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
15803
15804                 Each bit applies to a single IO. Bit 0 for MIO[52].
15805                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
15806
15807                 Each bit applies to a single IO. Bit 0 for MIO[52].
15808                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
15809
15810                 Each bit applies to a single IO. Bit 0 for MIO[52].
15811                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
15812
15813                 Each bit applies to a single IO. Bit 0 for MIO[52].
15814                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
15815
15816                 Each bit applies to a single IO. Bit 0 for MIO[52].
15817                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
15818
15819                 Each bit applies to a single IO. Bit 0 for MIO[52].
15820                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
15821
15822                 Each bit applies to a single IO. Bit 0 for MIO[52].
15823                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
15824
15825                 Each bit applies to a single IO. Bit 0 for MIO[52].
15826                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
15827
15828                 Each bit applies to a single IO. Bit 0 for MIO[52].
15829                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
15830
15831                 Each bit applies to a single IO. Bit 0 for MIO[52].
15832                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
15833
15834                 Each bit applies to a single IO. Bit 0 for MIO[52].
15835                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
15836
15837                 Each bit applies to a single IO. Bit 0 for MIO[52].
15838                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
15839
15840                 Each bit applies to a single IO. Bit 0 for MIO[52].
15841                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
15842
15843                 Each bit applies to a single IO. Bit 0 for MIO[52].
15844                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
15845
15846                 Each bit applies to a single IO. Bit 0 for MIO[52].
15847                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
15848
15849                 Each bit applies to a single IO. Bit 0 for MIO[52].
15850                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
15851
15852                 Each bit applies to a single IO. Bit 0 for MIO[52].
15853                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
15854
15855                 Each bit applies to a single IO. Bit 0 for MIO[52].
15856                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
15857
15858                 Each bit applies to a single IO. Bit 0 for MIO[52].
15859                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
15860
15861                 Each bit applies to a single IO. Bit 0 for MIO[52].
15862                 PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
15863
15864                 Drive0 control to MIO Bank 2 - control MIO[77:52]
15865                 (OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)
15866                 RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK |  0 );
15867
15868                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
15869                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
15870                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
15871                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
15872                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
15873                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
15874                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
15875                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
15876                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
15877                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
15878                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
15879                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
15880                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
15881                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
15882                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
15883                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
15884                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
15885                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
15886                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
15887                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
15888                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
15889                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
15890                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
15891                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
15892                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
15893                         | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
15894                         |  0 ) & RegMask); */
15895                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
15896         /*############################################################################################################################ */
15897
15898                 /*Register : bank2_ctrl1 @ 0XFF180174</p>
15899
15900                 Each bit applies to a single IO. Bit 0 for MIO[52].
15901                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
15902
15903                 Each bit applies to a single IO. Bit 0 for MIO[52].
15904                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
15905
15906                 Each bit applies to a single IO. Bit 0 for MIO[52].
15907                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
15908
15909                 Each bit applies to a single IO. Bit 0 for MIO[52].
15910                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
15911
15912                 Each bit applies to a single IO. Bit 0 for MIO[52].
15913                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
15914
15915                 Each bit applies to a single IO. Bit 0 for MIO[52].
15916                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
15917
15918                 Each bit applies to a single IO. Bit 0 for MIO[52].
15919                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
15920
15921                 Each bit applies to a single IO. Bit 0 for MIO[52].
15922                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
15923
15924                 Each bit applies to a single IO. Bit 0 for MIO[52].
15925                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
15926
15927                 Each bit applies to a single IO. Bit 0 for MIO[52].
15928                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
15929
15930                 Each bit applies to a single IO. Bit 0 for MIO[52].
15931                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
15932
15933                 Each bit applies to a single IO. Bit 0 for MIO[52].
15934                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
15935
15936                 Each bit applies to a single IO. Bit 0 for MIO[52].
15937                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
15938
15939                 Each bit applies to a single IO. Bit 0 for MIO[52].
15940                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
15941
15942                 Each bit applies to a single IO. Bit 0 for MIO[52].
15943                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
15944
15945                 Each bit applies to a single IO. Bit 0 for MIO[52].
15946                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
15947
15948                 Each bit applies to a single IO. Bit 0 for MIO[52].
15949                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
15950
15951                 Each bit applies to a single IO. Bit 0 for MIO[52].
15952                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
15953
15954                 Each bit applies to a single IO. Bit 0 for MIO[52].
15955                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
15956
15957                 Each bit applies to a single IO. Bit 0 for MIO[52].
15958                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
15959
15960                 Each bit applies to a single IO. Bit 0 for MIO[52].
15961                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
15962
15963                 Each bit applies to a single IO. Bit 0 for MIO[52].
15964                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
15965
15966                 Each bit applies to a single IO. Bit 0 for MIO[52].
15967                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
15968
15969                 Each bit applies to a single IO. Bit 0 for MIO[52].
15970                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
15971
15972                 Each bit applies to a single IO. Bit 0 for MIO[52].
15973                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
15974
15975                 Each bit applies to a single IO. Bit 0 for MIO[52].
15976                 PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
15977
15978                 Drive1 control to MIO Bank 2 - control MIO[77:52]
15979                 (OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)
15980                 RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK |  0 );
15981
15982                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
15983                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
15984                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
15985                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
15986                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
15987                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
15988                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
15989                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
15990                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
15991                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
15992                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
15993                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
15994                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
15995                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
15996                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
15997                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
15998                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
15999                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
16000                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
16001                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
16002                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
16003                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
16004                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
16005                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
16006                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
16007                         | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
16008                         |  0 ) & RegMask); */
16009                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16010         /*############################################################################################################################ */
16011
16012                 /*Register : bank2_ctrl3 @ 0XFF180178</p>
16013
16014                 Each bit applies to a single IO. Bit 0 for MIO[52].
16015                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
16016
16017                 Each bit applies to a single IO. Bit 0 for MIO[52].
16018                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
16019
16020                 Each bit applies to a single IO. Bit 0 for MIO[52].
16021                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
16022
16023                 Each bit applies to a single IO. Bit 0 for MIO[52].
16024                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
16025
16026                 Each bit applies to a single IO. Bit 0 for MIO[52].
16027                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
16028
16029                 Each bit applies to a single IO. Bit 0 for MIO[52].
16030                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
16031
16032                 Each bit applies to a single IO. Bit 0 for MIO[52].
16033                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
16034
16035                 Each bit applies to a single IO. Bit 0 for MIO[52].
16036                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
16037
16038                 Each bit applies to a single IO. Bit 0 for MIO[52].
16039                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
16040
16041                 Each bit applies to a single IO. Bit 0 for MIO[52].
16042                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
16043
16044                 Each bit applies to a single IO. Bit 0 for MIO[52].
16045                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
16046
16047                 Each bit applies to a single IO. Bit 0 for MIO[52].
16048                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
16049
16050                 Each bit applies to a single IO. Bit 0 for MIO[52].
16051                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
16052
16053                 Each bit applies to a single IO. Bit 0 for MIO[52].
16054                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
16055
16056                 Each bit applies to a single IO. Bit 0 for MIO[52].
16057                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
16058
16059                 Each bit applies to a single IO. Bit 0 for MIO[52].
16060                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
16061
16062                 Each bit applies to a single IO. Bit 0 for MIO[52].
16063                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
16064
16065                 Each bit applies to a single IO. Bit 0 for MIO[52].
16066                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
16067
16068                 Each bit applies to a single IO. Bit 0 for MIO[52].
16069                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
16070
16071                 Each bit applies to a single IO. Bit 0 for MIO[52].
16072                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
16073
16074                 Each bit applies to a single IO. Bit 0 for MIO[52].
16075                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
16076
16077                 Each bit applies to a single IO. Bit 0 for MIO[52].
16078                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
16079
16080                 Each bit applies to a single IO. Bit 0 for MIO[52].
16081                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
16082
16083                 Each bit applies to a single IO. Bit 0 for MIO[52].
16084                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
16085
16086                 Each bit applies to a single IO. Bit 0 for MIO[52].
16087                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
16088
16089                 Each bit applies to a single IO. Bit 0 for MIO[52].
16090                 PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
16091
16092                 Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
16093                 (OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)
16094                 RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
16095
16096                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
16097                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
16098                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
16099                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
16100                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
16101                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
16102                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
16103                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
16104                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
16105                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
16106                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
16107                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
16108                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
16109                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
16110                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
16111                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
16112                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
16113                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
16114                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
16115                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
16116                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
16117                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
16118                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
16119                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
16120                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
16121                         | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
16122                         |  0 ) & RegMask); */
16123                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
16124         /*############################################################################################################################ */
16125
16126                 /*Register : bank2_ctrl4 @ 0XFF18017C</p>
16127
16128                 Each bit applies to a single IO. Bit 0 for MIO[52].
16129                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
16130
16131                 Each bit applies to a single IO. Bit 0 for MIO[52].
16132                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
16133
16134                 Each bit applies to a single IO. Bit 0 for MIO[52].
16135                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
16136
16137                 Each bit applies to a single IO. Bit 0 for MIO[52].
16138                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
16139
16140                 Each bit applies to a single IO. Bit 0 for MIO[52].
16141                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
16142
16143                 Each bit applies to a single IO. Bit 0 for MIO[52].
16144                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
16145
16146                 Each bit applies to a single IO. Bit 0 for MIO[52].
16147                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
16148
16149                 Each bit applies to a single IO. Bit 0 for MIO[52].
16150                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
16151
16152                 Each bit applies to a single IO. Bit 0 for MIO[52].
16153                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
16154
16155                 Each bit applies to a single IO. Bit 0 for MIO[52].
16156                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
16157
16158                 Each bit applies to a single IO. Bit 0 for MIO[52].
16159                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
16160
16161                 Each bit applies to a single IO. Bit 0 for MIO[52].
16162                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
16163
16164                 Each bit applies to a single IO. Bit 0 for MIO[52].
16165                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
16166
16167                 Each bit applies to a single IO. Bit 0 for MIO[52].
16168                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
16169
16170                 Each bit applies to a single IO. Bit 0 for MIO[52].
16171                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
16172
16173                 Each bit applies to a single IO. Bit 0 for MIO[52].
16174                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
16175
16176                 Each bit applies to a single IO. Bit 0 for MIO[52].
16177                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
16178
16179                 Each bit applies to a single IO. Bit 0 for MIO[52].
16180                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
16181
16182                 Each bit applies to a single IO. Bit 0 for MIO[52].
16183                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
16184
16185                 Each bit applies to a single IO. Bit 0 for MIO[52].
16186                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
16187
16188                 Each bit applies to a single IO. Bit 0 for MIO[52].
16189                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
16190
16191                 Each bit applies to a single IO. Bit 0 for MIO[52].
16192                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
16193
16194                 Each bit applies to a single IO. Bit 0 for MIO[52].
16195                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
16196
16197                 Each bit applies to a single IO. Bit 0 for MIO[52].
16198                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
16199
16200                 Each bit applies to a single IO. Bit 0 for MIO[52].
16201                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
16202
16203                 Each bit applies to a single IO. Bit 0 for MIO[52].
16204                 PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
16205
16206                 When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16207                 (OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)
16208                 RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
16209
16210                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
16211                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
16212                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
16213                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
16214                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
16215                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
16216                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
16217                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
16218                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
16219                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
16220                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
16221                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
16222                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
16223                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
16224                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
16225                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
16226                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
16227                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
16228                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
16229                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
16230                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
16231                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
16232                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
16233                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
16234                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
16235                         | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
16236                         |  0 ) & RegMask); */
16237                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16238         /*############################################################################################################################ */
16239
16240                 /*Register : bank2_ctrl5 @ 0XFF180180</p>
16241
16242                 Each bit applies to a single IO. Bit 0 for MIO[52].
16243                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
16244
16245                 Each bit applies to a single IO. Bit 0 for MIO[52].
16246                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
16247
16248                 Each bit applies to a single IO. Bit 0 for MIO[52].
16249                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
16250
16251                 Each bit applies to a single IO. Bit 0 for MIO[52].
16252                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
16253
16254                 Each bit applies to a single IO. Bit 0 for MIO[52].
16255                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
16256
16257                 Each bit applies to a single IO. Bit 0 for MIO[52].
16258                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
16259
16260                 Each bit applies to a single IO. Bit 0 for MIO[52].
16261                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
16262
16263                 Each bit applies to a single IO. Bit 0 for MIO[52].
16264                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
16265
16266                 Each bit applies to a single IO. Bit 0 for MIO[52].
16267                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
16268
16269                 Each bit applies to a single IO. Bit 0 for MIO[52].
16270                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
16271
16272                 Each bit applies to a single IO. Bit 0 for MIO[52].
16273                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
16274
16275                 Each bit applies to a single IO. Bit 0 for MIO[52].
16276                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
16277
16278                 Each bit applies to a single IO. Bit 0 for MIO[52].
16279                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
16280
16281                 Each bit applies to a single IO. Bit 0 for MIO[52].
16282                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
16283
16284                 Each bit applies to a single IO. Bit 0 for MIO[52].
16285                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
16286
16287                 Each bit applies to a single IO. Bit 0 for MIO[52].
16288                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
16289
16290                 Each bit applies to a single IO. Bit 0 for MIO[52].
16291                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
16292
16293                 Each bit applies to a single IO. Bit 0 for MIO[52].
16294                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
16295
16296                 Each bit applies to a single IO. Bit 0 for MIO[52].
16297                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
16298
16299                 Each bit applies to a single IO. Bit 0 for MIO[52].
16300                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
16301
16302                 Each bit applies to a single IO. Bit 0 for MIO[52].
16303                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
16304
16305                 Each bit applies to a single IO. Bit 0 for MIO[52].
16306                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
16307
16308                 Each bit applies to a single IO. Bit 0 for MIO[52].
16309                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
16310
16311                 Each bit applies to a single IO. Bit 0 for MIO[52].
16312                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
16313
16314                 Each bit applies to a single IO. Bit 0 for MIO[52].
16315                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
16316
16317                 Each bit applies to a single IO. Bit 0 for MIO[52].
16318                 PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
16319
16320                 When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
16321                 (OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)
16322                 RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
16323
16324                 RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
16325                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
16326                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
16327                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
16328                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
16329                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
16330                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
16331                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
16332                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
16333                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
16334                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
16335                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
16336                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
16337                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
16338                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
16339                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
16340                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
16341                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
16342                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
16343                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
16344                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
16345                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
16346                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
16347                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
16348                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
16349                         | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
16350                         |  0 ) & RegMask); */
16351                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
16352         /*############################################################################################################################ */
16353
16354                 /*Register : bank2_ctrl6 @ 0XFF180184</p>
16355
16356                 Each bit applies to a single IO. Bit 0 for MIO[52].
16357                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
16358
16359                 Each bit applies to a single IO. Bit 0 for MIO[52].
16360                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
16361
16362                 Each bit applies to a single IO. Bit 0 for MIO[52].
16363                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
16364
16365                 Each bit applies to a single IO. Bit 0 for MIO[52].
16366                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
16367
16368                 Each bit applies to a single IO. Bit 0 for MIO[52].
16369                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
16370
16371                 Each bit applies to a single IO. Bit 0 for MIO[52].
16372                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
16373
16374                 Each bit applies to a single IO. Bit 0 for MIO[52].
16375                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
16376
16377                 Each bit applies to a single IO. Bit 0 for MIO[52].
16378                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
16379
16380                 Each bit applies to a single IO. Bit 0 for MIO[52].
16381                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
16382
16383                 Each bit applies to a single IO. Bit 0 for MIO[52].
16384                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
16385
16386                 Each bit applies to a single IO. Bit 0 for MIO[52].
16387                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
16388
16389                 Each bit applies to a single IO. Bit 0 for MIO[52].
16390                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
16391
16392                 Each bit applies to a single IO. Bit 0 for MIO[52].
16393                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
16394
16395                 Each bit applies to a single IO. Bit 0 for MIO[52].
16396                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
16397
16398                 Each bit applies to a single IO. Bit 0 for MIO[52].
16399                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
16400
16401                 Each bit applies to a single IO. Bit 0 for MIO[52].
16402                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
16403
16404                 Each bit applies to a single IO. Bit 0 for MIO[52].
16405                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
16406
16407                 Each bit applies to a single IO. Bit 0 for MIO[52].
16408                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
16409
16410                 Each bit applies to a single IO. Bit 0 for MIO[52].
16411                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
16412
16413                 Each bit applies to a single IO. Bit 0 for MIO[52].
16414                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
16415
16416                 Each bit applies to a single IO. Bit 0 for MIO[52].
16417                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
16418
16419                 Each bit applies to a single IO. Bit 0 for MIO[52].
16420                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
16421
16422                 Each bit applies to a single IO. Bit 0 for MIO[52].
16423                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
16424
16425                 Each bit applies to a single IO. Bit 0 for MIO[52].
16426                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
16427
16428                 Each bit applies to a single IO. Bit 0 for MIO[52].
16429                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
16430
16431                 Each bit applies to a single IO. Bit 0 for MIO[52].
16432                 PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
16433
16434                 Slew rate control to MIO Bank 2 - control MIO[77:52]
16435                 (OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)
16436                 RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
16437
16438                 RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
16439                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
16440                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
16441                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
16442                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
16443                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
16444                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
16445                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
16446                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
16447                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
16448                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
16449                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
16450                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
16451                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
16452                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
16453                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
16454                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
16455                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
16456                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
16457                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
16458                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
16459                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
16460                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
16461                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
16462                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
16463                         | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
16464                         |  0 ) & RegMask); */
16465                 PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
16466         /*############################################################################################################################ */
16467
16468                 // : LOOPBACK
16469                 /*Register : MIO_LOOPBACK @ 0XFF180200</p>
16470
16471                 I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
16472                 ts to I2C 0 inputs.
16473                 PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
16474
16475                 CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
16476                 .
16477                 PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
16478
16479                 UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
16480                 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
16481                 PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
16482
16483                 SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
16484                 ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
16485                 PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
16486
16487                 Loopback function within MIO
16488                 (OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)
16489                 RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
16490
16491                 RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
16492                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
16493                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
16494                         | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
16495                         |  0 ) & RegMask); */
16496                 PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U);
16497         /*############################################################################################################################ */
16498
16499
16500   return 1;
16501 }
16502 unsigned long psu_peripherals_init_data() {
16503                 // : RESET BLOCKS
16504                 // : ENET
16505                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
16506
16507                 GEM 3 reset
16508                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
16509
16510                 Software controlled reset for the GEMs
16511                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
16512                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
16513
16514                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
16515                         |  0 ) & RegMask); */
16516                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
16517         /*############################################################################################################################ */
16518
16519                 // : QSPI
16520                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16521
16522                 Block level reset
16523                 PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
16524
16525                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16526                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)
16527                 RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
16528
16529                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
16530                         |  0 ) & RegMask); */
16531                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
16532         /*############################################################################################################################ */
16533
16534                 // : NAND
16535                 // : USB
16536                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
16537
16538                 USB 0 reset for control registers
16539                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
16540
16541                 USB 0 sleep circuit reset
16542                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
16543
16544                 USB 0 reset
16545                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
16546
16547                 Software control register for the LPD block.
16548                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)
16549                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
16550
16551                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
16552                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
16553                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
16554                         |  0 ) & RegMask); */
16555                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U);
16556         /*############################################################################################################################ */
16557
16558                 // : FPD RESET
16559                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
16560
16561                 PCIE config reset
16562                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0
16563
16564                 PCIE control block level reset
16565                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0
16566
16567                 PCIE bridge block level reset (AXI interface)
16568                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0
16569
16570                 Display Port block level reset (includes DPDMA)
16571                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
16572
16573                 FPD WDT reset
16574                 PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
16575
16576                 GDMA block level reset
16577                 PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
16578
16579                 Pixel Processor (submodule of GPU) block level reset
16580                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
16581
16582                 Pixel Processor (submodule of GPU) block level reset
16583                 PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
16584
16585                 GPU block level reset
16586                 PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
16587
16588                 GT block level reset
16589                 PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
16590
16591                 Sata block level reset
16592                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
16593
16594                 FPD Block level software controlled reset
16595                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000F807EU ,0x00000000U)
16596                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
16597
16598                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
16599                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
16600                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
16601                         | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
16602                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
16603                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
16604                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
16605                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
16606                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
16607                         | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
16608                         | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
16609                         |  0 ) & RegMask); */
16610                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U);
16611         /*############################################################################################################################ */
16612
16613                 // : SD
16614                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16615
16616                 Block level reset
16617                 PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
16618
16619                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16620                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)
16621                 RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
16622
16623                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
16624                         |  0 ) & RegMask); */
16625                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U);
16626         /*############################################################################################################################ */
16627
16628                 /*Register : CTRL_REG_SD @ 0XFF180310</p>
16629
16630                 SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
16631                 PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
16632
16633                 SD eMMC selection
16634                 (OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)
16635                 RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
16636
16637                 RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
16638                         |  0 ) & RegMask); */
16639                 PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U);
16640         /*############################################################################################################################ */
16641
16642                 /*Register : SD_CONFIG_REG2 @ 0XFF180320</p>
16643
16644                 Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
16645                 t 11 - Reserved
16646                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
16647
16648                 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
16649                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
16650
16651                 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
16652                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
16653
16654                 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
16655                 PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
16656
16657                 SD Config Register 2
16658                 (OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)
16659                 RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
16660
16661                 RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
16662                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
16663                         | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
16664                         | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
16665                         |  0 ) & RegMask); */
16666                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U);
16667         /*############################################################################################################################ */
16668
16669                 // : SD1 BASE CLOCK
16670                 /*Register : SD_CONFIG_REG1 @ 0XFF18031C</p>
16671
16672                 Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
16673                 PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
16674
16675                 SD Config Register 1
16676                 (OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)
16677                 RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK |  0 );
16678
16679                 RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
16680                         |  0 ) & RegMask); */
16681                 PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
16682         /*############################################################################################################################ */
16683
16684                 // : CAN
16685                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16686
16687                 Block level reset
16688                 PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
16689
16690                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16691                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)
16692                 RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
16693
16694                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
16695                         |  0 ) & RegMask); */
16696                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U);
16697         /*############################################################################################################################ */
16698
16699                 // : I2C
16700                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16701
16702                 Block level reset
16703                 PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
16704
16705                 Block level reset
16706                 PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
16707
16708                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16709                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)
16710                 RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
16711
16712                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
16713                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
16714                         |  0 ) & RegMask); */
16715                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U);
16716         /*############################################################################################################################ */
16717
16718                 // : SWDT
16719                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16720
16721                 Block level reset
16722                 PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
16723
16724                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16725                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)
16726                 RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK |  0 );
16727
16728                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
16729                         |  0 ) & RegMask); */
16730                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U);
16731         /*############################################################################################################################ */
16732
16733                 // : SPI
16734                 // : TTC
16735                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16736
16737                 Block level reset
16738                 PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
16739
16740                 Block level reset
16741                 PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
16742
16743                 Block level reset
16744                 PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
16745
16746                 Block level reset
16747                 PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
16748
16749                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16750                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)
16751                 RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
16752
16753                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
16754                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
16755                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
16756                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
16757                         |  0 ) & RegMask); */
16758                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U);
16759         /*############################################################################################################################ */
16760
16761                 // : UART
16762                 /*Register : RST_LPD_IOU2 @ 0XFF5E0238</p>
16763
16764                 Block level reset
16765                 PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
16766
16767                 Block level reset
16768                 PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
16769
16770                 Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
16771                 (OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)
16772                 RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
16773
16774                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
16775                         | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
16776                         |  0 ) & RegMask); */
16777                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
16778         /*############################################################################################################################ */
16779
16780                 // : UART BAUD RATE
16781                 /*Register : Baud_rate_divider_reg0 @ 0XFF000034</p>
16782
16783                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
16784                 PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
16785
16786                 Baud Rate Divider Register
16787                 (OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)
16788                 RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
16789
16790                 RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
16791                         |  0 ) & RegMask); */
16792                 PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
16793         /*############################################################################################################################ */
16794
16795                 /*Register : Baud_rate_gen_reg0 @ 0XFF000018</p>
16796
16797                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
16798                 PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
16799
16800                 Baud Rate Generator Register.
16801                 (OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)
16802                 RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
16803
16804                 RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
16805                         |  0 ) & RegMask); */
16806                 PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
16807         /*############################################################################################################################ */
16808
16809                 /*Register : Control_reg0 @ 0XFF000000</p>
16810
16811                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
16812                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
16813                 PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
16814
16815                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
16816                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
16817                 PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
16818
16819                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
16820                 pleted.
16821                 PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
16822
16823                 Transmit disable: 0: enable transmitter 1: disable transmitter
16824                 PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
16825
16826                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
16827                 PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
16828
16829                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
16830                 PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
16831
16832                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
16833                 PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
16834
16835                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
16836                  bit is self clearing once the reset has completed.
16837                 PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
16838
16839                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
16840                 is self clearing once the reset has completed.
16841                 PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
16842
16843                 UART Control Register
16844                 (OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)
16845                 RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
16846
16847                 RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
16848                         | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
16849                         | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
16850                         | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
16851                         | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
16852                         | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
16853                         | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
16854                         | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
16855                         | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
16856                         |  0 ) & RegMask); */
16857                 PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
16858         /*############################################################################################################################ */
16859
16860                 /*Register : mode_reg0 @ 0XFF000004</p>
16861
16862                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
16863                 PSU_UART0_MODE_REG0_CHMODE                                                      0x0
16864
16865                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
16866                 stop bits 10: 2 stop bits 11: reserved
16867                 PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
16868
16869                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
16870                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
16871                 PSU_UART0_MODE_REG0_PAR                                                         0x4
16872
16873                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
16874                 PSU_UART0_MODE_REG0_CHRL                                                        0x0
16875
16876                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
16877                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
16878                 PSU_UART0_MODE_REG0_CLKS                                                        0x0
16879
16880                 UART Mode Register
16881                 (OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)
16882                 RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
16883
16884                 RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
16885                         | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
16886                         | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
16887                         | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
16888                         | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
16889                         |  0 ) & RegMask); */
16890                 PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
16891         /*############################################################################################################################ */
16892
16893                 /*Register : Baud_rate_divider_reg0 @ 0XFF010034</p>
16894
16895                 Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
16896                 PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
16897
16898                 Baud Rate Divider Register
16899                 (OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)
16900                 RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
16901
16902                 RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
16903                         |  0 ) & RegMask); */
16904                 PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
16905         /*############################################################################################################################ */
16906
16907                 /*Register : Baud_rate_gen_reg0 @ 0XFF010018</p>
16908
16909                 Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
16910                 PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
16911
16912                 Baud Rate Generator Register.
16913                 (OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)
16914                 RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
16915
16916                 RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
16917                         |  0 ) & RegMask); */
16918                 PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
16919         /*############################################################################################################################ */
16920
16921                 /*Register : Control_reg0 @ 0XFF010000</p>
16922
16923                 Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
16924                 high level during 12 bit periods. It can be set regardless of the value of STTBRK.
16925                 PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
16926
16927                 Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
16928                 transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
16929                 PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
16930
16931                 Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
16932                 pleted.
16933                 PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
16934
16935                 Transmit disable: 0: enable transmitter 1: disable transmitter
16936                 PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
16937
16938                 Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
16939                 PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
16940
16941                 Receive disable: 0: enable 1: disable, regardless of the value of RXEN
16942                 PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
16943
16944                 Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
16945                 PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
16946
16947                 Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
16948                  bit is self clearing once the reset has completed.
16949                 PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
16950
16951                 Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
16952                 is self clearing once the reset has completed.
16953                 PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
16954
16955                 UART Control Register
16956                 (OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)
16957                 RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
16958
16959                 RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
16960                         | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
16961                         | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
16962                         | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
16963                         | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
16964                         | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
16965                         | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
16966                         | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
16967                         | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
16968                         |  0 ) & RegMask); */
16969                 PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
16970         /*############################################################################################################################ */
16971
16972                 /*Register : mode_reg0 @ 0XFF010004</p>
16973
16974                 Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
16975                 PSU_UART1_MODE_REG0_CHMODE                                                      0x0
16976
16977                 Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
16978                 stop bits 10: 2 stop bits 11: reserved
16979                 PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
16980
16981                 Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity
16982                 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
16983                 PSU_UART1_MODE_REG0_PAR                                                         0x4
16984
16985                 Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
16986                 PSU_UART1_MODE_REG0_CHRL                                                        0x0
16987
16988                 Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
16989                 source is uart_ref_clk 1: clock source is uart_ref_clk/8
16990                 PSU_UART1_MODE_REG0_CLKS                                                        0x0
16991
16992                 UART Mode Register
16993                 (OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)
16994                 RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
16995
16996                 RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
16997                         | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
16998                         | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
16999                         | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
17000                         | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
17001                         |  0 ) & RegMask); */
17002                 PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
17003         /*############################################################################################################################ */
17004
17005                 // : GPIO
17006                 // : ADMA TZ
17007                 /*Register : slcr_adma @ 0XFF4B0024</p>
17008
17009                 TrustZone Classification for ADMA
17010                 PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
17011
17012                 RPU TrustZone settings
17013                 (OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)
17014                 RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
17015
17016                 RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
17017                         |  0 ) & RegMask); */
17018                 PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU);
17019         /*############################################################################################################################ */
17020
17021                 // : CSU TAMPERING
17022                 // : CSU TAMPER STATUS
17023                 /*Register : tamper_status @ 0XFFCA5000</p>
17024
17025                 CSU regsiter
17026                 PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
17027
17028                 External MIO
17029                 PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
17030
17031                 JTAG toggle detect
17032                 PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
17033
17034                 PL SEU error
17035                 PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
17036
17037                 AMS over temperature alarm for LPD
17038                 PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
17039
17040                 AMS over temperature alarm for APU
17041                 PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
17042
17043                 AMS voltage alarm for VCCPINT_FPD
17044                 PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
17045
17046                 AMS voltage alarm for VCCPINT_LPD
17047                 PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
17048
17049                 AMS voltage alarm for VCCPAUX
17050                 PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
17051
17052                 AMS voltage alarm for DDRPHY
17053                 PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
17054
17055                 AMS voltage alarm for PSIO bank 0/1/2
17056                 PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
17057
17058                 AMS voltage alarm for PSIO bank 3 (dedicated pins)
17059                 PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
17060
17061                 AMS voltaage alarm for GT
17062                 PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
17063
17064                 Tamper Response Status
17065                 (OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)
17066                 RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
17067
17068                 RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
17069                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
17070                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
17071                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
17072                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
17073                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
17074                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
17075                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
17076                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
17077                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
17078                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
17079                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
17080                         | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
17081                         |  0 ) & RegMask); */
17082                 PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U);
17083         /*############################################################################################################################ */
17084
17085                 // : CSU TAMPER RESPONSE
17086                 // : AFIFM INTERFACE WIDTH
17087                 // : CPU QOS DEFAULT
17088                 /*Register : ACE_CTRL @ 0XFD5C0060</p>
17089
17090                 Set ACE outgoing AWQOS value
17091                 PSU_APU_ACE_CTRL_AWQOS                                                          0X0
17092
17093                 Set ACE outgoing ARQOS value
17094                 PSU_APU_ACE_CTRL_ARQOS                                                          0X0
17095
17096                 ACE Control Register
17097                 (OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)
17098                 RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK |  0 );
17099
17100                 RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT
17101                         | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT
17102                         |  0 ) & RegMask); */
17103                 PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U);
17104         /*############################################################################################################################ */
17105
17106                 // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
17107                 /*Register : CONTROL @ 0XFFA60040</p>
17108
17109                 Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from
17110                 he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
17111                 pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
17112                 g a 0 to this bit.
17113                 PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
17114
17115                 This register controls various functionalities within the RTC
17116                 (OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)
17117                 RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK |  0 );
17118
17119                 RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT
17120                         |  0 ) & RegMask); */
17121                 PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
17122         /*############################################################################################################################ */
17123
17124
17125   return 1;
17126 }
17127 unsigned long psu_post_config_data() {
17128                 // : POST_CONFIG
17129
17130   return 1;
17131 }
17132 unsigned long psu_peripherals_powerdwn_data() {
17133                 // : POWER DOWN REQUEST INTERRUPT ENABLE
17134                 // : POWER DOWN TRIGGER
17135
17136   return 1;
17137 }
17138 unsigned long psu_serdes_init_data() {
17139                 // : SERDES INITIALIZATION
17140                 // : GT REFERENCE CLOCK SOURCE SELECTION
17141                 /*Register : PLL_REF_SEL0 @ 0XFD410000</p>
17142
17143                 PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17144                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17145                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17146                 PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0xD
17147
17148                 PLL0 Reference Selection Register
17149                 (OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x0000000DU)
17150                 RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK |  0 );
17151
17152                 RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
17153                         |  0 ) & RegMask); */
17154                 PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU);
17155         /*############################################################################################################################ */
17156
17157                 /*Register : PLL_REF_SEL1 @ 0XFD410004</p>
17158
17159                 PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17160                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17161                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17162                 PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
17163
17164                 PLL1 Reference Selection Register
17165                 (OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)
17166                 RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK |  0 );
17167
17168                 RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
17169                         |  0 ) & RegMask); */
17170                 PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
17171         /*############################################################################################################################ */
17172
17173                 /*Register : PLL_REF_SEL2 @ 0XFD410008</p>
17174
17175                 PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17176                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17177                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17178                 PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
17179
17180                 PLL2 Reference Selection Register
17181                 (OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)
17182                 RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK |  0 );
17183
17184                 RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
17185                         |  0 ) & RegMask); */
17186                 PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
17187         /*############################################################################################################################ */
17188
17189                 /*Register : PLL_REF_SEL3 @ 0XFD41000C</p>
17190
17191                 PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 -
17192                 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
17193                 Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
17194                 PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
17195
17196                 PLL3 Reference Selection Register
17197                 (OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)
17198                 RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK |  0 );
17199
17200                 RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
17201                         |  0 ) & RegMask); */
17202                 PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
17203         /*############################################################################################################################ */
17204
17205                 // : GT REFERENCE CLOCK FREQUENCY SELECTION
17206                 /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860</p>
17207
17208                 Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
17209                 PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x1
17210
17211                 Lane0 Ref Clock Selection Register
17212                 (OFFSET, MASK, VALUE)      (0XFD402860, 0x00000080U ,0x00000080U)
17213                 RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK |  0 );
17214
17215                 RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
17216                         |  0 ) & RegMask); */
17217                 PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
17218         /*############################################################################################################################ */
17219
17220                 /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864</p>
17221
17222                 Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
17223                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
17224
17225                 Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
17226                 PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
17227
17228                 Lane1 Ref Clock Selection Register
17229                 (OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)
17230                 RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK |  0 );
17231
17232                 RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
17233                         | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
17234                         |  0 ) & RegMask); */
17235                 PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
17236         /*############################################################################################################################ */
17237
17238                 /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868</p>
17239
17240                 Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
17241                 PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
17242
17243                 Lane2 Ref Clock Selection Register
17244                 (OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)
17245                 RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK |  0 );
17246
17247                 RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
17248                         |  0 ) & RegMask); */
17249                 PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
17250         /*############################################################################################################################ */
17251
17252                 /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C</p>
17253
17254                 Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
17255                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
17256
17257                 Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
17258                 PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
17259
17260                 Lane3 Ref Clock Selection Register
17261                 (OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)
17262                 RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK |  0 );
17263
17264                 RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
17265                         | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
17266                         |  0 ) & RegMask); */
17267                 PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
17268         /*############################################################################################################################ */
17269
17270                 // : ENABLE SPREAD SPECTRUM
17271                 /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094</p>
17272
17273                 Enable/Disable coarse code satureation limiting logic
17274                 PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
17275
17276                 Test mode register 37
17277                 (OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)
17278                 RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK |  0 );
17279
17280                 RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
17281                         |  0 ) & RegMask); */
17282                 PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
17283         /*############################################################################################################################ */
17284
17285                 /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368</p>
17286
17287                 Spread Spectrum No of Steps [7:0]
17288                 PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
17289
17290                 Spread Spectrum No of Steps bits 7:0
17291                 (OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)
17292                 RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17293
17294                 RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17295                         |  0 ) & RegMask); */
17296                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
17297         /*############################################################################################################################ */
17298
17299                 /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C</p>
17300
17301                 Spread Spectrum No of Steps [10:8]
17302                 PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
17303
17304                 Spread Spectrum No of Steps bits 10:8
17305                 (OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)
17306                 RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17307
17308                 RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17309                         |  0 ) & RegMask); */
17310                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
17311         /*############################################################################################################################ */
17312
17313                 /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368</p>
17314
17315                 Spread Spectrum No of Steps [7:0]
17316                 PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
17317
17318                 Spread Spectrum No of Steps bits 7:0
17319                 (OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x00000000U)
17320                 RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17321
17322                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17323                         |  0 ) & RegMask); */
17324                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
17325         /*############################################################################################################################ */
17326
17327                 /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C</p>
17328
17329                 Spread Spectrum No of Steps [10:8]
17330                 PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
17331
17332                 Spread Spectrum No of Steps bits 10:8
17333                 (OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000000U)
17334                 RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17335
17336                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17337                         |  0 ) & RegMask); */
17338                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
17339         /*############################################################################################################################ */
17340
17341                 /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368</p>
17342
17343                 Spread Spectrum No of Steps [7:0]
17344                 PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
17345
17346                 Spread Spectrum No of Steps bits 7:0
17347                 (OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000000U)
17348                 RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
17349
17350                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
17351                         |  0 ) & RegMask); */
17352                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
17353         /*############################################################################################################################ */
17354
17355                 /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C</p>
17356
17357                 Spread Spectrum No of Steps [10:8]
17358                 PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
17359
17360                 Spread Spectrum No of Steps bits 10:8
17361                 (OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000000U)
17362                 RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
17363
17364                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
17365                         |  0 ) & RegMask); */
17366                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
17367         /*############################################################################################################################ */
17368
17369                 /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370</p>
17370
17371                 Step Size for Spread Spectrum [7:0]
17372                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
17373
17374                 Step Size for Spread Spectrum LSB
17375                 (OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x00000000U)
17376                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
17377
17378                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
17379                         |  0 ) & RegMask); */
17380                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
17381         /*############################################################################################################################ */
17382
17383                 /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374</p>
17384
17385                 Step Size for Spread Spectrum [15:8]
17386                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
17387
17388                 Step Size for Spread Spectrum 1
17389                 (OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000000U)
17390                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
17391
17392                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
17393                         |  0 ) & RegMask); */
17394                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
17395         /*############################################################################################################################ */
17396
17397                 /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378</p>
17398
17399                 Step Size for Spread Spectrum [23:16]
17400                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
17401
17402                 Step Size for Spread Spectrum 2
17403                 (OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000000U)
17404                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
17405
17406                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
17407                         |  0 ) & RegMask); */
17408                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
17409         /*############################################################################################################################ */
17410
17411                 /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C</p>
17412
17413                 Step Size for Spread Spectrum [25:24]
17414                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
17415
17416                 Enable/Disable test mode force on SS step size
17417                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
17418
17419                 Enable/Disable test mode force on SS no of steps
17420                 PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
17421
17422                 Enable force on enable Spread Spectrum
17423                 (OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)
17424                 RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
17425
17426                 RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
17427                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
17428                         | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
17429                         |  0 ) & RegMask); */
17430                 PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
17431         /*############################################################################################################################ */
17432
17433                 /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370</p>
17434
17435                 Step Size for Spread Spectrum [7:0]
17436                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
17437
17438                 Step Size for Spread Spectrum LSB
17439                 (OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)
17440                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
17441
17442                 RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
17443                         |  0 ) & RegMask); */
17444                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
17445         /*############################################################################################################################ */
17446
17447                 /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374</p>
17448
17449                 Step Size for Spread Spectrum [15:8]
17450                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
17451
17452                 Step Size for Spread Spectrum 1
17453                 (OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)
17454                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
17455
17456                 RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
17457                         |  0 ) & RegMask); */
17458                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
17459         /*############################################################################################################################ */
17460
17461                 /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378</p>
17462
17463                 Step Size for Spread Spectrum [23:16]
17464                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
17465
17466                 Step Size for Spread Spectrum 2
17467                 (OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)
17468                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
17469
17470                 RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
17471                         |  0 ) & RegMask); */
17472                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
17473         /*############################################################################################################################ */
17474
17475                 /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C</p>
17476
17477                 Step Size for Spread Spectrum [25:24]
17478                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
17479
17480                 Enable/Disable test mode force on SS step size
17481                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
17482
17483                 Enable/Disable test mode force on SS no of steps
17484                 PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
17485
17486                 Enable force on enable Spread Spectrum
17487                 (OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)
17488                 RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
17489
17490                 RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
17491                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
17492                         | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
17493                         |  0 ) & RegMask); */
17494                 PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
17495         /*############################################################################################################################ */
17496
17497                 /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370</p>
17498
17499                 Step Size for Spread Spectrum [7:0]
17500                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
17501
17502                 Step Size for Spread Spectrum LSB
17503                 (OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x00000000U)
17504                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
17505
17506                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
17507                         |  0 ) & RegMask); */
17508                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
17509         /*############################################################################################################################ */
17510
17511                 /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374</p>
17512
17513                 Step Size for Spread Spectrum [15:8]
17514                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
17515
17516                 Step Size for Spread Spectrum 1
17517                 (OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x00000000U)
17518                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
17519
17520                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
17521                         |  0 ) & RegMask); */
17522                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
17523         /*############################################################################################################################ */
17524
17525                 /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378</p>
17526
17527                 Step Size for Spread Spectrum [23:16]
17528                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
17529
17530                 Step Size for Spread Spectrum 2
17531                 (OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000000U)
17532                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
17533
17534                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
17535                         |  0 ) & RegMask); */
17536                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
17537         /*############################################################################################################################ */
17538
17539                 /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C</p>
17540
17541                 Step Size for Spread Spectrum [25:24]
17542                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
17543
17544                 Enable/Disable test mode force on SS step size
17545                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
17546
17547                 Enable/Disable test mode force on SS no of steps
17548                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
17549
17550                 Enable test mode forcing on enable Spread Spectrum
17551                 PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
17552
17553                 Enable force on enable Spread Spectrum
17554                 (OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)
17555                 RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK |  0 );
17556
17557                 RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
17558                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
17559                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
17560                         | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
17561                         |  0 ) & RegMask); */
17562                 PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
17563         /*############################################################################################################################ */
17564
17565                 /*Register : L2_TM_DIG_6 @ 0XFD40906C</p>
17566
17567                 Bypass Descrambler
17568                 PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
17569
17570                 Enable Bypass for <1> TM_DIG_CTRL_6
17571                 PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
17572
17573                 Data path test modes in decoder and descram
17574                 (OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)
17575                 RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
17576
17577                 RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
17578                         | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
17579                         |  0 ) & RegMask); */
17580                 PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
17581         /*############################################################################################################################ */
17582
17583                 /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4</p>
17584
17585                 Bypass scrambler signal
17586                 PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
17587
17588                 Enable/disable scrambler bypass signal
17589                 PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
17590
17591                 MPHY PLL Gear and bypass scrambler
17592                 (OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)
17593                 RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
17594
17595                 RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
17596                         | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
17597                         |  0 ) & RegMask); */
17598                 PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
17599         /*############################################################################################################################ */
17600
17601                 /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360</p>
17602
17603                 Enable test mode force on fractional mode enable
17604                 PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
17605
17606                 Fractional feedback division control and fractional value for feedback division bits 26:24
17607                 (OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)
17608                 RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK |  0 );
17609
17610                 RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
17611                         |  0 ) & RegMask); */
17612                 PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
17613         /*############################################################################################################################ */
17614
17615                 /*Register : L3_TM_DIG_6 @ 0XFD40D06C</p>
17616
17617                 Bypass 8b10b decoder
17618                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
17619
17620                 Enable Bypass for <3> TM_DIG_CTRL_6
17621                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
17622
17623                 Bypass Descrambler
17624                 PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
17625
17626                 Enable Bypass for <1> TM_DIG_CTRL_6
17627                 PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
17628
17629                 Data path test modes in decoder and descram
17630                 (OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)
17631                 RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
17632
17633                 RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
17634                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
17635                         | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
17636                         | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
17637                         |  0 ) & RegMask); */
17638                 PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
17639         /*############################################################################################################################ */
17640
17641                 /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4</p>
17642
17643                 Enable/disable encoder bypass signal
17644                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
17645
17646                 Bypass scrambler signal
17647                 PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
17648
17649                 Enable/disable scrambler bypass signal
17650                 PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
17651
17652                 MPHY PLL Gear and bypass scrambler
17653                 (OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)
17654                 RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
17655
17656                 RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
17657                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
17658                         | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
17659                         |  0 ) & RegMask); */
17660                 PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
17661         /*############################################################################################################################ */
17662
17663                 /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00</p>
17664
17665                 PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
17666                 PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
17667
17668                 Opmode Info
17669                 (OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)
17670                 RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK |  0 );
17671
17672                 RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
17673                         |  0 ) & RegMask); */
17674                 PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
17675         /*############################################################################################################################ */
17676
17677                 // : GT LANE SETTINGS
17678                 /*Register : ICM_CFG0 @ 0XFD410010</p>
17679
17680                 Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
17681                 , 7 - Unused
17682                 PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  1
17683
17684                 Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
17685                  7 - Unused
17686                 PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
17687
17688                 ICM Configuration Register 0
17689                 (OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000041U)
17690                 RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK |  0 );
17691
17692                 RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
17693                         | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
17694                         |  0 ) & RegMask); */
17695                 PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
17696         /*############################################################################################################################ */
17697
17698                 /*Register : ICM_CFG1 @ 0XFD410014</p>
17699
17700                 Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
17701                  7 - Unused
17702                 PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
17703
17704                 Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
17705                  7 - Unused
17706                 PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
17707
17708                 ICM Configuration Register 1
17709                 (OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)
17710                 RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK |  0 );
17711
17712                 RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
17713                         | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
17714                         |  0 ) & RegMask); */
17715                 PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
17716         /*############################################################################################################################ */
17717
17718                 // : CHECKING PLL LOCK
17719                 // : ENABLE SERIAL DATA MUX DEEMPH
17720                 /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4</p>
17721
17722                 Enable/disable DP post2 path
17723                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
17724
17725                 Override enable/disable of DP post2 path
17726                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
17727
17728                 Override enable/disable of DP post1 path
17729                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
17730
17731                 Enable/disable DP main path
17732                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
17733
17734                 Override enable/disable of DP main path
17735                 PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
17736
17737                 Post or pre or main DP path selection
17738                 (OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)
17739                 RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
17740
17741                 RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
17742                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
17743                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
17744                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
17745                         | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
17746                         |  0 ) & RegMask); */
17747                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
17748         /*############################################################################################################################ */
17749
17750                 /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8</p>
17751
17752                 Test register force for enabling/disablign TX deemphasis bits <17:0>
17753                 PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
17754
17755                 Enable Override of TX deemphasis
17756                 (OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)
17757                 RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
17758
17759                 RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
17760                         |  0 ) & RegMask); */
17761                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
17762         /*############################################################################################################################ */
17763
17764                 // : ENABLE PRE EMPHAIS AND VOLTAGE SWING
17765                 /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0</p>
17766
17767                 Margining factor value
17768                 PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
17769
17770                 Margining factor
17771                 (OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)
17772                 RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
17773
17774                 RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
17775                         |  0 ) & RegMask); */
17776                 PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
17777         /*############################################################################################################################ */
17778
17779                 /*Register : L1_TX_ANA_TM_18 @ 0XFD404048</p>
17780
17781                 pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
17782                 PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
17783
17784                 Override for PIPE TX de-emphasis
17785                 (OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)
17786                 RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
17787
17788                 RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
17789                         |  0 ) & RegMask); */
17790                 PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
17791         /*############################################################################################################################ */
17792
17793
17794   return 1;
17795 }
17796 unsigned long psu_resetout_init_data() {
17797                 // : TAKING SERDES PERIPHERAL OUT OF RESET RESET
17798                 // : PUTTING USB0 IN RESET
17799                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
17800
17801                 USB 0 reset for control registers
17802                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
17803
17804                 Software control register for the LPD block.
17805                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)
17806                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK |  0 );
17807
17808                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
17809                         |  0 ) & RegMask); */
17810                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
17811         /*############################################################################################################################ */
17812
17813                 // : USB0 PIPE POWER PRESENT
17814                 /*Register : fpd_power_prsnt @ 0XFF9D0080</p>
17815
17816                 This bit is used to choose between PIPE power present and 1'b1
17817                 PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
17818
17819                 fpd_power_prsnt
17820                 (OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)
17821                 RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK |  0 );
17822
17823                 RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
17824                         |  0 ) & RegMask); */
17825                 PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
17826         /*############################################################################################################################ */
17827
17828                 // :
17829                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
17830
17831                 USB 0 sleep circuit reset
17832                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
17833
17834                 USB 0 reset
17835                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
17836
17837                 Software control register for the LPD block.
17838                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)
17839                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
17840
17841                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
17842                         | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
17843                         |  0 ) & RegMask); */
17844                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
17845         /*############################################################################################################################ */
17846
17847                 // : PUTTING GEM0 IN RESET
17848                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
17849
17850                 GEM 3 reset
17851                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
17852
17853                 Software controlled reset for the GEMs
17854                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)
17855                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
17856
17857                 RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
17858                         |  0 ) & RegMask); */
17859                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
17860         /*############################################################################################################################ */
17861
17862                 // : PUTTING SATA IN RESET
17863                 /*Register : sata_misc_ctrl @ 0XFD3D0100</p>
17864
17865                 Sata PM clock control select
17866                 PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
17867
17868                 Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
17869                 (OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)
17870                 RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK |  0 );
17871
17872                 RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
17873                         |  0 ) & RegMask); */
17874                 PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
17875         /*############################################################################################################################ */
17876
17877                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
17878
17879                 Sata block level reset
17880                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
17881
17882                 FPD Block level software controlled reset
17883                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)
17884                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
17885
17886                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
17887                         |  0 ) & RegMask); */
17888                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
17889         /*############################################################################################################################ */
17890
17891                 // : PUTTING PCIE IN RESET
17892                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
17893
17894                 PCIE config reset
17895                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X0
17896
17897                 PCIE control block level reset
17898                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X0
17899
17900                 PCIE bridge block level reset (AXI interface)
17901                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X0
17902
17903                 FPD Block level software controlled reset
17904                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x00000000U)
17905                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
17906
17907                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
17908                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
17909                         | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
17910                         |  0 ) & RegMask); */
17911                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x00000000U);
17912         /*############################################################################################################################ */
17913
17914                 // : PUTTING DP IN RESET
17915                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
17916
17917                 Display Port block level reset (includes DPDMA)
17918                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
17919
17920                 FPD Block level software controlled reset
17921                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)
17922                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
17923
17924                 RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
17925                         |  0 ) & RegMask); */
17926                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
17927         /*############################################################################################################################ */
17928
17929                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
17930
17931                 Set to '1' to hold the GT in reset. Clear to release.
17932                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
17933
17934                 Reset the transmitter PHY.
17935                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)
17936                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
17937
17938                 RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
17939                         |  0 ) & RegMask); */
17940                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
17941         /*############################################################################################################################ */
17942
17943                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
17944
17945                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
17946                 ane0 Bits [3:2] - lane 1
17947                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
17948
17949                 Control PHY Power down
17950                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)
17951                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
17952
17953                 RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
17954                         |  0 ) & RegMask); */
17955                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
17956         /*############################################################################################################################ */
17957
17958                 // : USB0 GFLADJ
17959                 /*Register : GUSB2PHYCFG @ 0XFE20C200</p>
17960
17961                 USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to
17962                 he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
17963                 C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
17964                 . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
17965                 UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger
17966                 alue. Note: This field is valid only in device mode.
17967                 PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0X9
17968
17969                 Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
17970                  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
17971                 time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
17972                 ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
17973                 off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
17974                 ng hibernation. - This bit is valid only in device mode.
17975                 PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0X0
17976
17977                 Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
17978                 _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
17979                  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY.
17980                 ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
17981                 n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
17982                 d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
17983                 d.
17984                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0X0
17985
17986                 USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
17987                 Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. -
17988                 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
17989                  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
17990                  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
17991                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0X0
17992
17993                 Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
17994                 figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
17995                 ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
17996                 r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
17997                 t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
17998                 g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
17999                  when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
18000                 PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20                                        0X1
18001
18002                 Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
18003                 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with
18004                 ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
18005                 B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
18006                 PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0X0
18007
18008                 ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
18009                 e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
18010                 ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
18011                 lected through DWC_USB3_HSPHY_INTERFACE.
18012                 PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0X1
18013
18014                 PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
18015                  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same
18016                 lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
18017                  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
18018                  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
18019                 PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0X0
18020
18021                 HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
18022                 a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for
18023                 dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
18024                 e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
18025                 The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this
18026                 ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
18027                  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
18028                 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
18029                 PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0X7
18030
18031                 Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either
18032                 he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
18033                 ented.
18034                 (OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FFFU ,0x00002457U)
18035                 RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK |  0 );
18036
18037                 RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
18038                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
18039                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
18040                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
18041                         | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
18042                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
18043                         | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
18044                         | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
18045                         | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
18046                         |  0 ) & RegMask); */
18047                 PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
18048         /*############################################################################################################################ */
18049
18050                 /*Register : GFLADJ @ 0XFE20C630</p>
18051
18052                 This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register
18053                 alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
18054                 _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
18055                 TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
18056                 riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
18057                 cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
18058                 uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
18059                 ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
18060                 RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
18061                 PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0X0
18062
18063                 Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
18064                 ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
18065                  to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely
18066                 rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
18067                 (OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)
18068                 RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK |  0 );
18069
18070                 RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
18071                         |  0 ) & RegMask); */
18072                 PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
18073         /*############################################################################################################################ */
18074
18075                 // : CHECK PLL LOCK FOR LANE0
18076                 /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4</p>
18077
18078                 Status Read value of PLL Lock
18079                 PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
18080                 (OFFSET, MASK, VALUE)      (0XFD4023E4, 0x00000010U ,0x00000010U)  */
18081                 mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
18082
18083         /*############################################################################################################################ */
18084
18085                 // : CHECK PLL LOCK FOR LANE1
18086                 /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4</p>
18087
18088                 Status Read value of PLL Lock
18089                 PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
18090                 (OFFSET, MASK, VALUE)      (0XFD4063E4, 0x00000010U ,0x00000010U)  */
18091                 mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
18092
18093         /*############################################################################################################################ */
18094
18095                 // : CHECK PLL LOCK FOR LANE2
18096                 /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4</p>
18097
18098                 Status Read value of PLL Lock
18099                 PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
18100                 (OFFSET, MASK, VALUE)      (0XFD40A3E4, 0x00000010U ,0x00000010U)  */
18101                 mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
18102
18103         /*############################################################################################################################ */
18104
18105                 // : CHECK PLL LOCK FOR LANE3
18106                 /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4</p>
18107
18108                 Status Read value of PLL Lock
18109                 PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
18110                 (OFFSET, MASK, VALUE)      (0XFD40E3E4, 0x00000010U ,0x00000010U)  */
18111                 mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
18112
18113         /*############################################################################################################################ */
18114
18115                 // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
18116                 /*Register : ATTR_37 @ 0XFD480094</p>
18117
18118                 Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
18119                 gister.; EP=0x0001; RP=0x0001
18120                 PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY                          0X1
18121
18122                 ATTR_37
18123                 (OFFSET, MASK, VALUE)      (0XFD480094, 0x00004000U ,0x00004000U)
18124                 RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK |  0 );
18125
18126                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
18127                         |  0 ) & RegMask); */
18128                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004000U ,0x00004000U);
18129         /*############################################################################################################################ */
18130
18131                 /*Register : ATTR_25 @ 0XFD480064</p>
18132
18133                 If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
18134                 ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
18135                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
18136
18137                 ATTR_25
18138                 (OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)
18139                 RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK |  0 );
18140
18141                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
18142                         |  0 ) & RegMask); */
18143                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
18144         /*############################################################################################################################ */
18145
18146                 // : PCIE SETTINGS
18147                 /*Register : ATTR_7 @ 0XFD48001C</p>
18148
18149                 Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
18150                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
18151                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
18152                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
18153                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
18154                 re size in bytes.; EP=0x0004; RP=0x0000
18155                 PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0                                                0x0
18156
18157                 ATTR_7
18158                 (OFFSET, MASK, VALUE)      (0XFD48001C, 0x0000FFFFU ,0x00000000U)
18159                 RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK |  0 );
18160
18161                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
18162                         |  0 ) & RegMask); */
18163                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U);
18164         /*############################################################################################################################ */
18165
18166                 /*Register : ATTR_8 @ 0XFD480020</p>
18167
18168                 Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
18169                 ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
18170                 Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
18171                 erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator
18172                 set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
18173                 re size in bytes.; EP=0xFFF0; RP=0x0000
18174                 PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0                                                0x0
18175
18176                 ATTR_8
18177                 (OFFSET, MASK, VALUE)      (0XFD480020, 0x0000FFFFU ,0x00000000U)
18178                 RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK |  0 );
18179
18180                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
18181                         |  0 ) & RegMask); */
18182                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U);
18183         /*############################################################################################################################ */
18184
18185                 /*Register : ATTR_9 @ 0XFD480024</p>
18186
18187                 Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
18188                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
18189                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
18190                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
18191                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
18192                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
18193                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
18194                 PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1                                                0x0
18195
18196                 ATTR_9
18197                 (OFFSET, MASK, VALUE)      (0XFD480024, 0x0000FFFFU ,0x00000000U)
18198                 RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK |  0 );
18199
18200                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
18201                         |  0 ) & RegMask); */
18202                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U);
18203         /*############################################################################################################################ */
18204
18205                 /*Register : ATTR_10 @ 0XFD480028</p>
18206
18207                 Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if
18208                 AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
18209                  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set
18210                 o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
18211                 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of
18212                 '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
18213                 ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
18214                 PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1                                               0x0
18215
18216                 ATTR_10
18217                 (OFFSET, MASK, VALUE)      (0XFD480028, 0x0000FFFFU ,0x00000000U)
18218                 RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK |  0 );
18219
18220                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
18221                         |  0 ) & RegMask); */
18222                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U);
18223         /*############################################################################################################################ */
18224
18225                 /*Register : ATTR_11 @ 0XFD48002C</p>
18226
18227                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
18228                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
18229                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
18230                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
18231                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
18232                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
18233                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
18234                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
18235                 PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2                                               0xFFFF
18236
18237                 ATTR_11
18238                 (OFFSET, MASK, VALUE)      (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)
18239                 RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK |  0 );
18240
18241                 RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
18242                         |  0 ) & RegMask); */
18243                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
18244         /*############################################################################################################################ */
18245
18246                 /*Register : ATTR_12 @ 0XFD480030</p>
18247
18248                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
18249                 AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
18250                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
18251                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
18252                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
18253                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to
18254                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
18255                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
18256                 PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2                                               0xFF
18257
18258                 ATTR_12
18259                 (OFFSET, MASK, VALUE)      (0XFD480030, 0x0000FFFFU ,0x000000FFU)
18260                 RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK |  0 );
18261
18262                 RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
18263                         |  0 ) & RegMask); */
18264                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU);
18265         /*############################################################################################################################ */
18266
18267                 /*Register : ATTR_13 @ 0XFD480034</p>
18268
18269                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
18270                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
18271                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
18272                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
18273                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
18274                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
18275                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
18276                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
18277                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
18278                 PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3                                               0x0
18279
18280                 ATTR_13
18281                 (OFFSET, MASK, VALUE)      (0XFD480034, 0x0000FFFFU ,0x00000000U)
18282                 RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK |  0 );
18283
18284                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
18285                         |  0 ) & RegMask); */
18286                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U);
18287         /*############################################################################################################################ */
18288
18289                 /*Register : ATTR_14 @ 0XFD480038</p>
18290
18291                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
18292                 AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
18293                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
18294                  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
18295                 t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
18296                 t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
18297                 if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits
18298                 f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
18299                  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
18300                 PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3                                               0xFFFF
18301
18302                 ATTR_14
18303                 (OFFSET, MASK, VALUE)      (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)
18304                 RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK |  0 );
18305
18306                 RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
18307                         |  0 ) & RegMask); */
18308                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
18309         /*############################################################################################################################ */
18310
18311                 /*Register : ATTR_15 @ 0XFD48003C</p>
18312
18313                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
18314                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
18315                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
18316                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
18317                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
18318                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
18319                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
18320                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
18321                 PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4                                               0xFFF0
18322
18323                 ATTR_15
18324                 (OFFSET, MASK, VALUE)      (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)
18325                 RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK |  0 );
18326
18327                 RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
18328                         |  0 ) & RegMask); */
18329                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
18330         /*############################################################################################################################ */
18331
18332                 /*Register : ATTR_16 @ 0XFD480040</p>
18333
18334                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
18335                 AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
18336                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
18337                 , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
18338                 ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
18339                 most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to
18340                 . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
18341                 ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
18342                 PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4                                               0xFFF0
18343
18344                 ATTR_16
18345                 (OFFSET, MASK, VALUE)      (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)
18346                 RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK |  0 );
18347
18348                 RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
18349                         |  0 ) & RegMask); */
18350                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
18351         /*############################################################################################################################ */
18352
18353                 /*Register : ATTR_17 @ 0XFD480044</p>
18354
18355                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
18356                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
18357                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
18358                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
18359                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
18360                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
18361                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
18362                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
18363                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
18364                 PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5                                               0xFFF1
18365
18366                 ATTR_17
18367                 (OFFSET, MASK, VALUE)      (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)
18368                 RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK |  0 );
18369
18370                 RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
18371                         |  0 ) & RegMask); */
18372                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
18373         /*############################################################################################################################ */
18374
18375                 /*Register : ATTR_18 @ 0XFD480048</p>
18376
18377                 For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
18378                 AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
18379                 tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
18380                 Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit
18381                 refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
18382                 R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] =
18383                 refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in
18384                 ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
18385                 permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
18386                 PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5                                               0xFFF1
18387
18388                 ATTR_18
18389                 (OFFSET, MASK, VALUE)      (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)
18390                 RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK |  0 );
18391
18392                 RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
18393                         |  0 ) & RegMask); */
18394                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
18395         /*############################################################################################################################ */
18396
18397                 /*Register : ATTR_27 @ 0XFD48006C</p>
18398
18399                 Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
18400                 to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
18401                 PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED                      1
18402
18403                 Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
18404                 state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
18405                  32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
18406                 PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY                        0x0
18407
18408                 ATTR_27
18409                 (OFFSET, MASK, VALUE)      (0XFD48006C, 0x00000738U ,0x00000100U)
18410                 RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK |  0 );
18411
18412                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
18413                         | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
18414                         |  0 ) & RegMask); */
18415                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U);
18416         /*############################################################################################################################ */
18417
18418                 /*Register : ATTR_50 @ 0XFD4800C8</p>
18419
18420                 Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
18421                 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
18422                 tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
18423                 gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
18424                 PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE                          4
18425
18426                 PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
18427                 lity.; EP=0x009C; RP=0x0000
18428                 PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR                                   0
18429
18430                 ATTR_50
18431                 (OFFSET, MASK, VALUE)      (0XFD4800C8, 0x0000FFF0U ,0x00000040U)
18432                 RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK |  0 );
18433
18434                 RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
18435                         | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
18436                         |  0 ) & RegMask); */
18437                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U);
18438         /*############################################################################################################################ */
18439
18440                 /*Register : ATTR_105 @ 0XFD4801A4</p>
18441
18442                 Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
18443                 ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
18444                 PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD                              0xCD
18445
18446                 ATTR_105
18447                 (OFFSET, MASK, VALUE)      (0XFD4801A4, 0x000007FFU ,0x000000CDU)
18448                 RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK |  0 );
18449
18450                 RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
18451                         |  0 ) & RegMask); */
18452                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU);
18453         /*############################################################################################################################ */
18454
18455                 /*Register : ATTR_106 @ 0XFD4801A8</p>
18456
18457                 Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non
18458                 osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
18459                 PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH                              0x24
18460
18461                 Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
18462                 a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
18463                 completion header credits must be <= 80; EP=0x0004; RP=0x000C
18464                 PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH                             0xC
18465
18466                 ATTR_106
18467                 (OFFSET, MASK, VALUE)      (0XFD4801A8, 0x00003FFFU ,0x00000624U)
18468                 RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK |  0 );
18469
18470                 RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
18471                         | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
18472                         |  0 ) & RegMask); */
18473                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U);
18474         /*############################################################################################################################ */
18475
18476                 /*Register : ATTR_107 @ 0XFD4801AC</p>
18477
18478                 Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data
18479                 redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
18480                 d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
18481                 less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
18482                 PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD                             0x18
18483
18484                 ATTR_107
18485                 (OFFSET, MASK, VALUE)      (0XFD4801AC, 0x000007FFU ,0x00000018U)
18486                 RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK |  0 );
18487
18488                 RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
18489                         |  0 ) & RegMask); */
18490                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U);
18491         /*############################################################################################################################ */
18492
18493                 /*Register : ATTR_108 @ 0XFD4801B0</p>
18494
18495                 Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less
18496                 han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
18497                 PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD                              0xB5
18498
18499                 ATTR_108
18500                 (OFFSET, MASK, VALUE)      (0XFD4801B0, 0x000007FFU ,0x000000B5U)
18501                 RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK |  0 );
18502
18503                 RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
18504                         |  0 ) & RegMask); */
18505                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U);
18506         /*############################################################################################################################ */
18507
18508                 /*Register : ATTR_109 @ 0XFD4801B4</p>
18509
18510                 Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
18511                 0
18512                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV                                      0x0
18513
18514                 Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
18515                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM                                    0x1
18516
18517                 Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
18518                 cap structure; EP=0x0003; RP=0x0003
18519                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK                                         0x3
18520
18521                 Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
18522                 mber of brams configured for transmit; EP=0x001C; RP=0x001C
18523                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET                                 0x1c
18524
18525                 Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
18526                 d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
18527                 PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH                              0x20
18528
18529                 ATTR_109
18530                 (OFFSET, MASK, VALUE)      (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)
18531                 RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK |  0 );
18532
18533                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
18534                         | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
18535                         | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
18536                         | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
18537                         | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
18538                         |  0 ) & RegMask); */
18539                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U);
18540         /*############################################################################################################################ */
18541
18542                 /*Register : ATTR_34 @ 0XFD480088</p>
18543
18544                 Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
18545                 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
18546                 PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE                                        0x1
18547
18548                 ATTR_34
18549                 (OFFSET, MASK, VALUE)      (0XFD480088, 0x000000FFU ,0x00000001U)
18550                 RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK |  0 );
18551
18552                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
18553                         |  0 ) & RegMask); */
18554                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U);
18555         /*############################################################################################################################ */
18556
18557                 /*Register : ATTR_53 @ 0XFD4800D4</p>
18558
18559                 PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
18560                 ty.; EP=0x0048; RP=0x0060
18561                 PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR                                     0x60
18562
18563                 ATTR_53
18564                 (OFFSET, MASK, VALUE)      (0XFD4800D4, 0x000000FFU ,0x00000060U)
18565                 RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK |  0 );
18566
18567                 RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
18568                         |  0 ) & RegMask); */
18569                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U);
18570         /*############################################################################################################################ */
18571
18572                 /*Register : ATTR_41 @ 0XFD4800A4</p>
18573
18574                 MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
18575                  to Cap structure; EP=0x0000; RP=0x0000
18576                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE                 0x0
18577
18578                 Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
18579                 he management port.; EP=0x0001; RP=0x0000
18580                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
18581
18582                 MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
18583                 ity.; EP=0x0060; RP=0x0000
18584                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR                                    0x0
18585
18586                 Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or
18587                 he management port.; EP=0x0001; RP=0x0000
18588                 PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
18589
18590                 ATTR_41
18591                 (OFFSET, MASK, VALUE)      (0XFD4800A4, 0x000003FFU ,0x00000000U)
18592                 RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK |  0 );
18593
18594                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
18595                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
18596                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
18597                         | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
18598                         |  0 ) & RegMask); */
18599                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U);
18600         /*############################################################################################################################ */
18601
18602                 /*Register : ATTR_97 @ 0XFD480184</p>
18603
18604                 Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
18605                 PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH                            0x1
18606
18607                 Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
18608                 4; RP=0x0004
18609                 PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH                               0x1
18610
18611                 ATTR_97
18612                 (OFFSET, MASK, VALUE)      (0XFD480184, 0x00000FFFU ,0x00000041U)
18613                 RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK |  0 );
18614
18615                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
18616                         | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
18617                         |  0 ) & RegMask); */
18618                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U);
18619         /*############################################################################################################################ */
18620
18621                 /*Register : ATTR_100 @ 0XFD480190</p>
18622
18623                 TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
18624                 PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING                                   0x0
18625
18626                 ATTR_100
18627                 (OFFSET, MASK, VALUE)      (0XFD480190, 0x00000040U ,0x00000000U)
18628                 RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK |  0 );
18629
18630                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
18631                         |  0 ) & RegMask); */
18632                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U);
18633         /*############################################################################################################################ */
18634
18635                 /*Register : ATTR_101 @ 0XFD480194</p>
18636
18637                 Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message
18638                 LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
18639                 Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
18640                 EP=0x0000; RP=0x07FF
18641                 PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE                                  0x7FF
18642
18643                 Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
18644                 PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING                             0x1
18645
18646                 ATTR_101
18647                 (OFFSET, MASK, VALUE)      (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)
18648                 RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK |  0 );
18649
18650                 RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
18651                         | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
18652                         |  0 ) & RegMask); */
18653                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U);
18654         /*############################################################################################################################ */
18655
18656                 /*Register : ATTR_37 @ 0XFD480094</p>
18657
18658                 Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
18659                 Required for Root.; EP=0x0000; RP=0x0001
18660                 PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP           0x1
18661
18662                 ATTR_37
18663                 (OFFSET, MASK, VALUE)      (0XFD480094, 0x00000200U ,0x00000200U)
18664                 RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK |  0 );
18665
18666                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
18667                         |  0 ) & RegMask); */
18668                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00000200U ,0x00000200U);
18669         /*############################################################################################################################ */
18670
18671                 /*Register : ATTR_93 @ 0XFD480174</p>
18672
18673                 Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
18674                 _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
18675                 PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN                               0x1
18676
18677                 Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
18678                 TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
18679                 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
18680                 PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT                                  0x1000
18681
18682                 ATTR_93
18683                 (OFFSET, MASK, VALUE)      (0XFD480174, 0x0000FFFFU ,0x00009000U)
18684                 RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK |  0 );
18685
18686                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
18687                         | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
18688                         |  0 ) & RegMask); */
18689                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U);
18690         /*############################################################################################################################ */
18691
18692                 /*Register : ID @ 0XFD480200</p>
18693
18694                 Device ID for the the PCIe Cap Structure Device ID field
18695                 PSU_PCIE_ATTRIB_ID_CFG_DEV_ID                                                   0xd021
18696
18697                 Vendor ID for the PCIe Cap Structure Vendor ID field
18698                 PSU_PCIE_ATTRIB_ID_CFG_VEND_ID                                                  0x10ee
18699
18700                 ID
18701                 (OFFSET, MASK, VALUE)      (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)
18702                 RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK |  0 );
18703
18704                 RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
18705                         | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
18706                         |  0 ) & RegMask); */
18707                 PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U);
18708         /*############################################################################################################################ */
18709
18710                 /*Register : SUBSYS_ID @ 0XFD480204</p>
18711
18712                 Subsystem ID for the the PCIe Cap Structure Subsystem ID field
18713                 PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID                                         0x7
18714
18715                 Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
18716                 PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID                                    0x10ee
18717
18718                 SUBSYS_ID
18719                 (OFFSET, MASK, VALUE)      (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)
18720                 RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK |  0 );
18721
18722                 RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
18723                         | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
18724                         |  0 ) & RegMask); */
18725                 PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U);
18726         /*############################################################################################################################ */
18727
18728                 /*Register : REV_ID @ 0XFD480208</p>
18729
18730                 Revision ID for the the PCIe Cap Structure
18731                 PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID                                               0x0
18732
18733                 REV_ID
18734                 (OFFSET, MASK, VALUE)      (0XFD480208, 0x000000FFU ,0x00000000U)
18735                 RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK |  0 );
18736
18737                 RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
18738                         |  0 ) & RegMask); */
18739                 PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U);
18740         /*############################################################################################################################ */
18741
18742                 /*Register : ATTR_24 @ 0XFD480060</p>
18743
18744                 Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
18745                 8000; RP=0x8000
18746                 PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE                                         0x400
18747
18748                 ATTR_24
18749                 (OFFSET, MASK, VALUE)      (0XFD480060, 0x0000FFFFU ,0x00000400U)
18750                 RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK |  0 );
18751
18752                 RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
18753                         |  0 ) & RegMask); */
18754                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U);
18755         /*############################################################################################################################ */
18756
18757                 /*Register : ATTR_25 @ 0XFD480064</p>
18758
18759                 Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
18760                 0005; RP=0x0006
18761                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE                                         0x6
18762
18763                 INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
18764                 PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED                               0
18765
18766                 ATTR_25
18767                 (OFFSET, MASK, VALUE)      (0XFD480064, 0x000001FFU ,0x00000006U)
18768                 RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK |  0 );
18769
18770                 RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
18771                         | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
18772                         |  0 ) & RegMask); */
18773                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U);
18774         /*############################################################################################################################ */
18775
18776                 /*Register : ATTR_4 @ 0XFD480010</p>
18777
18778                 Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
18779                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
18780                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001
18781                 PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
18782
18783                 Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or
18784                 he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
18785                 ges are sent if an error is detected).; EP=0x0001; RP=0x0001
18786                 PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
18787
18788                 ATTR_4
18789                 (OFFSET, MASK, VALUE)      (0XFD480010, 0x00001000U ,0x00000000U)
18790                 RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK |  0 );
18791
18792                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
18793                         | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
18794                         |  0 ) & RegMask); */
18795                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U);
18796         /*############################################################################################################################ */
18797
18798                 /*Register : ATTR_89 @ 0XFD480164</p>
18799
18800                 VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
18801                 0x0140; RP=0x0140
18802                 PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR                                   0
18803
18804                 ATTR_89
18805                 (OFFSET, MASK, VALUE)      (0XFD480164, 0x00001FFEU ,0x00000000U)
18806                 RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK |  0 );
18807
18808                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
18809                         |  0 ) & RegMask); */
18810                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U);
18811         /*############################################################################################################################ */
18812
18813                 /*Register : ATTR_79 @ 0XFD48013C</p>
18814
18815                 CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
18816                 PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY                         1
18817
18818                 ATTR_79
18819                 (OFFSET, MASK, VALUE)      (0XFD48013C, 0x00000020U ,0x00000020U)
18820                 RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK |  0 );
18821
18822                 RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
18823                         |  0 ) & RegMask); */
18824                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U);
18825         /*############################################################################################################################ */
18826
18827                 /*Register : ATTR_43 @ 0XFD4800AC</p>
18828
18829                 Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
18830                  the management port.; EP=0x0001; RP=0x0000
18831                 PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON                                        0
18832
18833                 ATTR_43
18834                 (OFFSET, MASK, VALUE)      (0XFD4800AC, 0x00000100U ,0x00000000U)
18835                 RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK |  0 );
18836
18837                 RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
18838                         |  0 ) & RegMask); */
18839                 PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
18840         /*############################################################################################################################ */
18841
18842
18843   return 1;
18844 }
18845 unsigned long psu_resetin_init_data() {
18846                 // : PUTTING SERDES PERIPHERAL IN RESET
18847                 // : PUTTING USB0 IN RESET
18848                 /*Register : RST_LPD_TOP @ 0XFF5E023C</p>
18849
18850                 USB 0 reset for control registers
18851                 PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
18852
18853                 USB 0 sleep circuit reset
18854                 PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
18855
18856                 USB 0 reset
18857                 PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
18858
18859                 Software control register for the LPD block.
18860                 (OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)
18861                 RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
18862
18863                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
18864                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
18865                         | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
18866                         |  0 ) & RegMask); */
18867                 PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
18868         /*############################################################################################################################ */
18869
18870                 // : PUTTING GEM0 IN RESET
18871                 /*Register : RST_LPD_IOU0 @ 0XFF5E0230</p>
18872
18873                 GEM 3 reset
18874                 PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
18875
18876                 Software controlled reset for the GEMs
18877                 (OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)
18878                 RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
18879
18880                 RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
18881                         |  0 ) & RegMask); */
18882                 PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U);
18883         /*############################################################################################################################ */
18884
18885                 // : PUTTING SATA IN RESET
18886                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
18887
18888                 Sata block level reset
18889                 PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
18890
18891                 FPD Block level software controlled reset
18892                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)
18893                 RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
18894
18895                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
18896                         |  0 ) & RegMask); */
18897                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
18898         /*############################################################################################################################ */
18899
18900                 // : PUTTING PCIE IN RESET
18901                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
18902
18903                 PCIE config reset
18904                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X1
18905
18906                 PCIE control block level reset
18907                 PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X1
18908
18909                 PCIE bridge block level reset (AXI interface)
18910                 PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X1
18911
18912                 FPD Block level software controlled reset
18913                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x000E0000U)
18914                 RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
18915
18916                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
18917                         | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
18918                         | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
18919                         |  0 ) & RegMask); */
18920                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U);
18921         /*############################################################################################################################ */
18922
18923                 // : PUTTING DP IN RESET
18924                 /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238</p>
18925
18926                 Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] -
18927                 ane0 Bits [3:2] - lane 1
18928                 PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
18929
18930                 Control PHY Power down
18931                 (OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)
18932                 RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
18933
18934                 RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
18935                         |  0 ) & RegMask); */
18936                 PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU);
18937         /*############################################################################################################################ */
18938
18939                 /*Register : DP_PHY_RESET @ 0XFD4A0200</p>
18940
18941                 Set to '1' to hold the GT in reset. Clear to release.
18942                 PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
18943
18944                 Reset the transmitter PHY.
18945                 (OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)
18946                 RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
18947
18948                 RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT
18949                         |  0 ) & RegMask); */
18950                 PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U);
18951         /*############################################################################################################################ */
18952
18953                 /*Register : RST_FPD_TOP @ 0XFD1A0100</p>
18954
18955                 Display Port block level reset (includes DPDMA)
18956                 PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
18957
18958                 FPD Block level software controlled reset
18959                 (OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)
18960                 RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
18961
18962                 RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
18963                         |  0 ) & RegMask); */
18964                 PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U);
18965         /*############################################################################################################################ */
18966
18967
18968   return 1;
18969 }
18970 unsigned long psu_ps_pl_isolation_removal_data() {
18971                 // : PS-PL POWER UP REQUEST
18972                 /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118</p>
18973
18974                 Power-up Request Interrupt Enable for PL
18975                 PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
18976
18977                 Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
18978                 (OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)
18979                 RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK |  0 );
18980
18981                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
18982                         |  0 ) & RegMask); */
18983                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U);
18984         /*############################################################################################################################ */
18985
18986                 /*Register : REQ_PWRUP_TRIG @ 0XFFD80120</p>
18987
18988                 Power-up Request Trigger for PL
18989                 PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
18990
18991                 Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
18992                 (OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)
18993                 RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK |  0 );
18994
18995                 RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
18996                         |  0 ) & RegMask); */
18997                 PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U);
18998         /*############################################################################################################################ */
18999
19000                 // : POLL ON PL POWER STATUS
19001                 /*Register : REQ_PWRUP_STATUS @ 0XFFD80110</p>
19002
19003                 Power-up Request Status for PL
19004                 PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
19005                 (OFFSET, MASK, VALUE)      (0XFFD80110, 0x00800000U ,0x00000000U)  */
19006                 mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U);
19007
19008         /*############################################################################################################################ */
19009
19010
19011   return 1;
19012 }
19013 unsigned long psu_ps_pl_reset_config_data() {
19014                 // : PS PL RESET SEQUENCE
19015                 // : FABRIC RESET USING EMIO
19016                 /*Register : MASK_DATA_5_MSW @ 0XFF0A002C</p>
19017
19018                 Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
19019                 PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
19020
19021                 Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
19022                 (OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)
19023                 RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );
19024
19025                 RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
19026                         |  0 ) & RegMask); */
19027                 PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);
19028         /*############################################################################################################################ */
19029
19030                 /*Register : DIRM_5 @ 0XFF0A0344</p>
19031
19032                 Operation is the same as DIRM_0[DIRECTION_0]
19033                 PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
19034
19035                 Direction mode (GPIO Bank5, EMIO)
19036                 (OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)
19037                 RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );
19038
19039                 RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT
19040                         |  0 ) & RegMask); */
19041                 PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
19042         /*############################################################################################################################ */
19043
19044                 /*Register : OEN_5 @ 0XFF0A0348</p>
19045
19046                 Operation is the same as OEN_0[OP_ENABLE_0]
19047                 PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
19048
19049                 Output enable (GPIO Bank5, EMIO)
19050                 (OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)
19051                 RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );
19052
19053                 RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT
19054                         |  0 ) & RegMask); */
19055                 PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
19056         /*############################################################################################################################ */
19057
19058                 /*Register : DATA_5 @ 0XFF0A0054</p>
19059
19060                 Output Data
19061                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
19062
19063                 Output Data (GPIO Bank5, EMIO)
19064                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
19065                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
19066
19067                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
19068                         |  0 ) & RegMask); */
19069                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
19070         /*############################################################################################################################ */
19071
19072                 mask_delay(1);
19073
19074         /*############################################################################################################################ */
19075
19076                 // : FABRIC RESET USING DATA_5 TOGGLE
19077                 /*Register : DATA_5 @ 0XFF0A0054</p>
19078
19079                 Output Data
19080                 PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
19081
19082                 Output Data (GPIO Bank5, EMIO)
19083                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)
19084                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
19085
19086                 RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT
19087                         |  0 ) & RegMask); */
19088                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);
19089         /*############################################################################################################################ */
19090
19091                 mask_delay(1);
19092
19093         /*############################################################################################################################ */
19094
19095                 // : FABRIC RESET USING DATA_5 TOGGLE
19096                 /*Register : DATA_5 @ 0XFF0A0054</p>
19097
19098                 Output Data
19099                 PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
19100
19101                 Output Data (GPIO Bank5, EMIO)
19102                 (OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)
19103                 RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
19104
19105                 RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
19106                         |  0 ) & RegMask); */
19107                 PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
19108         /*############################################################################################################################ */
19109
19110
19111   return 1;
19112 }
19113
19114 unsigned long psu_ddr_phybringup_data() {
19115
19116
19117                 unsigned int regval = 0;
19118         Xil_Out32(0xFD090000U, 0x0000A845U);
19119         Xil_Out32(0xFD090004U, 0x003FFFFFU);
19120         Xil_Out32(0xFD09000CU, 0x00000010U);
19121         Xil_Out32(0xFD090010U, 0x00000010U);
19122         // PHY BRINGUP SEQ
19123         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000000FU);
19124         prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
19125         //poll for PHY initialization to complete
19126         while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
19127
19128         Xil_Out32(0xFD0701B0U, 0x00000001U);
19129         Xil_Out32(0xFD070320U, 0x00000001U);
19130         while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U);
19131         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
19132          Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR
19133           regval = Xil_In32(0xFD080030); //PUB_PGSR0
19134           while(regval != 0x80000FFF){
19135              regval = Xil_In32(0xFD080030); //PUB_PGSR0
19136           }
19137
19138
19139  // Run Vref training in static read mode
19140         Xil_Out32(0xFD080200U, 0x110011C7U);
19141         Xil_Out32(0xFD080018U, 0x00F01EF2U);
19142         Xil_Out32(0xFD08001CU, 0x55AA0098U);
19143         Xil_Out32(0xFD08142CU, 0x00001830U);
19144         Xil_Out32(0xFD08146CU, 0x00001830U);
19145         Xil_Out32(0xFD0814ACU, 0x00001830U);
19146         Xil_Out32(0xFD0814ECU, 0x00001830U);
19147         Xil_Out32(0xFD08152CU, 0x00001830U);
19148
19149
19150          Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR
19151           regval = Xil_In32(0xFD080030); //PUB_PGSR0
19152           while((regval & 0x80004001) != 0x80004001){
19153              regval = Xil_In32(0xFD080030); //PUB_PGSR0
19154           }
19155
19156          // Vref training is complete, disabling static read mode
19157         Xil_Out32(0xFD080200U, 0x810011C7U);
19158         Xil_Out32(0xFD080018U, 0x00F12302U);
19159         Xil_Out32(0xFD08001CU, 0x55AA0080U);
19160         Xil_Out32(0xFD08142CU, 0x00001800U);
19161         Xil_Out32(0xFD08146CU, 0x00001800U);
19162         Xil_Out32(0xFD0814ACU, 0x00001800U);
19163         Xil_Out32(0xFD0814ECU, 0x00001800U);
19164         Xil_Out32(0xFD08152CU, 0x00001800U);
19165         Xil_Out32(0xFD070180U, 0x01000040U);
19166         Xil_Out32(0xFD070060U, 0x00000000U);
19167         prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
19168
19169 return 1;
19170 }
19171
19172 /**
19173  * CRL_APB Base Address
19174  */
19175 #define CRL_APB_BASEADDR      0XFF5E0000U
19176 #define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
19177 #define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
19178 #define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
19179 #define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
19180 #define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
19181
19182 /**
19183  * CRF_APB Base Address
19184  */
19185 #define CRF_APB_BASEADDR      0XFD1A0000U
19186
19187 #define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
19188 #define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
19189 #define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
19190 #define PSU_MASK_POLL_TIME 1100000
19191
19192
19193 int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
19194         volatile u32 *addr = (volatile u32*) add;
19195         int i = 0;
19196         while ((*addr & mask)!= value) {
19197                 if (i == PSU_MASK_POLL_TIME) {
19198                         return 0;
19199                 }
19200                 i++;
19201         }
19202         return 1;
19203         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
19204 }
19205
19206 int mask_poll(u32 add , u32 mask) {
19207         volatile u32 *addr = (volatile u32*) add;
19208         int i = 0;
19209         while (!(*addr & mask)) {
19210                 if (i == PSU_MASK_POLL_TIME) {
19211                         return 0;
19212                 }
19213                 i++;
19214         }
19215         return 1;
19216         //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
19217 }
19218
19219 void mask_delay(u32 delay) {
19220     usleep (delay);
19221 }
19222
19223 u32 mask_read(u32 add , u32 mask ) {
19224         volatile u32 *addr = (volatile u32*) add;
19225         u32 val = (*addr & mask);
19226         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
19227         return val;
19228 }
19229
19230
19231 //Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES.
19232 //These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are
19233 //required for current silicon version and are likely to undergo further changes with subsequent silicon versions.
19234
19235
19236
19237 int serdes_fixcal_code() {
19238         int MaskStatus = 1;
19239
19240    // L3_TM_CALIB_DIG19
19241    Xil_Out32(0xFD40EC4C,0x00000020);
19242    //ICM_CFG0
19243    Xil_Out32(0xFD410010,0x00000001);
19244
19245    //is calibration done, polling on L3_CALIB_DONE_STATUS
19246    MaskStatus = mask_poll(0xFD40EF14, 0x2);
19247
19248    if (MaskStatus == 0)
19249    {
19250         xil_printf("SERDES initialization timed out\n\r");
19251    }
19252
19253    unsigned int tmp_0_1;
19254    tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
19255
19256    unsigned int tmp_0_2 = tmp_0_1 & (0x7);
19257    unsigned int tmp_0_3 = tmp_0_1 & (0x38);
19258    //Configure ICM for de-asserting CMN_Resetn
19259    Xil_Out32(0xFD410010,0x00000000);
19260    Xil_Out32(0xFD410014,0x00000000);
19261
19262    unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1);
19263    tmp_0_2_mod = (tmp_0_2_mod <<4);
19264
19265    tmp_0_3 = tmp_0_3 >>3;
19266    Xil_Out32(0xFD40EC4C,tmp_0_3);
19267
19268    //L3_TM_CALIB_DIG18
19269    Xil_Out32(0xFD40EC48,tmp_0_2_mod);
19270    return MaskStatus;
19271
19272
19273 }
19274
19275 int serdes_enb_coarse_saturation() {
19276   //Enable PLL Coarse Code saturation Logic
19277    Xil_Out32(0xFD402094,0x00000010);
19278    Xil_Out32(0xFD406094,0x00000010);
19279    Xil_Out32(0xFD40A094,0x00000010);
19280    Xil_Out32(0xFD40E094,0x00000010);
19281    return 1;
19282 }
19283
19284 int init_serdes() {
19285         int status = 1;
19286         status &=  psu_resetin_init_data();
19287
19288         status &= serdes_fixcal_code();
19289         status &= serdes_enb_coarse_saturation();
19290
19291     status &=  psu_serdes_init_data();
19292         status &=  psu_resetout_init_data();
19293
19294         return status;
19295 }
19296
19297
19298
19299
19300
19301
19302 void init_peripheral()
19303 {
19304         unsigned int RegValue;
19305
19306         /* Turn on IOU Clock */
19307         //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
19308
19309         /* Release all resets in the IOU */
19310         Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
19311         Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
19312         Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
19313
19314         /* Activate GPU clocks */
19315         //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
19316
19317         /* Take LPD out of reset except R5 */
19318         RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
19319         RegValue &= 0x7;
19320         Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
19321
19322         /* Take most of FPD out of reset */
19323         Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
19324
19325         /* Making DPDMA as secure */
19326   unsigned int tmp_regval;
19327   tmp_regval = Xil_In32(0xFD690040);
19328   tmp_regval &= ~0x00000001;
19329   Xil_Out32(0xFD690040, tmp_regval);
19330
19331         /* Making PCIe as secure */
19332   tmp_regval = Xil_In32(0xFD690030);
19333   tmp_regval &= ~0x00000001;
19334   Xil_Out32(0xFD690030, tmp_regval);
19335 }
19336 int
19337 psu_init()
19338 {
19339         int status = 1;
19340         status &= psu_mio_init_data ();
19341         status &=   psu_pll_init_data ();
19342         status &=   psu_clock_init_data ();
19343
19344         status &=  psu_ddr_init_data ();
19345         status &=  psu_ddr_phybringup_data ();
19346         status &=  psu_peripherals_init_data ();
19347
19348         status &=  init_serdes();
19349         init_peripheral ();
19350
19351         status &=  psu_peripherals_powerdwn_data ();
19352
19353         if (status == 0) {
19354                 return 1;
19355         }
19356         return 0;
19357 }