2 ******************************************************************************
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3 * @file system_stm32f10x.c
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4 * @author MCD Application Team
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7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 ******************************************************************************
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10 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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12 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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14 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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18 ******************************************************************************
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21 /** @addtogroup CMSIS
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25 /** @addtogroup stm32f10x_system
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29 /** @addtogroup STM32F10x_System_Private_Includes
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33 #include "stm32f10x.h"
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39 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
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47 /** @addtogroup STM32F10x_System_Private_Defines
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51 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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52 frequency (after reset the HSI is used as SYSCLK source)
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56 1. After each device reset the HSI is used as System clock source.
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58 2. Please make sure that the selected System clock doesn't exceed your device's
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61 3. If none of the define below is enabled, the HSI is used as System clock
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64 4. The System clock configuration functions provided within this file assume that:
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65 - For Low, Medium and High density Value line devices an external 8MHz
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66 crystal is used to drive the System clock.
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67 - For Low, Medium and High density devices an external 8MHz crystal is
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68 used to drive the System clock.
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69 - For Connectivity line devices an external 25MHz crystal is used to drive
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71 If you are using different crystal you have to adapt those functions accordingly.
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74 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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75 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
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76 #define SYSCLK_FREQ_24MHz 24000000
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78 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
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79 /* #define SYSCLK_FREQ_24MHz 24000000 */
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80 /* #define SYSCLK_FREQ_36MHz 36000000 */
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81 /* #define SYSCLK_FREQ_48MHz 48000000 */
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82 /* #define SYSCLK_FREQ_56MHz 56000000 */
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83 #define SYSCLK_FREQ_72MHz 72000000
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86 /*!< Uncomment the following line if you need to use external SRAM mounted
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87 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
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88 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
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89 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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90 /* #define DATA_IN_ExtSRAM */
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93 /*!< Uncomment the following line if you need to relocate your vector Table in
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95 /* #define VECT_TAB_SRAM */
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96 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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97 This value must be a multiple of 0x100. */
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104 /** @addtogroup STM32F10x_System_Private_Macros
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112 /** @addtogroup STM32F10x_System_Private_Variables
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116 /*******************************************************************************
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117 * Clock Definitions
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118 *******************************************************************************/
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119 #ifdef SYSCLK_FREQ_HSE
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120 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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121 #elif defined SYSCLK_FREQ_24MHz
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122 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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123 #elif defined SYSCLK_FREQ_36MHz
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124 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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125 #elif defined SYSCLK_FREQ_48MHz
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126 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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127 #elif defined SYSCLK_FREQ_56MHz
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128 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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129 #elif defined SYSCLK_FREQ_72MHz
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130 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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131 #else /*!< HSI Selected as System Clock source */
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132 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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135 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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140 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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144 static void SetSysClock(void);
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146 #ifdef SYSCLK_FREQ_HSE
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147 static void SetSysClockToHSE(void);
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148 #elif defined SYSCLK_FREQ_24MHz
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149 static void SetSysClockTo24(void);
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150 #elif defined SYSCLK_FREQ_36MHz
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151 static void SetSysClockTo36(void);
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152 #elif defined SYSCLK_FREQ_48MHz
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153 static void SetSysClockTo48(void);
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154 #elif defined SYSCLK_FREQ_56MHz
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155 static void SetSysClockTo56(void);
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156 #elif defined SYSCLK_FREQ_72MHz
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157 static void SetSysClockTo72(void);
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160 #ifdef DATA_IN_ExtSRAM
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161 static void SystemInit_ExtMemCtl(void);
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162 #endif /* DATA_IN_ExtSRAM */
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168 /** @addtogroup STM32F10x_System_Private_Functions
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173 * @brief Setup the microcontroller system
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174 * Initialize the Embedded Flash Interface, the PLL and update the
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175 * SystemCoreClock variable.
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176 * @note This function should be used only after reset.
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180 void SystemInit (void)
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182 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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183 /* Set HSION bit */
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184 RCC->CR |= (uint32_t)0x00000001;
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186 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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187 #ifndef STM32F10X_CL
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188 RCC->CFGR &= (uint32_t)0xF8FF0000;
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190 RCC->CFGR &= (uint32_t)0xF0FF0000;
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191 #endif /* STM32F10X_CL */
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193 /* Reset HSEON, CSSON and PLLON bits */
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194 RCC->CR &= (uint32_t)0xFEF6FFFF;
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196 /* Reset HSEBYP bit */
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197 RCC->CR &= (uint32_t)0xFFFBFFFF;
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199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
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202 #ifdef STM32F10X_CL
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203 /* Reset PLL2ON and PLL3ON bits */
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204 RCC->CR &= (uint32_t)0xEBFFFFFF;
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206 /* Disable all interrupts and clear pending bits */
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207 RCC->CIR = 0x00FF0000;
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209 /* Reset CFGR2 register */
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210 RCC->CFGR2 = 0x00000000;
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211 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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212 /* Disable all interrupts and clear pending bits */
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213 RCC->CIR = 0x009F0000;
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215 /* Reset CFGR2 register */
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216 RCC->CFGR2 = 0x00000000;
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218 /* Disable all interrupts and clear pending bits */
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219 RCC->CIR = 0x009F0000;
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220 #endif /* STM32F10X_CL */
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222 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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223 #ifdef DATA_IN_ExtSRAM
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224 SystemInit_ExtMemCtl();
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225 #endif /* DATA_IN_ExtSRAM */
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228 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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229 /* Configure the Flash Latency cycles and enable prefetch buffer */
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232 #ifdef VECT_TAB_SRAM
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233 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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235 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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240 * @brief Update SystemCoreClock according to Clock Register Values
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245 void SystemCoreClockUpdate (void)
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247 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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249 #ifdef STM32F10X_CL
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250 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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251 #endif /* STM32F10X_CL */
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253 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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254 uint32_t prediv1factor = 0;
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255 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
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257 /* Get SYSCLK source -------------------------------------------------------*/
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258 tmp = RCC->CFGR & RCC_CFGR_SWS;
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262 case 0x00: /* HSI used as system clock */
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263 SystemCoreClock = HSI_VALUE;
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265 case 0x04: /* HSE used as system clock */
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266 SystemCoreClock = HSE_VALUE;
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268 case 0x08: /* PLL used as system clock */
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270 /* Get PLL clock source and multiplication factor ----------------------*/
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271 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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272 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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274 #ifndef STM32F10X_CL
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275 pllmull = ( pllmull >> 18) + 2;
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277 if (pllsource == 0x00)
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279 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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280 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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284 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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285 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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286 /* HSE oscillator clock selected as PREDIV1 clock entry */
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287 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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289 /* HSE selected as PLL clock entry */
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290 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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291 {/* HSE oscillator clock divided by 2 */
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292 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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296 SystemCoreClock = HSE_VALUE * pllmull;
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301 pllmull = pllmull >> 18;
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303 if (pllmull != 0x0D)
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308 { /* PLL multiplication factor = PLL input clock * 6.5 */
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312 if (pllsource == 0x00)
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314 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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315 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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318 {/* PREDIV1 selected as PLL clock entry */
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320 /* Get PREDIV1 clock source and division factor */
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321 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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322 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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324 if (prediv1source == 0)
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326 /* HSE oscillator clock selected as PREDIV1 clock entry */
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327 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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330 {/* PLL2 clock selected as PREDIV1 clock entry */
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332 /* Get PREDIV2 division factor and PLL2 multiplication factor */
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333 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
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334 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
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335 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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338 #endif /* STM32F10X_CL */
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342 SystemCoreClock = HSI_VALUE;
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346 /* Compute HCLK clock frequency ----------------*/
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347 /* Get HCLK prescaler */
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348 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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349 /* HCLK clock frequency */
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350 SystemCoreClock >>= tmp;
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354 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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358 static void SetSysClock(void)
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360 #ifdef SYSCLK_FREQ_HSE
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361 SetSysClockToHSE();
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362 #elif defined SYSCLK_FREQ_24MHz
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364 #elif defined SYSCLK_FREQ_36MHz
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366 #elif defined SYSCLK_FREQ_48MHz
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368 #elif defined SYSCLK_FREQ_56MHz
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369 SetSysClockTo56();
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370 #elif defined SYSCLK_FREQ_72MHz
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374 /* If none of the define above is enabled, the HSI is used as System clock
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375 source (default after reset) */
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379 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
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380 * before jump to __main
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384 #ifdef DATA_IN_ExtSRAM
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386 * @brief Setup the external memory controller.
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387 * Called in startup_stm32f10x_xx.s/.c before jump to main.
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388 * This function configures the external SRAM mounted on STM3210E-EVAL
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389 * board (STM32 High density devices). This SRAM will be used as program
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390 * data memory (including heap and stack).
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394 void SystemInit_ExtMemCtl(void)
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396 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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397 required, then adjust the Register Addresses */
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399 /* Enable FSMC clock */
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400 RCC->AHBENR = 0x00000114;
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402 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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403 RCC->APB2ENR = 0x000001E0;
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405 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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406 /*---------------- SRAM Address lines configuration -------------------------*/
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407 /*---------------- NOE and NWE configuration --------------------------------*/
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408 /*---------------- NE3 configuration ----------------------------------------*/
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409 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
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411 GPIOD->CRL = 0x44BB44BB;
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412 GPIOD->CRH = 0xBBBBBBBB;
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414 GPIOE->CRL = 0xB44444BB;
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415 GPIOE->CRH = 0xBBBBBBBB;
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417 GPIOF->CRL = 0x44BBBBBB;
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418 GPIOF->CRH = 0xBBBB4444;
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420 GPIOG->CRL = 0x44BBBBBB;
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421 GPIOG->CRH = 0x44444B44;
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423 /*---------------- FSMC Configuration ---------------------------------------*/
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424 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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426 FSMC_Bank1->BTCR[4] = 0x00001011;
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427 FSMC_Bank1->BTCR[5] = 0x00000200;
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429 #endif /* DATA_IN_ExtSRAM */
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431 #ifdef SYSCLK_FREQ_HSE
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433 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
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434 * and PCLK1 prescalers.
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435 * @note This function should be used only after reset.
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439 static void SetSysClockToHSE(void)
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441 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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443 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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445 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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447 /* Wait till HSE is ready and if Time out is reached exit */
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450 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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452 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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454 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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456 HSEStatus = (uint32_t)0x01;
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460 HSEStatus = (uint32_t)0x00;
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463 if (HSEStatus == (uint32_t)0x01)
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466 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
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467 /* Enable Prefetch Buffer */
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468 FLASH->ACR |= FLASH_ACR_PRFTBE;
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470 /* Flash 0 wait state */
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471 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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473 #ifndef STM32F10X_CL
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474 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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476 if (HSE_VALUE <= 24000000)
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478 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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482 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
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484 #endif /* STM32F10X_CL */
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487 /* HCLK = SYSCLK */
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488 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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491 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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494 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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496 /* Select HSE as system clock source */
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497 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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498 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
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500 /* Wait till HSE is used as system clock source */
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501 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
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506 { /* If HSE fails to start-up, the application will have wrong clock
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507 configuration. User can add here some code to deal with this error */
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510 #elif defined SYSCLK_FREQ_24MHz
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512 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
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513 * and PCLK1 prescalers.
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514 * @note This function should be used only after reset.
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518 static void SetSysClockTo24(void)
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520 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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522 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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524 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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526 /* Wait till HSE is ready and if Time out is reached exit */
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529 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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531 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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533 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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535 HSEStatus = (uint32_t)0x01;
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539 HSEStatus = (uint32_t)0x00;
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542 if (HSEStatus == (uint32_t)0x01)
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544 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
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545 /* Enable Prefetch Buffer */
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546 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
548 /* Flash 0 wait state */
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549 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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550 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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553 /* HCLK = SYSCLK */
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554 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
557 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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560 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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562 #ifdef STM32F10X_CL
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563 /* Configure PLLs ------------------------------------------------------*/
\r
564 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
\r
565 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
566 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
567 RCC_CFGR_PLLMULL6);
\r
569 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
570 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
\r
571 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
572 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
573 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
574 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
\r
577 RCC->CR |= RCC_CR_PLL2ON;
\r
578 /* Wait till PLL2 is ready */
\r
579 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
582 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
\r
583 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
\r
584 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
585 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
\r
587 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
\r
588 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
589 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
\r
590 #endif /* STM32F10X_CL */
\r
593 RCC->CR |= RCC_CR_PLLON;
\r
595 /* Wait till PLL is ready */
\r
596 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
600 /* Select PLL as system clock source */
\r
601 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
602 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
604 /* Wait till PLL is used as system clock source */
\r
605 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
610 { /* If HSE fails to start-up, the application will have wrong clock
\r
611 configuration. User can add here some code to deal with this error */
\r
614 #elif defined SYSCLK_FREQ_36MHz
\r
616 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
\r
617 * and PCLK1 prescalers.
\r
618 * @note This function should be used only after reset.
\r
622 static void SetSysClockTo36(void)
\r
624 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
626 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
628 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
630 /* Wait till HSE is ready and if Time out is reached exit */
\r
633 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
635 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
637 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
639 HSEStatus = (uint32_t)0x01;
\r
643 HSEStatus = (uint32_t)0x00;
\r
646 if (HSEStatus == (uint32_t)0x01)
\r
648 /* Enable Prefetch Buffer */
\r
649 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
651 /* Flash 1 wait state */
\r
652 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
653 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
655 /* HCLK = SYSCLK */
\r
656 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
659 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
662 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
664 #ifdef STM32F10X_CL
\r
665 /* Configure PLLs ------------------------------------------------------*/
\r
667 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
\r
668 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
669 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
670 RCC_CFGR_PLLMULL9);
\r
672 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
673 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
\r
675 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
676 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
677 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
678 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
\r
681 RCC->CR |= RCC_CR_PLL2ON;
\r
682 /* Wait till PLL2 is ready */
\r
683 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
688 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
\r
689 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
690 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
\r
691 #endif /* STM32F10X_CL */
\r
694 RCC->CR |= RCC_CR_PLLON;
\r
696 /* Wait till PLL is ready */
\r
697 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
701 /* Select PLL as system clock source */
\r
702 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
703 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
705 /* Wait till PLL is used as system clock source */
\r
706 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
711 { /* If HSE fails to start-up, the application will have wrong clock
\r
712 configuration. User can add here some code to deal with this error */
\r
715 #elif defined SYSCLK_FREQ_48MHz
\r
717 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
\r
718 * and PCLK1 prescalers.
\r
719 * @note This function should be used only after reset.
\r
723 static void SetSysClockTo48(void)
\r
725 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
727 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
729 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
731 /* Wait till HSE is ready and if Time out is reached exit */
\r
734 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
736 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
738 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
740 HSEStatus = (uint32_t)0x01;
\r
744 HSEStatus = (uint32_t)0x00;
\r
747 if (HSEStatus == (uint32_t)0x01)
\r
749 /* Enable Prefetch Buffer */
\r
750 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
752 /* Flash 1 wait state */
\r
753 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
754 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
756 /* HCLK = SYSCLK */
\r
757 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
760 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
763 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
765 #ifdef STM32F10X_CL
\r
766 /* Configure PLLs ------------------------------------------------------*/
\r
767 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
768 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
770 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
771 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
772 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
773 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
776 RCC->CR |= RCC_CR_PLL2ON;
\r
777 /* Wait till PLL2 is ready */
\r
778 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
783 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
\r
784 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
785 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
786 RCC_CFGR_PLLMULL6);
\r
788 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
\r
789 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
790 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
\r
791 #endif /* STM32F10X_CL */
\r
794 RCC->CR |= RCC_CR_PLLON;
\r
796 /* Wait till PLL is ready */
\r
797 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
801 /* Select PLL as system clock source */
\r
802 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
803 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
805 /* Wait till PLL is used as system clock source */
\r
806 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
811 { /* If HSE fails to start-up, the application will have wrong clock
\r
812 configuration. User can add here some code to deal with this error */
\r
816 #elif defined SYSCLK_FREQ_56MHz
\r
818 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
\r
819 * and PCLK1 prescalers.
\r
820 * @note This function should be used only after reset.
\r
824 static void SetSysClockTo56(void)
\r
826 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
828 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
830 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
832 /* Wait till HSE is ready and if Time out is reached exit */
\r
835 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
837 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
839 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
841 HSEStatus = (uint32_t)0x01;
\r
845 HSEStatus = (uint32_t)0x00;
\r
848 if (HSEStatus == (uint32_t)0x01)
\r
850 /* Enable Prefetch Buffer */
\r
851 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
853 /* Flash 2 wait state */
\r
854 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
855 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
857 /* HCLK = SYSCLK */
\r
858 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
861 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
864 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
866 #ifdef STM32F10X_CL
\r
867 /* Configure PLLs ------------------------------------------------------*/
\r
868 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
869 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
871 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
872 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
873 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
874 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
877 RCC->CR |= RCC_CR_PLL2ON;
\r
878 /* Wait till PLL2 is ready */
\r
879 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
884 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
\r
885 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
886 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
887 RCC_CFGR_PLLMULL7);
\r
889 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
\r
890 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
891 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
\r
893 #endif /* STM32F10X_CL */
\r
896 RCC->CR |= RCC_CR_PLLON;
\r
898 /* Wait till PLL is ready */
\r
899 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
903 /* Select PLL as system clock source */
\r
904 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
905 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
907 /* Wait till PLL is used as system clock source */
\r
908 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
913 { /* If HSE fails to start-up, the application will have wrong clock
\r
914 configuration. User can add here some code to deal with this error */
\r
918 #elif defined SYSCLK_FREQ_72MHz
\r
920 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
\r
921 * and PCLK1 prescalers.
\r
922 * @note This function should be used only after reset.
\r
926 static void SetSysClockTo72(void)
\r
928 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
930 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
932 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
934 /* Wait till HSE is ready and if Time out is reached exit */
\r
937 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
939 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
941 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
943 HSEStatus = (uint32_t)0x01;
\r
947 HSEStatus = (uint32_t)0x00;
\r
950 if (HSEStatus == (uint32_t)0x01)
\r
952 /* Enable Prefetch Buffer */
\r
953 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
955 /* Flash 2 wait state */
\r
956 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
957 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
960 /* HCLK = SYSCLK */
\r
961 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
964 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
967 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
969 #ifdef STM32F10X_CL
\r
970 /* Configure PLLs ------------------------------------------------------*/
\r
971 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
972 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
974 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
975 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
976 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
977 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
980 RCC->CR |= RCC_CR_PLL2ON;
\r
981 /* Wait till PLL2 is ready */
\r
982 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
987 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
\r
988 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
989 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
990 RCC_CFGR_PLLMULL9);
\r
992 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
\r
993 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
\r
994 RCC_CFGR_PLLMULL));
\r
995 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
\r
996 #endif /* STM32F10X_CL */
\r
999 RCC->CR |= RCC_CR_PLLON;
\r
1001 /* Wait till PLL is ready */
\r
1002 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
1006 /* Select PLL as system clock source */
\r
1007 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
1008 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
1010 /* Wait till PLL is used as system clock source */
\r
1011 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
1016 { /* If HSE fails to start-up, the application will have wrong clock
\r
1017 configuration. User can add here some code to deal with this error */
\r
1033 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r