1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32f10x_spi.h
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3 * Author : MCD Application Team
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6 * Description : This file contains all the functions prototypes for the
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7 * SPI firmware library.
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8 ********************************************************************************
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9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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15 *******************************************************************************/
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17 /* Define to prevent recursive inclusion -------------------------------------*/
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18 #ifndef __STM32F10x_SPI_H
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19 #define __STM32F10x_SPI_H
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_map.h"
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24 /* Exported types ------------------------------------------------------------*/
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25 /* SPI Init structure definition */
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34 u16 SPI_BaudRatePrescaler;
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36 u16 SPI_CRCPolynomial;
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39 /* I2S Init structure definition */
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50 /* Exported constants --------------------------------------------------------*/
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52 #define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \
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53 ((*(u32*)&(PERIPH)) == SPI2_BASE) || \
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54 ((*(u32*)&(PERIPH)) == SPI3_BASE))
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56 #define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \
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57 ((*(u32*)&(PERIPH)) == SPI3_BASE))
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59 /* SPI data direction mode */
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60 #define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
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61 #define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
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62 #define SPI_Direction_1Line_Rx ((u16)0x8000)
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63 #define SPI_Direction_1Line_Tx ((u16)0xC000)
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65 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
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66 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
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67 ((MODE) == SPI_Direction_1Line_Rx) || \
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68 ((MODE) == SPI_Direction_1Line_Tx))
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70 /* SPI master/slave mode */
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71 #define SPI_Mode_Master ((u16)0x0104)
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72 #define SPI_Mode_Slave ((u16)0x0000)
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74 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
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75 ((MODE) == SPI_Mode_Slave))
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78 #define SPI_DataSize_16b ((u16)0x0800)
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79 #define SPI_DataSize_8b ((u16)0x0000)
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81 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
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82 ((DATASIZE) == SPI_DataSize_8b))
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84 /* SPI Clock Polarity */
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85 #define SPI_CPOL_Low ((u16)0x0000)
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86 #define SPI_CPOL_High ((u16)0x0002)
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88 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
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89 ((CPOL) == SPI_CPOL_High))
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91 /* SPI Clock Phase */
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92 #define SPI_CPHA_1Edge ((u16)0x0000)
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93 #define SPI_CPHA_2Edge ((u16)0x0001)
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95 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
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96 ((CPHA) == SPI_CPHA_2Edge))
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98 /* SPI Slave Select management */
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99 #define SPI_NSS_Soft ((u16)0x0200)
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100 #define SPI_NSS_Hard ((u16)0x0000)
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102 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
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103 ((NSS) == SPI_NSS_Hard))
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105 /* SPI BaudRate Prescaler */
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106 #define SPI_BaudRatePrescaler_2 ((u16)0x0000)
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107 #define SPI_BaudRatePrescaler_4 ((u16)0x0008)
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108 #define SPI_BaudRatePrescaler_8 ((u16)0x0010)
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109 #define SPI_BaudRatePrescaler_16 ((u16)0x0018)
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110 #define SPI_BaudRatePrescaler_32 ((u16)0x0020)
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111 #define SPI_BaudRatePrescaler_64 ((u16)0x0028)
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112 #define SPI_BaudRatePrescaler_128 ((u16)0x0030)
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113 #define SPI_BaudRatePrescaler_256 ((u16)0x0038)
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115 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
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116 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
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117 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
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118 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
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119 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
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120 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
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121 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
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122 ((PRESCALER) == SPI_BaudRatePrescaler_256))
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124 /* SPI MSB/LSB transmission */
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125 #define SPI_FirstBit_MSB ((u16)0x0000)
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126 #define SPI_FirstBit_LSB ((u16)0x0080)
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128 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
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129 ((BIT) == SPI_FirstBit_LSB))
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132 #define I2S_Mode_SlaveTx ((u16)0x0000)
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133 #define I2S_Mode_SlaveRx ((u16)0x0100)
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134 #define I2S_Mode_MasterTx ((u16)0x0200)
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135 #define I2S_Mode_MasterRx ((u16)0x0300)
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137 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
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138 ((MODE) == I2S_Mode_SlaveRx) || \
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139 ((MODE) == I2S_Mode_MasterTx) || \
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140 ((MODE) == I2S_Mode_MasterRx) )
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143 #define I2S_Standard_Phillips ((u16)0x0000)
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144 #define I2S_Standard_MSB ((u16)0x0010)
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145 #define I2S_Standard_LSB ((u16)0x0020)
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146 #define I2S_Standard_PCMShort ((u16)0x0030)
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147 #define I2S_Standard_PCMLong ((u16)0x00B0)
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149 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
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150 ((STANDARD) == I2S_Standard_MSB) || \
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151 ((STANDARD) == I2S_Standard_LSB) || \
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152 ((STANDARD) == I2S_Standard_PCMShort) || \
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153 ((STANDARD) == I2S_Standard_PCMLong))
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155 /* I2S Data Format */
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156 #define I2S_DataFormat_16b ((u16)0x0000)
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157 #define I2S_DataFormat_16bextended ((u16)0x0001)
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158 #define I2S_DataFormat_24b ((u16)0x0003)
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159 #define I2S_DataFormat_32b ((u16)0x0005)
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161 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
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162 ((FORMAT) == I2S_DataFormat_16bextended) || \
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163 ((FORMAT) == I2S_DataFormat_24b) || \
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164 ((FORMAT) == I2S_DataFormat_32b))
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166 /* I2S MCLK Output */
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167 #define I2S_MCLKOutput_Enable ((u16)0x0200)
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168 #define I2S_MCLKOutput_Disable ((u16)0x0000)
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170 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
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171 ((OUTPUT) == I2S_MCLKOutput_Disable))
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173 /* I2S Audio Frequency */
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174 #define I2S_AudioFreq_48k ((u16)48000)
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175 #define I2S_AudioFreq_44k ((u16)44100)
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176 #define I2S_AudioFreq_22k ((u16)22050)
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177 #define I2S_AudioFreq_16k ((u16)16000)
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178 #define I2S_AudioFreq_8k ((u16)8000)
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179 #define I2S_AudioFreq_Default ((u16)2)
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181 #define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
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182 ((FREQ) == I2S_AudioFreq_44k) || \
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183 ((FREQ) == I2S_AudioFreq_22k) || \
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184 ((FREQ) == I2S_AudioFreq_16k) || \
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185 ((FREQ) == I2S_AudioFreq_8k) || \
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186 ((FREQ) == I2S_AudioFreq_Default))
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188 /* I2S Clock Polarity */
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189 #define I2S_CPOL_Low ((u16)0x0000)
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190 #define I2S_CPOL_High ((u16)0x0008)
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192 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
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193 ((CPOL) == I2S_CPOL_High))
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195 /* SPI_I2S DMA transfer requests */
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196 #define SPI_I2S_DMAReq_Tx ((u16)0x0002)
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197 #define SPI_I2S_DMAReq_Rx ((u16)0x0001)
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199 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
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201 /* SPI NSS internal software mangement */
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202 #define SPI_NSSInternalSoft_Set ((u16)0x0100)
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203 #define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
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205 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
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206 ((INTERNAL) == SPI_NSSInternalSoft_Reset))
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208 /* SPI CRC Transmit/Receive */
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209 #define SPI_CRC_Tx ((u8)0x00)
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210 #define SPI_CRC_Rx ((u8)0x01)
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212 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
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214 /* SPI direction transmit/receive */
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215 #define SPI_Direction_Rx ((u16)0xBFFF)
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216 #define SPI_Direction_Tx ((u16)0x4000)
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218 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
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219 ((DIRECTION) == SPI_Direction_Tx))
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221 /* SPI_I2S interrupts definition */
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222 #define SPI_I2S_IT_TXE ((u8)0x71)
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223 #define SPI_I2S_IT_RXNE ((u8)0x60)
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224 #define SPI_I2S_IT_ERR ((u8)0x50)
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226 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
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227 ((IT) == SPI_I2S_IT_RXNE) || \
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228 ((IT) == SPI_I2S_IT_ERR))
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230 #define SPI_I2S_IT_OVR ((u8)0x56)
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231 #define SPI_IT_MODF ((u8)0x55)
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232 #define SPI_IT_CRCERR ((u8)0x54)
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233 #define I2S_IT_UDR ((u8)0x53)
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235 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_I2S_IT_OVR) || \
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236 ((IT) == SPI_IT_MODF) || \
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237 ((IT) == SPI_IT_CRCERR) || \
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238 ((IT) == I2S_IT_UDR))
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240 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
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241 ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
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242 ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
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244 /* SPI_I2S flags definition */
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245 #define SPI_I2S_FLAG_RXNE ((u16)0x0001)
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246 #define SPI_I2S_FLAG_TXE ((u16)0x0002)
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247 #define I2S_FLAG_CHSIDE ((u16)0x0004)
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248 #define I2S_FLAG_UDR ((u16)0x0008)
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249 #define SPI_FLAG_CRCERR ((u16)0x0010)
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250 #define SPI_FLAG_MODF ((u16)0x0020)
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251 #define SPI_I2S_FLAG_OVR ((u16)0x0040)
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252 #define SPI_I2S_FLAG_BSY ((u16)0x0080)
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254 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_OVR) || ((FLAG) == SPI_FLAG_MODF) || \
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255 ((FLAG) == SPI_FLAG_CRCERR) || ((FLAG) == I2S_FLAG_UDR))
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256 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
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257 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
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258 ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
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259 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
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261 /* SPI CRC polynomial --------------------------------------------------------*/
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262 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
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264 /* Exported macro ------------------------------------------------------------*/
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265 /* Exported functions ------------------------------------------------------- */
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266 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
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267 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
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268 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
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269 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
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270 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
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271 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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272 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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273 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);
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274 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);
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275 void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);
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276 u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
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277 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
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278 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
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279 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
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280 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
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281 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
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282 u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
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283 u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
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284 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
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285 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
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286 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
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287 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
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288 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
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290 #endif /*__STM32F10x_SPI_H */
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292 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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