1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_rcc.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file contains all the functions prototypes for the
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6 * RCC firmware library.
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7 ********************************************************************************
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12 ********************************************************************************
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13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 *******************************************************************************/
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef __STM32F10x_RCC_H
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23 #define __STM32F10x_RCC_H
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25 /* Includes ------------------------------------------------------------------*/
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26 #include "stm32f10x_map.h"
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28 /* Exported types ------------------------------------------------------------*/
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31 u32 SYSCLK_Frequency;
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33 u32 PCLK1_Frequency;
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34 u32 PCLK2_Frequency;
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35 u32 ADCCLK_Frequency;
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38 /* Exported constants --------------------------------------------------------*/
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39 /* HSE configuration */
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40 #define RCC_HSE_OFF ((u32)0x00000000)
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41 #define RCC_HSE_ON ((u32)0x00010000)
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42 #define RCC_HSE_Bypass ((u32)0x00040000)
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44 #define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \
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45 (HSE == RCC_HSE_Bypass))
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47 /* PLL entry clock source */
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48 #define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
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49 #define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
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50 #define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
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52 #define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \
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53 (SOURCE == RCC_PLLSource_HSE_Div1) || \
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54 (SOURCE == RCC_PLLSource_HSE_Div2))
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56 /* PLL multiplication factor */
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57 #define RCC_PLLMul_2 ((u32)0x00000000)
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58 #define RCC_PLLMul_3 ((u32)0x00040000)
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59 #define RCC_PLLMul_4 ((u32)0x00080000)
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60 #define RCC_PLLMul_5 ((u32)0x000C0000)
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61 #define RCC_PLLMul_6 ((u32)0x00100000)
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62 #define RCC_PLLMul_7 ((u32)0x00140000)
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63 #define RCC_PLLMul_8 ((u32)0x00180000)
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64 #define RCC_PLLMul_9 ((u32)0x001C0000)
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65 #define RCC_PLLMul_10 ((u32)0x00200000)
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66 #define RCC_PLLMul_11 ((u32)0x00240000)
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67 #define RCC_PLLMul_12 ((u32)0x00280000)
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68 #define RCC_PLLMul_13 ((u32)0x002C0000)
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69 #define RCC_PLLMul_14 ((u32)0x00300000)
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70 #define RCC_PLLMul_15 ((u32)0x00340000)
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71 #define RCC_PLLMul_16 ((u32)0x00380000)
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73 #define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\
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74 (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\
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75 (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\
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76 (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\
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77 (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\
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78 (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\
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79 (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\
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80 (MUL == RCC_PLLMul_16))
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82 /* System clock source */
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83 #define RCC_SYSCLKSource_HSI ((u32)0x00000000)
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84 #define RCC_SYSCLKSource_HSE ((u32)0x00000001)
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85 #define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
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87 #define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \
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88 (SOURCE == RCC_SYSCLKSource_HSE) || \
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89 (SOURCE == RCC_SYSCLKSource_PLLCLK))
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91 /* AHB clock source */
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92 #define RCC_SYSCLK_Div1 ((u32)0x00000000)
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93 #define RCC_SYSCLK_Div2 ((u32)0x00000080)
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94 #define RCC_SYSCLK_Div4 ((u32)0x00000090)
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95 #define RCC_SYSCLK_Div8 ((u32)0x000000A0)
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96 #define RCC_SYSCLK_Div16 ((u32)0x000000B0)
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97 #define RCC_SYSCLK_Div64 ((u32)0x000000C0)
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98 #define RCC_SYSCLK_Div128 ((u32)0x000000D0)
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99 #define RCC_SYSCLK_Div256 ((u32)0x000000E0)
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100 #define RCC_SYSCLK_Div512 ((u32)0x000000F0)
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102 #define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \
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103 (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \
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104 (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \
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105 (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \
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106 (HCLK == RCC_SYSCLK_Div512))
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108 /* APB1/APB2 clock source */
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109 #define RCC_HCLK_Div1 ((u32)0x00000000)
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110 #define RCC_HCLK_Div2 ((u32)0x00000400)
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111 #define RCC_HCLK_Div4 ((u32)0x00000500)
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112 #define RCC_HCLK_Div8 ((u32)0x00000600)
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113 #define RCC_HCLK_Div16 ((u32)0x00000700)
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115 #define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \
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116 (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \
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117 (PCLK == RCC_HCLK_Div16))
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119 /* RCC Interrupt source */
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120 #define RCC_IT_LSIRDY ((u8)0x01)
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121 #define RCC_IT_LSERDY ((u8)0x02)
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122 #define RCC_IT_HSIRDY ((u8)0x04)
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123 #define RCC_IT_HSERDY ((u8)0x08)
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124 #define RCC_IT_PLLRDY ((u8)0x10)
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125 #define RCC_IT_CSS ((u8)0x80)
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127 #define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00))
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128 #define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \
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129 (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \
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130 (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS))
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131 #define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00))
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133 /* USB clock source */
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134 #define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
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135 #define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
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137 #define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \
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138 (SOURCE == RCC_USBCLKSource_PLLCLK_Div1))
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140 /* ADC clock source */
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141 #define RCC_PCLK2_Div2 ((u32)0x00000000)
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142 #define RCC_PCLK2_Div4 ((u32)0x00004000)
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143 #define RCC_PCLK2_Div6 ((u32)0x00008000)
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144 #define RCC_PCLK2_Div8 ((u32)0x0000C000)
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146 #define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \
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147 (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8))
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149 /* LSE configuration */
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150 #define RCC_LSE_OFF ((u8)0x00)
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151 #define RCC_LSE_ON ((u8)0x01)
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152 #define RCC_LSE_Bypass ((u8)0x04)
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154 #define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \
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155 (LSE == RCC_LSE_Bypass))
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157 /* RTC clock source */
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158 #define RCC_RTCCLKSource_LSE ((u32)0x00000100)
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159 #define RCC_RTCCLKSource_LSI ((u32)0x00000200)
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160 #define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
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162 #define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \
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163 (SOURCE == RCC_RTCCLKSource_LSI) || \
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164 (SOURCE == RCC_RTCCLKSource_HSE_Div128))
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166 /* AHB peripheral */
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167 #define RCC_AHBPeriph_DMA ((u32)0x00000001)
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168 #define RCC_AHBPeriph_SRAM ((u32)0x00000004)
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169 #define RCC_AHBPeriph_FLITF ((u32)0x00000010)
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171 #define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00))
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173 /* APB2 peripheral */
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174 #define RCC_APB2Periph_AFIO ((u32)0x00000001)
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175 #define RCC_APB2Periph_GPIOA ((u32)0x00000004)
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176 #define RCC_APB2Periph_GPIOB ((u32)0x00000008)
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177 #define RCC_APB2Periph_GPIOC ((u32)0x00000010)
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178 #define RCC_APB2Periph_GPIOD ((u32)0x00000020)
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179 #define RCC_APB2Periph_GPIOE ((u32)0x00000040)
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180 #define RCC_APB2Periph_ADC1 ((u32)0x00000200)
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181 #define RCC_APB2Periph_ADC2 ((u32)0x00000400)
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182 #define RCC_APB2Periph_TIM1 ((u32)0x00000800)
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183 #define RCC_APB2Periph_SPI1 ((u32)0x00001000)
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184 #define RCC_APB2Periph_USART1 ((u32)0x00004000)
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185 #define RCC_APB2Periph_ALL ((u32)0x00005E7D)
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187 #define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00))
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189 /* APB1 peripheral */
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190 #define RCC_APB1Periph_TIM2 ((u32)0x00000001)
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191 #define RCC_APB1Periph_TIM3 ((u32)0x00000002)
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192 #define RCC_APB1Periph_TIM4 ((u32)0x00000004)
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193 #define RCC_APB1Periph_WWDG ((u32)0x00000800)
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194 #define RCC_APB1Periph_SPI2 ((u32)0x00004000)
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195 #define RCC_APB1Periph_USART2 ((u32)0x00020000)
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196 #define RCC_APB1Periph_USART3 ((u32)0x00040000)
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197 #define RCC_APB1Periph_I2C1 ((u32)0x00200000)
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198 #define RCC_APB1Periph_I2C2 ((u32)0x00400000)
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199 #define RCC_APB1Periph_USB ((u32)0x00800000)
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200 #define RCC_APB1Periph_CAN ((u32)0x02000000)
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201 #define RCC_APB1Periph_BKP ((u32)0x08000000)
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202 #define RCC_APB1Periph_PWR ((u32)0x10000000)
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203 #define RCC_APB1Periph_ALL ((u32)0x1AE64807)
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205 #define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00))
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207 /* Clock source to output on MCO pin */
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208 #define RCC_MCO_NoClock ((u8)0x00)
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209 #define RCC_MCO_SYSCLK ((u8)0x04)
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210 #define RCC_MCO_HSI ((u8)0x05)
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211 #define RCC_MCO_HSE ((u8)0x06)
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212 #define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
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214 #define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \
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215 (MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \
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216 (MCO == RCC_MCO_PLLCLK_Div2))
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219 #define RCC_FLAG_HSIRDY ((u8)0x20)
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220 #define RCC_FLAG_HSERDY ((u8)0x31)
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221 #define RCC_FLAG_PLLRDY ((u8)0x39)
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222 #define RCC_FLAG_LSERDY ((u8)0x41)
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223 #define RCC_FLAG_LSIRDY ((u8)0x61)
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224 #define RCC_FLAG_PINRST ((u8)0x7A)
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225 #define RCC_FLAG_PORRST ((u8)0x7B)
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226 #define RCC_FLAG_SFTRST ((u8)0x7C)
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227 #define RCC_FLAG_IWDGRST ((u8)0x7D)
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228 #define RCC_FLAG_WWDGRST ((u8)0x7E)
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229 #define RCC_FLAG_LPWRRST ((u8)0x7F)
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231 #define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \
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232 (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \
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233 (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \
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234 (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \
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235 (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \
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236 (FLAG == RCC_FLAG_LPWRRST))
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238 #define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F)
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240 /* Exported macro ------------------------------------------------------------*/
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241 /* Exported functions ------------------------------------------------------- */
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242 void RCC_DeInit(void);
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243 void RCC_HSEConfig(u32 RCC_HSE);
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244 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
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245 void RCC_HSICmd(FunctionalState NewState);
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246 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
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247 void RCC_PLLCmd(FunctionalState NewState);
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248 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
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249 u8 RCC_GetSYSCLKSource(void);
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250 void RCC_HCLKConfig(u32 RCC_HCLK);
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251 void RCC_PCLK1Config(u32 RCC_PCLK1);
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252 void RCC_PCLK2Config(u32 RCC_PCLK2);
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253 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
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254 void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
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255 void RCC_ADCCLKConfig(u32 RCC_ADCCLK);
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256 void RCC_LSEConfig(u32 RCC_LSE);
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257 void RCC_LSICmd(FunctionalState NewState);
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258 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
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259 void RCC_RTCCLKCmd(FunctionalState NewState);
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260 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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261 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
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262 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
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263 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
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264 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
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265 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
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266 void RCC_BackupResetCmd(FunctionalState NewState);
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267 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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268 void RCC_MCOConfig(u8 RCC_MCO);
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269 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
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270 void RCC_ClearFlag(void);
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271 ITStatus RCC_GetITStatus(u8 RCC_IT);
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272 void RCC_ClearITPendingBit(u8 RCC_IT);
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274 #endif /* __STM32F10x_RCC_H */
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276 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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