2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /* FreeRTOS includes. */
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97 #include "FreeRTOS.h"
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102 /* Library includes. */
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103 #include "stm32fxxx_eth.h"
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104 #include "stm32f10x_gpio.h"
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105 #include "stm32f10x_rcc.h"
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106 #include "stm32f10x_nvic.h"
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108 /*-----------------------------------------------------------*/
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110 /* Hardware specifics. */
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111 #define uipRCC_MAC_CLOCK ( 1UL << 14UL )
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112 #define uipRCC_MAC_TX_CLOCK ( 1UL << 15UL )
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113 #define uipRCC_MAC_RX_CLOCK ( 1UL << 16UL )
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114 #define uipPHY_ADDRESS ( 1 )
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115 #define uipENET_IRQ_NUM ( 61 )
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116 #define uipMODE_MII ( 1UL << 23UL )
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117 #define uipREMAP_MAC_IO ( 1UL << 21UL )
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119 /* The number of descriptors to chain together for use by the Rx DMA. */
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120 #define uipNUM_RX_DESCRIPTORS 4
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122 /* The total number of buffers to be available. At most (?) there should be
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123 one available for each Rx descriptor, one for current use, and one that is
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124 in the process of being transmitted. */
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125 #define uipNUM_BUFFERS ( uipNUM_RX_DESCRIPTORS + 2 )
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127 /* Each buffer is sized to fit an entire Ethernet packet. This is for
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128 simplicity and speed, but could waste RAM. */
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129 #define uipMAX_PACKET_SIZE 1520
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131 /* The field in the descriptor that is unused by this configuration is used to
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132 hold the send count. This is just #defined to a meaningful name. */
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133 #define SendCount Buffer2NextDescAddr
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135 /* If no buffers are available, then wait this long before looking again.... */
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136 #define uipBUFFER_WAIT_DELAY ( 3 / portTICK_PERIOD_MS )
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138 /* ...and don't look more than this many times. */
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139 #define uipBUFFER_WAIT_ATTEMPTS ( 30 )
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141 /* Let the DMA know that a new descriptor has been made available to it. */
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142 #define prvRxDescriptorAvailable() ETH_DMA->DMARPDR = 0
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144 /*-----------------------------------------------------------*/
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147 * Configure the IO for Ethernet use.
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149 static void prvSetupEthGPIO( void );
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152 * Return a pointer to an unused buffer, marking the returned buffer as now
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155 static unsigned char *prvGetNextBuffer( void );
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157 /*-----------------------------------------------------------*/
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159 /* Allocate the Rx descriptors used by the DMA. */
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160 static ETH_DMADESCTypeDef xRxDescriptors[ uipNUM_RX_DESCRIPTORS ] __attribute__((aligned(4)));
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162 /* Allocate the descriptor used for transmitting. It might be that better
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163 performance could be achieved by having more than one Tx descriptor, but
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164 in this simple case only one is used. */
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165 static volatile ETH_DMADESCTypeDef xTxDescriptor __attribute__((aligned(4)));
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167 /* Buffers used for receiving and transmitting data. */
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168 static unsigned char ucMACBuffers[ uipNUM_BUFFERS ][ uipMAX_PACKET_SIZE ] __attribute__((aligned(4)));
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170 /* Each ucBufferInUse index corresponds to a position in the same index in the
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171 ucMACBuffers array. If the index contains a 1 then the buffer within
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172 ucMACBuffers is in use, if it contains a 0 then the buffer is free. */
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173 static unsigned char ucBufferInUse[ uipNUM_BUFFERS ] = { 0 };
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175 /* Index to the Rx descriptor to inspect next when looking for a received
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177 static unsigned long ulNextDescriptor;
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179 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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180 allocated within this file. */
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181 extern unsigned char * uip_buf;
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183 /*-----------------------------------------------------------*/
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185 portBASE_TYPE xEthInitialise( void )
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187 static ETH_InitTypeDef xEthInit; /* Static so as not to take up too much stack space. */
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188 NVIC_InitTypeDef xNVICInit;
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189 const unsigned char ucMACAddress[] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };
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190 portBASE_TYPE xReturn;
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193 /* Start with things in a safe known state. */
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195 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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197 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), DISABLE );
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200 /* Route clock to the peripheral. */
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201 RCC->AHBENR |= ( uipRCC_MAC_CLOCK | uipRCC_MAC_TX_CLOCK | uipRCC_MAC_RX_CLOCK );
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203 /* Set the MAC address. */
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204 ETH_MACAddressConfig( ETH_MAC_Address0, ( unsigned char * ) ucMACAddress );
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206 /* Use MII mode. */
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207 AFIO->MAPR &= ~( uipMODE_MII );
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209 /* Configure all the GPIO as required for MAC/PHY interfacing. */
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212 /* Reset the peripheral. */
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213 ETH_SoftwareReset();
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214 while( ETH_GetSoftwareResetStatus() == SET );
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216 /* Initialise using the whopping big structure. Code space could be saved
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217 by making this a const struct, however that would mean changes to the
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218 structure within the library header files could break the code, so for now
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219 just set everything manually at run time. */
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220 xEthInit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
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221 xEthInit.ETH_Watchdog = ETH_Watchdog_Disable;
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222 xEthInit.ETH_Jabber = ETH_Jabber_Disable;
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223 xEthInit.ETH_JumboFrame = ETH_JumboFrame_Disable;
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224 xEthInit.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
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225 xEthInit.ETH_CarrierSense = ETH_CarrierSense_Enable;
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226 xEthInit.ETH_Speed = ETH_Speed_10M;
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227 xEthInit.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;
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228 xEthInit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
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229 xEthInit.ETH_Mode = ETH_Mode_HalfDuplex;
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230 xEthInit.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
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231 xEthInit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
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232 xEthInit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
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233 xEthInit.ETH_BackOffLimit = ETH_BackOffLimit_10;
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234 xEthInit.ETH_DeferralCheck = ETH_DeferralCheck_Disable;
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235 xEthInit.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
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236 xEthInit.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
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237 xEthInit.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;
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238 xEthInit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
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239 xEthInit.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
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240 xEthInit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
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241 xEthInit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
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242 xEthInit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
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243 xEthInit.ETH_HashTableHigh = 0x0;
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244 xEthInit.ETH_HashTableLow = 0x0;
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245 xEthInit.ETH_PauseTime = 0x0;
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246 xEthInit.ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
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247 xEthInit.ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
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248 xEthInit.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
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249 xEthInit.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
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250 xEthInit.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
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251 xEthInit.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
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252 xEthInit.ETH_VLANTagIdentifier = 0x0;
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253 xEthInit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
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254 xEthInit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
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255 xEthInit.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
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256 xEthInit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
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257 xEthInit.ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
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258 xEthInit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
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259 xEthInit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
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260 xEthInit.ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
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261 xEthInit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
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262 xEthInit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
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263 xEthInit.ETH_FixedBurst = ETH_FixedBurst_Disable;
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264 xEthInit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
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265 xEthInit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
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266 xEthInit.ETH_DescriptorSkipLength = 0x0;
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267 xEthInit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
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269 xReturn = ETH_Init( &xEthInit, uipPHY_ADDRESS );
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271 /* Check a link was established. */
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272 if( xReturn != pdFAIL )
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274 /* Rx and Tx interrupts are used. */
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275 ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE );
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277 /* Only a single Tx descriptor is used. For now it is set to use an Rx
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278 buffer, but will get updated to point to where ever uip_buf is
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279 pointing prior to its use. */
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280 ETH_DMATxDescChainInit( ( void * ) &xTxDescriptor, ( void * ) ucMACBuffers, 1 );
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281 ETH_DMARxDescChainInit( xRxDescriptors, ( void * ) ucMACBuffers, uipNUM_RX_DESCRIPTORS );
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282 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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284 /* Ensure received data generates an interrupt. */
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285 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), ENABLE );
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287 /* Fix up the addresses used by the descriptors.
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288 The way ETH_DMARxDescChainInit() is not compatible with the buffer
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289 declarations in this file. */
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290 xRxDescriptors[ ul ].Buffer1Addr = ( unsigned long ) &( ucMACBuffers[ ul ][ 0 ] );
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292 /* Mark the buffer used by this descriptor as in use. */
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293 ucBufferInUse[ ul ] = pdTRUE;
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296 /* When receiving data, start at the first descriptor. */
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297 ulNextDescriptor = 0;
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299 /* Initialise uip_buf to ensure it points somewhere valid. */
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300 uip_buf = prvGetNextBuffer();
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302 /* SendCount must be initialised to 2 to ensure the Tx descriptor looks
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303 as if its available (as if it has already been sent twice. */
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304 xTxDescriptor.SendCount = 2;
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306 /* Switch on the interrupts in the NVIC. */
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307 xNVICInit.NVIC_IRQChannel = uipENET_IRQ_NUM;
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308 xNVICInit.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
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309 xNVICInit.NVIC_IRQChannelSubPriority = 0;
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310 xNVICInit.NVIC_IRQChannelCmd = ENABLE;
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311 NVIC_Init( &xNVICInit );
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313 /* Buffers and descriptors are all set up, now enable the MAC. */
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316 /* Let the DMA know there are Rx descriptors available. */
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317 prvRxDescriptorAvailable();
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322 /*-----------------------------------------------------------*/
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324 static unsigned char *prvGetNextBuffer( void )
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327 unsigned char *ucReturn = NULL;
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328 unsigned long ulAttempts = 0;
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330 while( ucReturn == NULL )
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332 /* Look through the buffers to find one that is not in use by
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334 for( x = 0; x < uipNUM_BUFFERS; x++ )
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336 if( ucBufferInUse[ x ] == pdFALSE )
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338 ucBufferInUse[ x ] = pdTRUE;
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339 ucReturn = &( ucMACBuffers[ x ][ 0 ] );
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344 /* Was a buffer found? */
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345 if( ucReturn == NULL )
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349 if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
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354 /* Wait then look again. */
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355 vTaskDelay( uipBUFFER_WAIT_DELAY );
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361 /*-----------------------------------------------------------*/
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363 unsigned short usGetMACRxData( void )
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365 unsigned short usReturn;
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367 if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_ES ) != 0 )
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369 /* Error in Rx. Discard the frame and give it back to the DMA. */
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370 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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371 prvRxDescriptorAvailable();
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373 /* No data to return. */
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376 /* Start from the next descriptor the next time this function is called. */
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377 ulNextDescriptor++;
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378 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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380 ulNextDescriptor = 0UL;
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383 else if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_OWN ) == 0 )
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385 /* Mark the current buffer as free as uip_buf is going to be set to
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386 the buffer that contains the received data. */
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387 vReturnBuffer( uip_buf );
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389 /* Get the received data length from the top 2 bytes of the Status
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390 word and the data itself. */
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391 usReturn = ( unsigned short ) ( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_FL ) >> 16UL );
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392 uip_buf = ( unsigned char * ) ( xRxDescriptors[ ulNextDescriptor ].Buffer1Addr );
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394 /* Allocate a new buffer to the descriptor. */
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395 xRxDescriptors[ ulNextDescriptor ].Buffer1Addr = ( unsigned long ) prvGetNextBuffer();
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397 /* Give the descriptor back to the DMA. */
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398 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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399 prvRxDescriptorAvailable();
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401 /* Start from the next descriptor the next time this function is called. */
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402 ulNextDescriptor++;
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403 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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405 ulNextDescriptor = 0UL;
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410 /* No received data at all. */
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416 /*-----------------------------------------------------------*/
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418 void vSendMACData( unsigned short usDataLen )
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420 unsigned long ulAttempts = 0UL;
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422 /* Check to see if the Tx descriptor is free. The check against <2 is to
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423 ensure the buffer has been sent twice and in so doing preventing a race
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424 condition with the DMA on the ETH_DMATxDesc_OWN bit. */
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425 while( ( xTxDescriptor.SendCount < 2 ) && ( xTxDescriptor.Status & ETH_DMATxDesc_OWN ) == ETH_DMATxDesc_OWN )
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427 /* Wait for the Tx descriptor to become available. */
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428 vTaskDelay( uipBUFFER_WAIT_DELAY );
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431 if( ulAttempts > uipBUFFER_WAIT_ATTEMPTS )
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433 /* Something has gone wrong as the Tx descriptor is still in use.
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434 Clear it down manually, the data it was sending will probably be
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436 xTxDescriptor.Status &= ~ETH_DMATxDesc_OWN;
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437 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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442 /* Setup the Tx descriptor for transmission. */
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443 xTxDescriptor.SendCount = 0;
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444 xTxDescriptor.Buffer1Addr = ( unsigned long ) uip_buf;
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445 xTxDescriptor.ControlBufferSize = ( unsigned long ) usDataLen;
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446 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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447 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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448 ETH_DMA->DMATPDR = 0;
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450 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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451 uip_buf = prvGetNextBuffer();
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453 /*-----------------------------------------------------------*/
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455 static void prvSetupEthGPIO( void )
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457 GPIO_InitTypeDef xEthInit;
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459 /* Remap MAC IO. */
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460 AFIO->MAPR |= ( uipREMAP_MAC_IO );
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462 /* Set PA2, PA8, PB5, PB8, PB11, PB12, PB13, PC1 and PC2 for Ethernet
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464 xEthInit.GPIO_Pin = GPIO_Pin_2;/* | GPIO_Pin_8; This should be set when the 25MHz is generated by MCO. */
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465 xEthInit.GPIO_Speed = GPIO_Speed_50MHz;
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466 xEthInit.GPIO_Mode = GPIO_Mode_AF_PP;
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467 GPIO_Init( GPIOA, &xEthInit );
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469 xEthInit.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; /*5*/
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470 GPIO_Init( GPIOB, &xEthInit );
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472 xEthInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
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473 GPIO_Init( GPIOC, &xEthInit );
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476 /* Configure PA0, PA1, PA3, PB10, PC3, PD8, PD9, PD10, PD11 and PD12 as
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478 xEthInit.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
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479 xEthInit.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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480 GPIO_Init( GPIOA, &xEthInit );
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482 xEthInit.GPIO_Pin = GPIO_Pin_10;
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483 GPIO_Init( GPIOB, &xEthInit );
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485 xEthInit.GPIO_Pin = GPIO_Pin_3;
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486 GPIO_Init( GPIOC, &xEthInit );
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488 xEthInit.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
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489 GPIO_Init( GPIOD, &xEthInit );
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491 /*-----------------------------------------------------------*/
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493 void vReturnBuffer( unsigned char *pucBuffer )
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497 /* Mark a buffer as free for use. */
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498 for( ul = 0; ul < uipNUM_BUFFERS; ul++ )
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500 if( ucMACBuffers[ ul ] == pucBuffer )
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502 ucBufferInUse[ ul ] = pdFALSE;
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507 /*-----------------------------------------------------------*/
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509 void vMAC_ISR( void )
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511 unsigned long ulStatus;
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512 extern SemaphoreHandle_t xEMACSemaphore;
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513 long xHigherPriorityTaskWoken = pdFALSE;
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515 /* What caused the interrupt? */
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516 ulStatus = ETH_DMA->DMASR;
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518 /* Clear everything before leaving. */
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519 ETH_DMA->DMASR = ulStatus;
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521 if( ulStatus & ETH_DMA_IT_R )
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523 /* Data was received. Ensure the uIP task is not blocked as data has
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525 xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
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528 if( ulStatus & ETH_DMA_IT_T )
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530 /* Data was transmitted. */
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531 if( xTxDescriptor.SendCount == 0 )
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534 ( xTxDescriptor.SendCount )++;
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536 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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537 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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538 ETH_DMA->DMATPDR = 0;
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542 /* The Tx buffer is no longer required. */
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543 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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547 /* If xSemaphoreGiveFromISR() unblocked a task, and the unblocked task has
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548 a higher priority than the currently executing task, then
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549 xHigherPriorityTaskWoken will have been set to pdTRUE and this ISR should
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550 return directly to the higher priority unblocked task. */
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551 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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