2 FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not itcan be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* FreeRTOS includes. */
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76 #include "FreeRTOS.h"
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81 /* Library includes. */
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82 #include "stm32fxxx_eth.h"
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83 #include "stm32f10x_gpio.h"
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84 #include "stm32f10x_rcc.h"
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85 #include "stm32f10x_nvic.h"
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87 /*-----------------------------------------------------------*/
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89 /* Hardware specifics. */
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90 #define uipRCC_MAC_CLOCK ( 1UL << 14UL )
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91 #define uipRCC_MAC_TX_CLOCK ( 1UL << 15UL )
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92 #define uipRCC_MAC_RX_CLOCK ( 1UL << 16UL )
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93 #define uipPHY_ADDRESS ( 1 )
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94 #define uipENET_IRQ_NUM ( 61 )
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95 #define uipMODE_MII ( 1UL << 23UL )
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96 #define uipREMAP_MAC_IO ( 1UL << 21UL )
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98 /* The number of descriptors to chain together for use by the Rx DMA. */
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99 #define uipNUM_RX_DESCRIPTORS 4
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101 /* The total number of buffers to be available. At most (?) there should be
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102 one available for each Rx descriptor, one for current use, and one that is
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103 in the process of being transmitted. */
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104 #define uipNUM_BUFFERS ( uipNUM_RX_DESCRIPTORS + 2 )
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106 /* Each buffer is sized to fit an entire Ethernet packet. This is for
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107 simplicity and speed, but could waste RAM. */
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108 #define uipMAX_PACKET_SIZE 1520
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110 /* The field in the descriptor that is unused by this configuration is used to
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111 hold the send count. This is just #defined to a meaningful name. */
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112 #define SendCount Buffer2NextDescAddr
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114 /* If no buffers are available, then wait this long before looking again.... */
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115 #define uipBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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117 /* ...and don't look more than this many times. */
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118 #define uipBUFFER_WAIT_ATTEMPTS ( 30 )
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120 /* Let the DMA know that a new descriptor has been made available to it. */
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121 #define prvRxDescriptorAvailable() ETH_DMA->DMARPDR = 0
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123 /*-----------------------------------------------------------*/
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126 * Configure the IO for Ethernet use.
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128 static void prvSetupEthGPIO( void );
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131 * Return a pointer to an unused buffer, marking the returned buffer as now
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134 static unsigned char *prvGetNextBuffer( void );
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136 /*-----------------------------------------------------------*/
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138 /* Allocate the Rx descriptors used by the DMA. */
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139 static ETH_DMADESCTypeDef xRxDescriptors[ uipNUM_RX_DESCRIPTORS ] __attribute__((aligned(4)));
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141 /* Allocate the descriptor used for transmitting. It might be that better
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142 performance could be achieved by having more than one Tx descriptor, but
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143 in this simple case only one is used. */
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144 static volatile ETH_DMADESCTypeDef xTxDescriptor __attribute__((aligned(4)));
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146 /* Buffers used for receiving and transmitting data. */
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147 static unsigned char ucMACBuffers[ uipNUM_BUFFERS ][ uipMAX_PACKET_SIZE ] __attribute__((aligned(4)));
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149 /* Each ucBufferInUse index corresponds to a position in the same index in the
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150 ucMACBuffers array. If the index contains a 1 then the buffer within
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151 ucMACBuffers is in use, if it contains a 0 then the buffer is free. */
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152 static unsigned char ucBufferInUse[ uipNUM_BUFFERS ] = { 0 };
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154 /* Index to the Rx descriptor to inspect next when looking for a received
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156 static unsigned long ulNextDescriptor;
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158 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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159 allocated within this file. */
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160 extern unsigned char * uip_buf;
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162 /*-----------------------------------------------------------*/
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164 portBASE_TYPE xEthInitialise( void )
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166 static ETH_InitTypeDef xEthInit; /* Static so as not to take up too much stack space. */
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167 NVIC_InitTypeDef xNVICInit;
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168 const unsigned char ucMACAddress[] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };
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169 portBASE_TYPE xReturn;
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172 /* Start with things in a safe known state. */
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174 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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176 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), DISABLE );
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179 /* Route clock to the peripheral. */
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180 RCC->AHBENR |= ( uipRCC_MAC_CLOCK | uipRCC_MAC_TX_CLOCK | uipRCC_MAC_RX_CLOCK );
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182 /* Set the MAC address. */
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183 ETH_MACAddressConfig( ETH_MAC_Address0, ( unsigned char * ) ucMACAddress );
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185 /* Use MII mode. */
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186 AFIO->MAPR &= ~( uipMODE_MII );
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188 /* Configure all the GPIO as required for MAC/PHY interfacing. */
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191 /* Reset the peripheral. */
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192 ETH_SoftwareReset();
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193 while( ETH_GetSoftwareResetStatus() == SET );
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195 /* Initialise using the whopping big structure. Code space could be saved
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196 by making this a const struct, however that would mean changes to the
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197 structure within the library header files could break the code, so for now
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198 just set everything manually at run time. */
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199 xEthInit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
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200 xEthInit.ETH_Watchdog = ETH_Watchdog_Disable;
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201 xEthInit.ETH_Jabber = ETH_Jabber_Disable;
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202 xEthInit.ETH_JumboFrame = ETH_JumboFrame_Disable;
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203 xEthInit.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
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204 xEthInit.ETH_CarrierSense = ETH_CarrierSense_Enable;
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205 xEthInit.ETH_Speed = ETH_Speed_10M;
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206 xEthInit.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;
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207 xEthInit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
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208 xEthInit.ETH_Mode = ETH_Mode_HalfDuplex;
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209 xEthInit.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
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210 xEthInit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
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211 xEthInit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
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212 xEthInit.ETH_BackOffLimit = ETH_BackOffLimit_10;
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213 xEthInit.ETH_DeferralCheck = ETH_DeferralCheck_Disable;
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214 xEthInit.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
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215 xEthInit.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
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216 xEthInit.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;
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217 xEthInit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
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218 xEthInit.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
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219 xEthInit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
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220 xEthInit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
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221 xEthInit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
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222 xEthInit.ETH_HashTableHigh = 0x0;
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223 xEthInit.ETH_HashTableLow = 0x0;
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224 xEthInit.ETH_PauseTime = 0x0;
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225 xEthInit.ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
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226 xEthInit.ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
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227 xEthInit.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
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228 xEthInit.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
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229 xEthInit.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
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230 xEthInit.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
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231 xEthInit.ETH_VLANTagIdentifier = 0x0;
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232 xEthInit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
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233 xEthInit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
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234 xEthInit.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
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235 xEthInit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
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236 xEthInit.ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
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237 xEthInit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
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238 xEthInit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
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239 xEthInit.ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
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240 xEthInit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
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241 xEthInit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
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242 xEthInit.ETH_FixedBurst = ETH_FixedBurst_Disable;
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243 xEthInit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
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244 xEthInit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
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245 xEthInit.ETH_DescriptorSkipLength = 0x0;
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246 xEthInit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
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248 xReturn = ETH_Init( &xEthInit, uipPHY_ADDRESS );
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250 /* Check a link was established. */
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251 if( xReturn != pdFAIL )
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253 /* Rx and Tx interrupts are used. */
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254 ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE );
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256 /* Only a single Tx descriptor is used. For now it is set to use an Rx
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257 buffer, but will get updated to point to where ever uip_buf is
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258 pointing prior to its use. */
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259 ETH_DMATxDescChainInit( ( void * ) &xTxDescriptor, ( void * ) ucMACBuffers, 1 );
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260 ETH_DMARxDescChainInit( xRxDescriptors, ( void * ) ucMACBuffers, uipNUM_RX_DESCRIPTORS );
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261 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
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263 /* Ensure received data generates an interrupt. */
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264 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), ENABLE );
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266 /* Fix up the addresses used by the descriptors.
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267 The way ETH_DMARxDescChainInit() is not compatible with the buffer
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268 declarations in this file. */
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269 xRxDescriptors[ ul ].Buffer1Addr = ( unsigned long ) &( ucMACBuffers[ ul ][ 0 ] );
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271 /* Mark the buffer used by this descriptor as in use. */
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272 ucBufferInUse[ ul ] = pdTRUE;
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275 /* When receiving data, start at the first descriptor. */
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276 ulNextDescriptor = 0;
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278 /* Initialise uip_buf to ensure it points somewhere valid. */
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279 uip_buf = prvGetNextBuffer();
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281 /* SendCount must be initialised to 2 to ensure the Tx descriptor looks
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282 as if its available (as if it has already been sent twice. */
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283 xTxDescriptor.SendCount = 2;
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285 /* Switch on the interrupts in the NVIC. */
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286 xNVICInit.NVIC_IRQChannel = uipENET_IRQ_NUM;
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287 xNVICInit.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
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288 xNVICInit.NVIC_IRQChannelSubPriority = 0;
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289 xNVICInit.NVIC_IRQChannelCmd = ENABLE;
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290 NVIC_Init( &xNVICInit );
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292 /* Buffers and descriptors are all set up, now enable the MAC. */
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295 /* Let the DMA know there are Rx descriptors available. */
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296 prvRxDescriptorAvailable();
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301 /*-----------------------------------------------------------*/
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303 static unsigned char *prvGetNextBuffer( void )
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306 unsigned char *ucReturn = NULL;
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307 unsigned long ulAttempts = 0;
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309 while( ucReturn == NULL )
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311 /* Look through the buffers to find one that is not in use by
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313 for( x = 0; x < uipNUM_BUFFERS; x++ )
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315 if( ucBufferInUse[ x ] == pdFALSE )
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317 ucBufferInUse[ x ] = pdTRUE;
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318 ucReturn = &( ucMACBuffers[ x ][ 0 ] );
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323 /* Was a buffer found? */
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324 if( ucReturn == NULL )
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328 if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
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333 /* Wait then look again. */
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334 vTaskDelay( uipBUFFER_WAIT_DELAY );
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340 /*-----------------------------------------------------------*/
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342 unsigned short usGetMACRxData( void )
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344 unsigned short usReturn;
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346 if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_ES ) != 0 )
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348 /* Error in Rx. Discard the frame and give it back to the DMA. */
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349 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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350 prvRxDescriptorAvailable();
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352 /* No data to return. */
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355 /* Start from the next descriptor the next time this function is called. */
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356 ulNextDescriptor++;
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357 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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359 ulNextDescriptor = 0UL;
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362 else if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_OWN ) == 0 )
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364 /* Mark the current buffer as free as uip_buf is going to be set to
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365 the buffer that contains the received data. */
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366 vReturnBuffer( uip_buf );
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368 /* Get the received data length from the top 2 bytes of the Status
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369 word and the data itself. */
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370 usReturn = ( unsigned short ) ( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_FL ) >> 16UL );
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371 uip_buf = ( unsigned char * ) ( xRxDescriptors[ ulNextDescriptor ].Buffer1Addr );
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373 /* Allocate a new buffer to the descriptor. */
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374 xRxDescriptors[ ulNextDescriptor ].Buffer1Addr = ( unsigned long ) prvGetNextBuffer();
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376 /* Give the descriptor back to the DMA. */
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377 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
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378 prvRxDescriptorAvailable();
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380 /* Start from the next descriptor the next time this function is called. */
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381 ulNextDescriptor++;
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382 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
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384 ulNextDescriptor = 0UL;
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389 /* No received data at all. */
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395 /*-----------------------------------------------------------*/
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397 void vSendMACData( unsigned short usDataLen )
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399 unsigned long ulAttempts = 0UL;
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401 /* Check to see if the Tx descriptor is free. The check against <2 is to
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402 ensure the buffer has been sent twice and in so doing preventing a race
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403 condition with the DMA on the ETH_DMATxDesc_OWN bit. */
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404 while( ( xTxDescriptor.SendCount < 2 ) && ( xTxDescriptor.Status & ETH_DMATxDesc_OWN ) == ETH_DMATxDesc_OWN )
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406 /* Wait for the Tx descriptor to become available. */
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407 vTaskDelay( uipBUFFER_WAIT_DELAY );
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410 if( ulAttempts > uipBUFFER_WAIT_ATTEMPTS )
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412 /* Something has gone wrong as the Tx descriptor is still in use.
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413 Clear it down manually, the data it was sending will probably be
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415 xTxDescriptor.Status &= ~ETH_DMATxDesc_OWN;
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416 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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421 /* Setup the Tx descriptor for transmission. */
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422 xTxDescriptor.SendCount = 0;
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423 xTxDescriptor.Buffer1Addr = ( unsigned long ) uip_buf;
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424 xTxDescriptor.ControlBufferSize = ( unsigned long ) usDataLen;
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425 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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426 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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427 ETH_DMA->DMATPDR = 0;
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429 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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430 uip_buf = prvGetNextBuffer();
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432 /*-----------------------------------------------------------*/
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434 static void prvSetupEthGPIO( void )
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436 GPIO_InitTypeDef xEthInit;
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438 /* Remap MAC IO. */
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439 AFIO->MAPR |= ( uipREMAP_MAC_IO );
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441 /* Set PA2, PA8, PB5, PB8, PB11, PB12, PB13, PC1 and PC2 for Ethernet
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443 xEthInit.GPIO_Pin = GPIO_Pin_2;/* | GPIO_Pin_8; This should be set when the 25MHz is generated by MCO. */
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444 xEthInit.GPIO_Speed = GPIO_Speed_50MHz;
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445 xEthInit.GPIO_Mode = GPIO_Mode_AF_PP;
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446 GPIO_Init( GPIOA, &xEthInit );
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448 xEthInit.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; /*5*/
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449 GPIO_Init( GPIOB, &xEthInit );
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451 xEthInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
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452 GPIO_Init( GPIOC, &xEthInit );
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455 /* Configure PA0, PA1, PA3, PB10, PC3, PD8, PD9, PD10, PD11 and PD12 as
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457 xEthInit.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
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458 xEthInit.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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459 GPIO_Init( GPIOA, &xEthInit );
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461 xEthInit.GPIO_Pin = GPIO_Pin_10;
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462 GPIO_Init( GPIOB, &xEthInit );
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464 xEthInit.GPIO_Pin = GPIO_Pin_3;
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465 GPIO_Init( GPIOC, &xEthInit );
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467 xEthInit.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
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468 GPIO_Init( GPIOD, &xEthInit );
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470 /*-----------------------------------------------------------*/
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472 void vReturnBuffer( unsigned char *pucBuffer )
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476 /* Mark a buffer as free for use. */
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477 for( ul = 0; ul < uipNUM_BUFFERS; ul++ )
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479 if( ucMACBuffers[ ul ] == pucBuffer )
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481 ucBufferInUse[ ul ] = pdFALSE;
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486 /*-----------------------------------------------------------*/
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488 void vMAC_ISR( void )
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490 unsigned long ulStatus;
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491 extern xSemaphoreHandle xEMACSemaphore;
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492 long xHigherPriorityTaskWoken = pdFALSE;
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494 /* What caused the interrupt? */
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495 ulStatus = ETH_DMA->DMASR;
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497 /* Clear everything before leaving. */
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498 ETH_DMA->DMASR = ulStatus;
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500 if( ulStatus & ETH_DMA_IT_R )
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502 /* Data was received. Ensure the uIP task is not blocked as data has
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504 xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
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507 if( ulStatus & ETH_DMA_IT_T )
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509 /* Data was transmitted. */
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510 if( xTxDescriptor.SendCount == 0 )
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513 ( xTxDescriptor.SendCount )++;
\r
515 xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
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516 ETH_DMA->DMASR = ETH_DMASR_TBUS;
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517 ETH_DMA->DMATPDR = 0;
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521 /* The Tx buffer is no longer required. */
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522 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
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526 /* If xSemaphoreGiveFromISR() unblocked a task, and the unblocked task has
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527 a higher priority than the currently executing task, then
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528 xHigherPriorityTaskWoken will have been set to pdTRUE and this ISR should
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529 return directly to the higher priority unblocked task. */
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530 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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