git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/ColdFire_MCF51CN128_CodeWarrior/Sources/main.c

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
  23     1 tab == 4 spaces!\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  28      *    not run, what could be wrong?".  Have you defined configASSERT()?  *\r
  29      *                                                                       *\r
  30      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  31      *                                                                       *\r
  32     ***************************************************************************\r
  33 \r
  34     ***************************************************************************\r
  35      *                                                                       *\r
  36      *    FreeRTOS provides completely free yet professionally developed,    *\r
  37      *    robust, strictly quality controlled, supported, and cross          *\r
  38      *    platform software that is more than just the market leader, it     *\r
  39      *    is the industry's de facto standard.                               *\r
  40      *                                                                       *\r
  41      *    Help yourself get started quickly while simultaneously helping     *\r
  42      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  43      *    tutorial book, reference manual, or both:                          *\r
  44      *    http://www.FreeRTOS.org/Documentation                              *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
  50      *   Investing in training allows your team to be as productive as       *\r
  51      *   possible as early as possible, lowering your overall development    *\r
  52      *   cost, and enabling you to bring a more robust product to market     *\r
  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
  56      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
  57      *   from Richard ensures your team will gain directly from his in-depth *\r
  58      *   product knowledge and years of usage experience.  Contact Real Time *\r
  59      *   Engineers Ltd to enquire about the FreeRTOS Masterclass, presented  *\r
  60      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
  67      *    fair and reciprocate by reporting any suspected issues and         *\r
  68      *    participating in the community forum:                              *\r
  69      *    http://www.FreeRTOS.org/support                                    *\r
  70      *                                                                       *\r
  71      *    Thank you!                                                         *\r
  72      *                                                                       *\r
  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  79     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  80     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  81 \r
  82     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  83     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  84 \r
  85     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  86     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  87     licenses offer ticketed support, indemnification and commercial middleware.\r
  88 \r
  89     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 \r
  97 /*\r
  98  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
  99  * documentation provides more details of the standard demo application tasks.\r
 100  * In addition to the standard demo tasks, the following tasks and tests are\r
 101  * defined and/or created within this file:\r
 102  *\r
 103  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
 104  * simply generates a page that shows the current state of all the tasks within\r
 105  * the system, including the high water mark of each task stack. The high water\r
 106  * mark is displayed as the amount of stack that has never been used, so the\r
 107  * closer the value is to zero the closer the task has come to overflowing its\r
 108  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
 109  * pages display some TCP/IP status information and permit LED3 to be turned on\r
 110  * and off using a check box.\r
 111  *\r
 112  * Tick hook function that implements a "Check" function -  This is executed\r
 113  * every 5 seconds from the tick hook function.  It checks to ensure that all\r
 114  * the standard demo tasks are still operational and running without error.\r
 115  * The system status (pass/fail) is then displayed underneith the task table on\r
 116  * the served WEB pages.\r
 117  *\r
 118  * "Reg test" tasks - These fill the registers with known values, then check\r
 119  * that each register still contains its expected value.  Each task uses\r
 120  * different values.  The tasks run with very low priority so get preempted very\r
 121  * frequently.  A register containing an unexpected value is indicative of an\r
 122  * error in the context switching mechanism.\r
 123  *\r
 124  */\r
 125 \r
 126 /* Standard includes. */\r
 127 #include <stdio.h>\r
 128 \r
 129 /* Scheduler includes. */\r
 130 #include "FreeRTOS.h"\r
 131 #include "task.h"\r
 132 #include "queue.h"\r
 133 #include "semphr.h"\r
 134 \r
 135 /* Demo app includes. */\r
 136 #include "BlockQ.h"\r
 137 #include "death.h"\r
 138 #include "flash.h"\r
 139 #include "partest.h"\r
 140 #include "GenQTest.h"\r
 141 #include "QPeek.h"\r
 142 #include "recmutex.h"\r
 143 \r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 /* ComTest constants - there is no free LED for the comtest tasks. */\r
 147 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
 148 #define mainCOM_TEST_LED                                        ( 5 )\r
 149 \r
 150 /* Task priorities. */\r
 151 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
 152 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
 153 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
 154 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
 155 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
 156 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
 157 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
 158 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
 159 \r
 160 /* WEB server requires enough stack for the string handling functions. */\r
 161 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
 162 \r
 163 /*\r
 164  * Configure the hardware for the demo.\r
 165  */\r
 166 static void prvSetupHardware( void );\r
 167 \r
 168 /*\r
 169  * Implements the 'check' function as described at the top of this file.\r
 170  */\r
 171 static void prvCheckFunction( void );\r
 172 \r
 173 /*\r
 174  * Implement the 'Reg test' functionality as described at the top of this file.\r
 175  */\r
 176 static void vRegTest1Task( void *pvParameters );\r
 177 static void vRegTest2Task( void *pvParameters );\r
 178 \r
 179 /*\r
 180  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
 181  * this task.\r
 182  */\r
 183 extern void vuIP_Task( void *pvParameters );\r
 184 \r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 /* Counters used to detect errors within the reg test tasks. */\r
 188 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
 189 \r
 190 /* Flag that latches any errors detected in the system. */\r
 191 unsigned long ulCheckErrors = 0;\r
 192 \r
 193 /*-----------------------------------------------------------*/\r
 194 \r
 195 int main( void )\r
 196 {\r
 197 extern void vBasicWEBServer( void *pv );\r
 198 \r
 199         /* Setup the hardware ready for this demo. */\r
 200         prvSetupHardware();\r
 201 \r
 202         xTaskCreate( vuIP_Task, "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
 203 \r
 204         /* Start the standard demo tasks. */\r
 205         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
 206         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
 207         vStartQueuePeekTasks();\r
 208         vStartRecursiveMutexTasks();\r
 209         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
 210 \r
 211         /* Start the reg test tasks - defined in this file. */\r
 212         xTaskCreate( vRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
 213         xTaskCreate( vRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
 214 \r
 215         /* Start the scheduler. */\r
 216         vTaskStartScheduler();\r
 217 \r
 218     /* Will only get here if there was insufficient memory to create the idle\r
 219     task. */\r
 220         for( ;; )\r
 221         {\r
 222         }\r
 223 }\r
 224 /*-----------------------------------------------------------*/\r
 225 \r
 226 void vApplicationTickHook( void )\r
 227 {\r
 228 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 229 const unsigned long ulExecutionRate = 5000 / portTICK_PERIOD_MS;\r
 230 \r
 231     /* Increment the count of how many times the tick hook has been called. */\r
 232     ulExecutionCount++;\r
 233 \r
 234     /* Is it time to perform the check again? */\r
 235         if( ulExecutionCount >= ulExecutionRate )\r
 236         {\r
 237                 /* Reset the execution count so this function is called again in 5\r
 238                 seconds time. */\r
 239                 ulExecutionCount = 0;\r
 240 \r
 241                 /* Has an error been found in any task? */\r
 242                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
 243                 {\r
 244                         ulCheckErrors |= 0x01UL;\r
 245                 }\r
 246 \r
 247                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
 248                 {\r
 249                         ulCheckErrors |= 0x02UL;\r
 250                 }\r
 251 \r
 252                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
 253                 {\r
 254                         ulCheckErrors |= 0x04UL;\r
 255                 }\r
 256 \r
 257                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
 258             {\r
 259                 ulCheckErrors |= 0x200UL;\r
 260             }\r
 261 \r
 262                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
 263                 {\r
 264                         ulCheckErrors |= 0x1000UL;\r
 265                 }\r
 266 \r
 267                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
 268                 {\r
 269                         ulCheckErrors |= 0x1000UL;\r
 270                 }\r
 271 \r
 272                 ulLastRegTest1Count = ulRegTest1Counter;\r
 273                 ulLastRegTest2Count = ulRegTest2Counter;\r
 274         }\r
 275 }\r
 276 /*-----------------------------------------------------------*/\r
 277 \r
 278 static void prvSetupHardware( void )\r
 279 {\r
 280         /* Disable the watchdog, STOP and WAIT modes. */\r
 281         SOPT1 = 0;\r
 282 \r
 283         /* --- Setup clock to use external 25MHz source. --- */\r
 284 \r
 285         /* Extal and xtal pin ON. */\r
 286         PTDPF1_D4 = 0x03;\r
 287         PTDPF1_D5 = 0x03;\r
 288 \r
 289         /* Switch from FEI to FBE (FLL bypassed external)\r
 290         enable external clock source */\r
 291         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
 292               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
 293               | MCGC2_RANGE_MASK;   /* High range */\r
 294 \r
 295         /* Select clock mode and clear IREFs. */\r
 296         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
 297               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
 298               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
 299 \r
 300         /* Wait for Reference and Clock status bits to update. */\r
 301         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
 302         {\r
 303                 /* Nothing to do here. */\r
 304         }\r
 305 \r
 306         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
 307         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
 308               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
 309 \r
 310         /* Wait for PLL status and lock bits to update. */\r
 311         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
 312         {\r
 313                 /* Nothing to do here. */\r
 314         }\r
 315 \r
 316 \r
 317         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external\r
 318         mode). */\r
 319         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
 320 \r
 321         /* Wait for the clock status bits to update. */\r
 322         while( MCGSC_CLKST != 0x03 )\r
 323         {\r
 324                 /* Nothing to do here. */\r
 325         }\r
 326 \r
 327         /* Setup the IO for the LED outputs. */\r
 328         vParTestInitialise();\r
 329 }\r
 330 /*-----------------------------------------------------------*/\r
 331 \r
 332 void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
 333 {\r
 334         /* This will get called if a stack overflow is detected during the context\r
 335         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
 336         problems within nested interrupts, but only do this for debug purposes as\r
 337         it will increase the context switch time. */\r
 338 \r
 339         ( void ) pxTask;\r
 340         ( void ) pcTaskName;\r
 341 \r
 342         for( ;; )\r
 343         {\r
 344         }\r
 345 }\r
 346 /*-----------------------------------------------------------*/\r
 347 \r
 348 static void vRegTest1Task( void *pvParameters )\r
 349 {\r
 350   /* Just to remove compiler warnings. */\r
 351   ( void ) pvParameters;\r
 352 \r
 353         /* Set all the registers to known values, then check that each retains its\r
 354         expected value - as described at the top of this file.  If an error is\r
 355         found then the loop counter will no longer be incremented allowing the check\r
 356         task to recognise the error. */\r
 357         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
 358                                                 "       moveq           #1, d0                                  \n\t"\r
 359                                                 "       moveq           #2, d1                                  \n\t"\r
 360                                                 "       moveq           #3, d2                                  \n\t"\r
 361                                                 "       moveq           #4, d3                                  \n\t"\r
 362                                                 "       moveq           #5, d4                                  \n\t"\r
 363                                                 "       moveq           #6, d5                                  \n\t"\r
 364                                                 "       moveq           #7, d6                                  \n\t"\r
 365                                                 "       moveq           #8, d7                                  \n\t"\r
 366                                                 "       move            #9, a0                                  \n\t"\r
 367                                                 "       move            #10, a1                                 \n\t"\r
 368                                                 "       move            #11, a2                                 \n\t"\r
 369                                                 "       move            #12, a3                                 \n\t"\r
 370                                                 "       move            #13, a4                                 \n\t"\r
 371                                                 "       move            #15, a6                                 \n\t"\r
 372                                                 "                                                                               \n\t"\r
 373                                                 "       cmpi.l          #1, d0                                  \n\t"\r
 374                                                 "       bne                     reg_test_1_error                \n\t"\r
 375                                                 "       cmpi.l          #2, d1                                  \n\t"\r
 376                                                 "       bne                     reg_test_1_error                \n\t"\r
 377                                                 "       cmpi.l          #3, d2                                  \n\t"\r
 378                                                 "       bne                     reg_test_1_error                \n\t"\r
 379                                                 "       cmpi.l          #4, d3                                  \n\t"\r
 380                                                 "       bne                     reg_test_1_error                \n\t"\r
 381                                                 "       cmpi.l          #5, d4                                  \n\t"\r
 382                                                 "       bne                     reg_test_1_error                \n\t"\r
 383                                                 "       cmpi.l          #6, d5                                  \n\t"\r
 384                                                 "       bne                     reg_test_1_error                \n\t"\r
 385                                                 "       cmpi.l          #7, d6                                  \n\t"\r
 386                                                 "       bne                     reg_test_1_error                \n\t"\r
 387                                                 "       cmpi.l          #8, d7                                  \n\t"\r
 388                                                 "       bne                     reg_test_1_error                \n\t"\r
 389                                                 "       move            a0, d0                                  \n\t"\r
 390                                                 "       cmpi.l          #9, d0                                  \n\t"\r
 391                                                 "       bne                     reg_test_1_error                \n\t"\r
 392                                                 "       move            a1, d0                                  \n\t"\r
 393                                                 "       cmpi.l          #10, d0                                 \n\t"\r
 394                                                 "       bne                     reg_test_1_error                \n\t"\r
 395                                                 "       move            a2, d0                                  \n\t"\r
 396                                                 "       cmpi.l          #11, d0                                 \n\t"\r
 397                                                 "       bne                     reg_test_1_error                \n\t"\r
 398                                                 "       move            a3, d0                                  \n\t"\r
 399                                                 "       cmpi.l          #12, d0                                 \n\t"\r
 400                                                 "       bne                     reg_test_1_error                \n\t"\r
 401                                                 "       move            a4, d0                                  \n\t"\r
 402                                                 "       cmpi.l          #13, d0                                 \n\t"\r
 403                                                 "       bne                     reg_test_1_error                \n\t"\r
 404                                                 "       move            a6, d0                                  \n\t"\r
 405                                                 "       cmpi.l          #15, d0                                 \n\t"\r
 406                                                 "       bne                     reg_test_1_error                \n\t"\r
 407                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
 408                                                 "       addq            #1, d0                                  \n\t"\r
 409                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
 410                                                 "       bra                     reg_test_1_start                \n\t"\r
 411                                                 "reg_test_1_error:                                              \n\t"\r
 412                                                 "       bra                     reg_test_1_error                \n\t"\r
 413                                         );\r
 414 }\r
 415 /*-----------------------------------------------------------*/\r
 416 \r
 417 static void vRegTest2Task( void *pvParameters )\r
 418 {\r
 419   /* Just to remove compiler warnings. */\r
 420   ( void ) pvParameters;\r
 421 \r
 422         /* Set all the registers to known values, then check that each retains its\r
 423         expected value - as described at the top of this file.  If an error is\r
 424         found then the loop counter will no longer be incremented allowing the check\r
 425         task to recognise the error. */\r
 426         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
 427                                                 "       moveq           #10, d0                                 \n\t"\r
 428                                                 "       moveq           #20, d1                                 \n\t"\r
 429                                                 "       moveq           #30, d2                                 \n\t"\r
 430                                                 "       moveq           #40, d3                                 \n\t"\r
 431                                                 "       moveq           #50, d4                                 \n\t"\r
 432                                                 "       moveq           #60, d5                                 \n\t"\r
 433                                                 "       moveq           #70, d6                                 \n\t"\r
 434                                                 "       moveq           #80, d7                                 \n\t"\r
 435                                                 "       move            #90, a0                                 \n\t"\r
 436                                                 "       move            #100, a1                                \n\t"\r
 437                                                 "       move            #110, a2                                \n\t"\r
 438                                                 "       move            #120, a3                                \n\t"\r
 439                                                 "       move            #130, a4                                \n\t"\r
 440                                                 "       move            #150, a6                                \n\t"\r
 441                                                 "                                                                               \n\t"\r
 442                                                 "       cmpi.l          #10, d0                                 \n\t"\r
 443                                                 "       bne                     reg_test_2_error                \n\t"\r
 444                                                 "       cmpi.l          #20, d1                                 \n\t"\r
 445                                                 "       bne                     reg_test_2_error                \n\t"\r
 446                                                 "       cmpi.l          #30, d2                                 \n\t"\r
 447                                                 "       bne                     reg_test_2_error                \n\t"\r
 448                                                 "       cmpi.l          #40, d3                                 \n\t"\r
 449                                                 "       bne                     reg_test_2_error                \n\t"\r
 450                                                 "       cmpi.l          #50, d4                                 \n\t"\r
 451                                                 "       bne                     reg_test_2_error                \n\t"\r
 452                                                 "       cmpi.l          #60, d5                                 \n\t"\r
 453                                                 "       bne                     reg_test_2_error                \n\t"\r
 454                                                 "       cmpi.l          #70, d6                                 \n\t"\r
 455                                                 "       bne                     reg_test_2_error                \n\t"\r
 456                                                 "       cmpi.l          #80, d7                                 \n\t"\r
 457                                                 "       bne                     reg_test_2_error                \n\t"\r
 458                                                 "       move            a0, d0                                  \n\t"\r
 459                                                 "       cmpi.l          #90, d0                                 \n\t"\r
 460                                                 "       bne                     reg_test_2_error                \n\t"\r
 461                                                 "       move            a1, d0                                  \n\t"\r
 462                                                 "       cmpi.l          #100, d0                                \n\t"\r
 463                                                 "       bne                     reg_test_2_error                \n\t"\r
 464                                                 "       move            a2, d0                                  \n\t"\r
 465                                                 "       cmpi.l          #110, d0                                \n\t"\r
 466                                                 "       bne                     reg_test_2_error                \n\t"\r
 467                                                 "       move            a3, d0                                  \n\t"\r
 468                                                 "       cmpi.l          #120, d0                                \n\t"\r
 469                                                 "       bne                     reg_test_2_error                \n\t"\r
 470                                                 "       move            a4, d0                                  \n\t"\r
 471                                                 "       cmpi.l          #130, d0                                \n\t"\r
 472                                                 "       bne                     reg_test_2_error                \n\t"\r
 473                                                 "       move            a6, d0                                  \n\t"\r
 474                                                 "       cmpi.l          #150, d0                                \n\t"\r
 475                                                 "       bne                     reg_test_2_error                \n\t"\r
 476                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
 477                                                 "       addq            #1, d0                                  \n\t"\r
 478                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
 479                                                 "       bra                     reg_test_2_start                \n\t"\r
 480                                                 "reg_test_2_error:                                              \n\t"\r
 481                                                 "       bra                     reg_test_2_error                \n\t"\r
 482                                         );\r
 483 }\r
 484 /*-----------------------------------------------------------*/\r
 485 \r