1 /* Coldfire C Header File
\r
2 * Copyright Freescale Semiconductor Inc
\r
3 * All rights reserved.
\r
5 * 2008/05/23 Revision: 0.95
\r
7 * (c) Copyright UNIS, a.s. 1997-2008
\r
12 * http : www.processorexpert.com
\r
13 * mail : info@processorexpert.com
\r
16 #ifndef __MCF52221_SCM_H__
\r
17 #define __MCF52221_SCM_H__
\r
20 /*********************************************************************
\r
22 * System Control Module (SCM)
\r
24 *********************************************************************/
\r
26 /* Register read/write macros */
\r
27 #define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008))
\r
28 #define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C))
\r
29 #define MCF_SCM_CRSR (*(vuint8 *)(0x40000010))
\r
30 #define MCF_SCM_CWCR (*(vuint8 *)(0x40000011))
\r
31 #define MCF_SCM_CWSR (*(vuint8 *)(0x40000013))
\r
32 #define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014))
\r
33 #define MCF_SCM_PPMRL (*(vuint32*)(0x40000018))
\r
34 #define MCF_SCM_MPARK (*(vuint32*)(0x4000001C))
\r
35 #define MCF_SCM_MPR (*(vuint8 *)(0x40000020))
\r
36 #define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021))
\r
37 #define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022))
\r
38 #define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023))
\r
39 #define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024))
\r
40 #define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025))
\r
41 #define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026))
\r
42 #define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027))
\r
43 #define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028))
\r
44 #define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029))
\r
45 #define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A))
\r
46 #define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B))
\r
47 #define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C))
\r
48 #define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030))
\r
49 #define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031))
\r
50 #define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1)))
\r
51 #define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1)))
\r
54 #define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000))
\r
55 #define MCF_SCM_IPSBAR_V (0x1)
\r
56 #define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
\r
59 /* Bit definitions and macros for MCF_SCM_RAMBAR */
\r
60 #define MCF_SCM_RAMBAR_BDE (0x200)
\r
61 #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
\r
63 /* Bit definitions and macros for MCF_SCM_PPMRH */
\r
64 #define MCF_SCM_PPMRH_CDPORTS (0x1)
\r
65 #define MCF_SCM_PPMRH_CDEPORT (0x2)
\r
66 #define MCF_SCM_PPMRH_CDPIT0 (0x8)
\r
67 #define MCF_SCM_PPMRH_CDPIT1 (0x10)
\r
68 #define MCF_SCM_PPMRH_CDADC (0x80)
\r
69 #define MCF_SCM_PPMRH_CDGPT (0x100)
\r
70 #define MCF_SCM_PPMRH_CDPWM (0x200)
\r
71 #define MCF_SCM_PPMRH_CDFCAN (0x400)
\r
72 #define MCF_SCM_PPMRH_CDCFM (0x800)
\r
74 /* Bit definitions and macros for MCF_SCM_CRSR */
\r
75 #define MCF_SCM_CRSR_EXT (0x80)
\r
77 /* Bit definitions and macros for MCF_SCM_CWCR */
\r
78 #define MCF_SCM_CWCR_CWTIF (0x1)
\r
79 #define MCF_SCM_CWCR_CWTAVAL (0x2)
\r
80 #define MCF_SCM_CWCR_CWTA (0x4)
\r
81 #define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
\r
82 #define MCF_SCM_CWCR_CWT_2_9 (0)
\r
83 #define MCF_SCM_CWCR_CWT_2_11 (0x8)
\r
84 #define MCF_SCM_CWCR_CWT_2_13 (0x10)
\r
85 #define MCF_SCM_CWCR_CWT_2_15 (0x18)
\r
86 #define MCF_SCM_CWCR_CWT_2_19 (0x20)
\r
87 #define MCF_SCM_CWCR_CWT_2_23 (0x28)
\r
88 #define MCF_SCM_CWCR_CWT_2_27 (0x30)
\r
89 #define MCF_SCM_CWCR_CWT_2_31 (0x38)
\r
90 #define MCF_SCM_CWCR_CWRI (0x40)
\r
91 #define MCF_SCM_CWCR_CWE (0x80)
\r
93 /* Bit definitions and macros for MCF_SCM_CWSR */
\r
94 #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
\r
96 /* Bit definitions and macros for MCF_SCM_DMAREQC */
\r
97 #define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
\r
98 #define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
\r
99 #define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
\r
100 #define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
\r
102 /* Bit definitions and macros for MCF_SCM_PPMRL */
\r
103 #define MCF_SCM_PPMRL_CDG (0x2)
\r
104 #define MCF_SCM_PPMRL_CDDMA (0x10)
\r
105 #define MCF_SCM_PPMRL_CDUART0 (0x20)
\r
106 #define MCF_SCM_PPMRL_CDUART1 (0x40)
\r
107 #define MCF_SCM_PPMRL_CDUART2 (0x80)
\r
108 #define MCF_SCM_PPMRL_CDI2C (0x200)
\r
109 #define MCF_SCM_PPMRL_CDQSPI (0x400)
\r
110 #define MCF_SCM_PPMRL_CDTMR0 (0x2000)
\r
111 #define MCF_SCM_PPMRL_CDTMR1 (0x4000)
\r
112 #define MCF_SCM_PPMRL_CDTMR2 (0x8000)
\r
113 #define MCF_SCM_PPMRL_CDTMR3 (0x10000)
\r
114 #define MCF_SCM_PPMRL_CDINTC0 (0x20000)
\r
116 /* Bit definitions and macros for MCF_SCM_MPARK */
\r
117 #define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
\r
118 #define MCF_SCM_MPARK_PRKLAST (0x1000)
\r
119 #define MCF_SCM_MPARK_TIMEOUT (0x2000)
\r
120 #define MCF_SCM_MPARK_FIXED (0x4000)
\r
121 #define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
\r
122 #define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
\r
123 #define MCF_SCM_MPARK_BCR24BIT (0x1000000)
\r
124 #define MCF_SCM_MPARK_M2_P_EN (0x2000000)
\r
126 /* Bit definitions and macros for MCF_SCM_MPR */
\r
127 #define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
\r
129 /* Bit definitions and macros for MCF_SCM_PPMRS */
\r
130 #define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
\r
131 #define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
\r
132 #define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
\r
133 #define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
\r
134 #define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
\r
135 #define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
\r
136 #define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
\r
137 #define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
\r
138 #define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
\r
139 #define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
\r
140 #define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
\r
141 #define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
\r
142 #define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
\r
143 #define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
\r
144 #define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
\r
145 #define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
\r
146 #define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
\r
147 #define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
\r
148 #define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
\r
149 #define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
\r
150 #define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
\r
151 #define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
\r
152 #define MCF_SCM_PPMRS_SET_CDG (0x1)
\r
154 /* Bit definitions and macros for MCF_SCM_PPMRC */
\r
155 #define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
\r
156 #define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
\r
157 #define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
\r
158 #define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
\r
159 #define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
\r
160 #define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
\r
161 #define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
\r
162 #define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
\r
163 #define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
\r
164 #define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
\r
165 #define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
\r
166 #define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
\r
167 #define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
\r
168 #define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
\r
169 #define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
\r
170 #define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
\r
171 #define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
\r
172 #define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
\r
173 #define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
\r
174 #define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
\r
175 #define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
\r
176 #define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
\r
177 #define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
\r
179 /* Bit definitions and macros for MCF_SCM_IPSBMT */
\r
180 #define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
\r
181 #define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
\r
182 #define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
\r
183 #define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
\r
184 #define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
\r
185 #define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
\r
186 #define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
\r
187 #define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
\r
188 #define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
\r
189 #define MCF_SCM_IPSBMT_BME (0x8)
\r
191 /* Bit definitions and macros for MCF_SCM_PACR */
\r
192 #define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
\r
193 #define MCF_SCM_PACR_LOCK0 (0x8)
\r
194 #define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
\r
195 #define MCF_SCM_PACR_LOCK1 (0x80)
\r
197 /* Bit definitions and macros for MCF_SCM_GPACR */
\r
198 #define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
\r
199 #define MCF_SCM_GPACR_LOCK (0x80)
\r
202 #endif /* __MCF52221_SCM_H__ */
\r