1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.91
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8 #ifndef __MCF52235_PIT_H__
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9 #define __MCF52235_PIT_H__
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12 /*********************************************************************
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14 * Programmable Interrupt Timer (PIT)
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000]))
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20 #define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002]))
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21 #define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004]))
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23 #define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000]))
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24 #define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002]))
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25 #define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004]))
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27 #define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))
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28 #define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))
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29 #define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))
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32 /* Bit definitions and macros for MCF_PIT_PCSR */
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33 #define MCF_PIT_PCSR_EN (0x1)
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34 #define MCF_PIT_PCSR_RLD (0x2)
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35 #define MCF_PIT_PCSR_PIF (0x4)
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36 #define MCF_PIT_PCSR_PIE (0x8)
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37 #define MCF_PIT_PCSR_OVW (0x10)
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38 #define MCF_PIT_PCSR_DBG (0x20)
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39 #define MCF_PIT_PCSR_DOZE (0x40)
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40 #define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
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42 /* Bit definitions and macros for MCF_PIT_PMR */
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43 #define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
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45 /* Bit definitions and macros for MCF_PIT_PCNTR */
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46 #define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
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49 #endif /* __MCF52235_PIT_H__ */
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