1 /* Coldfire C Header File
\r
2 * Copyright Freescale Semiconductor Inc
\r
3 * All rights reserved.
\r
5 * 2008/04/17 Revision: 0.2
\r
7 * (c) Copyright UNIS, spol. s r.o. 1997-2008
\r
12 * http : www.processorexpert.com
\r
13 * mail : info@processorexpert.com
\r
16 #ifndef __MCF52259_FBCS_H__
\r
17 #define __MCF52259_FBCS_H__
\r
20 /*********************************************************************
\r
22 * Mini-FlexBus Chip Select Module (FBCS)
\r
24 *********************************************************************/
\r
26 /* Register read/write macros */
\r
27 #define MCF_FBCS0_CSAR (*(vuint32*)(0x40000080))
\r
28 #define MCF_FBCS0_CSMR (*(vuint32*)(0x40000084))
\r
29 #define MCF_FBCS0_CSCR (*(vuint32*)(0x40000088))
\r
31 #define MCF_FBCS1_CSAR (*(vuint32*)(0x4000008C))
\r
32 #define MCF_FBCS1_CSMR (*(vuint32*)(0x40000090))
\r
33 #define MCF_FBCS1_CSCR (*(vuint32*)(0x40000094))
\r
35 #define MCF_FBCS_CSAR(x) (*(vuint32*)(0x40000080 + ((x)*0xC)))
\r
36 #define MCF_FBCS_CSMR(x) (*(vuint32*)(0x40000084 + ((x)*0xC)))
\r
37 #define MCF_FBCS_CSCR(x) (*(vuint32*)(0x40000088 + ((x)*0xC)))
\r
40 /* Bit definitions and macros for MCF_FBCS_CSAR */
\r
41 #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
\r
43 /* Bit definitions and macros for MCF_FBCS_CSMR */
\r
44 #define MCF_FBCS_CSMR_V (0x1)
\r
45 #define MCF_FBCS_CSMR_WP (0x100)
\r
46 #define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
\r
47 #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
\r
48 #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
\r
49 #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
\r
50 #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
\r
51 #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
\r
52 #define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
\r
53 #define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
\r
54 #define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
\r
55 #define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
\r
56 #define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
\r
57 #define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
\r
58 #define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
\r
59 #define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
\r
60 #define MCF_FBCS_CSMR_BAM_1M (0xF0000)
\r
61 #define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
\r
62 #define MCF_FBCS_CSMR_BAM_512K (0x70000)
\r
63 #define MCF_FBCS_CSMR_BAM_256K (0x30000)
\r
64 #define MCF_FBCS_CSMR_BAM_128K (0x10000)
\r
65 #define MCF_FBCS_CSMR_BAM_64K (0)
\r
67 /* Bit definitions and macros for MCF_FBCS_CSCR */
\r
68 #define MCF_FBCS_CSCR_BSTW (0x8)
\r
69 #define MCF_FBCS_CSCR_BSTR (0x10)
\r
70 #define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
\r
71 #define MCF_FBCS_CSCR_PS_8 (0x40)
\r
72 #define MCF_FBCS_CSCR_PS_16 (0x80)
\r
73 #define MCF_FBCS_CSCR_AA (0x100)
\r
74 #define MCF_FBCS_CSCR_MUX (0x200)
\r
75 #define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
\r
76 #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
\r
77 #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
\r
78 #define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
\r
79 #define MCF_FBCS_CSCR_SWSEN (0x800000)
\r
80 #define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
\r
83 #endif /* __MCF52259_FBCS_H__ */
\r