1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.9
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8 #ifndef __MCF5282_SCM_H__
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9 #define __MCF5282_SCM_H__
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12 /*********************************************************************
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14 * System Control Module (SCM)
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))
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20 #define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))
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21 #define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))
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22 #define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))
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23 #define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))
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24 #define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))
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25 #define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))
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26 #define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))
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27 #define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))
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28 #define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))
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29 #define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))
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30 #define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))
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31 #define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x2A]))
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32 #define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2B]))
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33 #define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2C]))
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34 #define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2E]))
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35 #define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))
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36 #define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))
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37 #define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))
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40 #define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))
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41 #define MCF_SCM_IPSBAR_V (0x1)
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42 #define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
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45 /* Bit definitions and macros for MCF_SCM_RAMBAR */
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46 #define MCF_SCM_RAMBAR_BDE (0x200)
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47 #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
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49 /* Bit definitions and macros for MCF_SCM_CRSR */
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50 #define MCF_SCM_CRSR_CWDR (0x20)
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51 #define MCF_SCM_CRSR_EXT (0x80)
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53 /* Bit definitions and macros for MCF_SCM_CWCR */
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54 #define MCF_SCM_CWCR_CWTIF (0x1)
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55 #define MCF_SCM_CWCR_CWTAVAL (0x2)
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56 #define MCF_SCM_CWCR_CWTA (0x4)
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57 #define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
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58 #define MCF_SCM_CWCR_CWT_2_9 (0)
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59 #define MCF_SCM_CWCR_CWT_2_11 (0x8)
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60 #define MCF_SCM_CWCR_CWT_2_13 (0x10)
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61 #define MCF_SCM_CWCR_CWT_2_15 (0x18)
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62 #define MCF_SCM_CWCR_CWT_2_19 (0x20)
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63 #define MCF_SCM_CWCR_CWT_2_23 (0x28)
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64 #define MCF_SCM_CWCR_CWT_2_27 (0x30)
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65 #define MCF_SCM_CWCR_CWT_2_31 (0x38)
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66 #define MCF_SCM_CWCR_CWRI (0x40)
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67 #define MCF_SCM_CWCR_CWE (0x80)
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69 /* Bit definitions and macros for MCF_SCM_CWSR */
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70 #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
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72 /* Bit definitions and macros for MCF_SCM_DMAREQC */
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73 #define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
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74 #define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
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75 #define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
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76 #define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
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78 /* Bit definitions and macros for MCF_SCM_MPARK */
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79 #define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
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80 #define MCF_SCM_MPARK_PRKLAST (0x1000)
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81 #define MCF_SCM_MPARK_TIMEOUT (0x2000)
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82 #define MCF_SCM_MPARK_FIXED (0x4000)
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83 #define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)
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84 #define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
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85 #define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
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86 #define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x3)<<0x16)
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87 #define MCF_SCM_MPARK_BCR24BIT (0x1000000)
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88 #define MCF_SCM_MPARK_M2_P_EN (0x2000000)
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90 /* Bit definitions and macros for MCF_SCM_MPR */
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91 #define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
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93 /* Bit definitions and macros for MCF_SCM_PACR0 */
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94 #define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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95 #define MCF_SCM_PACR0_LOCK0 (0x8)
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96 #define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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97 #define MCF_SCM_PACR0_LOCK1 (0x80)
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99 /* Bit definitions and macros for MCF_SCM_PACR1 */
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100 #define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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101 #define MCF_SCM_PACR1_LOCK0 (0x8)
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102 #define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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103 #define MCF_SCM_PACR1_LOCK1 (0x80)
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105 /* Bit definitions and macros for MCF_SCM_PACR2 */
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106 #define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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107 #define MCF_SCM_PACR2_LOCK0 (0x8)
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108 #define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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109 #define MCF_SCM_PACR2_LOCK1 (0x80)
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111 /* Bit definitions and macros for MCF_SCM_PACR3 */
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112 #define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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113 #define MCF_SCM_PACR3_LOCK0 (0x8)
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114 #define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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115 #define MCF_SCM_PACR3_LOCK1 (0x80)
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117 /* Bit definitions and macros for MCF_SCM_PACR4 */
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118 #define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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119 #define MCF_SCM_PACR4_LOCK0 (0x8)
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120 #define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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121 #define MCF_SCM_PACR4_LOCK1 (0x80)
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123 /* Bit definitions and macros for MCF_SCM_PACR5 */
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124 #define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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125 #define MCF_SCM_PACR5_LOCK0 (0x8)
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126 #define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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127 #define MCF_SCM_PACR5_LOCK1 (0x80)
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129 /* Bit definitions and macros for MCF_SCM_PACR6 */
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130 #define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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131 #define MCF_SCM_PACR6_LOCK0 (0x8)
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132 #define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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133 #define MCF_SCM_PACR6_LOCK1 (0x80)
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135 /* Bit definitions and macros for MCF_SCM_PACR7 */
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136 #define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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137 #define MCF_SCM_PACR7_LOCK0 (0x8)
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138 #define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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139 #define MCF_SCM_PACR7_LOCK1 (0x80)
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141 /* Bit definitions and macros for MCF_SCM_PACR8 */
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142 #define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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143 #define MCF_SCM_PACR8_LOCK0 (0x8)
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144 #define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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145 #define MCF_SCM_PACR8_LOCK1 (0x80)
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147 /* Bit definitions and macros for MCF_SCM_GPACR */
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148 #define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
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149 #define MCF_SCM_GPACR_LOCK (0x80)
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152 #endif /* __MCF5282_SCM_H__ */
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