1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.9
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8 #ifndef __MCF5282_SDRAMC_H__
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9 #define __MCF5282_SDRAMC_H__
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12 /*********************************************************************
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14 * Synchronous DRAM Controller (SDRAMC)
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_SDRAMC_DCR (*(vuint16*)(&__IPSBAR[0x40]))
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20 #define MCF_SDRAMC_DACR0 (*(vuint32*)(&__IPSBAR[0x48]))
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21 #define MCF_SDRAMC_DMR0 (*(vuint32*)(&__IPSBAR[0x4C]))
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22 #define MCF_SDRAMC_DACR1 (*(vuint32*)(&__IPSBAR[0x50]))
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23 #define MCF_SDRAMC_DMR1 (*(vuint32*)(&__IPSBAR[0x54]))
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24 #define MCF_SDRAMC_DACR(x) (*(vuint32*)(&__IPSBAR[0x48 + ((x)*0x8)]))
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25 #define MCF_SDRAMC_DMR(x) (*(vuint32*)(&__IPSBAR[0x4C + ((x)*0x8)]))
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28 /* Bit definitions and macros for MCF_SDRAMC_DCR */
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29 #define MCF_SDRAMC_DCR_RC(x) (((x)&0x1FF)<<0)
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30 #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x3)<<0x9)
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31 #define MCF_SDRAMC_DCR_RTIM_3 (0)
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32 #define MCF_SDRAMC_DCR_RTIM_6 (0x200)
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33 #define MCF_SDRAMC_DCR_RTIM_9 (0x400)
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34 #define MCF_SDRAMC_DCR_IS (0x800)
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35 #define MCF_SDRAMC_DCR_COC (0x1000)
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36 #define MCF_SDRAMC_DCR_NAM (0x2000)
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38 /* Bit definitions and macros for MCF_SDRAMC_DACR */
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39 #define MCF_SDRAMC_DACR_IP (0x8)
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40 #define MCF_SDRAMC_DACR_PS(x) (((x)&0x3)<<0x4)
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41 #define MCF_SDRAMC_DACR_PS_32 (0)
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42 #define MCF_SDRAMC_DACR_PS_8 (0x10)
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43 #define MCF_SDRAMC_DACR_PS_16 (0x20)
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44 #define MCF_SDRAMC_DACR_IMRS (0x40)
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45 #define MCF_SDRAMC_DACR_CBM(x) (((x)&0x7)<<0x8)
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46 #define MCF_SDRAMC_DACR_CASL(x) (((x)&0x3)<<0xC)
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47 #define MCF_SDRAMC_DACR_RE (0x8000)
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48 #define MCF_SDRAMC_DACR_BA(x) ((x)&0xFFFC0000)
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49 #define MCF_SDRAMC_DACR_CASL_1 (0)
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50 #define MCF_SDRAMC_DACR_CASL_2 (0x1000)
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51 #define MCF_SDRAMC_DACR_CASL_3 (0x2000)
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53 /* Bit definitions and macros for MCF_SDRAMC_DMR */
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54 #define MCF_SDRAMC_DMR_V (0x1)
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55 #define MCF_SDRAMC_DMR_UD (0x2)
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56 #define MCF_SDRAMC_DMR_UC (0x4)
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57 #define MCF_SDRAMC_DMR_SD (0x8)
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58 #define MCF_SDRAMC_DMR_SC (0x10)
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59 #define MCF_SDRAMC_DMR_AM (0x20)
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60 #define MCF_SDRAMC_DMR_CI (0x40)
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61 #define MCF_SDRAMC_DMR_WP (0x100)
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62 #define MCF_SDRAMC_DMR_BAM(x) (((x)&0x3FFF)<<0x12)
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63 #define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
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64 #define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
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65 #define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
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66 #define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
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67 #define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
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68 #define MCF_SDRAMC_DMR_BAM_256M (0xFFC0000)
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69 #define MCF_SDRAMC_DMR_BAM_128M (0x7FC0000)
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70 #define MCF_SDRAMC_DMR_BAM_64M (0x3FC0000)
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71 #define MCF_SDRAMC_DMR_BAM_32M (0x1FC0000)
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72 #define MCF_SDRAMC_DMR_BAM_16M (0xFC0000)
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73 #define MCF_SDRAMC_DMR_BAM_8M (0x7C0000)
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74 #define MCF_SDRAMC_DMR_BAM_4M (0x3C0000)
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75 #define MCF_SDRAMC_DMR_BAM_2M (0x1C0000)
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76 #define MCF_SDRAMC_DMR_BAM_1M (0xC0000)
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77 #define MCF_SDRAMC_DMR_BAM_1024K (0xC0000)
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78 #define MCF_SDRAMC_DMR_BAM_512K (0x40000)
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79 #define MCF_SDRAMC_DMR_BAM_256K (0)
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82 #endif /* __MCF5282_SDRAMC_H__ */
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