1 //*****************************************************************************
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3 // hw_can.h - Defines and macros used when accessing the can.
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5 // Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. You may not combine
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14 // this software with "viral" open-source software in order to form a larger
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15 // program. Any use in violation of the foregoing restrictions may subject
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16 // the user to criminal sanctions under applicable laws, as well as to civil
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17 // liability for the breach of the terms and conditions of this license.
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19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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27 //*****************************************************************************
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29 #ifndef __HW_CAN_H__
\r
30 #define __HW_CAN_H__
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32 //*****************************************************************************
\r
34 // The following are defines for the CAN register offsets.
\r
36 //*****************************************************************************
\r
37 #define CAN_O_CTL 0x00000000 // Control register
\r
38 #define CAN_O_STS 0x00000004 // Status register
\r
39 #define CAN_O_ERR 0x00000008 // Error register
\r
40 #define CAN_O_BIT 0x0000000C // Bit Timing register
\r
41 #define CAN_O_INT 0x00000010 // Interrupt register
\r
42 #define CAN_O_TST 0x00000014 // Test register
\r
43 #define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
\r
44 #define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
\r
45 #define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
\r
46 #define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
\r
47 #define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
\r
48 #define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
\r
49 #define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
\r
50 #define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
\r
51 #define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
\r
52 #define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
\r
53 #define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
\r
54 #define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
\r
55 #define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
\r
56 #define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
\r
57 #define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
\r
58 #define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
\r
59 #define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
\r
60 #define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
\r
61 #define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
\r
62 #define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
\r
63 #define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
\r
64 #define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
\r
65 #define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
\r
66 #define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
\r
67 #define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
\r
68 #define CAN_O_NWDA1 0x00000120 // New Data 1 register
\r
69 #define CAN_O_NWDA2 0x00000124 // New Data 2 register
\r
70 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
\r
71 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
\r
72 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
\r
73 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
\r
75 //*****************************************************************************
\r
77 // The following are defines for the bit fields in the CAN_CTL register.
\r
79 //*****************************************************************************
\r
80 #define CAN_CTL_TEST 0x00000080 // Test mode enable
\r
81 #define CAN_CTL_CCE 0x00000040 // Configuration change enable
\r
82 #define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
\r
83 #define CAN_CTL_EIE 0x00000008 // Error interrupt enable
\r
84 #define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
\r
85 #define CAN_CTL_IE 0x00000002 // Module interrupt enable
\r
86 #define CAN_CTL_INIT 0x00000001 // Initialization
\r
88 //*****************************************************************************
\r
90 // The following are defines for the bit fields in the CAN_STS register.
\r
92 //*****************************************************************************
\r
93 #define CAN_STS_BOFF 0x00000080 // Bus Off status
\r
94 #define CAN_STS_EWARN 0x00000040 // Error Warning status
\r
95 #define CAN_STS_EPASS 0x00000020 // Error Passive status
\r
96 #define CAN_STS_RXOK 0x00000010 // Received Message Successful
\r
97 #define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
\r
98 #define CAN_STS_LEC_M 0x00000007 // Last Error Code
\r
99 #define CAN_STS_LEC_NONE 0x00000000 // No error
\r
100 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
\r
101 #define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
\r
102 #define CAN_STS_LEC_ACK 0x00000003 // Ack error
\r
103 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
\r
104 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
\r
105 #define CAN_STS_LEC_CRC 0x00000006 // CRC error
\r
106 #define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
\r
108 //*****************************************************************************
\r
110 // The following are defines for the bit fields in the CAN_ERR register.
\r
112 //*****************************************************************************
\r
113 #define CAN_ERR_RP 0x00008000 // Receive error passive status
\r
114 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
\r
115 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
\r
116 #define CAN_ERR_REC_S 8 // Receive error counter bit pos
\r
117 #define CAN_ERR_TEC_S 0 // Transmit error counter bit pos
\r
119 //*****************************************************************************
\r
121 // The following are defines for the bit fields in the CAN_BIT register.
\r
123 //*****************************************************************************
\r
124 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
\r
125 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
\r
127 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
\r
128 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.
\r
129 #define CAN_BIT_TSEG2_S 12
\r
130 #define CAN_BIT_TSEG1_S 8
\r
131 #define CAN_BIT_SJW_S 6
\r
132 #define CAN_BIT_BRP_S 0
\r
134 //*****************************************************************************
\r
136 // The following are defines for the bit fields in the CAN_INT register.
\r
138 //*****************************************************************************
\r
139 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
\r
140 #define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
\r
141 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
\r
143 //*****************************************************************************
\r
145 // The following are defines for the bit fields in the CAN_TST register.
\r
147 //*****************************************************************************
\r
148 #define CAN_TST_RX 0x00000080 // CAN_RX pin status
\r
149 #define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin
\r
150 #define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
\r
151 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
\r
152 #define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
\r
153 #define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
\r
154 #define CAN_TST_LBACK 0x00000010 // Loop back mode
\r
155 #define CAN_TST_SILENT 0x00000008 // Silent mode
\r
156 #define CAN_TST_BASIC 0x00000004 // Basic mode
\r
158 //*****************************************************************************
\r
160 // The following are defines for the bit fields in the CAN_BRPE register.
\r
162 //*****************************************************************************
\r
163 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.
\r
164 #define CAN_BRPE_BRPE_S 0
\r
166 //*****************************************************************************
\r
168 // The following are defines for the bit fields in the CAN_TXRQ1 register.
\r
170 //*****************************************************************************
\r
171 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
\r
172 #define CAN_TXRQ1_TXRQST_S 0
\r
174 //*****************************************************************************
\r
176 // The following are defines for the bit fields in the CAN_TXRQ2 register.
\r
178 //*****************************************************************************
\r
179 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
\r
180 #define CAN_TXRQ2_TXRQST_S 0
\r
182 //*****************************************************************************
\r
184 // The following are defines for the bit fields in the CAN_NWDA1 register.
\r
186 //*****************************************************************************
\r
187 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
\r
188 #define CAN_NWDA1_NEWDAT_S 0
\r
190 //*****************************************************************************
\r
192 // The following are defines for the bit fields in the CAN_NWDA2 register.
\r
194 //*****************************************************************************
\r
195 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
\r
196 #define CAN_NWDA2_NEWDAT_S 0
\r
198 //*****************************************************************************
\r
200 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
\r
202 //*****************************************************************************
\r
203 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
\r
204 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
\r
205 #define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
\r
206 // it is interpreted as 0x20, or
\r
209 //*****************************************************************************
\r
211 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
\r
213 //*****************************************************************************
\r
214 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
\r
215 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
\r
216 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
\r
217 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
\r
218 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
\r
219 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.
\r
220 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.
\r
221 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
\r
222 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
\r
224 //*****************************************************************************
\r
226 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
\r
228 //*****************************************************************************
\r
229 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
\r
230 #define CAN_IF1MSK1_IDMSK_S 0
\r
232 //*****************************************************************************
\r
234 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
\r
236 //*****************************************************************************
\r
237 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
\r
238 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
\r
239 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
\r
240 #define CAN_IF1MSK2_IDMSK_S 0
\r
242 //*****************************************************************************
\r
244 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
\r
246 //*****************************************************************************
\r
247 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
\r
248 #define CAN_IF1ARB1_ID_S 0
\r
250 //*****************************************************************************
\r
252 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
\r
254 //*****************************************************************************
\r
255 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
\r
256 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
\r
257 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
\r
258 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
\r
259 #define CAN_IF1ARB2_ID_S 0
\r
261 //*****************************************************************************
\r
263 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
\r
265 //*****************************************************************************
\r
266 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
\r
267 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
\r
268 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
\r
269 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
\r
270 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
\r
271 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
\r
272 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
\r
273 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
\r
274 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
\r
275 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
\r
276 #define CAN_IF1MCTL_DLC_S 0
\r
278 //*****************************************************************************
\r
280 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
\r
282 //*****************************************************************************
\r
283 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
\r
284 #define CAN_IF1DA1_DATA_S 0
\r
286 //*****************************************************************************
\r
288 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
\r
290 //*****************************************************************************
\r
291 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
\r
292 #define CAN_IF1DA2_DATA_S 0
\r
294 //*****************************************************************************
\r
296 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
\r
298 //*****************************************************************************
\r
299 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
\r
300 #define CAN_IF1DB1_DATA_S 0
\r
302 //*****************************************************************************
\r
304 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
\r
306 //*****************************************************************************
\r
307 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
\r
308 #define CAN_IF1DB2_DATA_S 0
\r
310 //*****************************************************************************
\r
312 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
\r
314 //*****************************************************************************
\r
315 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
\r
316 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
\r
317 #define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
\r
318 // it is interpreted as 0x20, or
\r
321 //*****************************************************************************
\r
323 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
\r
325 //*****************************************************************************
\r
326 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
\r
327 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
\r
328 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
\r
329 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
\r
330 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
\r
331 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.
\r
332 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.
\r
333 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
\r
334 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
\r
336 //*****************************************************************************
\r
338 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
\r
340 //*****************************************************************************
\r
341 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
\r
342 #define CAN_IF2MSK1_IDMSK_S 0
\r
344 //*****************************************************************************
\r
346 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
\r
348 //*****************************************************************************
\r
349 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
\r
350 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
\r
351 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
\r
352 #define CAN_IF2MSK2_IDMSK_S 0
\r
354 //*****************************************************************************
\r
356 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
\r
358 //*****************************************************************************
\r
359 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
\r
360 #define CAN_IF2ARB1_ID_S 0
\r
362 //*****************************************************************************
\r
364 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
\r
366 //*****************************************************************************
\r
367 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
\r
368 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
\r
369 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
\r
370 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
\r
371 #define CAN_IF2ARB2_ID_S 0
\r
373 //*****************************************************************************
\r
375 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
\r
377 //*****************************************************************************
\r
378 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
\r
379 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
\r
380 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
\r
381 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
\r
382 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
\r
383 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
\r
384 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
\r
385 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
\r
386 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
\r
387 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
\r
388 #define CAN_IF2MCTL_DLC_S 0
\r
390 //*****************************************************************************
\r
392 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
\r
394 //*****************************************************************************
\r
395 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
\r
396 #define CAN_IF2DA1_DATA_S 0
\r
398 //*****************************************************************************
\r
400 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
\r
402 //*****************************************************************************
\r
403 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
\r
404 #define CAN_IF2DA2_DATA_S 0
\r
406 //*****************************************************************************
\r
408 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
\r
410 //*****************************************************************************
\r
411 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
\r
412 #define CAN_IF2DB1_DATA_S 0
\r
414 //*****************************************************************************
\r
416 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
\r
418 //*****************************************************************************
\r
419 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
\r
420 #define CAN_IF2DB2_DATA_S 0
\r
422 //*****************************************************************************
\r
424 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
\r
426 //*****************************************************************************
\r
427 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
\r
428 #define CAN_MSG1INT_INTPND_S 0
\r
430 //*****************************************************************************
\r
432 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
\r
434 //*****************************************************************************
\r
435 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
\r
436 #define CAN_MSG2INT_INTPND_S 0
\r
438 //*****************************************************************************
\r
440 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
\r
442 //*****************************************************************************
\r
443 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
\r
444 #define CAN_MSG1VAL_MSGVAL_S 0
\r
446 //*****************************************************************************
\r
448 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
\r
450 //*****************************************************************************
\r
451 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
\r
452 #define CAN_MSG2VAL_MSGVAL_S 0
\r
454 //*****************************************************************************
\r
456 // The following definitions are deprecated.
\r
458 //*****************************************************************************
\r
461 //*****************************************************************************
\r
463 // The following are deprecated defines for the CAN register offsets.
\r
465 //*****************************************************************************
\r
466 #define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
\r
467 #define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
\r
468 #define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
\r
469 #define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
\r
471 //*****************************************************************************
\r
473 // The following are deprecated defines for the reset values of the can
\r
476 //*****************************************************************************
\r
477 #define CAN_RV_IF1MSK2 0x0000FFFF
\r
478 #define CAN_RV_IF1MSK1 0x0000FFFF
\r
479 #define CAN_RV_IF2MSK1 0x0000FFFF
\r
480 #define CAN_RV_IF2MSK2 0x0000FFFF
\r
481 #define CAN_RV_BIT 0x00002301
\r
482 #define CAN_RV_CTL 0x00000001
\r
483 #define CAN_RV_IF1CRQ 0x00000001
\r
484 #define CAN_RV_IF2CRQ 0x00000001
\r
485 #define CAN_RV_TXRQ2 0x00000000
\r
486 #define CAN_RV_IF2DB1 0x00000000
\r
487 #define CAN_RV_INT 0x00000000
\r
488 #define CAN_RV_IF1DB2 0x00000000
\r
489 #define CAN_RV_BRPE 0x00000000
\r
490 #define CAN_RV_IF2DA2 0x00000000
\r
491 #define CAN_RV_MSGVAL2 0x00000000
\r
492 #define CAN_RV_TXRQ1 0x00000000
\r
493 #define CAN_RV_IF1MCTL 0x00000000
\r
494 #define CAN_RV_IF1DB1 0x00000000
\r
495 #define CAN_RV_STS 0x00000000
\r
496 #define CAN_RV_MSGINT1 0x00000000
\r
497 #define CAN_RV_IF1DA2 0x00000000
\r
498 #define CAN_RV_TST 0x00000000
\r
499 #define CAN_RV_IF1ARB1 0x00000000
\r
500 #define CAN_RV_IF1ARB2 0x00000000
\r
501 #define CAN_RV_NWDA2 0x00000000
\r
502 #define CAN_RV_IF2CMSK 0x00000000
\r
503 #define CAN_RV_NWDA1 0x00000000
\r
504 #define CAN_RV_IF1DA1 0x00000000
\r
505 #define CAN_RV_IF2DA1 0x00000000
\r
506 #define CAN_RV_IF2MCTL 0x00000000
\r
507 #define CAN_RV_MSGVAL1 0x00000000
\r
508 #define CAN_RV_IF1CMSK 0x00000000
\r
509 #define CAN_RV_ERR 0x00000000
\r
510 #define CAN_RV_IF2ARB2 0x00000000
\r
511 #define CAN_RV_MSGINT2 0x00000000
\r
512 #define CAN_RV_IF2ARB1 0x00000000
\r
513 #define CAN_RV_IF2DB2 0x00000000
\r
515 //*****************************************************************************
\r
517 // The following are deprecated defines for the bit fields in the CAN_STS
\r
520 //*****************************************************************************
\r
521 #define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
\r
523 //*****************************************************************************
\r
525 // The following are deprecated defines for the bit fields in the CAN_ERR
\r
528 //*****************************************************************************
\r
529 #define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
\r
530 #define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
\r
531 #define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
\r
532 #define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
\r
534 //*****************************************************************************
\r
536 // The following are deprecated defines for the bit fields in the CAN_BIT
\r
539 //*****************************************************************************
\r
540 #define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
\r
541 #define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
\r
542 #define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
\r
543 #define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
\r
545 //*****************************************************************************
\r
547 // The following are deprecated defines for the bit fields in the CAN_INT
\r
550 //*****************************************************************************
\r
551 #define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
\r
553 //*****************************************************************************
\r
555 // The following are deprecated defines for the bit fields in the CAN_TST
\r
558 //*****************************************************************************
\r
559 #define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
\r
561 //*****************************************************************************
\r
563 // The following are deprecated defines for the bit fields in the CAN_BRPE
\r
566 //*****************************************************************************
\r
567 #define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
\r
569 //*****************************************************************************
\r
571 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ
\r
572 // and CAN_IF1CRQ registers.
\r
573 // Note: All bits may not be available in all registers
\r
575 //*****************************************************************************
\r
576 #define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
\r
577 #define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
\r
579 //*****************************************************************************
\r
581 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK
\r
582 // and CAN_IF2CMSK registers.
\r
583 // Note: All bits may not be available in all registers
\r
585 //*****************************************************************************
\r
586 #define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
\r
587 #define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
\r
588 #define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
\r
589 #define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
\r
590 #define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
\r
591 #define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
\r
592 #define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
\r
593 #define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
\r
594 #define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
\r
596 //*****************************************************************************
\r
598 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1
\r
599 // and CAN_IF2MSK1 registers.
\r
600 // Note: All bits may not be available in all registers
\r
602 //*****************************************************************************
\r
603 #define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
\r
605 //*****************************************************************************
\r
607 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2
\r
608 // and CAN_IF2MSK2 registers.
\r
609 // Note: All bits may not be available in all registers
\r
611 //*****************************************************************************
\r
612 #define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
\r
613 #define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
\r
614 #define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
\r
616 //*****************************************************************************
\r
618 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1
\r
619 // and CAN_IF2ARB1 registers.
\r
620 // Note: All bits may not be available in all registers
\r
622 //*****************************************************************************
\r
623 #define CAN_IFARB1_ID 0x0000FFFF // Identifier
\r
625 //*****************************************************************************
\r
627 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2
\r
628 // and CAN_IF2ARB2 registers.
\r
629 // Note: All bits may not be available in all registers
\r
631 //*****************************************************************************
\r
632 #define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
\r
633 #define CAN_IFARB2_XTD 0x00004000 // Extended identifier
\r
634 #define CAN_IFARB2_DIR 0x00002000 // Message direction
\r
635 #define CAN_IFARB2_ID 0x00001FFF // Message identifier
\r
637 //*****************************************************************************
\r
639 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL
\r
640 // and CAN_IF2MCTL registers.
\r
641 // Note: All bits may not be available in all registers
\r
643 //*****************************************************************************
\r
644 #define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
\r
645 #define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
\r
646 #define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
\r
647 #define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
\r
648 #define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
\r
649 #define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
\r
650 #define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
\r
651 #define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
\r
652 #define CAN_IFMCTL_EOB 0x00000080 // End of buffer
\r
653 #define CAN_IFMCTL_DLC 0x0000000F // Data length code
\r
655 //*****************************************************************************
\r
657 // The following are deprecated defines for the bit fields in the CAN_IF1DA1
\r
658 // and CAN_IF2DA1 registers.
\r
659 // Note: All bits may not be available in all registers
\r
661 //*****************************************************************************
\r
662 #define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
\r
664 //*****************************************************************************
\r
666 // The following are deprecated defines for the bit fields in the CAN_IF1DA2
\r
667 // and CAN_IF2DA2 registers.
\r
668 // Note: All bits may not be available in all registers
\r
670 //*****************************************************************************
\r
671 #define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
\r
673 //*****************************************************************************
\r
675 // The following are deprecated defines for the bit fields in the CAN_IF1DB1
\r
676 // and CAN_IF2DB1 registers.
\r
677 // Note: All bits may not be available in all registers
\r
679 //*****************************************************************************
\r
680 #define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
\r
682 //*****************************************************************************
\r
684 // The following are deprecated defines for the bit fields in the CAN_IF1DB2
\r
685 // and CAN_IF2DB2 registers.
\r
686 // Note: All bits may not be available in all registers
\r
688 //*****************************************************************************
\r
689 #define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
\r
691 //*****************************************************************************
\r
693 // The following are deprecated defines for the bit fields in the CAN_TXRQ1
\r
696 //*****************************************************************************
\r
697 #define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
\r
699 //*****************************************************************************
\r
701 // The following are deprecated defines for the bit fields in the CAN_TXRQ2
\r
704 //*****************************************************************************
\r
705 #define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
\r
707 //*****************************************************************************
\r
709 // The following are deprecated defines for the bit fields in the CAN_NWDA1
\r
712 //*****************************************************************************
\r
713 #define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
\r
715 //*****************************************************************************
\r
717 // The following are deprecated defines for the bit fields in the CAN_NWDA2
\r
720 //*****************************************************************************
\r
721 #define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
\r
723 //*****************************************************************************
\r
725 // The following are deprecated defines for the bit fields in the CAN_MSGINT1
\r
728 //*****************************************************************************
\r
729 #define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
\r
731 //*****************************************************************************
\r
733 // The following are deprecated defines for the bit fields in the CAN_MSGINT2
\r
736 //*****************************************************************************
\r
737 #define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
\r
739 //*****************************************************************************
\r
741 // The following are deprecated defines for the bit fields in the CAN_MSGVAL1
\r
744 //*****************************************************************************
\r
745 #define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
\r
747 //*****************************************************************************
\r
749 // The following are deprecated defines for the bit fields in the CAN_MSGVAL2
\r
752 //*****************************************************************************
\r
753 #define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
\r
757 #endif // __HW_CAN_H__
\r