1 //*****************************************************************************
\r
3 // hw_hibernate.h - Defines and Macros for the Hibernation module.
\r
5 // Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
\r
7 // Software License Agreement
\r
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
\r
10 // exclusively on LMI's microcontroller products.
\r
12 // The software is owned by LMI and/or its suppliers, and is protected under
\r
13 // applicable copyright laws. All rights are reserved. You may not combine
\r
14 // this software with "viral" open-source software in order to form a larger
\r
15 // program. Any use in violation of the foregoing restrictions may subject
\r
16 // the user to criminal sanctions under applicable laws, as well as to civil
\r
17 // liability for the breach of the terms and conditions of this license.
\r
19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
\r
27 //*****************************************************************************
\r
29 #ifndef __HW_HIBERNATE_H__
\r
30 #define __HW_HIBERNATE_H__
\r
32 //*****************************************************************************
\r
34 // The following are defines for the Hibernation module register addresses.
\r
36 //*****************************************************************************
\r
37 #define HIB_RTCC 0x400FC000 // Hibernate RTC counter
\r
38 #define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0
\r
39 #define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1
\r
40 #define HIB_RTCLD 0x400FC00C // Hibernate RTC load
\r
41 #define HIB_CTL 0x400FC010 // Hibernate RTC control
\r
42 #define HIB_IM 0x400FC014 // Hibernate interrupt mask
\r
43 #define HIB_RIS 0x400FC018 // Hibernate raw interrupt status
\r
44 #define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat
\r
45 #define HIB_IC 0x400FC020 // Hibernate interrupt clear
\r
46 #define HIB_RTCT 0x400FC024 // Hibernate RTC trim
\r
47 #define HIB_DATA 0x400FC030 // Hibernate data area
\r
49 //*****************************************************************************
\r
51 // The following are defines for the bit fields in the Hibernate RTC counter
\r
54 //*****************************************************************************
\r
55 #define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
\r
56 #define HIB_RTCC_S 0
\r
58 //*****************************************************************************
\r
60 // The following are defines for the bit fields in the Hibernate RTC match 0
\r
63 //*****************************************************************************
\r
64 #define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
\r
65 #define HIB_RTCM0_S 0
\r
67 //*****************************************************************************
\r
69 // The following are defines for the bit fields in the Hibernate RTC match 1
\r
72 //*****************************************************************************
\r
73 #define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
\r
74 #define HIB_RTCM1_S 0
\r
76 //*****************************************************************************
\r
78 // The following are defines for the bit fields in the Hibernate RTC load
\r
81 //*****************************************************************************
\r
82 #define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
\r
83 #define HIB_RTCLD_S 0
\r
85 //*****************************************************************************
\r
87 // The following are defines for the bit fields in the Hibernate control
\r
90 //*****************************************************************************
\r
91 #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.
\r
92 #define HIB_CTL_VABORT 0x00000080 // low bat abort
\r
93 #define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
\r
94 #define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
\r
95 #define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
\r
96 #define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
\r
97 #define HIB_CTL_CLKSEL 0x00000004 // clock input selection
\r
98 #define HIB_CTL_HIBREQ 0x00000002 // request hibernation
\r
99 #define HIB_CTL_RTCEN 0x00000001 // RTC enable
\r
101 //*****************************************************************************
\r
103 // The following are defines for the bit fields in the Hibernate interrupt mask
\r
106 //*****************************************************************************
\r
107 #define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
\r
108 #define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
\r
109 #define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
\r
110 #define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
\r
112 //*****************************************************************************
\r
114 // The following are defines for the bit fields in the Hibernate raw interrupt
\r
117 //*****************************************************************************
\r
118 #define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
\r
119 #define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
\r
120 #define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
\r
121 #define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
\r
123 //*****************************************************************************
\r
125 // The following are defines for the bit fields in the Hibernate masked int
\r
128 //*****************************************************************************
\r
129 #define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
\r
130 #define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
\r
131 #define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
\r
132 #define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
\r
135 //*****************************************************************************
\r
137 // The following are defines for the bit fields in the Hibernate interrupt
\r
140 //*****************************************************************************
\r
141 #define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
\r
142 #define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
\r
143 #define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
\r
144 #define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
\r
146 //*****************************************************************************
\r
148 // The following are defines for the bit fields in the Hibernate RTC trim
\r
151 //*****************************************************************************
\r
152 #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
\r
153 #define HIB_RTCT_TRIM_S 0
\r
155 //*****************************************************************************
\r
157 // The following are defines for the bit fields in the Hibernate data register.
\r
159 //*****************************************************************************
\r
160 #define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
\r
161 // Registers[63:0].
\r
162 #define HIB_DATA_RTD_S 0
\r
164 //*****************************************************************************
\r
166 // The following definitions are deprecated.
\r
168 //*****************************************************************************
\r
171 //*****************************************************************************
\r
173 // The following are deprecated defines for the Hibernation module register
\r
176 //*****************************************************************************
\r
177 #define HIB_DATA_END 0x400FC130 // end of data area, exclusive
\r
179 //*****************************************************************************
\r
181 // The following are deprecated defines for the bit fields in the Hibernate RTC
\r
182 // counter register.
\r
184 //*****************************************************************************
\r
185 #define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
\r
187 //*****************************************************************************
\r
189 // The following are deprecated defines for the bit fields in the Hibernate RTC
\r
190 // match 0 register.
\r
192 //*****************************************************************************
\r
193 #define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
\r
195 //*****************************************************************************
\r
197 // The following are deprecated defines for the bit fields in the Hibernate RTC
\r
198 // match 1 register.
\r
200 //*****************************************************************************
\r
201 #define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
\r
203 //*****************************************************************************
\r
205 // The following are deprecated defines for the bit fields in the Hibernate RTC
\r
208 //*****************************************************************************
\r
209 #define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
\r
211 //*****************************************************************************
\r
213 // The following are deprecated defines for the bit fields in the Hibernate raw
\r
214 // interrupt status.
\r
216 //*****************************************************************************
\r
217 #define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
\r
219 //*****************************************************************************
\r
221 // The following are deprecated defines for the bit fields in the Hibernate
\r
222 // masked int status.
\r
224 //*****************************************************************************
\r
225 #define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
\r
227 //*****************************************************************************
\r
229 // The following are deprecated defines for the bit fields in the Hibernate RTC
\r
232 //*****************************************************************************
\r
233 #define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
\r
235 //*****************************************************************************
\r
237 // The following are deprecated defines for the bit fields in the Hibernate
\r
240 //*****************************************************************************
\r
241 #define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
\r
245 #endif // __HW_HIBERNATE_H__
\r