1 //*****************************************************************************
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3 // hw_memmap.h - Macros defining the memory map of Stellaris.
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5 // Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. You may not combine
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14 // this software with "viral" open-source software in order to form a larger
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15 // program. Any use in violation of the foregoing restrictions may subject
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16 // the user to criminal sanctions under applicable laws, as well as to civil
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17 // liability for the breach of the terms and conditions of this license.
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19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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27 //*****************************************************************************
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29 #ifndef __HW_MEMMAP_H__
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30 #define __HW_MEMMAP_H__
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32 //*****************************************************************************
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34 // The following are defines for the base address of the memories and
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37 //*****************************************************************************
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38 #define FLASH_BASE 0x00000000 // FLASH memory
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39 #define SRAM_BASE 0x20000000 // SRAM memory
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40 #define WATCHDOG_BASE 0x40000000 // Watchdog
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41 #define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
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42 #define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
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43 #define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
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44 #define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
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45 #define SSI0_BASE 0x40008000 // SSI0
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46 #define SSI1_BASE 0x40009000 // SSI1
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47 #define UART0_BASE 0x4000C000 // UART0
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48 #define UART1_BASE 0x4000D000 // UART1
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49 #define UART2_BASE 0x4000E000 // UART2
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50 #define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
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51 #define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
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52 #define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
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53 #define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
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54 #define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
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55 #define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
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56 #define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
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57 #define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
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58 #define PWM_BASE 0x40028000 // PWM
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59 #define QEI0_BASE 0x4002C000 // QEI0
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60 #define QEI1_BASE 0x4002D000 // QEI1
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61 #define TIMER0_BASE 0x40030000 // Timer0
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62 #define TIMER1_BASE 0x40031000 // Timer1
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63 #define TIMER2_BASE 0x40032000 // Timer2
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64 #define TIMER3_BASE 0x40033000 // Timer3
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65 #define ADC_BASE 0x40038000 // ADC
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66 #define COMP_BASE 0x4003C000 // Analog comparators
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67 #define CAN0_BASE 0x40040000 // CAN0
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68 #define CAN1_BASE 0x40041000 // CAN1
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69 #define CAN2_BASE 0x40042000 // CAN2
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70 #define ETH_BASE 0x40048000 // Ethernet
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71 #define MAC_BASE 0x40048000 // Ethernet
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72 #define USB0_BASE 0x40050000 // USB 0 Controller
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73 #define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
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74 #define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
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75 #define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
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76 #define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
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77 #define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
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78 #define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
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79 #define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
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80 #define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
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81 #define HIB_BASE 0x400FC000 // Hibernation Module
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82 #define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
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83 #define SYSCTL_BASE 0x400FE000 // System Control
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84 #define UDMA_BASE 0x400FF000 // uDMA Controller
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85 #define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
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86 #define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
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87 #define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
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88 #define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
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89 #define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
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91 //*****************************************************************************
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93 // The following definitions are deprecated.
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95 //*****************************************************************************
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98 //*****************************************************************************
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100 // The following are deprecated defines for the base address of the memories
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101 // and peripherals.
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103 //*****************************************************************************
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104 #define SSI_BASE 0x40008000 // SSI
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105 #define I2C_MASTER_BASE 0x40020000 // I2C Master
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106 #define I2C_SLAVE_BASE 0x40020800 // I2C Slave
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107 #define QEI_BASE 0x4002C000 // QEI
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111 #endif // __HW_MEMMAP_H__
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