1 ;====================================================================
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2 ; $Id: START.ASM,v 1.31 2008/02/27 10:23:34 mcuae Exp $
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3 ;====================================================================
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4 ; THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS.
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5 ; FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY
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6 ; FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES.
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8 ; Startup file for memory and basic controller initialisation
\r
10 ; MB96300 Family C Compiler
\r
12 ; (C) FUJITSU MICROELECTRONICS EUROPE 1998-2008
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13 ;====================================================================
\r
16 .TITLE "STARTUP FILE FOR MEMORY INITIALISATION"
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18 ;====================================================================
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20 ;====================================================================
\r
25 ; 4 SETTINGS (USER INTERFACE)
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26 ; 4.1 Controller Series, Device
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27 ; 4.2 C-language Memory model
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28 ; 4.3 Function-Call Interface
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29 ; 4.4 Constant Data Handling
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30 ; 4.5 Stack Type and Stack Size
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31 ; 4.6 General Register Bank
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32 ; 4.7 Low-Level Library Interface
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34 ; 4.8 Clock Selection
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35 ; 4.9 Clock Stabilization Time
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36 ; 4.10 External Bus Interface
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37 ; 4.11 ROM Mirror configuration
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38 ; 4.12 Flash Security
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39 ; 4.13 Flash Write Protection
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41 ; 4.15 UART scanning
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42 ; 4.16 Enable RAMCODE Copying
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43 ; 4.17 Enable information stamp in ROM
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44 ; 4.18 Enable Background Debugging Mode
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46 ; 5 Section and Data Declaration
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47 ; 5.1 Several fixed addresses (fixed for MB963xx controllers)
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48 ; 5.2 Declaration of __near addressed data sections
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49 ; 5.3 Declaration of RAMCODE section and labels
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50 ; 5.4 Declaration of sections containing other sections description
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51 ; 5.5 Stack area and stack top definition/declaration
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52 ; 5.6 Direct page register dummy label definition
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53 ; 5.7 Set Flash Security
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54 ; 5.8 Set Flash write protection
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55 ; 5.9 Debug address specification
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58 ; 6.1 Import external symbols
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59 ; 6.2 Program start (the boot vector should point here)
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60 ; 6.3 "NOT RESET YET" WARNING
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61 ; 6.4 Initialisation of processor status
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62 ; 6.5 Set clock ratio (ignore subclock)
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63 ; 6.6 Set external bus configuration
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64 ; 6.7 Prepare stacks and set the active stack type
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65 ; 6.8 Copy initial values to data areas
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66 ; 6.9 Clear uninitialized data areas to zero
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67 ; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR)
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68 ; 6.11 ICU register initialization workaround
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69 ; 6.12 Wait for PLL to stabilize
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70 ; 6.13 Initialise Low-Level Library Interface
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71 ; 6.14 Call C-language main function
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72 ; 6.15 Shut down library
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73 ; 6.16 Program end loop
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75 ;====================================================================
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77 ;====================================================================
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78 ; FUJITSU MICROELECTRONICS EUROPE GMBH
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79 ; Pittlerstrasse 47, 63225 Langen, Germany
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80 ; Tel.:++49 6103 690-0, Fax -122
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82 ; The following software is for demonstration purposes only.
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83 ; It is not fully tested, nor validated in order to fulfil
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84 ; its task under all circumstances. Therefore, this software
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85 ; or any part of it must only be used in an evaluation
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86 ; laboratory environment.
\r
87 ; This software is subject to the rules of our standard
\r
88 ; DISCLAIMER, that is delivered with our SW-tools on the
\r
89 ; Fujitsu Microcontrollers DVD (V5.0 or higher "\START.HTM") or
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90 ; on our Internet Pages:
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91 ; http://www.fme.gsdc.de/gsdc.htm
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92 ; http://emea.fujitsu.com/microelectronics
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94 ;====================================================================
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96 ;====================================================================
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97 ; $Id: START.ASM,v 1.31 2008/02/27 10:23:34 mcuae Exp $
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99 #define VERSION "1.31"
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101 $Log: START.ASM,v $
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102 Revision 1.31 2008/02/27 10:23:34 mcuae
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103 - CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ clock setting added
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105 Revision 1.30 2008/02/26 15:28:21 mcuae
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106 - clock settings corrected
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107 - Main/Satellite Flash term outdated, now: Flash A, Flash B
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109 Revision 1.29 2008/02/11 15:26:33 mwilla
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110 - device configuration for ext. bus i/f settings updated
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112 Revision 1.28 2008/01/25 08:03:48 mwilla
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113 - clock settings corrected and optimized
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115 Revision 1.27 2008/01/04 12:26:08 mwilla
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116 - device list expanded
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117 - clock settings optimized
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119 Revision 1.26 2007/10/17 11:53:34 mwilla
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120 - device list expanded
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121 - ICU initialization workaround added
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122 - sections settings grouped
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124 Revision 1.25 2007/09/28 07:33:18 mwilla
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125 - Bug in BDM baudrate calculation corrected
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127 Revision 1.24 2007/09/26 14:03:08 mwilla
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128 - Device list for MB96340 series updated and expanded
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130 Revision 1.23 2007/08/06 14:48:16 mwilla
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131 - BDM section always reserved, filled with 0xFF, if not configured
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133 Revision 1.22 2007/08/02 08:34:03 mwilla
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134 - communication mode bits of BDM configuration grouped
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136 Revision 1.21 2007/07/13 08:23:05 mwilla
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137 - device selection for BDM baud rate improved
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139 Revision 1.20 2007/06/12 10:43:57 mwilla
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140 - BDM-Baud-Rate calculation includes crystal frequency
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142 Revision 1.19 2007/06/06 07:46:55 mwilla
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143 - add Background Debugging Configuration
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144 - Stack initialization moved before variable initialization
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145 - values of cystal frequency and device macros changed
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147 Revision 1.18 2007/04/16 07:56:02 phuene
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148 - update clock settings when crystal is 8 MHz so that the CLKVCO is low
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150 Revision 1.17 2007/04/10 11:30:43 phuene
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151 - add MB96320 Series
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152 - Clock settings optimized for CPU_8MHZ_CLKP2_8MHZ, CPU_12MHZ_CLKP2_12MHZ, CPU_16MHZ_CLKP2_16MHZ, CPU_24MHZ_CLKP2_24MHZ, CPU_32MHZ_CLKP2_32MHZ
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153 - make the selection for the individual devices also consider the selected Series
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154 - support 8 MHz crystal
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155 - add clock setting CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ
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156 - prohibit CPU_32MHZ_CLKP2_16MHZ, CPU_CLKP1_16MHZ_CLKP2_16MHZ for MB96F348H and MB96F348T according to functional limitation 16FXFL0014
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158 Revision 1.16 2007/02/07 12:38:10 phuene
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159 - support disabling the UART scanning in Internal Vector Mode
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160 - distinguish between Reset Vector and Boot Vector: the Boot Vector points to the start of the user application
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162 Revision 1.15 2007/02/07 09:00:19 phuene
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163 - add .SKIP instructions to occupy the whole ROM configuration block area
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165 Revision 1.14 2007/01/29 13:15:06 phuene
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166 - fix CPU_4MHZ_MAIN_CLKP2_4MHZ clock setting
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168 Revision 1.13 2007/01/03 10:40:14 phuene
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169 - change clock setting CPU_24MHZ_CLKP2_16MHZ to CPU_24MHZ_CLKP2_12MHZ; this allows for better performance of MB96F348H/T
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170 - use additional preprocessor statements to avoid checking for PLL ready twice in some cases
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172 Revision 1.12 2007/01/02 10:16:20 phuene
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173 - correct CLKP2 (CAN) clock for CPU_32MHZ and MB96F348H/T
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174 - correct CLKP2 (CAN) clock for CPU_24MHZ for all other devices than MB96F348H/T
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176 Revision 1.11 2006/12/28 10:49:52 phuene
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177 - corrected PLL setting for CPU_16MHZ for MB96348H, MB96348T
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179 Revision 1.10 2006/12/28 08:41:57 phuene
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180 - correct revision number at new location
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182 Revision 1.1 2006/12/28 07:20:01 phuene
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183 - new location in CVS
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185 Revision 1.9 2006/12/27 13:00:45 phuene
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186 - add support for ROM Mirror when using the Simulator
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187 - add support for 16FXFL0022, 16FXFL0023
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189 Revision 1.8 2006/12/11 16:43:37 phuene
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192 Revision 1.7 2006/12/11 16:35:08 phuene
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193 - add setting for Clock Stabilization Times
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194 - modify clock settings:
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196 - remove clock settings using more wait cycles than absolutely required
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198 Revision 1.6 2006/11/03 13:38:45 phuene
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199 - modify clock settings to also set the Flash Memory Timing
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200 - add support for both parameter passing models
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202 Revision 1.5 2006/08/07 14:01:44 phuene
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203 - change default clock setting to PLLx4 for CLKS1, CLKS2
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204 - correct clock setting
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205 - disable Flash Security by default for Main Flash, Satellite Flash
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206 - disable availability of Satellite Flash by default
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208 Revision 0.1 2006/01/25 15:37:46 phu
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209 - initial version based on start.asm for MB90340 Series, version 3.8
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210 Revision 0.2 2006/07/14 15:37:46 phu
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211 - include PIER settings for External Bus operation
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212 Revision 0.3 2006/07/14 15:37:46 phu
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213 - add MB96350 Series
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214 - correct PIER settings for HRQ and RDY signals
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215 Revision 0.4 2006/08/07 15:35:35 phu
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216 - change default clock setting to PLLx4 for CLKS1, CLKS2
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217 - correct clock setting
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218 - disable Flash Security by default for Main Flash, Satellite Flash
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219 - disable availability of Satellite Flash by default
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221 ;====================================================================
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223 ;====================================================================
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225 ;====================================================================
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227 ; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION
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229 ; Configure this startup file in the "Settings" section. Search for
\r
230 ; comments with leading "; <<<". This points to the items to be set.
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231 ;====================================================================
\r
235 ;====================================================================
\r
236 ; 4.1 Controller Series, Device
\r
237 ;====================================================================
\r
248 #set SERIES MB96350 ; <<< select Series
\r
251 ; Please specify the device according to the following selection;
\r
253 ; Note: Do not change order because of device number dependency in
\r
254 ; 6.5 Clock settings, 5.9 Debug address specification,
\r
255 ; and 6.11 ICU register initialization workaround!
\r
275 #set MB96348YxA 10
\r
277 #set MB96346RxB 12
\r
279 #set MB96346YxB 14
\r
280 #set MB96347RxB 15
\r
282 #set MB96347YxB 17
\r
284 #set MB96348HxB 19
\r
285 #set MB96348TxB 20
\r
286 #set MB96348RxB 21
\r
288 #set MB96348YxB 23
\r
290 #set MB96348HxC 25
\r
291 #set MB96348TxC 26
\r
323 #set DEVICE MB96356RxA ; <<< select device
\r
325 ;====================================================================
\r
326 ; 4.2 C-language Memory model
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327 ;====================================================================
\r
330 #set SMALL 0 ; 16 Bit 16 Bit
\r
331 #set MEDIUM 1 ; 16 Bit 24 Bit
\r
332 #set COMPACT 2 ; 24 Bit 16 Bit
\r
333 #set LARGE 3 ; 24 Bit 24 Bit
\r
334 #set AUTOMODEL 4 ; works always, might occupy two
\r
338 #set MEMMODEL AUTOMODEL ; <<< C-memory model
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340 ; The selected memory model should be set in order to fit to the
\r
341 ; model selected for the compiler.
\r
342 ; Note, in this startup version AUTOMODEL will work for all
\r
343 ; C-models. However, if the compiler is configured for SMALL or
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344 ; COMPACT, two additional bytes on stack are occupied. If this is not
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345 ; acceptable, the above setting should be set to the correct model.
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347 ;====================================================================
\r
348 ; 4.3 Function-Call Interface
\r
349 ;====================================================================
\r
355 ; Above statement informs Assembler on compatibility of start-up code
\r
356 ; to Function Call Interface as selected for the application. There
\r
357 ; is nothing to configure.
\r
358 ; The Function-Call Interface specifies the method of passing parame-
\r
359 ; ter from function caller to callee. The standard method of FCC907S
\r
360 ; compiler uses "stack argument passing". Alternatively, language
\r
361 ; tools can be configured for "register argument passing".
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362 ; For details see the compiler manual.
\r
363 ; This start-up file is compatible to both interfaces.
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365 ;====================================================================
\r
366 ; 4.4 Constant Data Handling
\r
367 ;====================================================================
\r
369 #set ROMCONST 0 ; works only with compiler ROMCONST
\r
370 #set RAMCONST 1 ; works with BOTH compiler settings
\r
371 #set AUTOCONST RAMCONST ; works with BOTH compiler settings
\r
373 #set CONSTDATA AUTOCONST ; <<< set RAM/ROM/AUTOCONST
\r
375 ; - AUTOCONST (default) is the same as RAMCONST
\r
376 ; - RAMCONST/AUTOCONST should always work, even if compiler is set to
\r
377 ; ROMCONST. If compiler is set to ROMCONST and this startup file is
\r
378 ; set to RAMCONST or AUTOCONST, this startup file will generate an
\r
379 ; empty section CINIT in RAM. However, the code, which copies from
\r
380 ; CONST to CINIT will not have any effect, because size of section is 0.
\r
381 ; - It is highly recommended to set the compiler to ROMCONST for
\r
382 ; single-chip mode or internal ROM+ext bus. The start-up file
\r
383 ; should be set to AUTOCONST.
\r
384 ; - ROMCONST setting on systems with full external bus requires exter-
\r
385 ; nal address mapping.
\r
386 ; Single-chip can be emulated by the emulator debugger.
\r
387 ; ROM mirror can also be used with simulator.
\r
389 ; see also ROM MIRROR options
\r
391 ;====================================================================
\r
392 ; 4.5 Stack Type and Stack Size
\r
393 ;====================================================================
\r
395 #set USRSTACK 0 ; user stack: for main program
\r
396 #set SYSSTACK 1 ; system stack: for main program and interrupts
\r
398 #set STACKUSE SYSSTACK ; <<< set active stack
\r
400 #set STACK_RESERVE ON ; <<< reserve stack area in this module
\r
401 #set STACK_SYS_SIZE 200 ; <<< byte size of System stack
\r
402 #set STACK_USR_SIZE 2 ; <<< byte size of User stack
\r
404 #set STACK_FILL ON ; <<< fills the stack area with pattern
\r
405 #set STACK_PATTERN 0x55AA ; <<< the pattern to write to stack
\r
407 ; - If the active stack is set to SYSSTACK, it is used for main program
\r
408 ; and interrupts. In this case, the user stack can be set to a dummy
\r
410 ; If the active stack is set to user stack, it is used for the main
\r
411 ; program but the system stack is automatically activated, if an inter-
\r
412 ; rupt is serviced. Both stack areas must have a reasonable size.
\r
413 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved
\r
414 ; in this module. Otherwise, they have to be reserved in other modules.
\r
415 ; If STACK_RESERVE is OFF, the size definitions STACK_SYS_SIZE and
\r
416 ; STACK_USR_SIZE have no meaning.
\r
417 ; - Even if they are reserved in other modules, they are still initialised
\r
418 ; in this start-up file.
\r
419 ; - Filling the stack with a pattern allows to dynamically check the stack
\r
420 ; area, which had already been used.
\r
422 ; - If only system stack is used and SSB is linked to a different bank
\r
423 ; than USB, make sure that all C-modules (which generate far pointers
\r
424 ; to stack data) have "#pragma SSB". Applies only to exclusive confi-
\r
426 ; - Note, several library functions require quite a big stack (due to
\r
427 ; ANSI). Check the stack information files (*.stk) in the LIB\907
\r
430 ;====================================================================
\r
431 ; 4.6 General Register Bank
\r
432 ;====================================================================
\r
434 #set REGBANK 0 ; <<< set default register bank
\r
436 ; set the General Register Bank that is to be used after startup.
\r
437 ; Usually, this is bank 0, which applies to address H'180..H'18F. Set
\r
438 ; in the range from 0 to 31.
\r
439 ; Note: All used register banks have to be reserved (linker options).
\r
441 #if REGBANK > 31 || REGBANK < 0
\r
442 # error REGBANK setting out of range
\r
445 ;====================================================================
\r
446 ; 4.7 Low-Level Library Interface
\r
447 ;====================================================================
\r
449 #set CLIBINIT OFF ; <<< select extended library usage
\r
451 ; This option has only to be set, if stream-IO/standard-IO function of
\r
452 ; the C-library have to be used (printf(), fopen()...). This also
\r
453 ; requires low-level functions to be defined by the application
\r
455 ; For other library functions (like e.g. sprintf()) all this is not
\r
456 ; necessary. However, several functions consume a large amount of stack.
\r
458 ;====================================================================
\r
459 ; 4.8 Clock Selection
\r
460 ;====================================================================
\r
462 ; The clock selection requires that a 4 MHz external clock is provided
\r
463 ; as the Main Clock. If a different frequency is used, the Flash Memory
\r
464 ; Timing settings must be checked!
\r
466 #set CLOCKWAIT ON ; <<< wait for stabilized clock, if
\r
467 ; Main Clock or PLL is used
\r
469 ; The clock is set quite early. However, if CLOCKWAIT is ON, polling
\r
470 ; for machine clock to be switched to Main Clock or PLL is done at
\r
471 ; the end of this file. Therefore, the stabilization time is not
\r
472 ; wasted. Main() will finally start at correct speed. Resources can
\r
473 ; be used immediately.
\r
474 ; Note: Some frequency settings (below) necessarily need a stabilized
\r
475 ; PLL for final settings. In these cases, the CLOCKWAIT setting above
\r
476 ; does not have any effect.
\r
478 ; This startup file version does not support subclock.
\r
480 #set FREQ_4MHZ D'4000000L
\r
481 #set FREQ_8MHZ D'8000000L
\r
483 #set CRYSTAL FREQ_4MHZ ; <<< select external crystal frequency
\r
485 #set CPU_4MHZ_MAIN_CLKP2_4MHZ 0x0004
\r
486 #set CPU_4MHZ_PLL_CLKP2_4MHZ 0x0104
\r
487 #set CPU_8MHZ_CLKP2_8MHZ 0x0108
\r
488 #set CPU_12MHZ_CLKP2_12MHZ 0x010C
\r
489 #set CPU_16MHZ_CLKP2_16MHZ 0x0110
\r
490 #set CPU_24MHZ_CLKP2_12MHZ 0x0118
\r
491 #set CPU_32MHZ_CLKP2_16MHZ 0x0120
\r
492 #set CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ 0x0220
\r
493 #set CPU_48MHZ_CLKP2_16MHZ 0x0130
\r
494 #set CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ 0x0230
\r
495 #set CPU_56MHZ_CLKP2_14MHZ 0x0138
\r
497 #set CLOCK_SPEED CPU_56MHZ_CLKP2_14MHZ ; <<< set clock speeds
\r
499 ; The peripheral clock CLKP1 is set to the same frequency than the CPU.
\r
500 ; The peripheral clock CLKP2 has its setting. This is because it
\r
501 ; feeds only the CAN controllers and Sound Generators. These do not
\r
502 ; need high frequency clocks.
\r
504 ;====================================================================
\r
505 ; 4.9 Clock Stabilization Time
\r
506 ;====================================================================
\r
508 #set MC_2_10_CYCLES 0
\r
509 #set MC_2_12_CYCLES 1
\r
510 #set MC_2_13_CYCLES 2
\r
511 #set MC_2_14_CYCLES 3
\r
512 #set MC_2_15_CYCLES 4
\r
513 #set MC_2_16_CYCLES 5
\r
514 #set MC_2_17_CYCLES 6
\r
515 #set MC_2_18_CYCLES 7
\r
517 #set MC_STAB_TIME MC_2_15_CYCLES ; <<< select Main Clock Stabilization Time
\r
519 ;====================================================================
\r
520 ; 4.10 External Bus Interface
\r
521 ;====================================================================
\r
523 #set SINGLE_CHIP 0 ; all internal
\r
524 #set INTROM_EXTBUS 1 ; mask ROM or FLASH memory used
\r
525 #set EXTROM_EXTBUS 2 ; full external bus (INROM not used)
\r
527 #set BUSMODE SINGLE_CHIP ; <<< set bus mode (see mode pins)
\r
529 #set MULTIPLEXED 0 ;
\r
530 #set NON_MULTIPLEXED 1 ; only if supported by the device
\r
532 #set ADDRESSMODE MULTIPLEXED ; <<< set address-mode
\r
534 ; Some devices support multiplexed and/or non-multiplexed Bus mode
\r
535 ; please refer to the related datasheet/hardwaremanual
\r
538 ; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings.
\r
540 ; Select the used Chip Select areas
\r
541 #set CHIP_SELECT0 OFF ; <<< enable chip select area
\r
542 #set CHIP_SELECT1 OFF ; <<< enable chip select area
\r
543 #set CHIP_SELECT2 OFF ; <<< enable chip select area
\r
544 #set CHIP_SELECT3 OFF ; <<< enable chip select area
\r
545 #set CHIP_SELECT4 OFF ; <<< enable chip select area
\r
546 #set CHIP_SELECT5 OFF ; <<< enable chip select area
\r
548 #set HOLD_REQ OFF ; <<< select Hold function
\r
549 #set EXT_READY OFF ; <<< select external Ready function
\r
550 #set EXT_CLOCK_ENABLE OFF ; <<< select external bus clock output
\r
551 #set EXT_CLOCK_INVERT OFF ; <<< select clock inversion
\r
552 #set EXT_CLOCK_SUSPEND OFF ; <<< select if external clock is suspended when no transfer in progress
\r
554 ; The external bus clock is derived from core clock CLKB. Select the divider for the external bus clock.
\r
556 #set EXT_CLOCK_DIV1 0
\r
557 #set EXT_CLOCK_DIV2 1
\r
558 #set EXT_CLOCK_DIV4 2
\r
559 #set EXT_CLOCK_DIV8 3
\r
560 #set EXT_CLOCK_DIV16 4
\r
561 #set EXT_CLOCK_DIV32 5
\r
562 #set EXT_CLOCK_DIV64 6
\r
563 #set EXT_CLOCK_DIV128 7
\r
565 #set EXT_CLOCK_DIVISION EXT_CLOCK_DIV1 ; <<< select clock divider
\r
567 #set ADDR_PINS_23_16 B'00000000 ; <<< select used address lines
\r
568 ; A23..A16 to be output.
\r
569 #set ADDR_PINS_15_8 B'00000000 ; <<< select used address lines
\r
570 ; A15..A8 to be output.
\r
571 #set ADDR_PINS_7_0 B'00000000 ; <<< select used address lines
\r
572 ; A7..A0 to be output.
\r
574 #set LOW_BYTE_SIGNAL OFF ; <<< select low byte signal LBX
\r
575 #set HIGH_BYTE_SIGNAL OFF ; <<< select high byte signal UBX
\r
576 #set LOW_WRITE_STROBE OFF ; <<< select write strobe signal WRLX/WRX
\r
577 #set HIGH_WRITE_STROBE OFF ; <<< select write strobe signal WRHX
\r
578 #set READ_STROBE OFF ; <<< select read strobe signal RDX
\r
579 #set ADDRESS_STROBE OFF ; <<< select address strobe signal ALE/ASX
\r
580 #set ADDRESS_STROBE_LVL OFF ; <<< select address strobe function: OFF - active low; ON - active high
\r
583 #set CS0_CONFIG B'0000000000000000 ; <<< select Chip Select Area 0 configuration
\r
584 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
585 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
586 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
587 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
588 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
589 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
590 ; |||||+++---------- ignored
\r
591 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
592 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
593 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
594 ; ++---------------- ignored
\r
596 #set CS1_CONFIG B'0000000000000000 ; <<< select Chip Select Area 1 configuration
\r
597 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
598 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
599 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
600 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
601 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
602 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
603 ; |||||+++---------- ignored
\r
604 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
605 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
606 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
607 ; ++---------------- ignored
\r
609 #set CS2_CONFIG B'0000011000000000 ; <<< select Chip Select Area 2 configuration
\r
610 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
611 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
612 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
613 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
614 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
615 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
616 ; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
\r
617 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
618 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
619 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
620 ; ++---------------- ignored
\r
622 #set CS3_CONFIG B'0000011000000000 ; <<< select Chip Select Area 3 configuration
\r
623 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
624 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
625 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
626 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
627 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
628 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
629 ; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
\r
630 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
631 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
632 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
633 ; ++---------------- ignored
\r
635 #set CS4_CONFIG B'0000011000000000 ; <<< select Chip Select Area 4 configuration
\r
636 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
637 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
638 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
639 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
640 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
641 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
642 ; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
\r
643 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
644 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
645 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
646 ; ++---------------- ignored
\r
648 #set CS5_CONFIG B'0000011000000000 ; <<< select Chip Select Area 5 configuration
\r
649 ; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
\r
650 ; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
\r
651 ; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
\r
652 ; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
\r
653 ; |||||||||+-------- Endianess (0: little endian, 1: big endian)
\r
654 ; ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
\r
655 ; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
\r
656 ; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
\r
657 ; |||+-------------- Chip Select level (0: low active, 1: high active)
\r
658 ; ||+--------------- Access type limitation (0: code and data, 1: data only)
\r
659 ; ++---------------- ignored
\r
662 #set CS2_START 0x00 ; <<< select start bank of chip select area; valid values: 0x00..0xFF
\r
663 #set CS3_START 0x40 ; <<< select start bank of chip select area; valid values: 0x00..0xFF
\r
664 #set CS4_START 0x80 ; <<< select start bank of chip select area; valid values: 0x00..0xFF
\r
665 #set CS5_START 0xC0 ; <<< select start bank of chip select area; valid values: 0x00..0xFF
\r
668 ;====================================================================
\r
669 ; 4.11 ROM Mirror configuration
\r
670 ;====================================================================
\r
677 #set ROMMIRROR ON ; <<< ROM mirror function ON/OFF
\r
678 #set MIRROR_BANK 0xF ; <<< ROM Mirror bank, allowed entries: 0x0..0xF for the banks 0xF0..0xFF
\r
679 #set MIRROR_SIZE MIRROR_32KB ; <<< ROM Mirror size
\r
681 ; One can select which ROM area to mirror into the upper half of bank 00.
\r
682 ; If ROMMIRROR = OFF is selected, the address range 0x008000..0x00FFFF
\r
683 ; shows the contents of the respective area of bank 1: 0x018000..0x01FFFF.
\r
684 ; If ROMMIRROR = ON is selected, the memory bank to mirror can be selected.
\r
685 ; Available banks are 0xF0 to 0xFF. Furthermore, the ROM Mirror area size can
\r
686 ; be selected. 4 sizes are available: 8 kB, 16 kB, 24 kB, or 32 kB. The ROM Mirror
\r
687 ; from the highest address of the selected bank downwards, e.g. if bank 0xFF and
\r
688 ; mirror size 24 kB is selected, the memory range 0xFFA000..0xFFFFFF is mirrored
\r
689 ; to address range 0x00A000..0x00FFFF. The memory area not selected for
\r
690 ; ROM Mirror is still mirrored from bank 0x01.
\r
691 ; This is necessary to get the compiler ROMCONST option working. This is intended
\r
692 ; to increase performance, if a lot of dynamic data have to be accessed.
\r
693 ; In SMALL and MEDIUM model these data can be accessed within bank 0,
\r
694 ; which allows to use near addressing. Please make sure to have the linker
\r
695 ; setting adjusted accordingly!
\r
698 ;====================================================================
\r
699 ; 4.12 Flash Security
\r
700 ;====================================================================
\r
702 #set FLASH_A_SECURITY_ENABLE OFF ; <<< enable Flash Security for Flash A (old "Main Flash")
\r
703 #set FLASH_B_AVAILABLE OFF ; <<< select if Flash B is available
\r
704 #set FLASH_B_SECURITY_ENABLE OFF ; <<< enable Flash Security for Flash B (old "Satellite Flash")
\r
706 ; set the Flash Security unlock key (16 bytes)
\r
707 ; all 0: unlock not possible
\r
708 #set FLASH_A_UNLOCK_0 0x00
\r
709 #set FLASH_A_UNLOCK_1 0x00
\r
710 #set FLASH_A_UNLOCK_2 0x00
\r
711 #set FLASH_A_UNLOCK_3 0x00
\r
712 #set FLASH_A_UNLOCK_4 0x00
\r
713 #set FLASH_A_UNLOCK_5 0x00
\r
714 #set FLASH_A_UNLOCK_6 0x00
\r
715 #set FLASH_A_UNLOCK_7 0x00
\r
716 #set FLASH_A_UNLOCK_8 0x00
\r
717 #set FLASH_A_UNLOCK_9 0x00
\r
718 #set FLASH_A_UNLOCK_10 0x00
\r
719 #set FLASH_A_UNLOCK_11 0x00
\r
720 #set FLASH_A_UNLOCK_12 0x00
\r
721 #set FLASH_A_UNLOCK_13 0x00
\r
722 #set FLASH_A_UNLOCK_14 0x00
\r
723 #set FLASH_A_UNLOCK_15 0x00
\r
725 #set FLASH_B_UNLOCK_0 0x00
\r
726 #set FLASH_B_UNLOCK_1 0x00
\r
727 #set FLASH_B_UNLOCK_2 0x00
\r
728 #set FLASH_B_UNLOCK_3 0x00
\r
729 #set FLASH_B_UNLOCK_4 0x00
\r
730 #set FLASH_B_UNLOCK_5 0x00
\r
731 #set FLASH_B_UNLOCK_6 0x00
\r
732 #set FLASH_B_UNLOCK_7 0x00
\r
733 #set FLASH_B_UNLOCK_8 0x00
\r
734 #set FLASH_B_UNLOCK_9 0x00
\r
735 #set FLASH_B_UNLOCK_10 0x00
\r
736 #set FLASH_B_UNLOCK_11 0x00
\r
737 #set FLASH_B_UNLOCK_12 0x00
\r
738 #set FLASH_B_UNLOCK_13 0x00
\r
739 #set FLASH_B_UNLOCK_14 0x00
\r
740 #set FLASH_B_UNLOCK_15 0x00
\r
743 ;====================================================================
\r
744 ; 4.13 Flash Write Protection
\r
745 ;====================================================================
\r
747 #set FLASH_A_WRITE_PROTECT OFF ; <<< select Flash A write protection
\r
748 #set PROTECT_SECTOR_SA0 OFF ; <<< select individual sector to protect
\r
749 #set PROTECT_SECTOR_SA1 OFF ; <<< select individual sector to protect
\r
750 #set PROTECT_SECTOR_SA2 OFF ; <<< select individual sector to protect
\r
751 #set PROTECT_SECTOR_SA3 OFF ; <<< select individual sector to protect
\r
752 #set PROTECT_SECTOR_SA32 OFF ; <<< select individual sector to protect
\r
753 #set PROTECT_SECTOR_SA33 OFF ; <<< select individual sector to protect
\r
754 #set PROTECT_SECTOR_SA34 OFF ; <<< select individual sector to protect
\r
755 #set PROTECT_SECTOR_SA35 OFF ; <<< select individual sector to protect
\r
756 #set PROTECT_SECTOR_SA36 OFF ; <<< select individual sector to protect
\r
757 #set PROTECT_SECTOR_SA37 OFF ; <<< select individual sector to protect
\r
758 #set PROTECT_SECTOR_SA38 OFF ; <<< select individual sector to protect
\r
759 #set PROTECT_SECTOR_SA39 OFF ; <<< select individual sector to protect
\r
761 #set FLASH_B_WRITE_PROTECT OFF ; <<< select Flash write protection
\r
762 #set PROTECT_SECTOR_SB0 OFF ; <<< select individual sector to protect
\r
763 #set PROTECT_SECTOR_SB1 OFF ; <<< select individual sector to protect
\r
764 #set PROTECT_SECTOR_SB2 OFF ; <<< select individual sector to protect
\r
765 #set PROTECT_SECTOR_SB3 OFF ; <<< select individual sector to protect
\r
768 ;====================================================================
\r
770 ;====================================================================
\r
772 #set BOOT_VECTOR_TABLE 1 ; enable boot vector
\r
773 #set BOOT_VECTOR_FIXED 2 ; enable boot vector
\r
775 #set BOOT_VECTOR BOOT_VECTOR_TABLE ; <<< select type of boot vector
\r
777 ; If boot vector generation is enabled (BOOT_VECTOR_TABLE, BOOT_VECTOR_FIXED),
\r
778 ; appropriate code is generated. If it is disabled (OFF), start-up file does
\r
781 ; BOOT_VECTOR_TABLE: - Create table entry at address oxFFFFDC.
\r
782 ; - Any start address can be set and start-up file will
\r
783 ; set address of this start code.
\r
784 ; BOOT_VECTOR_FIXED: - Instead of table entry, a special marker is set in
\r
785 ; ROM Configuration Block, which enables the fixed
\r
786 ; start address 0xDF0080. This is prefered setting
\r
787 ; for user boot loaders.
\r
788 ; OFF: - Do not set table entry and marker. This might be used
\r
789 ; for application to be loaded by boot loader.
\r
792 ; BOOT_VECTOR_TABLE setting can also be used, if all other interrupt vectors
\r
793 ; are specified via "pragma intvect". Only if interrupts 0..7 are specified
\r
794 ; via "pragma intvect", these will conflict with the vector in this module.
\r
795 ; The reason is the INTVECT section, which includes the whole area from the
\r
796 ; lowest to the highest specified vector.
\r
798 #if BOOT_VECTOR == BOOT_VECTOR_TABLE
\r
799 .SECTION RESVECT, CONST, LOCATE=H'FFFFDC
\r
801 .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030
\r
805 # if BOOT_VECTOR == BOOT_VECTOR_FIXED
\r
806 .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030
\r
807 .DATA.L 0x292D3A7B ; "Magic Word"
\r
809 .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030
\r
814 ;====================================================================
\r
815 ; 4.15 UART scanning
\r
816 ;====================================================================
\r
818 #set UART_SCANNING OFF ; <<< enable UART scanning in
\r
819 ; Internal Vector Mode
\r
821 ; By default, the MCU scans in Internal Vector Mode for a UART
\r
822 ; communication after reset. This enables to establish a serial
\r
823 ; communication without switching to Serial Communication Mode.
\r
824 ; For the final application, set this switch to OFF to achieve the
\r
825 ; fastest start-up time.
\r
827 #if UART_SCANNING == ON
\r
828 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
829 # error Device does not support UART scanning on/off
\r
831 .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034
\r
833 # endif ; (SERIES == MB96340 && DEVICE < 3)
\r
835 .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034
\r
836 .DATA.L 0x292D3A7B ; Decativation "Magic Word"
\r
841 ;====================================================================
\r
842 ; 4.16 Enable RAMCODE Copying
\r
843 ;====================================================================
\r
845 #set COPY_RAMCODE OFF ; <<< enable RAMCODE section to
\r
846 ; be copied from ROM to RAM
\r
848 ; To get this option properly working the code to be executed has to
\r
849 ; be linked to section RAMCODE (e.g. by #pragma section). The section
\r
850 ; RAMCODE has be located in RAM and the section @RAMCODE has to be
\r
851 ; located at a fixed address in ROM by linker settings.
\r
853 ;====================================================================
\r
854 ; 4.17 Enable information stamp in ROM
\r
855 ;====================================================================
\r
857 #set VERSION_STAMP OFF ; <<< enable version number in
\r
858 ; separated section
\r
861 #if VERSION_STAMP == ON
\r
862 .SECTION VERSIONS, CONST ; change name, if necessary
\r
863 .SDATA "Start ", VERSION, "\n\0"
\r
866 ;====================================================================
\r
867 ; 4.18 Enable Background Debugging Mode
\r
868 ;====================================================================
\r
870 #set BACKGROUND_DEBUGGING ON ; <<< enable Background Debugging
\r
873 #set BDM_CONFIGURATION B'0000000000010011 ; <<< set BDM configuration
\r
874 ; ||||||||++--- BdmUART
\r
875 ; |||||||| (0: A, 1: B, 2: C, 3: D)
\r
876 ; ||||||++----- BdmSynchMode
\r
877 ; |||||| (0: Async., 1: Sync.
\r
878 ; |||||| 2: BdmKLine, 3: res.)
\r
879 ; |||||+------- BdmAutoStart
\r
880 ; ||||+-------- BdmExtBreakpointCfg
\r
881 ; |||+--------- BdmKeepRClock
\r
882 ; ||+---------- BdmCaliRClock
\r
883 ; |+----------- BdmKeepBCD
\r
884 ; +------------ BdmUserKernel
\r
886 #set BDM_BAUDRATE 115200 ; <<< set Baudrate in Bits/s for BDM
\r
888 #set BDM_EXT_CONFIG 0xFFFFFF ; <<< set external Config/Kernel
\r
890 #set BDM_WD_PATTERN 0x00 ; <<< set watchdog pattern
\r
892 #set BDM_PFCS0 0x0000 ; <<< set default breakpoint
\r
893 #set BDM_PFCS1 0x0000 ; configurations
\r
894 #set BDM_PFCS2 0x0000
\r
895 #set BDM_PFCS3 0x0000
\r
897 #set BDM_PFA0 0xFFFFFF ; <<< set address
\r
898 #set BDM_PFA1 0xFFFFFF ; configurations
\r
899 #set BDM_PFA2 0xFFFFFF
\r
900 #set BDM_PFA3 0xFFFFFF
\r
901 #set BDM_PFA4 0xFFFFFF
\r
902 #set BDM_PFA5 0xFFFFFF
\r
903 #set BDM_PFA6 0xFFFFFF
\r
904 #set BDM_PFA7 0xFFFFFF
\r
906 #set BDM_PFD0 0xFFFF ; <<< set patch data
\r
907 #set BDM_PFD1 0xFFFF ; configurations
\r
908 #set BDM_PFD2 0xFFFF
\r
909 #set BDM_PFD3 0xFFFF
\r
910 #set BDM_PFD4 0xFFFF
\r
911 #set BDM_PFD5 0xFFFF
\r
912 #set BDM_PFD6 0xFFFF
\r
913 #set BDM_PFD7 0xFFFF
\r
916 ; <<< END OF SETTINGS >>>
\r
918 ;====================================================================
\r
919 ; 5 Section and Data Declaration
\r
920 ;====================================================================
\r
922 ;====================================================================
\r
923 ; 5.1 Several fixed addresses (fixed for MB963xx controllers)
\r
924 ;====================================================================
\r
926 MCSRA .EQU 0x03F1 ; Flash A Memory configuration register
\r
927 MTCRA .EQU 0x03F2 ; Flash A Memory timing register
\r
928 MCSRB .EQU 0x03F5 ; Flash B Memory configuration register
\r
929 MTCRB .EQU 0x03F6 ; Flash B Memory timing register
\r
930 ROMM .EQU 0x03AE ; ROM mirror control register
\r
931 CKSR .EQU 0x0401 ; Clock select control register
\r
932 CKSSR .EQU 0x0402 ; Clock stabilization select register
\r
933 CKMR .EQU 0x0403 ; Clock monitor register
\r
934 CKFCR .EQU 0x0404 ; Clock frequency control register
\r
935 PLLCR .EQU 0x0406 ; PLL control register
\r
936 VRCR .EQU 0x042C ; Voltage Regulator Control register
\r
937 ICE01 .EQU 0x0041 ; Input capture 0/1 source
\r
938 ICE67 .EQU 0x0053 ; Input capture 6/7 source
\r
939 ICE89 .EQU 0x0515 ; Input capture 8/9 source
\r
940 ICE1011 .EQU 0x051B ; Input capture 10/11 source
\r
941 ICS89 .EQU 0x0514 ; Input capture 8/9 edge select
\r
942 ICS1011 .EQU 0x051A ; Input capture 10/11 edge select
\r
943 TCCSL2 .EQU 0x0502 ; Free running timer 2 control/status register
\r
944 TCCSL3 .EQU 0x0506 ; Free running timer 3 control/status register
\r
945 #if BUSMODE != SINGLE_CHIP ; only for devices with external bus
\r
973 #endif ; BUSMODE != SINGLE_CHIP
\r
975 ;====================================================================
\r
976 ; 5.2 Declaration of __near addressed data sections
\r
977 ;====================================================================
\r
979 ; sections to be cleared
\r
980 .SECTION DATA, DATA, ALIGN=2 ; zero clear area
\r
981 .SECTION DATA2, DATA, ALIGN=2 ; zero clear area
\r
982 .SECTION DIRDATA, DIR, ALIGN=2 ; zero clear direct
\r
983 .SECTION LIBDATA, DATA, ALIGN=2 ; zero clear lib area
\r
985 ; sections to be initialised with start-up values
\r
986 .SECTION INIT, DATA, ALIGN=2 ; initialised area
\r
987 .SECTION INIT2, DATA, ALIGN=2 ; initialised area
\r
988 .SECTION DIRINIT, DIR, ALIGN=2 ; initialised dir
\r
989 .SECTION LIBINIT, DATA, ALIGN=2 ; initialised lib area
\r
990 #if CONSTDATA == RAMCONST
\r
991 .SECTION CINIT, DATA, ALIGN=2 ; initialised const
\r
992 .SECTION CINIT2, DATA, ALIGN=2 ; initialised const
\r
995 ; sections containing start-up values for initialised sections above
\r
996 .SECTION DCONST, CONST, ALIGN=2 ; DINIT initialisers
\r
997 .SECTION DIRCONST, DIRCONST,ALIGN=2 ; DIRINIT initialisers
\r
998 .SECTION LIBDCONST, CONST, ALIGN=2 ; LIBDCONST init val
\r
1000 ; following section is either copied to CINIT (RAMCONST) or
\r
1001 ; mapped by ROM-mirror function (ROMCONST)
\r
1002 .SECTION CONST, CONST, ALIGN=2 ; CINIT initialisers
\r
1003 .SECTION CONST2, CONST, ALIGN=2 ; CINIT initialisers
\r
1005 ;====================================================================
\r
1006 ; 5.3 Declaration of RAMCODE section and labels
\r
1007 ;====================================================================
\r
1009 #if COPY_RAMCODE == ON
\r
1010 .SECTION RAMCODE, CODE, ALIGN=1
\r
1011 .IMPORT _RAM_RAMCODE ; provided by linker
\r
1012 .IMPORT _ROM_RAMCODE ; provided by linker
\r
1016 ;====================================================================
\r
1017 ; 5.4 Declaration of sections containing other sections description
\r
1018 ;====================================================================
\r
1020 ; DCLEAR contains start address and size of all sections to be cleared
\r
1021 ; DTRANS contains source and destination address and size of all
\r
1022 ; sections to be initialised with start-up values
\r
1023 ; The compiler automatically adds a descriptor for each __far addressed
\r
1024 ; data section to DCLEAR or DTRANS. These __far sections are separated
\r
1025 ; for each C-module.
\r
1027 ; In addition the start-up file adds the descriptors of the previously
\r
1028 ; declared __near section here. This way the same code in the start-up
\r
1029 ; file can be used for initialising all sections.
\r
1031 .SECTION DCLEAR, CONST, ALIGN=2 ; zero clear table
\r
1032 ; Address Bank Size
\r
1033 .DATA.H DATA, BNKSEC DATA, SIZEOF(DATA )
\r
1034 .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA)
\r
1035 .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA)
\r
1037 .SECTION DTRANS, CONST, ALIGN=2 ; copy table
\r
1038 ; Address Bank Address Bank Size
\r
1039 .DATA.H DCONST, BNKSEC DCONST, INIT, BNKSEC INIT, SIZEOF INIT
\r
1040 .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT
\r
1041 .DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT
\r
1043 #if CONSTDATA == RAMCONST
\r
1044 .DATA.H CONST, BNKSEC CONST, CINIT, BNKSEC CINIT, SIZEOF CINIT
\r
1045 .DATA.H CONST2, BNKSEC CONST, CINIT2, BNKSEC CINIT2, SIZEOF CINIT2
\r
1048 #if COPY_RAMCODE == ON
\r
1049 .DATA.L _ROM_RAMCODE, _RAM_RAMCODE
\r
1050 .DATA.H SIZEOF RAMCODE
\r
1053 ;====================================================================
\r
1054 ; 5.5 Stack area and stack top definition/declaration
\r
1055 ;====================================================================
\r
1056 #if STACK_RESERVE == ON
\r
1057 .SECTION SSTACK, STACK, ALIGN=2
\r
1059 .EXPORT __systemstack, __systemstack_top
\r
1061 .RES.B (STACK_SYS_SIZE + 1) & 0xFFFE
\r
1062 __systemstack_top:
\r
1065 .SECTION USTACK, STACK, ALIGN=2
\r
1067 .EXPORT __userstack, __userstack_top
\r
1069 .RES.B (STACK_USR_SIZE + 1) & 0xFFFE
\r
1074 .SECTION SSTACK, STACK, ALIGN=2
\r
1075 .SECTION USTACK, STACK, ALIGN=2
\r
1077 .IMPORT __systemstack, __systemstack_top
\r
1078 .IMPORT __userstack, __userstack_top
\r
1081 ;====================================================================
\r
1082 ; 5.6 Direct page register dummy label definition
\r
1083 ;====================================================================
\r
1085 .SECTION DIRDATA ; zero clear direct
\r
1086 DIRDATA_S: ; label for DPR init
\r
1088 ; This label is used to get the page of the __direct data.
\r
1089 ; Depending on the linkage order of this startup file the label is
\r
1090 ; placed anywhere within the __direct data page. However, the
\r
1091 ; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower
\r
1092 ; 8 Bit of the address of DIRDATA_S are not relevant and this feature
\r
1093 ; becomes linkage order independent.
\r
1094 ; Note, the linker settings have to make sure that all __direct
\r
1095 ; data are located within the same physical page (256 Byte block).
\r
1097 ;====================================================================
\r
1098 ; 5.7 Set Flash Security
\r
1099 ;====================================================================
\r
1101 .SECTION FLASH_A_SECURITY, CONST, LOCATE=H'DF0000
\r
1102 #if FLASH_A_SECURITY_ENABLE == 0
\r
1103 .DATA.W 0xFFFF ; Security DISABLED
\r
1105 #else FLASH_A_SECURITY_ENABLE == 1
\r
1106 .DATA.W 0x0099 ; Security ENABLED
\r
1107 .DATA.W ((FLASH_A_UNLOCK_1 << 8) | FLASH_A_UNLOCK_0)
\r
1108 .DATA.W ((FLASH_A_UNLOCK_3 << 8) | FLASH_A_UNLOCK_2)
\r
1109 .DATA.W ((FLASH_A_UNLOCK_5 << 8) | FLASH_A_UNLOCK_4)
\r
1110 .DATA.W ((FLASH_A_UNLOCK_7 << 8) | FLASH_A_UNLOCK_6)
\r
1111 .DATA.W ((FLASH_A_UNLOCK_9 << 8) | FLASH_A_UNLOCK_8)
\r
1112 .DATA.W ((FLASH_A_UNLOCK_11 << 8) | FLASH_A_UNLOCK_10)
\r
1113 .DATA.W ((FLASH_A_UNLOCK_13 << 8) | FLASH_A_UNLOCK_12)
\r
1114 .DATA.W ((FLASH_A_UNLOCK_15 << 8) | FLASH_A_UNLOCK_14)
\r
1119 #if FLASH_B_AVAILABLE == ON
\r
1120 .SECTION FLASH_B_SECURITY, CONST, LOCATE=H'DE0000
\r
1121 # if FLASH_B_SECURITY_ENABLE == 0
\r
1122 .DATA.W 0xFFFF ; Security DISABLED
\r
1124 # else FLASH_B_SECURITY_ENABLE == 1
\r
1125 .DATA.W 0x0099 ; Security ENABLED
\r
1126 .DATA.W ((FLASH_B_UNLOCK_1 << 8) | FLASH_B_UNLOCK_0)
\r
1127 .DATA.W ((FLASH_B_UNLOCK_3 << 8) | FLASH_B_UNLOCK_2)
\r
1128 .DATA.W ((FLASH_B_UNLOCK_5 << 8) | FLASH_B_UNLOCK_4)
\r
1129 .DATA.W ((FLASH_B_UNLOCK_7 << 8) | FLASH_B_UNLOCK_6)
\r
1130 .DATA.W ((FLASH_B_UNLOCK_9 << 8) | FLASH_B_UNLOCK_8)
\r
1131 .DATA.W ((FLASH_B_UNLOCK_11 << 8) | FLASH_B_UNLOCK_10)
\r
1132 .DATA.W ((FLASH_B_UNLOCK_13 << 8) | FLASH_B_UNLOCK_12)
\r
1133 .DATA.W ((FLASH_B_UNLOCK_15 << 8) | FLASH_B_UNLOCK_14)
\r
1137 #endif ; FLASH_B_AVAILABLE == ON
\r
1140 ;====================================================================
\r
1141 ; 5.8 Set Flash write protection
\r
1142 ;====================================================================
\r
1144 .SECTION FLASH_A_PROTECT, CONST, LOCATE=H'DF001C
\r
1145 #if FLASH_A_WRITE_PROTECT == ON
\r
1146 .DATA.L 0x292D3A7B
\r
1147 .DATA.B ~((PROTECT_SECTOR_SA3 << 3) | (PROTECT_SECTOR_SA2 << 2) | (PROTECT_SECTOR_SA1 << 1) | PROTECT_SECTOR_SA0)
\r
1149 .DATA.B ~((PROTECT_SECTOR_SA39 << 7) | (PROTECT_SECTOR_SA38 << 6) | (PROTECT_SECTOR_SA37 << 5) | (PROTECT_SECTOR_SA36 << 4) | (PROTECT_SECTOR_SA35 << 3) | (PROTECT_SECTOR_SA34 << 2) | (PROTECT_SECTOR_SA33 << 1) | PROTECT_SECTOR_SA32)
\r
1152 .DATA.L 0xFFFFFFFF
\r
1154 #endif ; FLASH_A_WRITE_PROTECT
\r
1157 #if FLASH_B_AVAILABLE == ON
\r
1158 .SECTION FLASH_B_PROTECT, CONST, LOCATE=H'DE001C
\r
1159 # if FLASH_B_WRITE_PROTECT == ON
\r
1160 .DATA.L 0x292D3A7B
\r
1161 .DATA.B ~((PROTECT_SECTOR_SB3 << 3) | (PROTECT_SECTOR_SB2 << 2) | (PROTECT_SECTOR_SB1 << 1) | PROTECT_SECTOR_SB0)
\r
1164 .DATA.L 0xFFFFFFFF
\r
1166 # endif ; FLASH_B_WRITE_PROTECT
\r
1168 #endif ; FLASH_B_AVAILABLE == ON
\r
1171 ;====================================================================
\r
1172 ; 5.9 Debug address specification
\r
1173 ;====================================================================
\r
1175 ; BDM configuration section should always be defined for later
\r
1176 ; configuration by e.g. debugger tool or (special) programmer tool.
\r
1178 .SECTION BDM_CONFIG, CONST, LOCATE=H'DF0040
\r
1180 #if BACKGROUND_DEBUGGING == ON
\r
1182 .DATA.L 0x292D3A7B
\r
1185 .DATA.W BDM_CONFIGURATION
\r
1188 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1189 # error Device does not support background debugging
\r
1190 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1192 # if ((SERIES == MB96340) && (DEVICE < 12))
\r
1193 .DATA.W (D'16 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE
\r
1195 .DATA.W (D'32 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE
\r
1196 # endif ; ((SERIES == MB96340) && (DEVICE < 12))
\r
1199 .DATA.E BDM_EXT_CONFIG
\r
1202 .DATA.B BDM_WD_PATTERN
\r
1207 .DATA.W BDM_PFCS2
\r
1208 .DATA.W BDM_PFCS3
\r
1210 .DATA.E BDM_PFA0, BDM_PFA1
\r
1211 .DATA.E BDM_PFA2, BDM_PFA3
\r
1212 .DATA.E BDM_PFA4, BDM_PFA5
\r
1213 .DATA.E BDM_PFA6, BDM_PFA7
\r
1215 .DATA.W BDM_PFD0, BDM_PFD1
\r
1216 .DATA.W BDM_PFD2, BDM_PFD3
\r
1217 .DATA.W BDM_PFD4, BDM_PFD5
\r
1218 .DATA.W BDM_PFD6, BDM_PFD7
\r
1220 .DATAB.B 64, 0xFF ; fill section with 0xFF
\r
1222 #endif ; BACKGROUND_DEBUGGING == ON
\r
1226 ;====================================================================
\r
1228 ;====================================================================
\r
1230 ;====================================================================
\r
1231 ; 6.1 Import external symbols
\r
1232 ;====================================================================
\r
1234 .IMPORT _main ; user code entrance
\r
1235 #if CLIBINIT == ON
\r
1236 .IMPORT __stream_init
\r
1242 ;====================================================================
\r
1243 ; ___ _____ __ ___ _____
\r
1245 ; \___ | | | |___/ |
\r
1246 ; \ | |----| | \ |
\r
1247 ; ___/ | | | | \ | Begin of actual code section
\r
1249 ;====================================================================
\r
1250 .SECTION CODE_START, CODE, ALIGN=1
\r
1252 ;====================================================================
\r
1253 ; 6.2 Program start (the reset vector should point here)
\r
1254 ;====================================================================
\r
1256 NOP ; This NOP is only for debugging. On debugger the IP
\r
1257 ; (instruction pointer) should point here after reset
\r
1259 ;====================================================================
\r
1260 ; 6.3 "NOT RESET YET" WARNING
\r
1261 ;====================================================================
\r
1263 NOP ; read hint below!!!!!!!
\r
1264 ; If the debugger stays at this NOP after download, the controller has
\r
1265 ; not been reset yet. In order to reset all hardware registers it is
\r
1266 ; highly recommended to reset the controller.
\r
1267 ; However, if no reset vector has been defined on purpose, this start
\r
1268 ; address can also be used.
\r
1269 ; This mechanism is using the .END instruction at the end of this mo-
\r
1270 ; dule. It is not necessary for controller operation but improves
\r
1271 ; security during debugging (mainly emulator debugger).
\r
1272 ; If the debugger stays here after a single step from label "_start"
\r
1273 ; to label "notresetyet", this note can be ignored.
\r
1275 ;====================================================================
\r
1276 ; 6.4 Initialisation of processor status
\r
1277 ;====================================================================
\r
1278 AND CCR, #0x80 ; disable interrupts
\r
1279 MOV ILM,#7 ; set interrupt level mask to ALL
\r
1280 MOV RP,#REGBANK ; set register bank pointer
\r
1282 ;====================================================================
\r
1283 ; 6.5 Set clock ratio (ignore subclock)
\r
1284 ;====================================================================
\r
1285 MOVN A, #0 ; set bank 0 in DTB for the case that
\r
1286 MOV DTB, A ; start-up code was not jumped by reset
\r
1288 MOV CKSSR, #(0xF8 | MC_STAB_TIME) ; set clock stabilization time
\r
1290 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
\r
1292 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
\r
1294 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
\r
1299 MOVW CKFCR, #0x1111
\r
1300 MOVW MTCRA, #0x2128
\r
1301 # if FLASH_B_AVAILABLE == ON
\r
1302 MOVW MTCRB, #0x2128
\r
1303 # endif ; FLASH_B_AVAILABLE == ON
\r
1305 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
\r
1307 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
\r
1308 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1309 MOVW PLLCR, #0x00E0
\r
1312 MOVW PLLCR, #0x00A1
\r
1313 MOVW CKFCR, #0x1111
\r
1314 MOVW MTCRA, #0x2128
\r
1315 # if FLASH_B_AVAILABLE == ON
\r
1316 MOVW MTCRB, #0x2128
\r
1317 # endif ; FLASH_B_AVAILABLE == ON
\r
1319 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1320 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
\r
1322 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
\r
1323 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1324 MOVW PLLCR, #0x0060
\r
1329 MOVW CKFCR, #0x1111
\r
1332 MOVW PLLCR, #0x0060
\r
1333 MOVW CKFCR, #0x1111
\r
1334 MOVW MTCRA, #0x2128
\r
1335 # if FLASH_B_AVAILABLE == ON
\r
1336 MOVW MTCRB, #0x2128
\r
1337 # endif ; FLASH_B_AVAILABLE == ON
\r
1339 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1340 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
\r
1342 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
\r
1343 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1344 MOVW PLLCR, #0x00A1
\r
1347 MOVW PLLCR, #0x0043
\r
1348 MOVW CKFCR, #0x1111
\r
1349 MOVW MTCRA, #0x2128
\r
1350 # if FLASH_B_AVAILABLE == ON
\r
1351 MOVW MTCRB, #0x2128
\r
1352 # endif ; FLASH_B_AVAILABLE == ON
\r
1354 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1355 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
\r
1357 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
\r
1358 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1359 MOVW PLLCR, #0x0060
\r
1362 MOVW PLLCR, #0x0081
\r
1363 MOVW CKFCR, #0x1111
\r
1364 MOVW MTCRA, #0x2128
\r
1365 # if FLASH_B_AVAILABLE == ON
\r
1366 MOVW MTCRB, #0x2128
\r
1367 # endif ; FLASH_B_AVAILABLE == ON
\r
1369 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1370 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
\r
1372 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
\r
1373 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1374 MOVW PLLCR, #0x0062
\r
1377 MOVW PLLCR, #0x0025
\r
1378 MOVW CKFCR, #0x1111
\r
1379 MOVW MTCRA, #0x2128
\r
1380 # if FLASH_B_AVAILABLE == ON
\r
1381 MOVW MTCRB, #0x2128
\r
1382 # endif ; FLASH_B_AVAILABLE == ON
\r
1384 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1385 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
\r
1387 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
\r
1388 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1389 MOVW PLLCR, #0x0061
\r
1394 MOVW CKFCR, #0x1111
\r
1397 MOVW PLLCR, #0x0061
\r
1398 MOVW CKFCR, #0x1111
\r
1399 MOVW MTCRA, #0x2128
\r
1400 # if FLASH_B_AVAILABLE == ON
\r
1401 MOVW MTCRB, #0x2128
\r
1402 # endif ; FLASH_B_AVAILABLE == ON
\r
1404 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1405 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
\r
1407 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
\r
1408 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1409 MOVW PLLCR, #0x0043
\r
1412 MOVW PLLCR, #0x0027
\r
1413 MOVW CKFCR, #0x1111
\r
1414 MOVW MTCRA, #0x2128
\r
1416 # if FLASH_B_AVAILABLE == ON
\r
1417 MOVW MTCRB, #0x2128
\r
1419 # endif ; FLASH_B_AVAILABLE == ON
\r
1422 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1423 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
\r
1425 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
\r
1426 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1427 MOVW PLLCR, #0x0081
\r
1430 MOVW PLLCR, #0x0003
\r
1431 MOVW CKFCR, #0x1111
\r
1432 MOVW MTCRA, #0x2128
\r
1434 # if FLASH_B_AVAILABLE == ON
\r
1435 MOVW MTCRB, #0x2128
\r
1437 # endif ; FLASH_B_AVAILABLE == ON
\r
1440 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1441 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
\r
1443 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
\r
1444 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1445 MOVW PLLCR, #0x0025
\r
1446 MOVW CKFCR, #0x1001
\r
1449 MOVW PLLCR, #0x000B
\r
1450 MOVW CKFCR, #0x3111
\r
1451 MOVW MTCRA, #0x4C09
\r
1452 # if FLASH_B_AVAILABLE == ON
\r
1453 MOVW MTCRB, #0x4C09
\r
1454 # endif ; FLASH_B_AVAILABLE == ON
\r
1456 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1457 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
\r
1459 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
\r
1460 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1461 MOVW PLLCR, #0x0082
\r
1462 MOVW CKFCR, #0x1001
\r
1465 MOVW PLLCR, #0x0005
\r
1466 MOVW CKFCR, #0x3111
\r
1467 MOVW MTCRA, #0x4C09
\r
1468 # if FLASH_B_AVAILABLE == ON
\r
1469 MOVW MTCRB, #0x4C09
\r
1470 # endif ; FLASH_B_AVAILABLE == ON
\r
1472 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1473 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
\r
1475 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
\r
1476 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1477 # error Setting prohibited due to 16FXFL0014
\r
1479 MOVW PLLCR, #0x0027
\r
1480 MOVW CKFCR, #0x1001
\r
1481 MOVW MTCRA, #0x2129
\r
1483 # if FLASH_B_AVAILABLE == ON
\r
1484 MOVW MTCRB, #0x2129
\r
1486 # endif ; FLASH_B_AVAILABLE == ON
\r
1489 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1490 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
\r
1492 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
\r
1493 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1494 # error Setting prohibited due to 16FXFL0014
\r
1496 MOVW PLLCR, #0x0003
\r
1497 MOVW CKFCR, #0x1001
\r
1498 MOVW MTCRA, #0x2129
\r
1500 # if FLASH_B_AVAILABLE == ON
\r
1501 MOVW MTCRB, #0x2129
\r
1503 # endif ; FLASH_B_AVAILABLE == ON
\r
1506 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1507 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
\r
1509 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
\r
1510 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1511 # error Setting prohibited due to 16FXFL0014
\r
1513 MOVW PLLCR, #0x0027
\r
1514 MOVW CKFCR, #0x1101
\r
1515 MOVW MTCRA, #0x2129
\r
1517 # if FLASH_B_AVAILABLE == ON
\r
1518 MOVW MTCRB, #0x2129
\r
1520 # endif ; FLASH_B_AVAILABLE == ON
\r
1523 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1524 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
\r
1526 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
\r
1527 # if ((SERIES == MB96340) && (DEVICE < 3))
\r
1528 # error Setting prohibited due to 16FXFL0014
\r
1530 MOVW PLLCR, #0x0003
\r
1531 MOVW CKFCR, #0x1101
\r
1532 MOVW MTCRA, #0x2129
\r
1534 # if FLASH_B_AVAILABLE == ON
\r
1535 MOVW MTCRB, #0x2129
\r
1537 # endif ; FLASH_B_AVAILABLE == ON
\r
1540 # endif ; ((SERIES == MB96340) && (DEVICE < 3))
\r
1541 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
\r
1543 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
\r
1544 MOVW PLLCR, #0x0017
\r
1545 MOVW CKFCR, #0x5111
\r
1546 MOVW MTCRA, #0x6E3D
\r
1548 # if FLASH_B_AVAILABLE == ON
\r
1549 MOVW MTCRB, #0x6E3D
\r
1551 # endif ; FLASH_B_AVAILABLE == ON
\r
1554 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
\r
1556 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
\r
1557 MOVW PLLCR, #0x000B
\r
1558 MOVW CKFCR, #0x5111
\r
1559 MOVW MTCRA, #0x6E3D
\r
1561 # if FLASH_B_AVAILABLE == ON
\r
1562 MOVW MTCRB, #0x6E3D
\r
1564 # endif ; FLASH_B_AVAILABLE == ON
\r
1567 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
\r
1569 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
\r
1570 MOVW PLLCR, #0x0017
\r
1571 MOVW CKFCR, #0x5211
\r
1572 MOVW MTCRA, #0x6E3D
\r
1574 # if FLASH_B_AVAILABLE == ON
\r
1575 MOVW MTCRB, #0x6E3D
\r
1577 # endif ; FLASH_B_AVAILABLE == ON
\r
1580 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
\r
1582 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
\r
1583 MOVW PLLCR, #0x000B
\r
1584 MOVW CKFCR, #0x5211
\r
1585 MOVW MTCRA, #0x6E3D
\r
1587 # if FLASH_B_AVAILABLE == ON
\r
1588 MOVW MTCRB, #0x6E3D
\r
1590 # endif ; FLASH_B_AVAILABLE == ON
\r
1593 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
\r
1595 #if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
\r
1596 MOVW PLLCR, #0x000D
\r
1597 MOVW CKFCR, #0x3001
\r
1598 MOVW MTCRA, #0x233A
\r
1600 # if FLASH_B_AVAILABLE == ON
\r
1601 MOVW MTCRB, #0x233A
\r
1603 # endif ; FLASH_B_AVAILABLE == ON
\r
1606 #endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
\r
1608 #if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
\r
1609 MOVW PLLCR, #0x0006
\r
1610 MOVW CKFCR, #0x3001
\r
1611 MOVW MTCRA, #0x233A
\r
1613 # if FLASH_B_AVAILABLE == ON
\r
1614 MOVW MTCRB, #0x233A
\r
1616 # endif ; FLASH_B_AVAILABLE == ON
\r
1619 #endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
\r
1622 ;====================================================================
\r
1623 ; 6.6 Set external bus configuaration
\r
1624 ;====================================================================
\r
1626 #if BUSMODE != SINGLE_CHIP ; ext bus used
\r
1627 MOV EBCF, #((HOLD_REQ << 7) | (EXT_READY << 6) | (EXT_CLOCK_ENABLE << 5) | (EXT_CLOCK_INVERT << 4) | (EXT_CLOCK_SUSPEND << 3) | EXT_CLOCK_DIVISION)
\r
1628 MOV EBAE0,#ADDR_PINS_7_0
\r
1629 MOV EBAE1,#ADDR_PINS_15_8
\r
1630 MOV EBAE2,#ADDR_PINS_23_16
\r
1631 MOV EBCS, #((ADDRESS_STROBE_LVL << 6) | (ADDRESS_STROBE << 5) | (READ_STROBE << 4) | (HIGH_WRITE_STROBE << 3) | (LOW_WRITE_STROBE << 2) | (HIGH_BYTE_SIGNAL << 1) | LOW_BYTE_SIGNAL)
\r
1632 MOVW EACL0,#CS0_CONFIG
\r
1633 MOVW EACL1,#CS1_CONFIG
\r
1634 MOVW EACL2,#CS2_CONFIG
\r
1635 MOVW EACL3,#CS3_CONFIG
\r
1636 MOVW EACL4,#CS4_CONFIG
\r
1637 MOVW EACL5,#CS5_CONFIG
\r
1638 MOV EAS2, #CS2_START
\r
1639 MOV EAS3, #CS3_START
\r
1640 MOV EAS4, #CS4_START
\r
1641 MOV EAS5, #CS5_START
\r
1642 MOV EBM, #((ADDRESSMODE << 7) | ((BUSMODE-1) << 6) | (CHIP_SELECT5 << 5) | (CHIP_SELECT4 << 4) | (CHIP_SELECT3 << 3) | (CHIP_SELECT2 << 2) | (CHIP_SELECT1 << 1) | CHIP_SELECT0) ; set address mode, ROM access
\r
1644 # if SERIES == MB96320 || SERIES == MB96330 || SERIES == MB96340 || SERIES == MB96350
\r
1646 # if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0
\r
1649 # if HOLD_REQ == ON
\r
1652 # if EXT_READY == ON
\r
1656 # else if SERIES == MB96370 || SERIES == MB96380
\r
1658 # if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0
\r
1661 # if HOLD_REQ == ON
\r
1664 # if EXT_READY == ON
\r
1671 #if BUSMODE == INTROM_EXTBUS ; EXTBUS and INTROM/EXTROM
\r
1672 # if ROMMIRROR == OFF && CONSTDATA == ROMCONST
\r
1673 # error Mirror function must be ON to mirror internal ROM
\r
1677 ROMM_CONFIG .EQU ((MIRROR_BANK << 4) | (MIRROR_SIZE << 1) | (ROMMIRROR))
\r
1678 MOV ROMM, #ROMM_CONFIG
\r
1681 ;====================================================================
\r
1682 ; 6.7 Prepare stacks and set the default stack type
\r
1683 ;====================================================================
\r
1685 AND CCR,#H'DF ; clear system stack flag
\r
1686 MOVL A, #(__userstack_top) & ~1
\r
1687 MOVW SP,A ; load offset of stack top to pointer
\r
1688 SWAPW ; swap higher word to AL
\r
1689 MOV USB, A ; set bank
\r
1691 #if STACK_FILL == ON ; preset the stack
\r
1693 MOVW A, #USTACK ; load start stack address to AL
\r
1694 MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL
\r
1695 MOVW RW0, #SIZEOF(USTACK) / 2 ; get byte count
\r
1696 FILSWI ADB ; write pattern to stack
\r
1699 OR CCR,#H'20 ; set System stack flag
\r
1700 MOVL A, #(__systemstack_top) & ~1
\r
1701 MOVW SP,A ; load offset of stack top to pointer
\r
1702 SWAPW ; swap higher word to AL
\r
1703 MOV SSB, A ; set bank
\r
1705 #if STACK_FILL == ON ; preset the stack
\r
1707 MOVW A, #SSTACK ; load start stack address to AL
\r
1708 MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL
\r
1709 MOVW RW0, #SIZEOF(SSTACK) / 2; get byte count
\r
1710 FILSWI ADB ; write pattern to stack
\r
1713 #if STACKUSE == USRSTACK
\r
1714 AND CCR,#H'DF ; clear system stack flag
\r
1718 ; The following macro is needed because of the AUTOMODEL option. If the
\r
1719 ; model is not known while assembling the module, one has to expect
\r
1720 ; completion of streaminit() by RET or RETP. Because RET removes 2 bytes
\r
1721 ; from stack and RETP removes 4 bytes from stack, SP is reloaded.
\r
1725 #if STACKUSE == USRSTACK
\r
1726 MOVW A, #(__userstack_top) & ~1
\r
1728 MOVW A, #(__systemstack_top) & ~1
\r
1734 ;====================================================================
\r
1735 ; 6.8 Copy initial values to data areas.
\r
1736 ;====================================================================
\r
1738 ; Each C-module has its own __far INIT section. The names are generic.
\r
1739 ; DCONST_module contains the initializers for the far data of the one
\r
1740 ; module. INIT_module reserves the RAM area, which has to be loaded
\r
1741 ; with the data from DCONST_module. ("module" is the name of the *.c
\r
1743 ; All separated DCONST_module/INIT_module areas are described in
\r
1744 ; DTRANS section by start addresses and length of each far section.
\r
1745 ; 0000 1. source address (ROM)
\r
1746 ; 0004 1. destination address (RAM)
\r
1747 ; 0008 length of sections 1
\r
1748 ; 000A 2. source address (ROM)
\r
1749 ; 000E 2. destination address (RAM)
\r
1750 ; 0012 length of sections 2
\r
1751 ; 0014 3. source address ...
\r
1752 ; In addition the start-up file adds the descriptors of the __near
\r
1753 ; sections to this table. The order of the descriptors in this table
\r
1754 ; depends on the linkage order.
\r
1755 ;====================================================================
\r
1756 MOV A, #BNKSEC DTRANS ; get bank of table
\r
1757 MOV DTB, A ; store bank in DTB
\r
1758 MOVW RW1, #DTRANS ; get start offset of table
\r
1759 OR CCR, #H'20 ; System stack flag set (SSB used)
\r
1760 BRA LABEL2 ; branch to loop condition
\r
1762 MOVW A, @RW1+6 ; get bank of destination
\r
1763 MOV SSB, A ; save dest bank in SSB
\r
1764 MOVW A, @RW1+2 ; get source bank
\r
1765 MOV ADB, A ; save source bank in ADB
\r
1766 MOVW A, @RW1+4 ; move destination addr in AL
\r
1767 MOVW A, @RW1 ; AL -> AH, src addr -> AL
\r
1768 MOVW RW0, @RW1+8 ; number of bytes to copy -> RW0
\r
1769 MOVSI SPB, ADB ; copy data
\r
1770 MOVN A, #10 ; length of one table entry is 10
\r
1771 ADDW RW1, A ; set pointer to next table entry
\r
1773 MOVW A, RW1 ; get address of next block
\r
1774 SUBW A, #DTRANS ; sub address of first block
\r
1775 CMPW A, #SIZEOF (DTRANS) ; all blocks processed ?
\r
1776 BNE LABEL1 ; if not, branch
\r
1779 ;====================================================================
\r
1780 ; 6.9 Clear uninitialized data areas to zero
\r
1781 ;====================================================================
\r
1783 ; Each C-module has its own __far DATA section. The names are generic.
\r
1784 ; DATA_module contains the reserved area (RAM) to be cleared.
\r
1785 ; ("module" is the name of the *.c file)
\r
1786 ; All separated DATA_module areas are described in DCLEAR section by
\r
1787 ; start addresses and length of all far section.
\r
1788 ; 0000 1. section address (RAM)
\r
1789 ; 0004 length of section 1
\r
1790 ; 0006 2. section address (RAM)
\r
1791 ; 000A length of section 2
\r
1792 ; 000C 3. section address (RAM)
\r
1793 ; 0010 length of section 3 ...
\r
1794 ; In addition the start-up file adds the descriptors of the __near
\r
1795 ; sections to this table. The order of the descriptors in this table
\r
1796 ; depends on the linkage order.
\r
1797 ;====================================================================
\r
1798 MOV A, #BNKSEC DCLEAR ; get bank of table
\r
1799 MOV DTB, A ; store bank in DTB
\r
1800 MOVW RW1, #DCLEAR ; get start offset of table
\r
1801 BRA LABEL4 ; branch to loop condition
\r
1803 MOV A, @RW1+2 ; get section bank
\r
1804 MOV ADB, A ; save section bank in ADB
\r
1805 MOVW RW0, @RW1+4 ; number of bytes to copy -> RW0
\r
1806 MOVW A, @RW1 ; move section addr in AL
\r
1807 MOVN A, #0 ; AL -> AH, init value -> AL
\r
1808 FILSI ADB ; write 0 to section
\r
1809 MOVN A, #6 ; length of one table entry is 6
\r
1810 ADDW RW1, A ; set pointer to next table entry
\r
1812 MOVW A, RW1 ; get address of next block
\r
1813 SUBW A, #DCLEAR ; sub address of first block
\r
1814 CMPW A, #SIZEOF (DCLEAR) ; all blocks processed ?
\r
1815 BNE LABEL3 ; if not, branch
\r
1819 ;====================================================================
\r
1820 ; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR)
\r
1821 ;====================================================================
\r
1822 MOV A,#BNKSEC DATA ; User data bank offset
\r
1825 MOV A,#PAGE DIRDATA_S ; User direct page
\r
1828 ;====================================================================
\r
1829 ; 6.11 ICU register initialization workaround
\r
1830 ;====================================================================
\r
1832 #if (UART_SCANNING == ON)
\r
1833 # if (((SERIES == MB96320) && (DEVICE < 3)) || \
\r
1834 ((SERIES == MB96350) && (DEVICE < 3)))
\r
1843 # endif ; ((SERIES == 96350) && ...
\r
1844 # if (((SERIES == MB96330) && (DEVICE < 2)) || \
\r
1845 ((SERIES == MB96340) && (DEVICE < 27)) || \
\r
1846 ((SERIES == MB96370) && (DEVICE < 3)) || \
\r
1847 ((SERIES == MB96380) && (DEVICE < 13)))
\r
1851 # endif ; (((SERIES == MB96330) && (DEVICE < 2)) || ...
\r
1852 #endif ; (UART_SCANNING == ON)
\r
1854 ;====================================================================
\r
1855 ; 6.12 Wait for clocks to stabilize
\r
1856 ;====================================================================
\r
1858 #if (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) && (CLOCKWAIT == ON)
\r
1860 BBC CKMR:5,no_MC_yet ; check MCM and wait for
\r
1861 ; Main Clock to stabilize
\r
1862 #endif ; wait for Main Clock
\r
1864 #if (((CRYSTAL == FREQ_4MHZ) ||(CRYSTAL == FREQ_8MHZ)) && \
\r
1865 ((CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) || \
\r
1866 (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) || \
\r
1867 (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)))
\r
1869 BBC CKMR:6, no_PLL_0WS
\r
1871 # if ! ((SERIES == MB96340) && (DEVICE < 3))
\r
1872 MOVW MTCRA, #0x2208
\r
1873 # if FLASH_B_AVAILABLE == ON
\r
1874 MOVW MTCRB, #0x2208
\r
1875 # endif ; FLASH_B_AVAILABLE == ON
\r
1876 # endif ; ! ((SERIES == MB96340) && (DEVICE < 3))
\r
1879 #if ((CRYSTAL == FREQ_4MHZ) || (CRYSTAL == FREQ_8MHZ)) && \
\r
1880 ((CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) || \
\r
1881 (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)) && \
\r
1882 ! ((SERIES == MB96340) && (DEVICE < 3))
\r
1884 BBC CKMR:6, no_PLL_1WS
\r
1886 MOVW MTCRA, #0x6B09
\r
1887 # if FLASH_B_AVAILABLE == ON
\r
1888 MOVW MTCRB, #0x6B09
\r
1889 # endif ; FLASH_B_AVAILABLE == ON
\r
1892 #if (CLOCKWAIT == ON) && \
\r
1893 ((CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) || \
\r
1894 (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) || \
\r
1895 (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ))
\r
1897 BBC CKMR:6,no_PLL_yet ; check PCM and wait for
\r
1898 ; PLL to stabilize
\r
1899 #endif ; wait for PLL
\r
1901 ;====================================================================
\r
1902 ; 6.13 Initialise Low-Level Library Interface
\r
1903 ;====================================================================
\r
1905 ; Call lib init function and reload stack afterwards, if AUTOMODEL
\r
1906 ;====================================================================
\r
1907 #if CLIBINIT == ON
\r
1908 # if MEMMODEL == SMALL || MEMMODEL == COMPACT
\r
1909 CALL __stream_init ; initialise library IO
\r
1910 # else ; MEDIUM, LARGE, AUTOMODEL
\r
1911 CALLP __stream_init ; initialise library IO
\r
1912 # if MEMMODEL == AUTOMODEL
\r
1913 RELOAD_SP ; reload stack since stream_init was
\r
1914 ; possibly left by RET (not RETP)
\r
1915 # endif ; AUTOMODEL
\r
1916 # endif ; MEDIUM, LARGE, AUTOMODEL
\r
1919 ;====================================================================
\r
1920 ; 6.14 Call C-language main function
\r
1921 ;====================================================================
\r
1922 #if MEMMODEL == SMALL || MEMMODEL == COMPACT
\r
1923 CALL _main ; Start main function
\r
1924 #else ; MEDIUM, LARGE, AUTOMODEL
\r
1925 CALLP _main ; Start main function
\r
1926 ; ignore remaining word on stack,
\r
1927 ; if main was completed by RET
\r
1929 ;====================================================================
\r
1930 ; 6.15 Shut down library
\r
1931 ;====================================================================
\r
1932 #if CLIBINIT == ON
\r
1933 # if MEMMODEL == SMALL || MEMMODEL == COMPACT
\r
1935 # else ; MEDIUM, LARGE, AUTOMODEL
\r
1936 CALLP _exit ; ignore remaining word on stack,
\r
1937 ; if main was completed by RET
\r
1942 ;====================================================================
\r
1943 ; 6.16 Program end loop
\r
1944 ;====================================================================
\r
1946 end: BRA end ; Loop
\r
1948 .END notresetyet ; define debugger start address
\r
1951 ;====================================================================
\r
1952 ; ----------------------- End of Start-up file ---------------------
\r
1953 ;====================================================================
\r
projects / freertos / blob