2 * These files are taken from the MCF523X source code example package
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3 * which is available on the Freescale website. Freescale explicitly
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4 * grants the redistribution and modification of these source files.
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5 * The complete licensing information is available in the file
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6 * LICENSE_FREESCALE.TXT.
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8 * File: mcf523x_intc1.h
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9 * Purpose: Register and bit definitions for the MCF523X
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15 #ifndef __MCF523X_INTC1_H__
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16 #define __MCF523X_INTC1_H__
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18 /*********************************************************************
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20 * Interrupt Controller 1 (INTC1)
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22 *********************************************************************/
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24 /* Register read/write macros */
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25 #define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
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26 #define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
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27 #define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
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28 #define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
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29 #define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
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30 #define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
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31 #define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
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32 #define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
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33 #define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
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34 #define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
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35 #define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
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36 #define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
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37 #define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
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38 #define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
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39 #define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
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40 #define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
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41 #define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
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42 #define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
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43 #define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
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44 #define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
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45 #define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
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46 #define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
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47 #define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
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48 #define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
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49 #define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
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50 #define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
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51 #define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
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52 #define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
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53 #define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
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54 #define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
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55 #define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
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56 #define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
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57 #define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
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58 #define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
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59 #define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
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60 #define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
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61 #define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
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62 #define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
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63 #define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
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64 #define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
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65 #define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
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66 #define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
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67 #define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
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68 #define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
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69 #define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
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70 #define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
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71 #define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
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72 #define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
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73 #define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
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74 #define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
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75 #define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
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76 #define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
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77 #define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
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78 #define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
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79 #define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
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80 #define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
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81 #define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
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82 #define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
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83 #define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
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84 #define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
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85 #define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
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86 #define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
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87 #define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
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88 #define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
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89 #define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
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90 #define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
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91 #define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
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92 #define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
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93 #define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
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94 #define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
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95 #define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
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96 #define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
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97 #define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
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98 #define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
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99 #define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
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100 #define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
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101 #define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
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102 #define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
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103 #define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
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104 #define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
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105 #define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
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106 #define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
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108 /* Bit definitions and macros for MCF_INTC1_IPRH */
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109 #define MCF_INTC1_IPRH_INT32 (0x00000001)
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110 #define MCF_INTC1_IPRH_INT33 (0x00000002)
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111 #define MCF_INTC1_IPRH_INT34 (0x00000004)
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112 #define MCF_INTC1_IPRH_INT35 (0x00000008)
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113 #define MCF_INTC1_IPRH_INT36 (0x00000010)
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114 #define MCF_INTC1_IPRH_INT37 (0x00000020)
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115 #define MCF_INTC1_IPRH_INT38 (0x00000040)
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116 #define MCF_INTC1_IPRH_INT39 (0x00000080)
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117 #define MCF_INTC1_IPRH_INT40 (0x00000100)
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118 #define MCF_INTC1_IPRH_INT41 (0x00000200)
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119 #define MCF_INTC1_IPRH_INT42 (0x00000400)
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120 #define MCF_INTC1_IPRH_INT43 (0x00000800)
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121 #define MCF_INTC1_IPRH_INT44 (0x00001000)
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122 #define MCF_INTC1_IPRH_INT45 (0x00002000)
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123 #define MCF_INTC1_IPRH_INT46 (0x00004000)
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124 #define MCF_INTC1_IPRH_INT47 (0x00008000)
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125 #define MCF_INTC1_IPRH_INT48 (0x00010000)
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126 #define MCF_INTC1_IPRH_INT49 (0x00020000)
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127 #define MCF_INTC1_IPRH_INT50 (0x00040000)
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128 #define MCF_INTC1_IPRH_INT51 (0x00080000)
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129 #define MCF_INTC1_IPRH_INT52 (0x00100000)
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130 #define MCF_INTC1_IPRH_INT53 (0x00200000)
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131 #define MCF_INTC1_IPRH_INT54 (0x00400000)
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132 #define MCF_INTC1_IPRH_INT55 (0x00800000)
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133 #define MCF_INTC1_IPRH_INT56 (0x01000000)
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134 #define MCF_INTC1_IPRH_INT57 (0x02000000)
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135 #define MCF_INTC1_IPRH_INT58 (0x04000000)
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136 #define MCF_INTC1_IPRH_INT59 (0x08000000)
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137 #define MCF_INTC1_IPRH_INT60 (0x10000000)
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138 #define MCF_INTC1_IPRH_INT61 (0x20000000)
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139 #define MCF_INTC1_IPRH_INT62 (0x40000000)
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140 #define MCF_INTC1_IPRH_INT63 (0x80000000)
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142 /* Bit definitions and macros for MCF_INTC1_IPRL */
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143 #define MCF_INTC1_IPRL_INT1 (0x00000002)
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144 #define MCF_INTC1_IPRL_INT2 (0x00000004)
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145 #define MCF_INTC1_IPRL_INT3 (0x00000008)
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146 #define MCF_INTC1_IPRL_INT4 (0x00000010)
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147 #define MCF_INTC1_IPRL_INT5 (0x00000020)
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148 #define MCF_INTC1_IPRL_INT6 (0x00000040)
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149 #define MCF_INTC1_IPRL_INT7 (0x00000080)
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150 #define MCF_INTC1_IPRL_INT8 (0x00000100)
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151 #define MCF_INTC1_IPRL_INT9 (0x00000200)
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152 #define MCF_INTC1_IPRL_INT10 (0x00000400)
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153 #define MCF_INTC1_IPRL_INT11 (0x00000800)
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154 #define MCF_INTC1_IPRL_INT12 (0x00001000)
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155 #define MCF_INTC1_IPRL_INT13 (0x00002000)
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156 #define MCF_INTC1_IPRL_INT14 (0x00004000)
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157 #define MCF_INTC1_IPRL_INT15 (0x00008000)
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158 #define MCF_INTC1_IPRL_INT16 (0x00010000)
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159 #define MCF_INTC1_IPRL_INT17 (0x00020000)
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160 #define MCF_INTC1_IPRL_INT18 (0x00040000)
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161 #define MCF_INTC1_IPRL_INT19 (0x00080000)
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162 #define MCF_INTC1_IPRL_INT20 (0x00100000)
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163 #define MCF_INTC1_IPRL_INT21 (0x00200000)
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164 #define MCF_INTC1_IPRL_INT22 (0x00400000)
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165 #define MCF_INTC1_IPRL_INT23 (0x00800000)
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166 #define MCF_INTC1_IPRL_INT24 (0x01000000)
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167 #define MCF_INTC1_IPRL_INT25 (0x02000000)
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168 #define MCF_INTC1_IPRL_INT26 (0x04000000)
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169 #define MCF_INTC1_IPRL_INT27 (0x08000000)
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170 #define MCF_INTC1_IPRL_INT28 (0x10000000)
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171 #define MCF_INTC1_IPRL_INT29 (0x20000000)
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172 #define MCF_INTC1_IPRL_INT30 (0x40000000)
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173 #define MCF_INTC1_IPRL_INT31 (0x80000000)
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175 /* Bit definitions and macros for MCF_INTC1_IMRH */
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176 #define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
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177 #define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
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178 #define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
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179 #define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
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180 #define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
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181 #define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
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182 #define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
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183 #define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
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184 #define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
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185 #define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
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186 #define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
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187 #define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
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188 #define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
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189 #define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
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190 #define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
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191 #define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
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192 #define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
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193 #define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
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194 #define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
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195 #define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
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196 #define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
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197 #define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
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198 #define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
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199 #define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
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200 #define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
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201 #define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
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202 #define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
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203 #define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
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204 #define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
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205 #define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
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206 #define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
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207 #define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
\r
209 /* Bit definitions and macros for MCF_INTC1_IMRL */
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210 #define MCF_INTC1_IMRL_MASKALL (0x00000001)
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211 #define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
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212 #define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
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213 #define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
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214 #define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
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215 #define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
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216 #define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
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217 #define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
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218 #define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
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219 #define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
\r
220 #define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
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221 #define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
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222 #define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
\r
223 #define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
\r
224 #define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
\r
225 #define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
\r
226 #define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
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227 #define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
\r
228 #define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
\r
229 #define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
\r
230 #define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
\r
231 #define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
\r
232 #define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
\r
233 #define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
\r
234 #define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
\r
235 #define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
\r
236 #define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
\r
237 #define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
\r
238 #define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
\r
239 #define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
\r
240 #define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
\r
241 #define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
\r
243 /* Bit definitions and macros for MCF_INTC1_INTFRCH */
\r
244 #define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
\r
245 #define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
\r
246 #define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
\r
247 #define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
\r
248 #define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
\r
249 #define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
\r
250 #define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
\r
251 #define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
\r
252 #define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
\r
253 #define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
\r
254 #define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
\r
255 #define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
\r
256 #define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
\r
257 #define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
\r
258 #define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
\r
259 #define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
\r
260 #define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
\r
261 #define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
\r
262 #define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
\r
263 #define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
\r
264 #define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
\r
265 #define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
\r
266 #define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
\r
267 #define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
\r
268 #define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
\r
269 #define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
\r
270 #define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
\r
271 #define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
\r
272 #define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
\r
273 #define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
\r
274 #define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
\r
275 #define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
\r
277 /* Bit definitions and macros for MCF_INTC1_INTFRCL */
\r
278 #define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
\r
279 #define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
\r
280 #define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
\r
281 #define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
\r
282 #define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
\r
283 #define MCF_INTC1_INTFRCL_INT6 (0x00000040)
\r
284 #define MCF_INTC1_INTFRCL_INT7 (0x00000080)
\r
285 #define MCF_INTC1_INTFRCL_INT8 (0x00000100)
\r
286 #define MCF_INTC1_INTFRCL_INT9 (0x00000200)
\r
287 #define MCF_INTC1_INTFRCL_INT10 (0x00000400)
\r
288 #define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
\r
289 #define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
\r
290 #define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
\r
291 #define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
\r
292 #define MCF_INTC1_INTFRCL_INT15 (0x00008000)
\r
293 #define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
\r
294 #define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
\r
295 #define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
\r
296 #define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
\r
297 #define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
\r
298 #define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
\r
299 #define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
\r
300 #define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
\r
301 #define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
\r
302 #define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
\r
303 #define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
\r
304 #define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
\r
305 #define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
\r
306 #define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
\r
307 #define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
\r
308 #define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
\r
310 /* Bit definitions and macros for MCF_INTC1_IRLR */
\r
311 #define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
\r
313 /* Bit definitions and macros for MCF_INTC1_IACKLPR */
\r
314 #define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
\r
315 #define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
\r
317 /* Bit definitions and macros for MCF_INTC1_ICRn */
\r
318 #define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
\r
319 #define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
\r
321 /********************************************************************/
\r
323 #endif /* __MCF523X_INTC1_H__ */
\r
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