2 * Copyright (c) 2014, Texas Instruments Incorporated
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3 * All rights reserved.
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5 * Redistribution and use in source and binary forms, with or without
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6 * modification, are permitted provided that the following conditions
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9 * * Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
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12 * * Redistributions in binary form must reproduce the above copyright
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13 * notice, this list of conditions and the following disclaimer in the
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14 * documentation and/or other materials provided with the distribution.
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16 * * Neither the name of Texas Instruments Incorporated nor the names of
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17 * its contributors may be used to endorse or promote products derived
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18 * from this software without specific prior written permission.
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 //*****************************************************************************
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34 // eusci_a_uart.c - Driver for the eusci_a_uart Module.
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36 //*****************************************************************************
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38 //*****************************************************************************
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40 //! \addtogroup eusci_a_uart_api eusci_a_uart
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43 //*****************************************************************************
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45 #include "inc/hw_regaccess.h"
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46 #include "inc/hw_memmap.h"
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48 #ifdef __MSP430_HAS_EUSCI_Ax__
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49 #include "eusci_a_uart.h"
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53 bool EUSCI_A_UART_init(uint16_t baseAddress,
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54 EUSCI_A_UART_initParam *param)
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56 bool retVal = STATUS_SUCCESS;
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58 //Disable the USCI Module
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59 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;
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61 //Clock source select
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62 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3;
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63 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;
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66 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB;
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67 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst;
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69 //UCSPB = 0(1 stop bit) OR 1(2 stop bits)
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70 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB;
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71 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits;
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74 switch(param->parity)
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76 case EUSCI_A_UART_NO_PARITY:
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78 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN;
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80 case EUSCI_A_UART_ODD_PARITY:
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82 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;
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83 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR;
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85 case EUSCI_A_UART_EVEN_PARITY:
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87 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;
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88 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR;
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92 //BaudRate Control Register
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93 HWREG16(baseAddress + OFS_UCAxBRW) = param->clockPrescalar;
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94 //Modulation Control Register
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95 HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8)
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96 + (param->firstModReg <<
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97 4) + param->overSampling);
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99 //Asynchronous mode & 8 bit character select & clear mode
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100 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC +
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105 //Configure UART mode.
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106 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode;
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108 //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK
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109 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM +
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115 void EUSCI_A_UART_transmitData(uint16_t baseAddress,
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116 uint8_t transmitData)
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118 //If interrupts are not used, poll for flags
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119 if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))
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121 //Poll for transmit interrupt flag
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122 while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG))
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128 HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData;
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131 uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress)
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133 //If interrupts are not used, poll for flags
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134 if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE))
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136 //Poll for receive interrupt flag
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137 while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG))
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143 return (HWREG16(baseAddress + OFS_UCAxRXBUF));
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146 void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress,
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151 locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT
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152 | EUSCI_A_UART_TRANSMIT_INTERRUPT
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153 | EUSCI_A_UART_STARTBIT_INTERRUPT
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154 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
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156 HWREG16(baseAddress + OFS_UCAxIE) |= locMask;
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158 locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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159 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
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160 HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask;
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163 void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress,
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168 locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT
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169 | EUSCI_A_UART_TRANSMIT_INTERRUPT
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170 | EUSCI_A_UART_STARTBIT_INTERRUPT
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171 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
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172 HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask;
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174 locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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175 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
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176 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask;
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179 uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress,
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182 return (HWREG16(baseAddress + OFS_UCAxIFG) & mask);
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185 void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress,
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188 //Clear the UART interrupt source.
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189 HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask);
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192 void EUSCI_A_UART_enable(uint16_t baseAddress)
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194 //Reset the UCSWRST bit to enable the USCI Module
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195 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);
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198 void EUSCI_A_UART_disable(uint16_t baseAddress)
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200 //Set the UCSWRST bit to disable the USCI Module
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201 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;
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204 uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress,
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207 return (HWREG16(baseAddress + OFS_UCAxSTATW) & mask);
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210 void EUSCI_A_UART_setDormant(uint16_t baseAddress)
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212 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM;
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215 void EUSCI_A_UART_resetDormant(uint16_t baseAddress)
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217 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM;
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220 void EUSCI_A_UART_transmitAddress(uint16_t baseAddress,
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221 uint8_t transmitAddress)
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224 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR;
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226 //Place next byte to be sent into the transmit buffer
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227 HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress;
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230 void EUSCI_A_UART_transmitBreak(uint16_t baseAddress)
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233 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK;
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235 //If current mode is automatic baud-rate detection
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236 if(EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==
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237 (HWREG16(baseAddress + OFS_UCAxCTLW0) &
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238 EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
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240 HWREG16(baseAddress +
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241 OFS_UCAxTXBUF) = EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
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245 HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;
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248 //If interrupts are not used, poll for flags
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249 if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))
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251 //Poll for transmit interrupt flag
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252 while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG))
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259 uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress)
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261 return (baseAddress + OFS_UCAxRXBUF);
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264 uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress)
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266 return (baseAddress + OFS_UCAxTXBUF);
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269 void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress,
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270 uint16_t deglitchTime)
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272 HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0);
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274 HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime;
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278 //*****************************************************************************
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280 //! Close the doxygen group for eusci_a_uart_api
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283 //*****************************************************************************
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