2 * Copyright (c) 2014, Texas Instruments Incorporated
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3 * All rights reserved.
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5 * Redistribution and use in source and binary forms, with or without
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6 * modification, are permitted provided that the following conditions
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9 * * Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
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12 * * Redistributions in binary form must reproduce the above copyright
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13 * notice, this list of conditions and the following disclaimer in the
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14 * documentation and/or other materials provided with the distribution.
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16 * * Neither the name of Texas Instruments Incorporated nor the names of
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17 * its contributors may be used to endorse or promote products derived
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18 * from this software without specific prior written permission.
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 //*****************************************************************************
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34 // eusci_b_spi.c - Driver for the eusci_b_spi Module.
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36 //*****************************************************************************
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38 //*****************************************************************************
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40 //! \addtogroup eusci_b_spi_api eusci_b_spi
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43 //*****************************************************************************
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45 #include "inc/hw_regaccess.h"
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46 #include "inc/hw_memmap.h"
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48 #ifdef __MSP430_HAS_EUSCI_Bx__
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49 #include "eusci_b_spi.h"
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53 void EUSCI_B_SPI_initMaster(uint16_t baseAddress,
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54 EUSCI_B_SPI_initMasterParam *param)
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56 //Disable the USCI Module
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57 HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;
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59 //Reset OFS_UCBxCTLW0 values
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60 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB +
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61 UCMST + UCMODE_3 + UCSYNC);
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63 //Reset OFS_UCBxCTLW0 values
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64 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3);
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67 HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource;
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69 HWREG16(baseAddress + OFS_UCBxBRW) =
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70 (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);
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73 * Configure as SPI master mode.
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74 * Clock phase select, polarity, msb
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75 * UCMST = Master mode
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76 * UCSYNC = Synchronous mode
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77 * UCMODE_0 = 3-pin SPI
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79 HWREG16(baseAddress + OFS_UCBxCTLW0) |= (
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82 param->clockPolarity +
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89 void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,
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90 uint8_t select4PinFunctionality)
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92 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM;
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93 HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality;
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96 void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,
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97 EUSCI_B_SPI_changeMasterClockParam *param)
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99 //Disable the USCI Module
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100 HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;
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102 HWREG16(baseAddress + OFS_UCBxBRW) =
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103 (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock);
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105 //Reset the UCSWRST bit to enable the USCI Module
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106 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);
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109 void EUSCI_B_SPI_initSlave(uint16_t baseAddress,
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110 EUSCI_B_SPI_initSlaveParam *param)
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112 //Disable USCI Module
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113 HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;
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115 //Reset OFS_UCBxCTLW0 register
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116 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB +
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124 //Clock polarity, phase select, msbFirst, SYNC, Mode0
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125 HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase +
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126 param->clockPolarity +
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133 void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,
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134 uint16_t clockPhase,
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135 uint16_t clockPolarity)
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137 //Disable the USCI Module
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138 HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;
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140 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL);
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142 HWREG16(baseAddress + OFS_UCBxCTLW0) |= (
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147 //Reset the UCSWRST bit to enable the USCI Module
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148 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);
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151 void EUSCI_B_SPI_transmitData(uint16_t baseAddress,
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152 uint8_t transmitData)
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154 HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData;
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157 uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress)
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159 return (HWREG16(baseAddress + OFS_UCBxRXBUF));
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162 void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,
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165 HWREG16(baseAddress + OFS_UCBxIE) |= mask;
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168 void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,
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171 HWREG16(baseAddress + OFS_UCBxIE) &= ~mask;
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174 uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,
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177 return (HWREG16(baseAddress + OFS_UCBxIFG) & mask);
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180 void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,
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183 HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask;
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186 void EUSCI_B_SPI_enable(uint16_t baseAddress)
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188 //Reset the UCSWRST bit to enable the USCI Module
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189 HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST);
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192 void EUSCI_B_SPI_disable(uint16_t baseAddress)
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194 //Set the UCSWRST bit to disable the USCI Module
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195 HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST;
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198 uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress)
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200 return (baseAddress + OFS_UCBxRXBUF);
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203 uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress)
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205 return (baseAddress + OFS_UCBxTXBUF);
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208 uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress)
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210 //Return the bus busy status.
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211 return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY);
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215 //*****************************************************************************
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217 //! Close the doxygen group for eusci_b_spi_api
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220 //*****************************************************************************
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