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   1 /*******************************************************************************\r
   2  *\r
   3  * HAL_PMM.h\r
   4  * Power Management Module Library for MSP430F5xx/6xx family\r
   5  *\r
   6  *\r
   7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
   8  *\r
   9  *\r
  10  *  Redistribution and use in source and binary forms, with or without\r
  11  *  modification, are permitted provided that the following conditions\r
  12  *  are met:\r
  13  *\r
  14  *    Redistributions of source code must retain the above copyright\r
  15  *    notice, this list of conditions and the following disclaimer.\r
  16  *\r
  17  *    Redistributions in binary form must reproduce the above copyright\r
  18  *    notice, this list of conditions and the following disclaimer in the\r
  19  *    documentation and/or other materials provided with the\r
  20  *    distribution.\r
  21  *\r
  22  *    Neither the name of Texas Instruments Incorporated nor the names of\r
  23  *    its contributors may be used to endorse or promote products derived\r
  24  *    from this software without specific prior written permission.\r
  25  *\r
  26  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
  27  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
  28  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  29  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
  30  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
  31  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  32  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  33  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  34  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
  35  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
  36  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  37  *\r
  38  ******************************************************************************/\r
  39 \r
  40 #ifndef HAL_PMM_H\r
  41 #define HAL_PMM_H\r
  42 \r
  43 #include <stdint.h>\r
  44 #include "HAL_MACROS.h"\r
  45 \r
  46 /*******************************************************************************\r
  47  * Macros\r
  48  ******************************************************************************/\r
  49 #define ENABLE_SVSL()        st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00; )\r
  50 #define DISABLE_SVSL()       st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00; )\r
  51 #define ENABLE_SVML()        st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00; )\r
  52 #define DISABLE_SVML()       st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00; )\r
  53 #define ENABLE_SVSH()        st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00; )\r
  54 #define DISABLE_SVSH()       st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00; )\r
  55 #define ENABLE_SVMH()        st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00; )\r
  56 #define DISABLE_SVMH()       st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00; )\r
  57 #define ENABLE_SVSL_SVML()   st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00; )\r
  58 #define DISABLE_SVSL_SVML()  st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00; )\r
  59 #define ENABLE_SVSH_SVMH()   st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00; )\r
  60 #define DISABLE_SVSH_SVMH()  st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00; )\r
  61 \r
  62 #define ENABLE_SVSL_RESET()       st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00; )\r
  63 #define DISABLE_SVSL_RESET()      st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00; )\r
  64 #define ENABLE_SVML_INTERRUPT()   st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00; )\r
  65 #define DISABLE_SVML_INTERRUPT()  st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00; )\r
  66 #define ENABLE_SVSH_RESET()       st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00; )\r
  67 #define DISABLE_SVSH_RESET()      st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00; )\r
  68 #define ENABLE_SVMH_INTERRUPT()   st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00; )\r
  69 #define DISABLE_SVMH_INTERRUPT()  st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00; )\r
  70 #define CLEAR_PMM_IFGS()          st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00; )\r
  71 \r
  72 // These settings use SVSH/LACE = 0\r
  73 #define SVSL_ENABLED_IN_LPM_FAST_WAKE()  st( \\r
  74         PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP + SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00; )\r
  75 #define SVSL_ENABLED_IN_LPM_SLOW_WAKE()  st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= \\r
  76                                                 ~(SVSLFP + SVSMLACE); PMMCTL0_H = 0x00; )\r
  77 \r
  78 #define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= \\r
  79                                                 ~(SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )\r
  80 #define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= \\r
  81                                                 ~(SVSLFP + SVSMLACE + SVSLMD); PMMCTL0_H = 0x00; )\r
  82 \r
  83 #define SVSH_ENABLED_IN_LPM_NORM_PERF()  st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= \\r
  84                                                 ~(SVSMHACE + SVSHFP); PMMCTL0_H = 0x00; )\r
  85 #define SVSH_ENABLED_IN_LPM_FULL_PERF()  st( \\r
  86         PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD + SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00; )\r
  87 \r
  88 #define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= \\r
  89                                                 ~(SVSMHACE + SVSHFP + SVSHMD); PMMCTL0_H = 0x00; )\r
  90 #define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= \\r
  91                                                 ~(SVSMHACE + SVSHMD); PMMCTL0_H = 0x00; )\r
  92 \r
  93 // These setting use SVSH/LACE = 1\r
  94 #define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= \\r
  95                                                  (SVSLFP + SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )\r
  96 #define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= \\r
  97                                                  (SVSHMD + SVSHFP + SVSMHACE); PMMCTL0_H = 0x00; )\r
  98 \r
  99 /*******************************************************************************\r
 100  * Defines\r
 101  ******************************************************************************/\r
 102 #define PMM_STATUS_OK     0\r
 103 #define PMM_STATUS_ERROR  1\r
 104 \r
 105 /*******************************************************************************\r
 106  * \brief   Set Vcore to expected level\r
 107  *\r
 108  * \param level     Level to which Vcore needs to be increased/decreased\r
 109  * \return status   Success/failure\r
 110  ******************************************************************************/\r
 111 extern uint16_t SetVCore(uint8_t level);\r
 112 \r
 113 #endif /* HAL_PMM_H */\r