1 ############################################################################
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2 ## This system.ucf file is generated by Base System Builder based on the
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3 ## settings in the selected Xilinx Board Definition file. Please add other
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4 ## user constraints to this file based on customer design specifications.
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5 ############################################################################
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7 Net sys_clk_pin LOC=AE14;
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8 Net sys_clk_pin IOSTANDARD = LVCMOS33;
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9 Net sys_rst_pin LOC=D6;
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10 Net sys_rst_pin PULLUP;
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11 ## System level constraints
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12 Net sys_clk_pin TNM_NET = sys_clk_pin;
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13 TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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14 Net sys_rst_pin TIG;
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16 ## FPGA pin constraints
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17 Net fpga_0_RS232_Uart_RX_pin LOC=W2;
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18 Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
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19 Net fpga_0_RS232_Uart_TX_pin LOC=W1;
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20 Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
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21 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
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22 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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23 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
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24 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
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25 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
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26 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
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27 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
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28 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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29 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
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30 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
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31 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
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32 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
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33 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
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34 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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35 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
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36 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
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37 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
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38 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
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39 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
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40 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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41 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
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42 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
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43 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
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44 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
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45 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
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46 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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47 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
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48 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
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49 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
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50 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
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51 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
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52 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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53 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
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54 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
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55 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
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56 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
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57 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
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58 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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59 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
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60 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
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61 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
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62 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
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63 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
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64 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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65 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
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66 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
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67 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
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68 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
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69 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
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70 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
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71 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
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72 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
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73 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
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74 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;
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projects / freertos / blob