2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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98 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
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101 /* Scheduler includes. */
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102 #include "FreeRTOS.h"
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106 /* Demo application includes. */
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107 #include "serial.h"
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109 /* Microblaze driver includes. */
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110 #include "xuartlite_l.h"
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111 #include "xintc_l.h"
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113 /*-----------------------------------------------------------*/
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115 /* Queues used to hold received characters, and characters waiting to be
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117 static QueueHandle_t xRxedChars;
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118 static QueueHandle_t xCharsForTx;
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120 /*-----------------------------------------------------------*/
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122 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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124 unsigned long ulControlReg, ulMask;
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126 /* NOTE: The baud rate used by this driver is determined by the hardware
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127 parameterization of the UART Lite peripheral, and the baud value passed to
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128 this function has no effect. */
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130 /* Create the queues used to hold Rx and Tx characters. */
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131 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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132 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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134 if( ( xRxedChars ) && ( xCharsForTx ) )
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136 /* Disable the interrupt. */
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137 XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
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139 /* Flush the fifos. */
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140 ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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141 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
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143 /* Enable the interrupt again. The interrupt controller has not yet been
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144 initialised so there is no chance of receiving an interrupt until the
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145 scheduler has been started. */
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146 XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
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148 /* Enable the interrupt in the interrupt controller while maintaining
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149 all the other bit settings. */
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150 ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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151 ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
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152 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
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153 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
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156 return ( xComPortHandle ) 0;
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158 /*-----------------------------------------------------------*/
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160 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
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162 /* The port handle is not required as this driver only supports one UART. */
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165 /* Get the next character from the buffer. Return false if no characters
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166 are available, or arrive before xBlockTime expires. */
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167 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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176 /*-----------------------------------------------------------*/
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178 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
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180 portBASE_TYPE xReturn = pdTRUE;
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182 portENTER_CRITICAL();
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184 /* If the UART FIFO is full we can block posting the new data on the
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186 if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
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188 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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193 /* Otherwise, if there is data already in the queue we should add the
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194 new data to the back of the queue to ensure the sequencing is
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196 else if( uxQueueMessagesWaiting( xCharsForTx ) )
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198 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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203 /* If the UART FIFO is not full and there is no data already in the
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204 queue we can write directly to the FIFO without disrupting the
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208 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
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211 portEXIT_CRITICAL();
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215 /*-----------------------------------------------------------*/
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217 void vSerialClose( xComPortHandle xPort )
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219 /* Not supported as not required by the demo application. */
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222 /*-----------------------------------------------------------*/
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224 void vSerialISR( void *pvBaseAddress )
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226 unsigned long ulISRStatus;
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227 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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230 /* Determine the cause of the interrupt. */
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231 ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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233 if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
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235 /* A character is available - place it in the queue of received
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236 characters. This might wake a task that was blocked waiting for
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238 cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
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239 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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242 if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
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244 /* There is space in the FIFO - if there are any characters queue for
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245 transmission they can be send to the UART now. This might unblock a
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246 task that was waiting for space to become available on the Tx queue. */
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247 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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249 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
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253 /* If we woke any tasks we may require a context switch. */
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254 if( xHigherPriorityTaskWoken )
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256 portYIELD_FROM_ISR();
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