1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
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31 ******************************************************************************/
32 /*****************************************************************************/
36 * If ECC is not enabled, this driver exists only to allow the tools to
37 * create a memory test application and to populate xparameters.h with memory
38 * range constants. In this case there is no source code.
40 * If ECC is enabled, this file contains the software API definition of the
41 * Xilinx BRAM Interface Controller (XBram) device driver.
43 * The Xilinx BRAM controller is a soft IP core designed for Xilinx
44 * FPGAs and contains the following general features:
45 * - LMB v2.0 bus interfaces with byte enable support
46 * - Used in conjunction with bram_block peripheral to provide fast BRAM
47 * memory solution for MicroBlaze ILMB and DLMB ports
48 * - Supports byte, half-word, and word transfers
49 * - Supports optional BRAM error correction and detection.
51 * The driver provides interrupt management functions. Implementation of
52 * interrupt handlers is left to the user. Refer to the provided interrupt
53 * example in the examples directory for details.
55 * This driver is intended to be RTOS and processor independent. Any needs for
56 * dynamic memory management, threads or thread mutual exclusion, virtual
57 * memory, or cache control must be satisfied by the layer above this driver.
59 * <b>Initialization & Configuration</b>
61 * The XBram_Config structure is used by the driver to configure
62 * itself. This configuration structure is typically created by the tool-chain
63 * based on HW build properties.
65 * To support multiple runtime loading and initialization strategies employed
66 * by various operating systems, the driver instance can be initialized as
69 * - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
70 * Uses a configuration structure provided by the caller. If running in a
71 * system with address translation, the provided virtual memory base address
72 * replaces the physical address present in the configuration structure.
76 * This API utilizes 32 bit I/O to the BRAM registers. With less
77 * than 32 bits, the unused bits from registers are read as zero and written as
81 * MODIFICATION HISTORY:
83 * Ver Who Date Changes
84 * ----- ---- -------- -----------------------------------------------
85 * 3.00a sa 05/11/10 Added ECC support
86 * 3.01a sa 01/13/12 Changed Selftest API from
87 * XBram_SelfTest(XBram *InstancePtr) to
88 * XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
89 * fixed a problem with interrupt generation for CR 639274
90 * Modified Selftest example to return XST_SUCCESS when
91 * ECC is not enabled and return XST_FAILURE when ECC is
92 * enabled and Control Base Address is zero (CR 636581)
93 * Modified Selftest to use correct CorrectableCounterBits
95 * Updated to check CorrectableFailingDataRegs in the case
97 * Added CorrectableFailingDataRegs and
98 * UncorrectableFailingDataRegs to the config structure to
99 * distinguish between AXI BRAM and LMB BRAM.
100 * These registers are not present in the current version of
101 * the AXI BRAM Controller.
102 * 3.02a sa 04/16/12 Added test of byte and halfword read-modify-write
103 * 3.02a sa 04/16/12 Modified driver tcl to sort the address parameters
104 * to support both xps and vivado designs.
105 * 3.02a adk 24/4/13 Modified the tcl file to avoid warnings
106 * when ecc is disabled cr:705002.
107 * 3.03a bss 05/22/13 Added Xil_DCacheFlushRange in xbram_selftest.c to
108 * flush the Cache after writing to BRAM in InjectErrors
110 * 4.0 adk 19/12/13 Updated as per the New Tcl API's
112 *****************************************************************************/
113 #ifndef XBRAM_H /* prevent circular inclusions */
114 #define XBRAM_H /* by using protection macros */
120 /***************************** Include Files ********************************/
122 #include "xil_types.h"
123 #include "xil_assert.h"
125 #include "xbram_hw.h"
127 /************************** Constant Definitions ****************************/
130 /**************************** Type Definitions ******************************/
133 * This typedef contains configuration information for the device.
136 u16 DeviceId; /**< Unique ID of device */
137 u32 DataWidth; /**< BRAM data width */
138 int EccPresent; /**< Is ECC supported in H/W */
139 int FaultInjectionPresent; /**< Is Fault Injection
140 * supported in H/W */
141 int CorrectableFailingRegisters; /**< Is Correctable Failing Registers
142 * supported in H/W */
143 int CorrectableFailingDataRegs; /**< Is Correctable Failing Data
144 * Registers supported in H/W */
145 int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
146 * Registers supported in H/W */
147 int UncorrectableFailingDataRegs; /**< Is Un-correctable Failing Data
148 * Registers supported in H/W */
149 int EccStatusInterruptPresent; /**< Are ECC status and interrupts
150 * supported in H/W */
151 int CorrectableCounterBits; /**< Number of bits in the
152 * Correctable Error Counter */
153 int EccOnOffRegister; /**< Is ECC on/off register supported
155 int EccOnOffResetValue; /**< Reset value of the ECC on/off
157 int WriteAccess; /**< Is write access enabled in
159 u32 MemBaseAddress; /**< Device memory base address */
160 u32 MemHighAddress; /**< Device memory high address */
161 u32 CtrlBaseAddress; /**< Device register base address.*/
162 u32 CtrlHighAddress; /**< Device register base address.*/
166 * The XBram driver instance data. The user is required to
167 * allocate a variable of this type for every BRAM device in the
168 * system. A pointer to a variable of this type is then passed to the driver
172 XBram_Config Config; /* BRAM config structure */
173 u32 IsReady; /* Device is initialized and ready */
176 /***************** Macros (Inline Functions) Definitions ********************/
179 /************************** Function Prototypes *****************************/
182 * Functions in xbram_sinit.c
184 XBram_Config *XBram_LookupConfig(u16 DeviceId);
187 * Functions implemented in xbram.c
189 int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
193 * Functions implemented in xbram_selftest.c
195 int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
198 * Functions implemented in xbram_intr.c
200 void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
201 void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
202 void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
203 u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
204 u32 XBram_InterruptGetStatus(XBram *InstancePtr);
210 #endif /* end of protection macro */