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31 ******************************************************************************/
32 /*****************************************************************************/
36 * Implements GPIO interrupt processing functions for the XGpio driver.
37 * See xgpio.h for more information about the driver.
39 * The functions in this file require the hardware device to be built with
40 * interrupt capabilities. The functions will assert if called using hardware
41 * that does not have interrupt capabilities.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -----------------------------------------------
48 * 2.00a jhl 11/26/03 Initial release
49 * 2.11a mta 03/21/07 Updated to new coding style
50 * 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
51 * to properly update the Interrupt Enable register
52 * 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
53 * XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
58 *****************************************************************************/
60 /***************************** Include Files ********************************/
64 /************************** Constant Definitions ****************************/
66 /**************************** Type Definitions ******************************/
68 /***************** Macros (Inline Functions) Definitions ********************/
70 /************************** Variable Definitions ****************************/
72 /************************** Function Prototypes *****************************/
75 /****************************************************************************/
77 * Enable the interrupt output signal. Interrupts enabled through
78 * XGpio_InterruptEnable() will not be passed through until the global enable
79 * bit is set by this function. This function is designed to allow all
80 * interrupts (both channels) to be enabled easily for exiting a critical
81 * section. This function will assert if the hardware device has not been
82 * built with interrupt capabilities.
84 * @param InstancePtr is the GPIO instance to operate on.
90 *****************************************************************************/
91 void XGpio_InterruptGlobalEnable(XGpio * InstancePtr)
93 Xil_AssertVoid(InstancePtr != NULL);
94 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
95 Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
97 XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
98 XGPIO_GIE_GINTR_ENABLE_MASK);
102 /****************************************************************************/
104 * Disable the interrupt output signal. Interrupts enabled through
105 * XGpio_InterruptEnable() will no longer be passed through until the global
106 * enable bit is set by XGpio_InterruptGlobalEnable(). This function is
107 * designed to allow all interrupts (both channels) to be disabled easily for
108 * entering a critical section. This function will assert if the hardware
109 * device has not been built with interrupt capabilities.
111 * @param InstancePtr is the GPIO instance to operate on.
117 *****************************************************************************/
118 void XGpio_InterruptGlobalDisable(XGpio * InstancePtr)
120 Xil_AssertVoid(InstancePtr != NULL);
121 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
122 Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
125 XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
130 /****************************************************************************/
132 * Enable interrupts. The global interrupt must also be enabled by calling
133 * XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
134 * assert if the hardware device has not been built with interrupt capabilities.
136 * @param InstancePtr is the GPIO instance to operate on.
137 * @param Mask is the mask to enable. Bit positions of 1 are enabled.
138 * This mask is formed by OR'ing bits from XGPIO_IR* bits which
139 * are contained in xgpio_l.h.
145 *****************************************************************************/
146 void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask)
150 Xil_AssertVoid(InstancePtr != NULL);
151 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
152 Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
155 * Read the interrupt enable register and only enable the specified
156 * interrupts without disabling or enabling any others.
159 Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
160 XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
166 /****************************************************************************/
168 * Disable interrupts. This function allows specific interrupts for each
169 * channel to be disabled. This function will assert if the hardware device
170 * has not been built with interrupt capabilities.
172 * @param InstancePtr is the GPIO instance to operate on.
173 * @param Mask is the mask to disable. Bits set to 1 are disabled. This
174 * mask is formed by OR'ing bits from XGPIO_IR* bits which are
175 * contained in xgpio_l.h.
181 *****************************************************************************/
182 void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask)
186 Xil_AssertVoid(InstancePtr != NULL);
187 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
188 Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
191 * Read the interrupt enable register and only disable the specified
192 * interrupts without enabling or disabling any others.
194 Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
195 XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
200 /****************************************************************************/
202 * Clear pending interrupts with the provided mask. This function should be
203 * called after the software has serviced the interrupts that are pending.
204 * This function will assert if the hardware device has not been built with
205 * interrupt capabilities.
207 * @param InstancePtr is the GPIO instance to operate on.
208 * @param Mask is the mask to clear pending interrupts for. Bit positions
209 * of 1 are cleared. This mask is formed by OR'ing bits from
210 * XGPIO_IR* bits which are contained in xgpio_l.h.
216 *****************************************************************************/
217 void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
221 Xil_AssertVoid(InstancePtr != NULL);
222 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
223 Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
226 * Read the interrupt status register and only clear the interrupts
227 * that are specified without affecting any others. Since the register
228 * is a toggle on write, make sure any bits to be written are already
231 Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
232 XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
239 /****************************************************************************/
241 * Returns the interrupt enable mask. This function will assert if the
242 * hardware device has not been built with interrupt capabilities.
244 * @param InstancePtr is the GPIO instance to operate on.
246 * @return A mask of bits made from XGPIO_IR* bits which are contained in
253 *****************************************************************************/
254 u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
256 Xil_AssertNonvoid(InstancePtr != NULL);
257 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
258 Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
260 return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
264 /****************************************************************************/
266 * Returns the status of interrupt signals. Any bit in the mask set to 1
267 * indicates that the channel associated with the bit has asserted an interrupt
268 * condition. This function will assert if the hardware device has not been
269 * built with interrupt capabilities.
271 * @param InstancePtr is the GPIO instance to operate on.
273 * @return A pointer to a mask of bits made from XGPIO_IR* bits which are
274 * contained in xgpio_l.h.
278 * The interrupt status indicates the status of the device irregardless if
279 * the interrupts from the devices have been enabled or not through
280 * XGpio_InterruptEnable().
282 *****************************************************************************/
283 u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
285 Xil_AssertNonvoid(InstancePtr != NULL);
286 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
287 Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
290 return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);