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31 ******************************************************************************/
32 /*****************************************************************************/
37 * The Xilinx interrupt controller driver component. This component supports the
38 * Xilinx interrupt controller.
40 * The interrupt controller driver uses the idea of priority for the various
41 * handlers. Priority is an integer within the range of 0 and 31 inclusive with
42 * 0 being the highest priority interrupt source.
44 * The Xilinx interrupt controller supports the following features:
46 * - specific individual interrupt enabling/disabling
47 * - specific individual interrupt acknowledging
48 * - attaching specific callback function to handle interrupt source
49 * - master enable/disable
50 * - single callback per interrupt or all pending interrupts handled for
51 * each interrupt of the processor
53 * The acknowledgement of the interrupt within the interrupt controller is
54 * selectable, either prior to the device's handler being called or after
55 * the handler is called. This is necessary to support interrupt signal inputs
56 * which are either edge or level signals. Edge driven interrupt signals
57 * require that the interrupt is acknowledged prior to the interrupt being
58 * serviced in order to prevent the loss of interrupts which are occurring
59 * extremely close together. A level driven interrupt input signal requires
60 * the interrupt to acknowledged after servicing the interrupt to ensure that
61 * the interrupt only generates a single interrupt condition.
63 * Details about connecting the interrupt handler of the driver are contained
64 * in the source file specific to interrupt processing, xintc_intr.c.
66 * This driver is intended to be RTOS and processor independent. It works with
67 * physical addresses only. Any needs for dynamic memory management, threads
68 * or thread mutual exclusion, virtual memory, or cache control must be
69 * satisfied by the layer above this driver.
71 * <b>Interrupt Vector Tables</b>
73 * The interrupt vector table for each interrupt controller device is declared
74 * statically in xintc_g.c within the configuration data for each instance.
75 * The device ID of the interrupt controller device is used by the driver as a
76 * direct index into the configuration data table - to retrieve the vector table
77 * for an instance of the interrupt controller. The user should populate the
78 * vector table with handlers and callbacks at run-time using the XIntc_Connect()
79 * and XIntc_Disconnect() functions.
81 * Each vector table entry corresponds to a device that can generate an
82 * interrupt. Each entry contains an interrupt handler function and an argument
83 * to be passed to the handler when an interrupt occurs. The tools default this
84 * argument to the base address of the interrupting device. Note that the
85 * device driver interrupt handlers given in this file do not take a base
86 * address as an argument, but instead take a pointer to the driver instance.
87 * This means that although the table is created statically, the user must still
88 * use XIntc_Connect() when the interrupt handler takes an argument other than
89 * the base address. This is only to say that the existence of the static vector
90 * tables should not mislead the user into thinking they no longer need to
91 * register/connect interrupt handlers with this driver.
94 * MODIFICATION HISTORY:
96 * Ver Who Date Changes
97 * ----- ---- -------- -------------------------------------------------------
98 * 1.00a ecm 08/16/01 First release
99 * 1.00a rpm 01/09/02 Removed the AckLocation argument from XIntc_Connect().
100 * This information is now internal in xintc_g.c.
101 * 1.00b jhl 02/13/02 Repartitioned the driver for smaller files
102 * 1.00b jhl 04/24/02 Made LookupConfig function global and relocated config
104 * 1.00c rpm 10/17/03 New release. Support the static vector table created
105 * in the xintc_g.c configuration table. Moved vector
106 * table and options out of instance structure and into
107 * the configuration table.
108 * 1.10c mta 03/21/07 Updated to new coding style
109 * 1.11a sv 11/21/07 Updated driver to support access through a DCR bridge
110 * 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed from
111 * all the macro names/definitions.
112 * 2.01a sdm 04/27/10 Updated the tcl so that the defintions are generated in
113 * the xparameters.h to know whether the optional registers
114 * SIE, CIE and IVR are enabled in the HW - Refer CR 555392.
115 * This driver doesnot make use of these definitions and does
116 * not use the optional registers.
117 * 2.03a hvm 05/24/11 Updated the tcl to generate vector Ids for external
118 * interrupts. CR565336
119 * 2.04a bss 01/13/12 Added XIntc_ConnectFastHandler API for Fast Interrupt
120 * and XIntc_SetNormalIntrMode for setting to normal
122 * 2.04a asa 03/19/12 Changed the XIntc_Config struct. The order of entries
123 * declared in the structure now matches with the
124 * XIntc_ConfigTable generated by the driver tcl.
125 * 2.05a bss 08/16/12 Updated to support relocatable vectors in Microblaze,
126 * added IntVectorAddr to XIntc_Config for this.
127 * Added XIntc_RegisterFastHandler API to register fast
128 * interrupt handlers using base address.
129 * 2.06a bss 01/28/13 To support Cascade mode:
130 * Added XIN_INTC_NOCASCADE,XIN_INTC_PRIMARY,
131 * XIN_INTC_SECONDARY,XIN_INTC_LAST and
132 * XIN_CONTROLLER_MAX_INTRS macros
133 * Added NumberofIntrs and IntcType fields in XIntc_Config
135 * Modified XIntc_Initialize,XIntc_Start,XIntc_Connect
136 * XIntc_Disconnect,XIntc_Enable,XIntc_Disable,
137 * XIntc_Acknowledge,XIntc_ConnectFastHandler and
138 * XIntc_SetNormalIntrMode APIs.Added XIntc_InitializeSlaves
140 * Modified XIntc_DeviceInterruptHandler,
141 * XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
142 * XIntc_RegisterFastHandler APIs.Added XIntc_CascadeHandler
144 * Modified XIntc_SetOptions API in xintc_options.c.
145 * Modified XIntc_SimulateIntr API in xintc_selftest.c.
146 * Modified driver tcl:
147 * to check for Cascade mode and generate XPAR_INTC_TYPE
148 * for each controller.
149 * Generate XPAR_INTC_MAX_NUM_INTR_INPUTS by adding all
150 * interrupt sources of all Controllers in Cascade mode.
151 * 2.07a bss 10/18/13 To support Nested interrupts:
152 * Modified XIntc_DeviceInterruptHandler API.
153 * Added XIN_ILR_OFFSET macro in xintc_l.h.
154 * Modified driver tcl to generate HAS_ILR parameter in
156 * 3.0 bss 01/28/13 Modified xintc.c to initialize IVAR register with
157 * XPAR_MICROBLAZE_BASE_VECTORS + 0x10 to fix
159 * Modified driver tcl to generate XPAR_AXI_INTC_0_TYPE
160 * correctly(CR#764865).
163 * For Cascade mode, Interrupt IDs are generated in xparameters.h
166 * Master/Primary INTC
168 * | |-0 Secondary INTC
170 * | |-. | |-32 Last INTC
172 * |______|<-31------| |-. | |-64
174 * |______|<-63-------| |-.
178 * All driver functions has to be called using DeviceId/
179 * InstancePtr/BaseAddress of Primary/Master Controller and
180 * Interrupts IDs generated in xparameters.h only.
181 * Driver functions takes care of Slave Controllers based on
182 * Interrupt ID passed. User must not use Interrupt source/ID
183 * 31 of Primary and Secondary controllers to call driver
186 * For nested interrupts, XIntc_DeviceInterruptHandler saves
187 * microblaze r14 register on entry and restores on exit. This is
188 * required since compiler does not support nesting. It enables
189 * Microblaze interrupts after blocking further interrupts from
190 * the current interrupt number and interrupts below current
191 * interrupt proirity by writing to Interrupt Level Register of
192 * INTC on entry. On exit, it disables microblaze interrupts and
193 * restores ILR register default value(0xFFFFFFFF)back. It is
194 * recommended to increase STACK_SIZE in linker script for nested
196 * 3.0 adk 12/10/13 Updated as per the New Tcl API's
197 * 3.0 adk 17/02/14 Fixed the CR:771287 Changes are made in the intc
199 * 3.1 adk 8/4/14 Fixed the CR:783248 Changes are made in
201 * 3.2 bss 4/8/14 Fixed driver tcl to handle external interrupt pins
202 * correctly (CR#799609).
206 ******************************************************************************/
208 #ifndef XINTC_H /* prevent circular inclusions */
209 #define XINTC_H /* by using protection macros */
216 /***************************** Include Files *********************************/
218 #include "xil_types.h"
219 #include "xil_assert.h"
220 #include "xparameters.h"
224 /************************** Constant Definitions *****************************/
227 * @name Configuration options
228 * These options are used in XIntc_SetOptions() to configure the device.
233 * XIN_SVC_SGL_ISR_OPTION Service the highest priority pending interrupt
235 * XIN_SVC_ALL_ISRS_OPTION Service all of the pending interrupts and then
239 #define XIN_SVC_SGL_ISR_OPTION 1UL
240 #define XIN_SVC_ALL_ISRS_OPTION 2UL
245 * One of these values is passed to XIntc_Start() to start the device.
248 /** Simulation only mode, no hardware interrupts recognized */
249 #define XIN_SIMULATION_MODE 0
250 /** Real mode, no simulation allowed, hardware interrupts recognized */
251 #define XIN_REAL_MODE 1
255 * @name Masks to specify Interrupt Controller Mode
258 #define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
259 #define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
260 #define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
261 #define XIN_INTC_LAST 3 /* Last Slave Controller */
266 * @name Mask to specify maximum number of interrupt sources per controller
269 #define XIN_CONTROLLER_MAX_INTRS 32 /* Each Controller has 32
273 /**************************** Type Definitions *******************************/
276 * This typedef contains configuration information for the device.
279 u16 DeviceId; /**< Unique ID of device */
280 u32 BaseAddress; /**< Register base address */
281 u32 AckBeforeService; /**< Ack location per interrupt */
282 int FastIntr; /**< Fast Interrupt enabled */
283 u32 IntVectorAddr; /**< Interrupt Vector Address */
284 int NumberofIntrs; /**< Number of Interrupt sources */
285 u32 Options; /**< Device options */
286 int IntcType; /**< Intc type 0 - No Cascade Mode
288 2 - secondary instance
291 /** Static vector table of interrupt handlers */
292 #if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
293 XIntc_VectorTableEntry HandlerTable[XIN_CONTROLLER_MAX_INTRS];
295 XIntc_VectorTableEntry HandlerTable[XPAR_INTC_MAX_NUM_INTR_INPUTS];
301 * The XIntc driver instance data. The user is required to allocate a
302 * variable of this type for every intc device in the system. A pointer
303 * to a variable of this type is then passed to the driver API functions.
306 u32 BaseAddress; /**< Base address of registers */
307 u32 IsReady; /**< Device is initialized and ready */
308 u32 IsStarted; /**< Device has been started */
309 u32 UnhandledInterrupts; /**< Intc Statistics */
310 XIntc_Config *CfgPtr; /**< Pointer to instance config entry */
314 /***************** Macros (Inline Functions) Definitions *********************/
316 /************************** Function Prototypes ******************************/
319 * Required functions in xintc.c
321 int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId);
323 int XIntc_Start(XIntc * InstancePtr, u8 Mode);
324 void XIntc_Stop(XIntc * InstancePtr);
326 int XIntc_Connect(XIntc * InstancePtr, u8 Id,
327 XInterruptHandler Handler, void *CallBackRef);
328 void XIntc_Disconnect(XIntc * InstancePtr, u8 Id);
330 void XIntc_Enable(XIntc * InstancePtr, u8 Id);
331 void XIntc_Disable(XIntc * InstancePtr, u8 Id);
333 void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id);
335 XIntc_Config *XIntc_LookupConfig(u16 DeviceId);
337 int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
338 XFastInterruptHandler Handler);
339 void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id);
342 * Interrupt functions in xintr_intr.c
344 void XIntc_VoidInterruptHandler(void);
345 void XIntc_InterruptHandler(XIntc * InstancePtr);
348 * Options functions in xintc_options.c
350 int XIntc_SetOptions(XIntc * InstancePtr, u32 Options);
351 u32 XIntc_GetOptions(XIntc * InstancePtr);
354 * Self-test functions in xintc_selftest.c
356 int XIntc_SelfTest(XIntc * InstancePtr);
357 int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id);
363 #endif /* end of protection macro */