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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xtmrctr_l.h
  36 *
  37 * This header file contains identifiers and low-level driver functions (or
  38 * macros) that can be used to access the device.  The user should refer to the
  39 * hardware device specification for more details of the device operation.
  40 * High-level driver functions are defined in xtmrctr.h.
  41 *
  42 * <pre>
  43 * MODIFICATION HISTORY:
  44 *
  45 * Ver   Who  Date     Changes
  46 * ----- ---- -------- -----------------------------------------------
  47 * 1.00b jhl  04/24/02 First release
  48 * 1.10b mta  03/21/07 Updated to new coding style
  49 * 2.00a ktn  10/30/09 Updated to use HAL API's. _m is removed from all the macro
  50 *                     definitions.
  51 * 2.01a ktn  07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg
  52 *                     for naming consistency (CR 559142).
  53 * 2.04a sdm  07/12/11 Added the CASC mode bit in the TCSRO register for the
  54 *                     cascade mode operation.
  55 *                     The cascade mode of operation is present in the latest
  56 *                     versions of the axi_timer IP. Please check the HW
  57 *                     Datasheet to see whether this feature is present in the
  58 *                     version of the IP that you are using.
  59 * </pre>
  60 *
  61 ******************************************************************************/
  62
  63 #ifndef XTMRCTR_L_H             /* prevent circular inclusions */
  64 #define XTMRCTR_L_H             /* by using protection macros */
  65
  66 #ifdef __cplusplus
  67 extern "C" {
  68 #endif
  69
  70 /***************************** Include Files *********************************/
  71
  72 #include "xil_types.h"
  73 #include "xil_io.h"
  74
  75 /************************** Constant Definitions *****************************/
  76
  77 /**
  78  * Defines the number of timer counters within a single hardware device. This
  79  * number is not currently parameterized in the hardware but may be in the
  80  * future.
  81  */
  82 #define XTC_DEVICE_TIMER_COUNT          2
  83
  84 /* Each timer counter consumes 16 bytes of address space */
  85
  86 #define XTC_TIMER_COUNTER_OFFSET        16
  87
  88 /** @name Register Offset Definitions
  89  * Register offsets within a timer counter, there are multiple
  90  * timer counters within a single device
  91  * @{
  92  */
  93
  94 #define XTC_TCSR_OFFSET         0       /**< Control/Status register */
  95 #define XTC_TLR_OFFSET          4       /**< Load register */
  96 #define XTC_TCR_OFFSET          8       /**< Timer counter register */
  97
  98 /* @} */
  99
 100 /** @name Control Status Register Bit Definitions
 101  * Control Status Register bit masks
 102  * Used to configure the timer counter device.
 103  * @{
 104  */
 105
 106 #define XTC_CSR_CASC_MASK               0x00000800 /**< Cascade Mode */
 107 #define XTC_CSR_ENABLE_ALL_MASK         0x00000400 /**< Enables all timer
 108                                                         counters */
 109 #define XTC_CSR_ENABLE_PWM_MASK         0x00000200 /**< Enables the Pulse Width
 110                                                         Modulation */
 111 #define XTC_CSR_INT_OCCURED_MASK        0x00000100 /**< If bit is set, an
 112                                                         interrupt has occured.
 113                                                         If set and '1' is
 114                                                         written to this bit
 115                                                         position, bit is
 116                                                         cleared. */
 117 #define XTC_CSR_ENABLE_TMR_MASK         0x00000080 /**< Enables only the
 118                                                         specific timer */
 119 #define XTC_CSR_ENABLE_INT_MASK         0x00000040 /**< Enables the interrupt
 120                                                         output. */
 121 #define XTC_CSR_LOAD_MASK               0x00000020 /**< Loads the timer using
 122                                                         the load value provided
 123                                                         earlier in the Load
 124                                                         Register,
 125                                                         XTC_TLR_OFFSET. */
 126 #define XTC_CSR_AUTO_RELOAD_MASK        0x00000010 /**< In compare mode,
 127                                                         configures
 128                                                         the timer counter to
 129                                                         reload  from the
 130                                                         Load Register. The
 131                                                         default  mode
 132                                                         causes the timer counter
 133                                                         to hold when the compare
 134                                                         value is hit. In capture
 135                                                         mode, configures  the
 136                                                         timer counter to not
 137                                                         hold the previous
 138                                                         capture value if a new
 139                                                         event occurs. The
 140                                                         default mode cause the
 141                                                         timer counter to hold
 142                                                         the capture value until
 143                                                         recognized. */
 144 #define XTC_CSR_EXT_CAPTURE_MASK        0x00000008 /**< Enables the
 145                                                         external input
 146                                                         to the timer counter. */
 147 #define XTC_CSR_EXT_GENERATE_MASK       0x00000004 /**< Enables the
 148                                                         external generate output
 149                                                         for the timer. */
 150 #define XTC_CSR_DOWN_COUNT_MASK         0x00000002 /**< Configures the timer
 151                                                         counter to count down
 152                                                         from start value, the
 153                                                         default is to count
 154                                                         up.*/
 155 #define XTC_CSR_CAPTURE_MODE_MASK       0x00000001 /**< Enables the timer to
 156                                                         capture the timer
 157                                                         counter value when the
 158                                                         external capture line is
 159                                                         asserted. The default
 160                                                         mode is compare mode.*/
 161 /* @} */
 162
 163 /**************************** Type Definitions *******************************/
 164
 165 extern u8 XTmrCtr_Offsets[];
 166
 167 /***************** Macros (Inline Functions) Definitions *********************/
 168
 169 /*****************************************************************************/
 170 /**
 171 * Read one of the timer counter registers.
 172 *
 173 * @param        BaseAddress contains the base address of the timer counter
 174 *               device.
 175 * @param        TmrCtrNumber contains the specific timer counter within the
 176 *               device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 177 * @param        RegOffset contains the offset from the 1st register of the timer
 178 *               counter to select the specific register of the timer counter.
 179 *
 180 * @return       The value read from the register, a 32 bit value.
 181 *
 182 * @note         C-Style signature:
 183 *               u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber,
 184                                         unsigned RegOffset);
 185 ******************************************************************************/
 186 #define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)   \
 187         Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \
 188                         (RegOffset))
 189
 190 #ifndef XTimerCtr_ReadReg
 191 #define XTimerCtr_ReadReg XTmrCtr_ReadReg
 192 #endif
 193
 194 /*****************************************************************************/
 195 /**
 196 * Write a specified value to a register of a timer counter.
 197 *
 198 * @param        BaseAddress is the base address of the timer counter device.
 199 * @param        TmrCtrNumber is the specific timer counter within the device, a
 200 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 201 * @param        RegOffset contain the offset from the 1st register of the timer
 202 *               counter to select the specific register of the timer counter.
 203 * @param        ValueToWrite is the 32 bit value to be written to the register.
 204 *
 205 * @note         C-Style signature:
 206 *               void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber,
 207 *                                       unsigned RegOffset, u32 ValueToWrite);
 208 ******************************************************************************/
 209 #define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
 210         Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +    \
 211                            (RegOffset)), (ValueToWrite))
 212
 213 /****************************************************************************/
 214 /**
 215 *
 216 * Set the Control Status Register of a timer counter to the specified value.
 217 *
 218 * @param        BaseAddress is the base address of the device.
 219 * @param        TmrCtrNumber is the specific timer counter within the device, a
 220 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 221 * @param        RegisterValue is the 32 bit value to be written to the register.
 222 *
 223 * @return       None.
 224 *
 225 * @note         C-Style signature:
 226 *               void XTmrCtr_SetControlStatusReg(u32 BaseAddress,
 227 *                                       u8 TmrCtrNumber,u32 RegisterValue);
 228 *****************************************************************************/
 229 #define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
 230         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
 231                                            (RegisterValue))
 232
 233 /****************************************************************************/
 234 /**
 235 *
 236 * Get the Control Status Register of a timer counter.
 237 *
 238 * @param        BaseAddress is the base address of the device.
 239 * @param        TmrCtrNumber is the specific timer counter within the device,
 240 *               a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 241 *
 242 * @return       The value read from the register, a 32 bit value.
 243 *
 244 * @note         C-Style signature:
 245 *               u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress,
 246 *                                               u8 TmrCtrNumber);
 247 *****************************************************************************/
 248 #define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber)          \
 249         XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
 250
 251 /****************************************************************************/
 252 /**
 253 *
 254 * Get the Timer Counter Register of a timer counter.
 255 *
 256 * @param        BaseAddress is the base address of the device.
 257 * @param        TmrCtrNumber is the specific timer counter within the device,
 258 *               a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 259 *
 260 * @return       The value read from the register, a 32 bit value.
 261 *
 262 * @note         C-Style signature:
 263 *               u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress,
 264 *                                               u8 TmrCtrNumber);
 265 *****************************************************************************/
 266 #define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber)             \
 267         XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
 268
 269 /****************************************************************************/
 270 /**
 271 *
 272 * Set the Load Register of a timer counter to the specified value.
 273 *
 274 * @param        BaseAddress is the base address of the device.
 275 * @param        TmrCtrNumber is the specific timer counter within the device, a
 276 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 277 * @param        RegisterValue is the 32 bit value to be written to the register.
 278 *
 279 * @return       None.
 280 *
 281 * @note         C-Style signature:
 282 *               void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber,
 283 *                                                 u32 RegisterValue);
 284 *****************************************************************************/
 285 #define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue)     \
 286         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \
 287                                            (RegisterValue))
 288
 289 /****************************************************************************/
 290 /**
 291 *
 292 * Get the Load Register of a timer counter.
 293 *
 294 * @param        BaseAddress is the base address of the device.
 295 * @param        TmrCtrNumber is the specific timer counter within the device, a
 296 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 297 *
 298 * @return       The value read from the register, a 32 bit value.
 299 *
 300 * @note         C-Style signature:
 301 *               u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber);
 302 *****************************************************************************/
 303 #define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber)   \
 304 XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
 305
 306 /****************************************************************************/
 307 /**
 308 *
 309 * Enable a timer counter such that it starts running.
 310 *
 311 * @param        BaseAddress is the base address of the device.
 312 * @param        TmrCtrNumber is the specific timer counter within the device, a
 313 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 314 *
 315 * @return       None.
 316 *
 317 * @note         C-Style signature:
 318 *               void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber);
 319 *****************************************************************************/
 320 #define XTmrCtr_Enable(BaseAddress, TmrCtrNumber)                           \
 321         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
 322                         (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \
 323                         XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK))
 324
 325 /****************************************************************************/
 326 /**
 327 *
 328 * Disable a timer counter such that it stops running.
 329 *
 330 * @param        BaseAddress is the base address of the device.
 331 * @param        TmrCtrNumber is the specific timer counter within the device,
 332 *               a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 333 *
 334 * @return       None.
 335 *
 336 * @note         C-Style signature:
 337 *               void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber);
 338 *****************************************************************************/
 339 #define XTmrCtr_Disable(BaseAddress, TmrCtrNumber)                        \
 340         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
 341                         (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
 342                         XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK))
 343
 344 /****************************************************************************/
 345 /**
 346 *
 347 * Enable the interrupt for a timer counter.
 348 *
 349 * @param        BaseAddress is the base address of the device.
 350 * @param        TmrCtrNumber is the specific timer counter within the device, a
 351 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 352 *
 353 * @return       None.
 354 *
 355 * @note         C-Style signature:
 356 *               void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber);
 357 *****************************************************************************/
 358 #define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber)                       \
 359         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,   \
 360                         (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),  \
 361                         XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK))
 362
 363 /****************************************************************************/
 364 /**
 365 *
 366 * Disable the interrupt for a timer counter.
 367 *
 368 * @param        BaseAddress is the base address of the device.
 369 * @param        TmrCtrNumber is the specific timer counter within the device, a
 370 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 371 *
 372 * @return       None.
 373 *
 374 * @note         C-Style signature:
 375 *               void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber);
 376 *****************************************************************************/
 377 #define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber)                     \
 378         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,  \
 379         (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),            \
 380                 XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK))
 381
 382 /****************************************************************************/
 383 /**
 384 *
 385 * Cause the timer counter to load it's Timer Counter Register with the value
 386 * in the Load Register.
 387 *
 388 * @param        BaseAddress is the base address of the device.
 389 * @param        TmrCtrNumber is the specific timer counter within the device, a
 390 *                  zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 391 *
 392 * @return       None.
 393 *
 394 * @note         C-Style signature:
 395 *               void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress,
 396                                         u8 TmrCtrNumber);
 397 *****************************************************************************/
 398 #define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber)            \
 399         XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
 400                         (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\
 401                         XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK))
 402
 403 /****************************************************************************/
 404 /**
 405 *
 406 * Determine if a timer counter event has occurred.  Events are defined to be
 407 * when a capture has occurred or the counter has roller over.
 408 *
 409 * @param        BaseAddress is the base address of the device.
 410 * @param        TmrCtrNumber is the specific timer counter within the device, a
 411 *               zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1).
 412 *
 413 * @note         C-Style signature:
 414 *               int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber);
 415 *****************************************************************************/
 416 #define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber)             \
 417                 ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),        \
 418                 XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) ==         \
 419                 XTC_CSR_INT_OCCURED_MASK)
 420
 421 /************************** Function Prototypes ******************************/
 422 /************************** Variable Definitions *****************************/
 423 #ifdef __cplusplus
 424 }
 425 #endif
 426 #endif /* end of protection macro */