git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/Hardware/base_microblaze_design.hwh

   1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
   2 <EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Jan 20 12:53:16 2015" VIVADOVERSION="2014.4">
   3
   4   <SYSTEMINFO ARCH="kintex7" BOARD="xilinx.com:kc705:part0:1.1" DEVICE="7k325t" NAME="base_microblaze_design_imp" PACKAGE="ffg900" SPEEDGRADE="-2"/>
   5
   6   <EXTERNALPORTS>
   7     <PORT DIR="I" NAME="rs232_uart_rxd" SIGIS="undef"/>
   8     <PORT DIR="O" NAME="rs232_uart_txd" SIGIS="undef"/>
   9     <PORT DIR="O" LEFT="7" NAME="led_8bits_tri_o" RIGHT="0" SIGIS="undef"/>
  10     <PORT DIR="I" NAME="mii_col" SIGIS="undef"/>
  11     <PORT DIR="I" NAME="mii_crs" SIGIS="undef"/>
  12     <PORT DIR="O" NAME="mii_rst_n" SIGIS="undef"/>
  13     <PORT DIR="I" NAME="mii_rx_clk" SIGIS="undef"/>
  14     <PORT DIR="I" NAME="mii_rx_dv" SIGIS="undef"/>
  15     <PORT DIR="I" NAME="mii_rx_er" SIGIS="undef"/>
  16     <PORT DIR="I" LEFT="3" NAME="mii_rxd" RIGHT="0" SIGIS="undef"/>
  17     <PORT DIR="I" NAME="mii_tx_clk" SIGIS="undef"/>
  18     <PORT DIR="O" NAME="mii_tx_en" SIGIS="undef"/>
  19     <PORT DIR="O" LEFT="3" NAME="mii_txd" RIGHT="0" SIGIS="undef"/>
  20     <PORT DIR="O" NAME="mdio_mdc_mdc" SIGIS="undef"/>
  21     <PORT DIR="I" NAME="mdio_mdc_mdio_i" SIGIS="undef"/>
  22     <PORT DIR="O" NAME="mdio_mdc_mdio_o" SIGIS="undef"/>
  23     <PORT DIR="O" NAME="mdio_mdc_mdio_t" SIGIS="undef"/>
  24     <PORT DIR="IO" LEFT="63" NAME="ddr3_sdram_dq" RIGHT="0" SIGIS="undef"/>
  25     <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_p" RIGHT="0" SIGIS="undef"/>
  26     <PORT DIR="IO" LEFT="7" NAME="ddr3_sdram_dqs_n" RIGHT="0" SIGIS="undef"/>
  27     <PORT DIR="O" LEFT="13" NAME="ddr3_sdram_addr" RIGHT="0" SIGIS="undef"/>
  28     <PORT DIR="O" LEFT="2" NAME="ddr3_sdram_ba" RIGHT="0" SIGIS="undef"/>
  29     <PORT DIR="O" NAME="ddr3_sdram_ras_n" SIGIS="undef"/>
  30     <PORT DIR="O" NAME="ddr3_sdram_cas_n" SIGIS="undef"/>
  31     <PORT DIR="O" NAME="ddr3_sdram_we_n" SIGIS="undef"/>
  32     <PORT DIR="O" NAME="ddr3_sdram_reset_n" SIGIS="undef"/>
  33     <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_p" RIGHT="0" SIGIS="undef"/>
  34     <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_ck_n" RIGHT="0" SIGIS="undef"/>
  35     <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cke" RIGHT="0" SIGIS="undef"/>
  36     <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_cs_n" RIGHT="0" SIGIS="undef"/>
  37     <PORT DIR="O" LEFT="7" NAME="ddr3_sdram_dm" RIGHT="0" SIGIS="undef"/>
  38     <PORT DIR="O" LEFT="0" NAME="ddr3_sdram_odt" RIGHT="0" SIGIS="undef"/>
  39     <PORT DIR="I" NAME="sys_diff_clock_clk_p" SIGIS="undef"/>
  40     <PORT DIR="I" NAME="sys_diff_clock_clk_n" SIGIS="undef"/>
  41     <PORT DIR="I" NAME="reset" SIGIS="rst" SIGNAME="External_Ports_reset">
  42       <CONNECTIONS>
  43         <CONNECTION INSTANCE="mig_7series_0" PORT="sys_rst"/>
  44       </CONNECTIONS>
  45     </PORT>
  46   </EXTERNALPORTS>
  47
  48   <MODULES>
  49     <MODULE FULLNAME="/axi_ethernetlite_0" HWVERSION="3.0" INSTANCE="axi_ethernetlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite" VLNV="xilinx.com:ip:axi_ethernetlite:3.0">
  50       <DOCUMENTS>
  51         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ethernetlite;v=v3_0;d=pg135-axi-ethernetlite.pdf"/>
  52       </DOCUMENTS>
  53       <PARAMETERS>
  54         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
  55         <PARAMETER NAME="C_INSTANCE" VALUE="axi_ethernetlite_inst"/>
  56         <PARAMETER NAME="C_S_AXI_ACLK_PERIOD_PS" VALUE="10000"/>
  57         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="13"/>
  58         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
  59         <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
  60         <PARAMETER NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
  61         <PARAMETER NAME="C_INCLUDE_MDIO" VALUE="1"/>
  62         <PARAMETER NAME="C_INCLUDE_INTERNAL_LOOPBACK" VALUE="0"/>
  63         <PARAMETER NAME="C_INCLUDE_GLOBAL_BUFFERS" VALUE="1"/>
  64         <PARAMETER NAME="C_DUPLEX" VALUE="1"/>
  65         <PARAMETER NAME="C_TX_PING_PONG" VALUE="1"/>
  66         <PARAMETER NAME="C_RX_PING_PONG" VALUE="1"/>
  67         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_ethernetlite_0_0"/>
  68         <PARAMETER NAME="AXI_ACLK_FREQ_MHZ" VALUE="100"/>
  69         <PARAMETER NAME="Enable_Constraints" VALUE="1"/>
  70         <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
  71         <PARAMETER NAME="MII_BOARD_INTERFACE" VALUE="mii"/>
  72         <PARAMETER NAME="MDIO_BOARD_INTERFACE" VALUE="mdio_mdc"/>
  73         <PARAMETER NAME="C_USE_INTERNAL" VALUE="0"/>
  74         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
  75         <PARAMETER NAME="C_BASEADDR" VALUE="0x40E00000"/>
  76         <PARAMETER NAME="C_HIGHADDR" VALUE="0x40E0FFFF"/>
  77       </PARAMETERS>
  78       <PORTS>
  79         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
  80           <CONNECTIONS>
  81             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
  82           </CONNECTIONS>
  83         </PORT>
  84         <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
  85           <CONNECTIONS>
  86             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
  87           </CONNECTIONS>
  88         </PORT>
  89         <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt">
  90           <CONNECTIONS>
  91             <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
  92           </CONNECTIONS>
  93         </PORT>
  94         <PORT DIR="I" LEFT="12" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
  95           <CONNECTIONS>
  96             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awaddr"/>
  97           </CONNECTIONS>
  98         </PORT>
  99         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
 100           <CONNECTIONS>
 101             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awvalid"/>
 102           </CONNECTIONS>
 103         </PORT>
 104         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
 105           <CONNECTIONS>
 106             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_awready"/>
 107           </CONNECTIONS>
 108         </PORT>
 109         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
 110           <CONNECTIONS>
 111             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wdata"/>
 112           </CONNECTIONS>
 113         </PORT>
 114         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
 115           <CONNECTIONS>
 116             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wstrb"/>
 117           </CONNECTIONS>
 118         </PORT>
 119         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
 120           <CONNECTIONS>
 121             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wvalid"/>
 122           </CONNECTIONS>
 123         </PORT>
 124         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
 125           <CONNECTIONS>
 126             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_wready"/>
 127           </CONNECTIONS>
 128         </PORT>
 129         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
 130           <CONNECTIONS>
 131             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bresp"/>
 132           </CONNECTIONS>
 133         </PORT>
 134         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
 135           <CONNECTIONS>
 136             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bvalid"/>
 137           </CONNECTIONS>
 138         </PORT>
 139         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
 140           <CONNECTIONS>
 141             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_bready"/>
 142           </CONNECTIONS>
 143         </PORT>
 144         <PORT DIR="I" LEFT="12" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
 145           <CONNECTIONS>
 146             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_araddr"/>
 147           </CONNECTIONS>
 148         </PORT>
 149         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
 150           <CONNECTIONS>
 151             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arvalid"/>
 152           </CONNECTIONS>
 153         </PORT>
 154         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
 155           <CONNECTIONS>
 156             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_arready"/>
 157           </CONNECTIONS>
 158         </PORT>
 159         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
 160           <CONNECTIONS>
 161             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rdata"/>
 162           </CONNECTIONS>
 163         </PORT>
 164         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
 165           <CONNECTIONS>
 166             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rresp"/>
 167           </CONNECTIONS>
 168         </PORT>
 169         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
 170           <CONNECTIONS>
 171             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rvalid"/>
 172           </CONNECTIONS>
 173         </PORT>
 174         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
 175           <CONNECTIONS>
 176             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_AXI_rready"/>
 177           </CONNECTIONS>
 178         </PORT>
 179         <PORT DIR="I" NAME="phy_tx_clk" SIGIS="undef"/>
 180         <PORT DIR="I" NAME="phy_rx_clk" SIGIS="undef"/>
 181         <PORT DIR="I" NAME="phy_crs" SIGIS="undef"/>
 182         <PORT DIR="I" NAME="phy_dv" SIGIS="undef"/>
 183         <PORT DIR="I" LEFT="3" NAME="phy_rx_data" RIGHT="0" SIGIS="undef"/>
 184         <PORT DIR="I" NAME="phy_col" SIGIS="undef"/>
 185         <PORT DIR="I" NAME="phy_rx_er" SIGIS="undef"/>
 186         <PORT DIR="O" NAME="phy_rst_n" SIGIS="undef"/>
 187         <PORT DIR="O" NAME="phy_tx_en" SIGIS="undef"/>
 188         <PORT DIR="O" LEFT="3" NAME="phy_tx_data" RIGHT="0" SIGIS="undef"/>
 189         <PORT DIR="I" NAME="phy_mdio_i" SIGIS="undef"/>
 190         <PORT DIR="O" NAME="phy_mdio_o" SIGIS="undef"/>
 191         <PORT DIR="O" NAME="phy_mdio_t" SIGIS="undef"/>
 192         <PORT DIR="O" NAME="phy_mdc" SIGIS="undef"/>
 193       </PORTS>
 194       <BUSINTERFACES>
 195         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="S_AXI" TYPE="SLAVE">
 196           <PORTMAPS>
 197             <PORTMAP PHYSICAL="s_axi_araddr"/>
 198             <PORTMAP PHYSICAL="s_axi_arready"/>
 199             <PORTMAP PHYSICAL="s_axi_arvalid"/>
 200             <PORTMAP PHYSICAL="s_axi_awaddr"/>
 201             <PORTMAP PHYSICAL="s_axi_awready"/>
 202             <PORTMAP PHYSICAL="s_axi_awvalid"/>
 203             <PORTMAP PHYSICAL="s_axi_bready"/>
 204             <PORTMAP PHYSICAL="s_axi_bresp"/>
 205             <PORTMAP PHYSICAL="s_axi_bvalid"/>
 206             <PORTMAP PHYSICAL="s_axi_rdata"/>
 207             <PORTMAP PHYSICAL="s_axi_rready"/>
 208             <PORTMAP PHYSICAL="s_axi_rresp"/>
 209             <PORTMAP PHYSICAL="s_axi_rvalid"/>
 210             <PORTMAP PHYSICAL="s_axi_wdata"/>
 211             <PORTMAP PHYSICAL="s_axi_wready"/>
 212             <PORTMAP PHYSICAL="s_axi_wstrb"/>
 213             <PORTMAP PHYSICAL="s_axi_wvalid"/>
 214           </PORTMAPS>
 215         </BUSINTERFACE>
 216         <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MII" NAME="MII" TYPE="INITIATOR">
 217           <PORTMAPS>
 218             <PORTMAP PHYSICAL="phy_col"/>
 219             <PORTMAP PHYSICAL="phy_crs"/>
 220             <PORTMAP PHYSICAL="phy_rst_n"/>
 221             <PORTMAP PHYSICAL="phy_rx_clk"/>
 222             <PORTMAP PHYSICAL="phy_dv"/>
 223             <PORTMAP PHYSICAL="phy_rx_er"/>
 224             <PORTMAP PHYSICAL="phy_rx_data"/>
 225             <PORTMAP PHYSICAL="phy_tx_clk"/>
 226             <PORTMAP PHYSICAL="phy_tx_en"/>
 227             <PORTMAP PHYSICAL="phy_tx_data"/>
 228           </PORTMAPS>
 229         </BUSINTERFACE>
 230         <BUSINTERFACE BUSNAME="axi_ethernetlite_0_MDIO" NAME="MDIO" TYPE="INITIATOR">
 231           <PORTMAPS>
 232             <PORTMAP PHYSICAL="phy_mdc"/>
 233             <PORTMAP PHYSICAL="phy_mdio_i"/>
 234             <PORTMAP PHYSICAL="phy_mdio_o"/>
 235             <PORTMAP PHYSICAL="phy_mdio_t"/>
 236           </PORTMAPS>
 237         </BUSINTERFACE>
 238       </BUSINTERFACES>
 239       <INTERRUPTINFO TYPE="SOURCE">
 240         <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="2"/>
 241       </INTERRUPTINFO>
 242     </MODULE>
 243     <MODULE FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
 244       <DOCUMENTS>
 245         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
 246       </DOCUMENTS>
 247       <PARAMETERS>
 248         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
 249         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
 250         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
 251         <PARAMETER NAME="C_GPIO_WIDTH" VALUE="8"/>
 252         <PARAMETER NAME="C_GPIO2_WIDTH" VALUE="32"/>
 253         <PARAMETER NAME="C_ALL_INPUTS" VALUE="0"/>
 254         <PARAMETER NAME="C_ALL_INPUTS_2" VALUE="0"/>
 255         <PARAMETER NAME="C_ALL_OUTPUTS" VALUE="1"/>
 256         <PARAMETER NAME="C_ALL_OUTPUTS_2" VALUE="0"/>
 257         <PARAMETER NAME="C_INTERRUPT_PRESENT" VALUE="0"/>
 258         <PARAMETER NAME="C_DOUT_DEFAULT" VALUE="0x00000000"/>
 259         <PARAMETER NAME="C_TRI_DEFAULT" VALUE="0xFFFFFFFF"/>
 260         <PARAMETER NAME="C_IS_DUAL" VALUE="0"/>
 261         <PARAMETER NAME="C_DOUT_DEFAULT_2" VALUE="0x00000000"/>
 262         <PARAMETER NAME="C_TRI_DEFAULT_2" VALUE="0xFFFFFFFF"/>
 263         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_gpio_0_0"/>
 264         <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
 265         <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="led_8bits"/>
 266         <PARAMETER NAME="GPIO2_BOARD_INTERFACE" VALUE="Custom"/>
 267         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
 268         <PARAMETER NAME="C_BASEADDR" VALUE="0x40000000"/>
 269         <PARAMETER NAME="C_HIGHADDR" VALUE="0x4000FFFF"/>
 270       </PARAMETERS>
 271       <PORTS>
 272         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 273           <CONNECTIONS>
 274             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 275           </CONNECTIONS>
 276         </PORT>
 277         <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
 278           <CONNECTIONS>
 279             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
 280           </CONNECTIONS>
 281         </PORT>
 282         <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
 283           <CONNECTIONS>
 284             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awaddr"/>
 285           </CONNECTIONS>
 286         </PORT>
 287         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
 288           <CONNECTIONS>
 289             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awvalid"/>
 290           </CONNECTIONS>
 291         </PORT>
 292         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
 293           <CONNECTIONS>
 294             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_awready"/>
 295           </CONNECTIONS>
 296         </PORT>
 297         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
 298           <CONNECTIONS>
 299             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wdata"/>
 300           </CONNECTIONS>
 301         </PORT>
 302         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
 303           <CONNECTIONS>
 304             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wstrb"/>
 305           </CONNECTIONS>
 306         </PORT>
 307         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
 308           <CONNECTIONS>
 309             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wvalid"/>
 310           </CONNECTIONS>
 311         </PORT>
 312         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
 313           <CONNECTIONS>
 314             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_wready"/>
 315           </CONNECTIONS>
 316         </PORT>
 317         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
 318           <CONNECTIONS>
 319             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bresp"/>
 320           </CONNECTIONS>
 321         </PORT>
 322         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
 323           <CONNECTIONS>
 324             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bvalid"/>
 325           </CONNECTIONS>
 326         </PORT>
 327         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
 328           <CONNECTIONS>
 329             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_bready"/>
 330           </CONNECTIONS>
 331         </PORT>
 332         <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
 333           <CONNECTIONS>
 334             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_araddr"/>
 335           </CONNECTIONS>
 336         </PORT>
 337         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
 338           <CONNECTIONS>
 339             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arvalid"/>
 340           </CONNECTIONS>
 341         </PORT>
 342         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
 343           <CONNECTIONS>
 344             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_arready"/>
 345           </CONNECTIONS>
 346         </PORT>
 347         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
 348           <CONNECTIONS>
 349             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rdata"/>
 350           </CONNECTIONS>
 351         </PORT>
 352         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
 353           <CONNECTIONS>
 354             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rresp"/>
 355           </CONNECTIONS>
 356         </PORT>
 357         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
 358           <CONNECTIONS>
 359             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rvalid"/>
 360           </CONNECTIONS>
 361         </PORT>
 362         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
 363           <CONNECTIONS>
 364             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_AXI_rready"/>
 365           </CONNECTIONS>
 366         </PORT>
 367         <PORT DIR="O" LEFT="7" NAME="gpio_io_o" RIGHT="0" SIGIS="undef"/>
 368       </PORTS>
 369       <BUSINTERFACES>
 370         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="S_AXI" TYPE="SLAVE">
 371           <PORTMAPS>
 372             <PORTMAP PHYSICAL="s_axi_araddr"/>
 373             <PORTMAP PHYSICAL="s_axi_arready"/>
 374             <PORTMAP PHYSICAL="s_axi_arvalid"/>
 375             <PORTMAP PHYSICAL="s_axi_awaddr"/>
 376             <PORTMAP PHYSICAL="s_axi_awready"/>
 377             <PORTMAP PHYSICAL="s_axi_awvalid"/>
 378             <PORTMAP PHYSICAL="s_axi_bready"/>
 379             <PORTMAP PHYSICAL="s_axi_bresp"/>
 380             <PORTMAP PHYSICAL="s_axi_bvalid"/>
 381             <PORTMAP PHYSICAL="s_axi_rdata"/>
 382             <PORTMAP PHYSICAL="s_axi_rready"/>
 383             <PORTMAP PHYSICAL="s_axi_rresp"/>
 384             <PORTMAP PHYSICAL="s_axi_rvalid"/>
 385             <PORTMAP PHYSICAL="s_axi_wdata"/>
 386             <PORTMAP PHYSICAL="s_axi_wready"/>
 387             <PORTMAP PHYSICAL="s_axi_wstrb"/>
 388             <PORTMAP PHYSICAL="s_axi_wvalid"/>
 389           </PORTMAPS>
 390         </BUSINTERFACE>
 391         <BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="GPIO" TYPE="INITIATOR">
 392           <PORTMAPS>
 393             <PORTMAP PHYSICAL="gpio_io_o"/>
 394           </PORTMAPS>
 395         </BUSINTERFACE>
 396       </BUSINTERFACES>
 397     </MODULE>
 398     <MODULE FULLNAME="/axi_intc_0" HWVERSION="4.1" INSTANCE="axi_intc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc" VLNV="xilinx.com:ip:axi_intc:4.1">
 399       <DOCUMENTS>
 400         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=v4_1;d=pg099-axi-intc.pdf"/>
 401       </DOCUMENTS>
 402       <PARAMETERS>
 403         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
 404         <PARAMETER NAME="C_INSTANCE" VALUE="axi_intc_inst"/>
 405         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
 406         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
 407         <PARAMETER NAME="C_NUM_INTR_INPUTS" VALUE="3"/>
 408         <PARAMETER NAME="C_NUM_SW_INTR" VALUE="0"/>
 409         <PARAMETER NAME="C_KIND_OF_INTR" VALUE="0xfffffffe"/>
 410         <PARAMETER NAME="C_KIND_OF_EDGE" VALUE="0xffffffff"/>
 411         <PARAMETER NAME="C_KIND_OF_LVL" VALUE="0xffffffff"/>
 412         <PARAMETER NAME="C_ASYNC_INTR" VALUE="0xFFFFFFF8"/>
 413         <PARAMETER NAME="C_NUM_SYNC_FF" VALUE="2"/>
 414         <PARAMETER NAME="C_IVAR_RESET_VALUE" VALUE="0x00000010"/>
 415         <PARAMETER NAME="C_ENABLE_ASYNC" VALUE="0"/>
 416         <PARAMETER NAME="C_HAS_IPR" VALUE="1"/>
 417         <PARAMETER NAME="C_HAS_SIE" VALUE="1"/>
 418         <PARAMETER NAME="C_HAS_CIE" VALUE="1"/>
 419         <PARAMETER NAME="C_HAS_IVR" VALUE="1"/>
 420         <PARAMETER NAME="C_HAS_ILR" VALUE="0"/>
 421         <PARAMETER NAME="C_IRQ_IS_LEVEL" VALUE="1"/>
 422         <PARAMETER NAME="C_IRQ_ACTIVE" VALUE="0x1"/>
 423         <PARAMETER NAME="C_DISABLE_SYNCHRONIZERS" VALUE="1"/>
 424         <PARAMETER NAME="C_MB_CLK_NOT_CONNECTED" VALUE="1"/>
 425         <PARAMETER NAME="C_HAS_FAST" VALUE="0"/>
 426         <PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
 427         <PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
 428         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_intc_0_0"/>
 429         <PARAMETER NAME="Sense_of_IRQ_Level_Type" VALUE="Active_High"/>
 430         <PARAMETER NAME="Sense_of_IRQ_Edge_Type" VALUE="Rising"/>
 431         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
 432         <PARAMETER NAME="EDK_SPECIAL" VALUE="INTR_CTRL"/>
 433         <PARAMETER NAME="C_BASEADDR" VALUE="0x41200000"/>
 434         <PARAMETER NAME="C_HIGHADDR" VALUE="0x4120FFFF"/>
 435       </PARAMETERS>
 436       <PORTS>
 437         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 438           <CONNECTIONS>
 439             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 440           </CONNECTIONS>
 441         </PORT>
 442         <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
 443           <CONNECTIONS>
 444             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
 445           </CONNECTIONS>
 446         </PORT>
 447         <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
 448           <CONNECTIONS>
 449             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awaddr"/>
 450           </CONNECTIONS>
 451         </PORT>
 452         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
 453           <CONNECTIONS>
 454             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awvalid"/>
 455           </CONNECTIONS>
 456         </PORT>
 457         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
 458           <CONNECTIONS>
 459             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_awready"/>
 460           </CONNECTIONS>
 461         </PORT>
 462         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
 463           <CONNECTIONS>
 464             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wdata"/>
 465           </CONNECTIONS>
 466         </PORT>
 467         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
 468           <CONNECTIONS>
 469             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wstrb"/>
 470           </CONNECTIONS>
 471         </PORT>
 472         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
 473           <CONNECTIONS>
 474             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wvalid"/>
 475           </CONNECTIONS>
 476         </PORT>
 477         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
 478           <CONNECTIONS>
 479             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_wready"/>
 480           </CONNECTIONS>
 481         </PORT>
 482         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
 483           <CONNECTIONS>
 484             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bresp"/>
 485           </CONNECTIONS>
 486         </PORT>
 487         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
 488           <CONNECTIONS>
 489             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bvalid"/>
 490           </CONNECTIONS>
 491         </PORT>
 492         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
 493           <CONNECTIONS>
 494             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_bready"/>
 495           </CONNECTIONS>
 496         </PORT>
 497         <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
 498           <CONNECTIONS>
 499             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_araddr"/>
 500           </CONNECTIONS>
 501         </PORT>
 502         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
 503           <CONNECTIONS>
 504             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arvalid"/>
 505           </CONNECTIONS>
 506         </PORT>
 507         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
 508           <CONNECTIONS>
 509             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_arready"/>
 510           </CONNECTIONS>
 511         </PORT>
 512         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
 513           <CONNECTIONS>
 514             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rdata"/>
 515           </CONNECTIONS>
 516         </PORT>
 517         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
 518           <CONNECTIONS>
 519             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rresp"/>
 520           </CONNECTIONS>
 521         </PORT>
 522         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
 523           <CONNECTIONS>
 524             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rvalid"/>
 525           </CONNECTIONS>
 526         </PORT>
 527         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
 528           <CONNECTIONS>
 529             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_AXI_rready"/>
 530           </CONNECTIONS>
 531         </PORT>
 532         <PORT DIR="I" LEFT="2" NAME="intr" RIGHT="0" SENSITIVITY="EDGE_RISING:EDGE_RISING:LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_ethernetlite_0_ip2intc_irpt &amp; axi_uartlite_0_interrupt &amp; axi_timer_0_interrupt">
 533           <CONNECTIONS>
 534             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="ip2intc_irpt"/>
 535             <CONNECTION INSTANCE="axi_uartlite_0" PORT="interrupt"/>
 536             <CONNECTION INSTANCE="axi_timer_0" PORT="interrupt"/>
 537           </CONNECTIONS>
 538         </PORT>
 539         <PORT DIR="O" NAME="irq" SIGIS="undef" SIGNAME="axi_intc_0_irq">
 540           <CONNECTIONS>
 541             <CONNECTION INSTANCE="microblaze_0" PORT="Interrupt"/>
 542           </CONNECTIONS>
 543         </PORT>
 544       </PORTS>
 545       <BUSINTERFACES>
 546         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="s_axi" TYPE="SLAVE">
 547           <PORTMAPS>
 548             <PORTMAP PHYSICAL="s_axi_araddr"/>
 549             <PORTMAP PHYSICAL="s_axi_arready"/>
 550             <PORTMAP PHYSICAL="s_axi_arvalid"/>
 551             <PORTMAP PHYSICAL="s_axi_awaddr"/>
 552             <PORTMAP PHYSICAL="s_axi_awready"/>
 553             <PORTMAP PHYSICAL="s_axi_awvalid"/>
 554             <PORTMAP PHYSICAL="s_axi_bready"/>
 555             <PORTMAP PHYSICAL="s_axi_bresp"/>
 556             <PORTMAP PHYSICAL="s_axi_bvalid"/>
 557             <PORTMAP PHYSICAL="s_axi_rdata"/>
 558             <PORTMAP PHYSICAL="s_axi_rready"/>
 559             <PORTMAP PHYSICAL="s_axi_rresp"/>
 560             <PORTMAP PHYSICAL="s_axi_rvalid"/>
 561             <PORTMAP PHYSICAL="s_axi_wdata"/>
 562             <PORTMAP PHYSICAL="s_axi_wready"/>
 563             <PORTMAP PHYSICAL="s_axi_wstrb"/>
 564             <PORTMAP PHYSICAL="s_axi_wvalid"/>
 565           </PORTMAPS>
 566         </BUSINTERFACE>
 567         <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="interrupt" TYPE="INITIATOR">
 568           <PORTMAPS>
 569             <PORTMAP PHYSICAL="irq"/>
 570           </PORTMAPS>
 571         </BUSINTERFACE>
 572       </BUSINTERFACES>
 573       <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
 574         <SOURCE INSTANCE="axi_timer_0" PRIORITY="0" SIGNAME="axi_timer_0_interrupt"/>
 575         <SOURCE INSTANCE="axi_uartlite_0" PRIORITY="1" SIGNAME="axi_uartlite_0_interrupt"/>
 576         <SOURCE INSTANCE="axi_ethernetlite_0" PRIORITY="2" SIGNAME="axi_ethernetlite_0_ip2intc_irpt"/>
 577       </INTERRUPTINFO>
 578     </MODULE>
 579     <MODULE FULLNAME="/axi_mem_intercon" HWVERSION="2.1" INSTANCE="axi_mem_intercon" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
 580       <DOCUMENTS>
 581         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
 582       </DOCUMENTS>
 583       <PARAMETERS>
 584         <PARAMETER NAME="NUM_SI" VALUE="2"/>
 585         <PARAMETER NAME="NUM_MI" VALUE="1"/>
 586         <PARAMETER NAME="STRATEGY" VALUE="0"/>
 587         <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
 588         <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
 589         <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
 590         <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
 591         <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
 592         <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
 593         <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
 594         <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
 595         <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
 596         <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
 597         <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
 598         <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
 599         <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
 600         <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
 601         <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
 602         <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
 603         <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
 604         <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
 605         <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
 606         <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
 607         <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
 608         <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
 609         <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
 610         <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
 611         <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
 612         <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
 613         <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
 614         <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
 615         <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
 616         <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
 617         <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
 618         <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
 619         <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
 620         <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
 621         <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
 622         <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
 623         <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
 624         <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
 625         <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
 626         <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
 627         <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
 628         <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
 629         <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
 630         <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
 631         <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
 632         <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
 633         <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
 634         <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
 635         <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
 636         <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
 637         <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
 638         <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
 639         <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
 640         <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
 641         <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
 642         <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
 643         <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
 644         <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
 645         <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
 646         <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
 647         <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
 648         <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
 649         <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
 650         <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
 651         <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
 652         <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
 653         <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
 654         <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
 655         <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
 656         <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
 657         <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
 658         <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
 659         <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
 660         <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
 661         <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
 662         <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
 663         <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
 664         <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
 665         <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
 666         <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
 667         <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
 668         <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
 669         <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
 670         <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
 671         <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
 672         <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
 673         <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
 674         <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
 675         <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
 676         <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
 677         <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
 678         <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
 679         <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
 680         <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
 681         <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
 682         <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
 683         <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
 684         <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
 685         <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
 686         <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
 687         <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
 688         <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
 689         <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
 690         <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
 691         <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
 692         <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
 693         <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
 694         <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
 695         <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
 696         <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
 697         <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
 698         <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
 699         <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
 700         <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
 701         <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
 702         <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
 703         <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
 704         <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
 705         <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
 706         <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
 707         <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
 708         <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
 709         <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
 710         <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
 711         <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
 712         <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
 713         <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
 714         <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
 715         <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
 716         <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
 717         <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
 718         <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
 719         <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
 720         <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
 721         <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
 722         <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
 723         <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
 724         <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
 725         <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
 726         <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
 727         <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
 728         <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
 729         <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
 730         <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
 731         <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
 732         <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
 733         <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
 734         <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
 735         <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
 736         <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
 737         <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
 738         <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
 739         <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
 740         <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
 741         <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
 742         <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
 743         <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
 744         <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
 745         <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
 746         <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
 747         <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
 748         <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
 749         <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
 750         <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
 751         <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
 752         <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
 753         <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
 754         <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
 755         <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
 756         <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
 757         <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
 758         <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
 759         <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
 760         <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
 761         <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
 762         <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
 763         <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
 764         <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
 765         <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
 766         <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
 767         <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
 768         <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
 769         <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
 770         <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
 771         <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
 772         <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
 773         <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
 774         <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
 775         <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
 776         <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
 777         <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
 778         <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
 779         <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
 780         <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
 781         <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
 782         <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
 783         <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
 784         <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
 785         <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
 786         <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
 787         <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
 788         <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
 789         <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
 790         <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
 791         <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
 792         <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
 793         <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
 794         <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
 795         <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
 796         <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
 797         <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
 798         <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
 799         <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
 800         <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
 801         <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
 802         <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
 803         <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
 804         <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
 805         <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
 806         <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
 807         <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
 808         <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
 809         <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
 810         <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
 811         <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
 812         <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
 813         <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
 814         <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
 815         <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
 816         <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
 817         <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
 818         <PARAMETER NAME="M00_SECURE" VALUE="0"/>
 819         <PARAMETER NAME="M01_SECURE" VALUE="0"/>
 820         <PARAMETER NAME="M02_SECURE" VALUE="0"/>
 821         <PARAMETER NAME="M03_SECURE" VALUE="0"/>
 822         <PARAMETER NAME="M04_SECURE" VALUE="0"/>
 823         <PARAMETER NAME="M05_SECURE" VALUE="0"/>
 824         <PARAMETER NAME="M06_SECURE" VALUE="0"/>
 825         <PARAMETER NAME="M07_SECURE" VALUE="0"/>
 826         <PARAMETER NAME="M08_SECURE" VALUE="0"/>
 827         <PARAMETER NAME="M09_SECURE" VALUE="0"/>
 828         <PARAMETER NAME="M10_SECURE" VALUE="0"/>
 829         <PARAMETER NAME="M11_SECURE" VALUE="0"/>
 830         <PARAMETER NAME="M12_SECURE" VALUE="0"/>
 831         <PARAMETER NAME="M13_SECURE" VALUE="0"/>
 832         <PARAMETER NAME="M14_SECURE" VALUE="0"/>
 833         <PARAMETER NAME="M15_SECURE" VALUE="0"/>
 834         <PARAMETER NAME="M16_SECURE" VALUE="0"/>
 835         <PARAMETER NAME="M17_SECURE" VALUE="0"/>
 836         <PARAMETER NAME="M18_SECURE" VALUE="0"/>
 837         <PARAMETER NAME="M19_SECURE" VALUE="0"/>
 838         <PARAMETER NAME="M20_SECURE" VALUE="0"/>
 839         <PARAMETER NAME="M21_SECURE" VALUE="0"/>
 840         <PARAMETER NAME="M22_SECURE" VALUE="0"/>
 841         <PARAMETER NAME="M23_SECURE" VALUE="0"/>
 842         <PARAMETER NAME="M24_SECURE" VALUE="0"/>
 843         <PARAMETER NAME="M25_SECURE" VALUE="0"/>
 844         <PARAMETER NAME="M26_SECURE" VALUE="0"/>
 845         <PARAMETER NAME="M27_SECURE" VALUE="0"/>
 846         <PARAMETER NAME="M28_SECURE" VALUE="0"/>
 847         <PARAMETER NAME="M29_SECURE" VALUE="0"/>
 848         <PARAMETER NAME="M30_SECURE" VALUE="0"/>
 849         <PARAMETER NAME="M31_SECURE" VALUE="0"/>
 850         <PARAMETER NAME="M32_SECURE" VALUE="0"/>
 851         <PARAMETER NAME="M33_SECURE" VALUE="0"/>
 852         <PARAMETER NAME="M34_SECURE" VALUE="0"/>
 853         <PARAMETER NAME="M35_SECURE" VALUE="0"/>
 854         <PARAMETER NAME="M36_SECURE" VALUE="0"/>
 855         <PARAMETER NAME="M37_SECURE" VALUE="0"/>
 856         <PARAMETER NAME="M38_SECURE" VALUE="0"/>
 857         <PARAMETER NAME="M39_SECURE" VALUE="0"/>
 858         <PARAMETER NAME="M40_SECURE" VALUE="0"/>
 859         <PARAMETER NAME="M41_SECURE" VALUE="0"/>
 860         <PARAMETER NAME="M42_SECURE" VALUE="0"/>
 861         <PARAMETER NAME="M43_SECURE" VALUE="0"/>
 862         <PARAMETER NAME="M44_SECURE" VALUE="0"/>
 863         <PARAMETER NAME="M45_SECURE" VALUE="0"/>
 864         <PARAMETER NAME="M46_SECURE" VALUE="0"/>
 865         <PARAMETER NAME="M47_SECURE" VALUE="0"/>
 866         <PARAMETER NAME="M48_SECURE" VALUE="0"/>
 867         <PARAMETER NAME="M49_SECURE" VALUE="0"/>
 868         <PARAMETER NAME="M50_SECURE" VALUE="0"/>
 869         <PARAMETER NAME="M51_SECURE" VALUE="0"/>
 870         <PARAMETER NAME="M52_SECURE" VALUE="0"/>
 871         <PARAMETER NAME="M53_SECURE" VALUE="0"/>
 872         <PARAMETER NAME="M54_SECURE" VALUE="0"/>
 873         <PARAMETER NAME="M55_SECURE" VALUE="0"/>
 874         <PARAMETER NAME="M56_SECURE" VALUE="0"/>
 875         <PARAMETER NAME="M57_SECURE" VALUE="0"/>
 876         <PARAMETER NAME="M58_SECURE" VALUE="0"/>
 877         <PARAMETER NAME="M59_SECURE" VALUE="0"/>
 878         <PARAMETER NAME="M60_SECURE" VALUE="0"/>
 879         <PARAMETER NAME="M61_SECURE" VALUE="0"/>
 880         <PARAMETER NAME="M62_SECURE" VALUE="0"/>
 881         <PARAMETER NAME="M63_SECURE" VALUE="0"/>
 882         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_mem_intercon_0"/>
 883         <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
 884       </PARAMETERS>
 885       <PORTS>
 886         <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 887           <CONNECTIONS>
 888             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 889           </CONNECTIONS>
 890         </PORT>
 891         <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
 892           <CONNECTIONS>
 893             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
 894           </CONNECTIONS>
 895         </PORT>
 896         <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 897           <CONNECTIONS>
 898             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 899           </CONNECTIONS>
 900         </PORT>
 901         <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
 902           <CONNECTIONS>
 903             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
 904           </CONNECTIONS>
 905         </PORT>
 906         <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 907           <CONNECTIONS>
 908             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 909           </CONNECTIONS>
 910         </PORT>
 911         <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
 912           <CONNECTIONS>
 913             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
 914           </CONNECTIONS>
 915         </PORT>
 916         <PORT DIR="I" NAME="S01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
 917           <CONNECTIONS>
 918             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
 919           </CONNECTIONS>
 920         </PORT>
 921         <PORT DIR="I" LEFT="0" NAME="S01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
 922           <CONNECTIONS>
 923             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
 924           </CONNECTIONS>
 925         </PORT>
 926         <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
 927           <CONNECTIONS>
 928             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARADDR"/>
 929           </CONNECTIONS>
 930         </PORT>
 931         <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
 932           <CONNECTIONS>
 933             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARBURST"/>
 934           </CONNECTIONS>
 935         </PORT>
 936         <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
 937           <CONNECTIONS>
 938             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARCACHE"/>
 939           </CONNECTIONS>
 940         </PORT>
 941         <PORT DIR="I" LEFT="0" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
 942           <CONNECTIONS>
 943             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARID"/>
 944           </CONNECTIONS>
 945         </PORT>
 946         <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
 947           <CONNECTIONS>
 948             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLEN"/>
 949           </CONNECTIONS>
 950         </PORT>
 951         <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
 952           <CONNECTIONS>
 953             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARLOCK"/>
 954           </CONNECTIONS>
 955         </PORT>
 956         <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
 957           <CONNECTIONS>
 958             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARPROT"/>
 959           </CONNECTIONS>
 960         </PORT>
 961         <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
 962           <CONNECTIONS>
 963             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARQOS"/>
 964           </CONNECTIONS>
 965         </PORT>
 966         <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
 967           <CONNECTIONS>
 968             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARREADY"/>
 969           </CONNECTIONS>
 970         </PORT>
 971         <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
 972           <CONNECTIONS>
 973             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARSIZE"/>
 974           </CONNECTIONS>
 975         </PORT>
 976         <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
 977           <CONNECTIONS>
 978             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_ARVALID"/>
 979           </CONNECTIONS>
 980         </PORT>
 981         <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
 982           <CONNECTIONS>
 983             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWADDR"/>
 984           </CONNECTIONS>
 985         </PORT>
 986         <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
 987           <CONNECTIONS>
 988             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWBURST"/>
 989           </CONNECTIONS>
 990         </PORT>
 991         <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
 992           <CONNECTIONS>
 993             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWCACHE"/>
 994           </CONNECTIONS>
 995         </PORT>
 996         <PORT DIR="I" LEFT="0" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
 997           <CONNECTIONS>
 998             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWID"/>
 999           </CONNECTIONS>
1000         </PORT>
1001         <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
1002           <CONNECTIONS>
1003             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLEN"/>
1004           </CONNECTIONS>
1005         </PORT>
1006         <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
1007           <CONNECTIONS>
1008             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWLOCK"/>
1009           </CONNECTIONS>
1010         </PORT>
1011         <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
1012           <CONNECTIONS>
1013             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWPROT"/>
1014           </CONNECTIONS>
1015         </PORT>
1016         <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
1017           <CONNECTIONS>
1018             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWQOS"/>
1019           </CONNECTIONS>
1020         </PORT>
1021         <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
1022           <CONNECTIONS>
1023             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWREADY"/>
1024           </CONNECTIONS>
1025         </PORT>
1026         <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
1027           <CONNECTIONS>
1028             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWSIZE"/>
1029           </CONNECTIONS>
1030         </PORT>
1031         <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
1032           <CONNECTIONS>
1033             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_AWVALID"/>
1034           </CONNECTIONS>
1035         </PORT>
1036         <PORT DIR="O" LEFT="0" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
1037           <CONNECTIONS>
1038             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BID"/>
1039           </CONNECTIONS>
1040         </PORT>
1041         <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
1042           <CONNECTIONS>
1043             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BREADY"/>
1044           </CONNECTIONS>
1045         </PORT>
1046         <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
1047           <CONNECTIONS>
1048             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BRESP"/>
1049           </CONNECTIONS>
1050         </PORT>
1051         <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
1052           <CONNECTIONS>
1053             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_BVALID"/>
1054           </CONNECTIONS>
1055         </PORT>
1056         <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
1057           <CONNECTIONS>
1058             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RDATA"/>
1059           </CONNECTIONS>
1060         </PORT>
1061         <PORT DIR="O" LEFT="0" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
1062           <CONNECTIONS>
1063             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RID"/>
1064           </CONNECTIONS>
1065         </PORT>
1066         <PORT DIR="O" LEFT="0" NAME="S00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
1067           <CONNECTIONS>
1068             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RLAST"/>
1069           </CONNECTIONS>
1070         </PORT>
1071         <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
1072           <CONNECTIONS>
1073             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RREADY"/>
1074           </CONNECTIONS>
1075         </PORT>
1076         <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
1077           <CONNECTIONS>
1078             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RRESP"/>
1079           </CONNECTIONS>
1080         </PORT>
1081         <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
1082           <CONNECTIONS>
1083             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_RVALID"/>
1084           </CONNECTIONS>
1085         </PORT>
1086         <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
1087           <CONNECTIONS>
1088             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WDATA"/>
1089           </CONNECTIONS>
1090         </PORT>
1091         <PORT DIR="I" LEFT="0" NAME="S00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
1092           <CONNECTIONS>
1093             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WLAST"/>
1094           </CONNECTIONS>
1095         </PORT>
1096         <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
1097           <CONNECTIONS>
1098             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WREADY"/>
1099           </CONNECTIONS>
1100         </PORT>
1101         <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
1102           <CONNECTIONS>
1103             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WSTRB"/>
1104           </CONNECTIONS>
1105         </PORT>
1106         <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
1107           <CONNECTIONS>
1108             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DC_WVALID"/>
1109           </CONNECTIONS>
1110         </PORT>
1111         <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
1112           <CONNECTIONS>
1113             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awid"/>
1114           </CONNECTIONS>
1115         </PORT>
1116         <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
1117           <CONNECTIONS>
1118             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awaddr"/>
1119           </CONNECTIONS>
1120         </PORT>
1121         <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
1122           <CONNECTIONS>
1123             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlen"/>
1124           </CONNECTIONS>
1125         </PORT>
1126         <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
1127           <CONNECTIONS>
1128             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awsize"/>
1129           </CONNECTIONS>
1130         </PORT>
1131         <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
1132           <CONNECTIONS>
1133             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awburst"/>
1134           </CONNECTIONS>
1135         </PORT>
1136         <PORT DIR="O" LEFT="0" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
1137           <CONNECTIONS>
1138             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awlock"/>
1139           </CONNECTIONS>
1140         </PORT>
1141         <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
1142           <CONNECTIONS>
1143             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awcache"/>
1144           </CONNECTIONS>
1145         </PORT>
1146         <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
1147           <CONNECTIONS>
1148             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awprot"/>
1149           </CONNECTIONS>
1150         </PORT>
1151         <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
1152           <CONNECTIONS>
1153             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awqos"/>
1154           </CONNECTIONS>
1155         </PORT>
1156         <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
1157           <CONNECTIONS>
1158             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awvalid"/>
1159           </CONNECTIONS>
1160         </PORT>
1161         <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
1162           <CONNECTIONS>
1163             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_awready"/>
1164           </CONNECTIONS>
1165         </PORT>
1166         <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
1167           <CONNECTIONS>
1168             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wdata"/>
1169           </CONNECTIONS>
1170         </PORT>
1171         <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
1172           <CONNECTIONS>
1173             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wstrb"/>
1174           </CONNECTIONS>
1175         </PORT>
1176         <PORT DIR="O" LEFT="0" NAME="M00_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
1177           <CONNECTIONS>
1178             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wlast"/>
1179           </CONNECTIONS>
1180         </PORT>
1181         <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
1182           <CONNECTIONS>
1183             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wvalid"/>
1184           </CONNECTIONS>
1185         </PORT>
1186         <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
1187           <CONNECTIONS>
1188             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_wready"/>
1189           </CONNECTIONS>
1190         </PORT>
1191         <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
1192           <CONNECTIONS>
1193             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bready"/>
1194           </CONNECTIONS>
1195         </PORT>
1196         <PORT DIR="I" LEFT="0" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
1197           <CONNECTIONS>
1198             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bid"/>
1199           </CONNECTIONS>
1200         </PORT>
1201         <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
1202           <CONNECTIONS>
1203             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bresp"/>
1204           </CONNECTIONS>
1205         </PORT>
1206         <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
1207           <CONNECTIONS>
1208             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_bvalid"/>
1209           </CONNECTIONS>
1210         </PORT>
1211         <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
1212           <CONNECTIONS>
1213             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arid"/>
1214           </CONNECTIONS>
1215         </PORT>
1216         <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
1217           <CONNECTIONS>
1218             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_araddr"/>
1219           </CONNECTIONS>
1220         </PORT>
1221         <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
1222           <CONNECTIONS>
1223             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlen"/>
1224           </CONNECTIONS>
1225         </PORT>
1226         <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
1227           <CONNECTIONS>
1228             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arsize"/>
1229           </CONNECTIONS>
1230         </PORT>
1231         <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
1232           <CONNECTIONS>
1233             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arburst"/>
1234           </CONNECTIONS>
1235         </PORT>
1236         <PORT DIR="O" LEFT="0" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
1237           <CONNECTIONS>
1238             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arlock"/>
1239           </CONNECTIONS>
1240         </PORT>
1241         <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
1242           <CONNECTIONS>
1243             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arcache"/>
1244           </CONNECTIONS>
1245         </PORT>
1246         <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
1247           <CONNECTIONS>
1248             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arprot"/>
1249           </CONNECTIONS>
1250         </PORT>
1251         <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
1252           <CONNECTIONS>
1253             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arqos"/>
1254           </CONNECTIONS>
1255         </PORT>
1256         <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
1257           <CONNECTIONS>
1258             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arvalid"/>
1259           </CONNECTIONS>
1260         </PORT>
1261         <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
1262           <CONNECTIONS>
1263             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_arready"/>
1264           </CONNECTIONS>
1265         </PORT>
1266         <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
1267           <CONNECTIONS>
1268             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rready"/>
1269           </CONNECTIONS>
1270         </PORT>
1271         <PORT DIR="I" LEFT="0" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
1272           <CONNECTIONS>
1273             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rid"/>
1274           </CONNECTIONS>
1275         </PORT>
1276         <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
1277           <CONNECTIONS>
1278             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rdata"/>
1279           </CONNECTIONS>
1280         </PORT>
1281         <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
1282           <CONNECTIONS>
1283             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rresp"/>
1284           </CONNECTIONS>
1285         </PORT>
1286         <PORT DIR="I" LEFT="0" NAME="M00_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
1287           <CONNECTIONS>
1288             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rlast"/>
1289           </CONNECTIONS>
1290         </PORT>
1291         <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
1292           <CONNECTIONS>
1293             <CONNECTION INSTANCE="mig_7series_0" PORT="s_axi_rvalid"/>
1294           </CONNECTIONS>
1295         </PORT>
1296         <PORT DIR="I" LEFT="31" NAME="S01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
1297           <CONNECTIONS>
1298             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARADDR"/>
1299           </CONNECTIONS>
1300         </PORT>
1301         <PORT DIR="I" LEFT="1" NAME="S01_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
1302           <CONNECTIONS>
1303             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARBURST"/>
1304           </CONNECTIONS>
1305         </PORT>
1306         <PORT DIR="I" LEFT="3" NAME="S01_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
1307           <CONNECTIONS>
1308             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARCACHE"/>
1309           </CONNECTIONS>
1310         </PORT>
1311         <PORT DIR="I" LEFT="0" NAME="S01_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
1312           <CONNECTIONS>
1313             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARID"/>
1314           </CONNECTIONS>
1315         </PORT>
1316         <PORT DIR="I" LEFT="7" NAME="S01_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
1317           <CONNECTIONS>
1318             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLEN"/>
1319           </CONNECTIONS>
1320         </PORT>
1321         <PORT DIR="I" LEFT="0" NAME="S01_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
1322           <CONNECTIONS>
1323             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARLOCK"/>
1324           </CONNECTIONS>
1325         </PORT>
1326         <PORT DIR="I" LEFT="2" NAME="S01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
1327           <CONNECTIONS>
1328             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARPROT"/>
1329           </CONNECTIONS>
1330         </PORT>
1331         <PORT DIR="I" LEFT="3" NAME="S01_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
1332           <CONNECTIONS>
1333             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARQOS"/>
1334           </CONNECTIONS>
1335         </PORT>
1336         <PORT DIR="O" LEFT="0" NAME="S01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
1337           <CONNECTIONS>
1338             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARREADY"/>
1339           </CONNECTIONS>
1340         </PORT>
1341         <PORT DIR="I" LEFT="2" NAME="S01_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
1342           <CONNECTIONS>
1343             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARSIZE"/>
1344           </CONNECTIONS>
1345         </PORT>
1346         <PORT DIR="I" LEFT="0" NAME="S01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
1347           <CONNECTIONS>
1348             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_ARVALID"/>
1349           </CONNECTIONS>
1350         </PORT>
1351         <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
1352           <CONNECTIONS>
1353             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWADDR"/>
1354           </CONNECTIONS>
1355         </PORT>
1356         <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
1357           <CONNECTIONS>
1358             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWBURST"/>
1359           </CONNECTIONS>
1360         </PORT>
1361         <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
1362           <CONNECTIONS>
1363             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWCACHE"/>
1364           </CONNECTIONS>
1365         </PORT>
1366         <PORT DIR="I" LEFT="0" NAME="S01_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
1367           <CONNECTIONS>
1368             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWID"/>
1369           </CONNECTIONS>
1370         </PORT>
1371         <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
1372           <CONNECTIONS>
1373             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLEN"/>
1374           </CONNECTIONS>
1375         </PORT>
1376         <PORT DIR="I" LEFT="0" NAME="S01_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
1377           <CONNECTIONS>
1378             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWLOCK"/>
1379           </CONNECTIONS>
1380         </PORT>
1381         <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
1382           <CONNECTIONS>
1383             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWPROT"/>
1384           </CONNECTIONS>
1385         </PORT>
1386         <PORT DIR="I" LEFT="3" NAME="S01_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
1387           <CONNECTIONS>
1388             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWQOS"/>
1389           </CONNECTIONS>
1390         </PORT>
1391         <PORT DIR="O" LEFT="0" NAME="S01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
1392           <CONNECTIONS>
1393             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWREADY"/>
1394           </CONNECTIONS>
1395         </PORT>
1396         <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
1397           <CONNECTIONS>
1398             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWSIZE"/>
1399           </CONNECTIONS>
1400         </PORT>
1401         <PORT DIR="I" LEFT="0" NAME="S01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
1402           <CONNECTIONS>
1403             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_AWVALID"/>
1404           </CONNECTIONS>
1405         </PORT>
1406         <PORT DIR="O" LEFT="0" NAME="S01_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
1407           <CONNECTIONS>
1408             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BID"/>
1409           </CONNECTIONS>
1410         </PORT>
1411         <PORT DIR="I" LEFT="0" NAME="S01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
1412           <CONNECTIONS>
1413             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BREADY"/>
1414           </CONNECTIONS>
1415         </PORT>
1416         <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
1417           <CONNECTIONS>
1418             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BRESP"/>
1419           </CONNECTIONS>
1420         </PORT>
1421         <PORT DIR="O" LEFT="0" NAME="S01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
1422           <CONNECTIONS>
1423             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_BVALID"/>
1424           </CONNECTIONS>
1425         </PORT>
1426         <PORT DIR="O" LEFT="31" NAME="S01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
1427           <CONNECTIONS>
1428             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RDATA"/>
1429           </CONNECTIONS>
1430         </PORT>
1431         <PORT DIR="O" LEFT="0" NAME="S01_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
1432           <CONNECTIONS>
1433             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RID"/>
1434           </CONNECTIONS>
1435         </PORT>
1436         <PORT DIR="O" LEFT="0" NAME="S01_AXI_rlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
1437           <CONNECTIONS>
1438             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RLAST"/>
1439           </CONNECTIONS>
1440         </PORT>
1441         <PORT DIR="I" LEFT="0" NAME="S01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
1442           <CONNECTIONS>
1443             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RREADY"/>
1444           </CONNECTIONS>
1445         </PORT>
1446         <PORT DIR="O" LEFT="1" NAME="S01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
1447           <CONNECTIONS>
1448             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RRESP"/>
1449           </CONNECTIONS>
1450         </PORT>
1451         <PORT DIR="O" LEFT="0" NAME="S01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
1452           <CONNECTIONS>
1453             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_RVALID"/>
1454           </CONNECTIONS>
1455         </PORT>
1456         <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
1457           <CONNECTIONS>
1458             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WDATA"/>
1459           </CONNECTIONS>
1460         </PORT>
1461         <PORT DIR="I" LEFT="0" NAME="S01_AXI_wlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
1462           <CONNECTIONS>
1463             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WLAST"/>
1464           </CONNECTIONS>
1465         </PORT>
1466         <PORT DIR="O" LEFT="0" NAME="S01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
1467           <CONNECTIONS>
1468             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WREADY"/>
1469           </CONNECTIONS>
1470         </PORT>
1471         <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
1472           <CONNECTIONS>
1473             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WSTRB"/>
1474           </CONNECTIONS>
1475         </PORT>
1476         <PORT DIR="I" LEFT="0" NAME="S01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
1477           <CONNECTIONS>
1478             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_IC_WVALID"/>
1479           </CONNECTIONS>
1480         </PORT>
1481       </PORTS>
1482       <BUSINTERFACES>
1483         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="S00_AXI" TYPE="SLAVE">
1484           <PORTMAPS>
1485             <PORTMAP PHYSICAL="S00_AXI_araddr"/>
1486             <PORTMAP PHYSICAL="S00_AXI_arburst"/>
1487             <PORTMAP PHYSICAL="S00_AXI_arcache"/>
1488             <PORTMAP PHYSICAL="S00_AXI_arid"/>
1489             <PORTMAP PHYSICAL="S00_AXI_arlen"/>
1490             <PORTMAP PHYSICAL="S00_AXI_arlock"/>
1491             <PORTMAP PHYSICAL="S00_AXI_arprot"/>
1492             <PORTMAP PHYSICAL="S00_AXI_arqos"/>
1493             <PORTMAP PHYSICAL="S00_AXI_arready"/>
1494             <PORTMAP PHYSICAL="S00_AXI_arsize"/>
1495             <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
1496             <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
1497             <PORTMAP PHYSICAL="S00_AXI_awburst"/>
1498             <PORTMAP PHYSICAL="S00_AXI_awcache"/>
1499             <PORTMAP PHYSICAL="S00_AXI_awid"/>
1500             <PORTMAP PHYSICAL="S00_AXI_awlen"/>
1501             <PORTMAP PHYSICAL="S00_AXI_awlock"/>
1502             <PORTMAP PHYSICAL="S00_AXI_awprot"/>
1503             <PORTMAP PHYSICAL="S00_AXI_awqos"/>
1504             <PORTMAP PHYSICAL="S00_AXI_awready"/>
1505             <PORTMAP PHYSICAL="S00_AXI_awsize"/>
1506             <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
1507             <PORTMAP PHYSICAL="S00_AXI_bid"/>
1508             <PORTMAP PHYSICAL="S00_AXI_bready"/>
1509             <PORTMAP PHYSICAL="S00_AXI_bresp"/>
1510             <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
1511             <PORTMAP PHYSICAL="S00_AXI_rdata"/>
1512             <PORTMAP PHYSICAL="S00_AXI_rid"/>
1513             <PORTMAP PHYSICAL="S00_AXI_rlast"/>
1514             <PORTMAP PHYSICAL="S00_AXI_rready"/>
1515             <PORTMAP PHYSICAL="S00_AXI_rresp"/>
1516             <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
1517             <PORTMAP PHYSICAL="S00_AXI_wdata"/>
1518             <PORTMAP PHYSICAL="S00_AXI_wlast"/>
1519             <PORTMAP PHYSICAL="S00_AXI_wready"/>
1520             <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
1521             <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
1522           </PORTMAPS>
1523         </BUSINTERFACE>
1524         <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
1525           <PORTMAPS>
1526             <PORTMAP PHYSICAL="M00_AXI_awid"/>
1527             <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
1528             <PORTMAP PHYSICAL="M00_AXI_awlen"/>
1529             <PORTMAP PHYSICAL="M00_AXI_awsize"/>
1530             <PORTMAP PHYSICAL="M00_AXI_awburst"/>
1531             <PORTMAP PHYSICAL="M00_AXI_awlock"/>
1532             <PORTMAP PHYSICAL="M00_AXI_awcache"/>
1533             <PORTMAP PHYSICAL="M00_AXI_awprot"/>
1534             <PORTMAP PHYSICAL="M00_AXI_awqos"/>
1535             <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
1536             <PORTMAP PHYSICAL="M00_AXI_awready"/>
1537             <PORTMAP PHYSICAL="M00_AXI_wdata"/>
1538             <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
1539             <PORTMAP PHYSICAL="M00_AXI_wlast"/>
1540             <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
1541             <PORTMAP PHYSICAL="M00_AXI_wready"/>
1542             <PORTMAP PHYSICAL="M00_AXI_bready"/>
1543             <PORTMAP PHYSICAL="M00_AXI_bid"/>
1544             <PORTMAP PHYSICAL="M00_AXI_bresp"/>
1545             <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
1546             <PORTMAP PHYSICAL="M00_AXI_arid"/>
1547             <PORTMAP PHYSICAL="M00_AXI_araddr"/>
1548             <PORTMAP PHYSICAL="M00_AXI_arlen"/>
1549             <PORTMAP PHYSICAL="M00_AXI_arsize"/>
1550             <PORTMAP PHYSICAL="M00_AXI_arburst"/>
1551             <PORTMAP PHYSICAL="M00_AXI_arlock"/>
1552             <PORTMAP PHYSICAL="M00_AXI_arcache"/>
1553             <PORTMAP PHYSICAL="M00_AXI_arprot"/>
1554             <PORTMAP PHYSICAL="M00_AXI_arqos"/>
1555             <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
1556             <PORTMAP PHYSICAL="M00_AXI_arready"/>
1557             <PORTMAP PHYSICAL="M00_AXI_rready"/>
1558             <PORTMAP PHYSICAL="M00_AXI_rid"/>
1559             <PORTMAP PHYSICAL="M00_AXI_rdata"/>
1560             <PORTMAP PHYSICAL="M00_AXI_rresp"/>
1561             <PORTMAP PHYSICAL="M00_AXI_rlast"/>
1562             <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
1563           </PORTMAPS>
1564         </BUSINTERFACE>
1565         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="S01_AXI" TYPE="SLAVE">
1566           <PORTMAPS>
1567             <PORTMAP PHYSICAL="S01_AXI_araddr"/>
1568             <PORTMAP PHYSICAL="S01_AXI_arburst"/>
1569             <PORTMAP PHYSICAL="S01_AXI_arcache"/>
1570             <PORTMAP PHYSICAL="S01_AXI_arid"/>
1571             <PORTMAP PHYSICAL="S01_AXI_arlen"/>
1572             <PORTMAP PHYSICAL="S01_AXI_arlock"/>
1573             <PORTMAP PHYSICAL="S01_AXI_arprot"/>
1574             <PORTMAP PHYSICAL="S01_AXI_arqos"/>
1575             <PORTMAP PHYSICAL="S01_AXI_arready"/>
1576             <PORTMAP PHYSICAL="S01_AXI_arsize"/>
1577             <PORTMAP PHYSICAL="S01_AXI_arvalid"/>
1578             <PORTMAP PHYSICAL="S01_AXI_awaddr"/>
1579             <PORTMAP PHYSICAL="S01_AXI_awburst"/>
1580             <PORTMAP PHYSICAL="S01_AXI_awcache"/>
1581             <PORTMAP PHYSICAL="S01_AXI_awid"/>
1582             <PORTMAP PHYSICAL="S01_AXI_awlen"/>
1583             <PORTMAP PHYSICAL="S01_AXI_awlock"/>
1584             <PORTMAP PHYSICAL="S01_AXI_awprot"/>
1585             <PORTMAP PHYSICAL="S01_AXI_awqos"/>
1586             <PORTMAP PHYSICAL="S01_AXI_awready"/>
1587             <PORTMAP PHYSICAL="S01_AXI_awsize"/>
1588             <PORTMAP PHYSICAL="S01_AXI_awvalid"/>
1589             <PORTMAP PHYSICAL="S01_AXI_bid"/>
1590             <PORTMAP PHYSICAL="S01_AXI_bready"/>
1591             <PORTMAP PHYSICAL="S01_AXI_bresp"/>
1592             <PORTMAP PHYSICAL="S01_AXI_bvalid"/>
1593             <PORTMAP PHYSICAL="S01_AXI_rdata"/>
1594             <PORTMAP PHYSICAL="S01_AXI_rid"/>
1595             <PORTMAP PHYSICAL="S01_AXI_rlast"/>
1596             <PORTMAP PHYSICAL="S01_AXI_rready"/>
1597             <PORTMAP PHYSICAL="S01_AXI_rresp"/>
1598             <PORTMAP PHYSICAL="S01_AXI_rvalid"/>
1599             <PORTMAP PHYSICAL="S01_AXI_wdata"/>
1600             <PORTMAP PHYSICAL="S01_AXI_wlast"/>
1601             <PORTMAP PHYSICAL="S01_AXI_wready"/>
1602             <PORTMAP PHYSICAL="S01_AXI_wstrb"/>
1603             <PORTMAP PHYSICAL="S01_AXI_wvalid"/>
1604           </PORTMAPS>
1605         </BUSINTERFACE>
1606       </BUSINTERFACES>
1607     </MODULE>
1608     <MODULE FULLNAME="/axi_timer_0" HWVERSION="2.0" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_timer" VLNV="xilinx.com:ip:axi_timer:2.0">
1609       <DOCUMENTS>
1610         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v2_0;d=pg079-axi-timer.pdf"/>
1611       </DOCUMENTS>
1612       <PARAMETERS>
1613         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
1614         <PARAMETER NAME="C_COUNT_WIDTH" VALUE="32"/>
1615         <PARAMETER NAME="C_ONE_TIMER_ONLY" VALUE="0"/>
1616         <PARAMETER NAME="C_TRIG0_ASSERT" VALUE="&quot;1&quot;"/>
1617         <PARAMETER NAME="C_TRIG1_ASSERT" VALUE="&quot;1&quot;"/>
1618         <PARAMETER NAME="C_GEN0_ASSERT" VALUE="&quot;1&quot;"/>
1619         <PARAMETER NAME="C_GEN1_ASSERT" VALUE="&quot;1&quot;"/>
1620         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
1621         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="5"/>
1622         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_timer_0_0"/>
1623         <PARAMETER NAME="TRIG0_ASSERT" VALUE="Active_High"/>
1624         <PARAMETER NAME="TRIG1_ASSERT" VALUE="Active_High"/>
1625         <PARAMETER NAME="GEN0_ASSERT" VALUE="Active_High"/>
1626         <PARAMETER NAME="GEN1_ASSERT" VALUE="Active_High"/>
1627         <PARAMETER NAME="COUNT_WIDTH" VALUE="32"/>
1628         <PARAMETER NAME="mode_64bit" VALUE="0"/>
1629         <PARAMETER NAME="enable_timer2" VALUE="1"/>
1630         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
1631         <PARAMETER NAME="C_BASEADDR" VALUE="0x41C00000"/>
1632         <PARAMETER NAME="C_HIGHADDR" VALUE="0x41C0FFFF"/>
1633       </PARAMETERS>
1634       <PORTS>
1635         <PORT DIR="I" NAME="capturetrig0" SIGIS="undef"/>
1636         <PORT DIR="I" NAME="capturetrig1" SIGIS="undef"/>
1637         <PORT DIR="O" NAME="generateout0" SIGIS="undef"/>
1638         <PORT DIR="O" NAME="generateout1" SIGIS="undef"/>
1639         <PORT DIR="O" NAME="pwm0" SIGIS="undef"/>
1640         <PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_interrupt">
1641           <CONNECTIONS>
1642             <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
1643           </CONNECTIONS>
1644         </PORT>
1645         <PORT DIR="I" NAME="freeze" SIGIS="undef"/>
1646         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
1647           <CONNECTIONS>
1648             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
1649           </CONNECTIONS>
1650         </PORT>
1651         <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
1652           <CONNECTIONS>
1653             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
1654           </CONNECTIONS>
1655         </PORT>
1656         <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
1657           <CONNECTIONS>
1658             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awaddr"/>
1659           </CONNECTIONS>
1660         </PORT>
1661         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
1662           <CONNECTIONS>
1663             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awvalid"/>
1664           </CONNECTIONS>
1665         </PORT>
1666         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
1667           <CONNECTIONS>
1668             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_awready"/>
1669           </CONNECTIONS>
1670         </PORT>
1671         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
1672           <CONNECTIONS>
1673             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wdata"/>
1674           </CONNECTIONS>
1675         </PORT>
1676         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
1677           <CONNECTIONS>
1678             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wstrb"/>
1679           </CONNECTIONS>
1680         </PORT>
1681         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
1682           <CONNECTIONS>
1683             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wvalid"/>
1684           </CONNECTIONS>
1685         </PORT>
1686         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
1687           <CONNECTIONS>
1688             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_wready"/>
1689           </CONNECTIONS>
1690         </PORT>
1691         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
1692           <CONNECTIONS>
1693             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bresp"/>
1694           </CONNECTIONS>
1695         </PORT>
1696         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
1697           <CONNECTIONS>
1698             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bvalid"/>
1699           </CONNECTIONS>
1700         </PORT>
1701         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
1702           <CONNECTIONS>
1703             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_bready"/>
1704           </CONNECTIONS>
1705         </PORT>
1706         <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
1707           <CONNECTIONS>
1708             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_araddr"/>
1709           </CONNECTIONS>
1710         </PORT>
1711         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
1712           <CONNECTIONS>
1713             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arvalid"/>
1714           </CONNECTIONS>
1715         </PORT>
1716         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
1717           <CONNECTIONS>
1718             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_arready"/>
1719           </CONNECTIONS>
1720         </PORT>
1721         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
1722           <CONNECTIONS>
1723             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rdata"/>
1724           </CONNECTIONS>
1725         </PORT>
1726         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
1727           <CONNECTIONS>
1728             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rresp"/>
1729           </CONNECTIONS>
1730         </PORT>
1731         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
1732           <CONNECTIONS>
1733             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rvalid"/>
1734           </CONNECTIONS>
1735         </PORT>
1736         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
1737           <CONNECTIONS>
1738             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_AXI_rready"/>
1739           </CONNECTIONS>
1740         </PORT>
1741       </PORTS>
1742       <BUSINTERFACES>
1743         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="S_AXI" TYPE="SLAVE">
1744           <PORTMAPS>
1745             <PORTMAP PHYSICAL="s_axi_araddr"/>
1746             <PORTMAP PHYSICAL="s_axi_arready"/>
1747             <PORTMAP PHYSICAL="s_axi_arvalid"/>
1748             <PORTMAP PHYSICAL="s_axi_awaddr"/>
1749             <PORTMAP PHYSICAL="s_axi_awready"/>
1750             <PORTMAP PHYSICAL="s_axi_awvalid"/>
1751             <PORTMAP PHYSICAL="s_axi_bready"/>
1752             <PORTMAP PHYSICAL="s_axi_bresp"/>
1753             <PORTMAP PHYSICAL="s_axi_bvalid"/>
1754             <PORTMAP PHYSICAL="s_axi_rdata"/>
1755             <PORTMAP PHYSICAL="s_axi_rready"/>
1756             <PORTMAP PHYSICAL="s_axi_rresp"/>
1757             <PORTMAP PHYSICAL="s_axi_rvalid"/>
1758             <PORTMAP PHYSICAL="s_axi_wdata"/>
1759             <PORTMAP PHYSICAL="s_axi_wready"/>
1760             <PORTMAP PHYSICAL="s_axi_wstrb"/>
1761             <PORTMAP PHYSICAL="s_axi_wvalid"/>
1762           </PORTMAPS>
1763         </BUSINTERFACE>
1764       </BUSINTERFACES>
1765       <INTERRUPTINFO TYPE="SOURCE">
1766         <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="0"/>
1767       </INTERRUPTINFO>
1768     </MODULE>
1769     <MODULE FULLNAME="/axi_uartlite_0" HWVERSION="2.0" INSTANCE="axi_uartlite_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite" VLNV="xilinx.com:ip:axi_uartlite:2.0">
1770       <DOCUMENTS>
1771         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_uartlite;v=v2_0;d=pg142-axi-uartlite.pdf"/>
1772       </DOCUMENTS>
1773       <PARAMETERS>
1774         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
1775         <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
1776         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="4"/>
1777         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
1778         <PARAMETER NAME="C_BAUDRATE" VALUE="115200"/>
1779         <PARAMETER NAME="C_DATA_BITS" VALUE="8"/>
1780         <PARAMETER NAME="C_USE_PARITY" VALUE="0"/>
1781         <PARAMETER NAME="C_ODD_PARITY" VALUE="0"/>
1782         <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ_d" VALUE="100"/>
1783         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_axi_uartlite_0_0"/>
1784         <PARAMETER NAME="PARITY" VALUE="No_Parity"/>
1785         <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
1786         <PARAMETER NAME="UARTLITE_BOARD_INTERFACE" VALUE="rs232_uart"/>
1787         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
1788         <PARAMETER NAME="C_BASEADDR" VALUE="0x40600000"/>
1789         <PARAMETER NAME="C_HIGHADDR" VALUE="0x4060FFFF"/>
1790       </PARAMETERS>
1791       <PORTS>
1792         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
1793           <CONNECTIONS>
1794             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
1795           </CONNECTIONS>
1796         </PORT>
1797         <PORT DIR="I" NAME="s_axi_aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
1798           <CONNECTIONS>
1799             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
1800           </CONNECTIONS>
1801         </PORT>
1802         <PORT DIR="O" NAME="interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_uartlite_0_interrupt">
1803           <CONNECTIONS>
1804             <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
1805           </CONNECTIONS>
1806         </PORT>
1807         <PORT DIR="I" LEFT="3" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
1808           <CONNECTIONS>
1809             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awaddr"/>
1810           </CONNECTIONS>
1811         </PORT>
1812         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
1813           <CONNECTIONS>
1814             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awvalid"/>
1815           </CONNECTIONS>
1816         </PORT>
1817         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
1818           <CONNECTIONS>
1819             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_awready"/>
1820           </CONNECTIONS>
1821         </PORT>
1822         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
1823           <CONNECTIONS>
1824             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wdata"/>
1825           </CONNECTIONS>
1826         </PORT>
1827         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
1828           <CONNECTIONS>
1829             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wstrb"/>
1830           </CONNECTIONS>
1831         </PORT>
1832         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
1833           <CONNECTIONS>
1834             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wvalid"/>
1835           </CONNECTIONS>
1836         </PORT>
1837         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
1838           <CONNECTIONS>
1839             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_wready"/>
1840           </CONNECTIONS>
1841         </PORT>
1842         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
1843           <CONNECTIONS>
1844             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bresp"/>
1845           </CONNECTIONS>
1846         </PORT>
1847         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
1848           <CONNECTIONS>
1849             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bvalid"/>
1850           </CONNECTIONS>
1851         </PORT>
1852         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
1853           <CONNECTIONS>
1854             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_bready"/>
1855           </CONNECTIONS>
1856         </PORT>
1857         <PORT DIR="I" LEFT="3" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
1858           <CONNECTIONS>
1859             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_araddr"/>
1860           </CONNECTIONS>
1861         </PORT>
1862         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
1863           <CONNECTIONS>
1864             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arvalid"/>
1865           </CONNECTIONS>
1866         </PORT>
1867         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
1868           <CONNECTIONS>
1869             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_arready"/>
1870           </CONNECTIONS>
1871         </PORT>
1872         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
1873           <CONNECTIONS>
1874             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rdata"/>
1875           </CONNECTIONS>
1876         </PORT>
1877         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
1878           <CONNECTIONS>
1879             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rresp"/>
1880           </CONNECTIONS>
1881         </PORT>
1882         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
1883           <CONNECTIONS>
1884             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rvalid"/>
1885           </CONNECTIONS>
1886         </PORT>
1887         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
1888           <CONNECTIONS>
1889             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_AXI_rready"/>
1890           </CONNECTIONS>
1891         </PORT>
1892         <PORT DIR="I" NAME="rx" SIGIS="undef"/>
1893         <PORT DIR="O" NAME="tx" SIGIS="undef"/>
1894       </PORTS>
1895       <BUSINTERFACES>
1896         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
1897           <PORTMAPS>
1898             <PORTMAP PHYSICAL="s_axi_araddr"/>
1899             <PORTMAP PHYSICAL="s_axi_arready"/>
1900             <PORTMAP PHYSICAL="s_axi_arvalid"/>
1901             <PORTMAP PHYSICAL="s_axi_awaddr"/>
1902             <PORTMAP PHYSICAL="s_axi_awready"/>
1903             <PORTMAP PHYSICAL="s_axi_awvalid"/>
1904             <PORTMAP PHYSICAL="s_axi_bready"/>
1905             <PORTMAP PHYSICAL="s_axi_bresp"/>
1906             <PORTMAP PHYSICAL="s_axi_bvalid"/>
1907             <PORTMAP PHYSICAL="s_axi_rdata"/>
1908             <PORTMAP PHYSICAL="s_axi_rready"/>
1909             <PORTMAP PHYSICAL="s_axi_rresp"/>
1910             <PORTMAP PHYSICAL="s_axi_rvalid"/>
1911             <PORTMAP PHYSICAL="s_axi_wdata"/>
1912             <PORTMAP PHYSICAL="s_axi_wready"/>
1913             <PORTMAP PHYSICAL="s_axi_wstrb"/>
1914             <PORTMAP PHYSICAL="s_axi_wvalid"/>
1915           </PORTMAPS>
1916         </BUSINTERFACE>
1917         <BUSINTERFACE BUSNAME="axi_uartlite_0_UART" NAME="UART" TYPE="INITIATOR">
1918           <PORTMAPS>
1919             <PORTMAP PHYSICAL="rx"/>
1920             <PORTMAP PHYSICAL="tx"/>
1921           </PORTMAPS>
1922         </BUSINTERFACE>
1923       </BUSINTERFACES>
1924       <INTERRUPTINFO TYPE="SOURCE">
1925         <TARGET INSTANCE="axi_intc_0" INTC_INDEX="0" PRIORITY="1"/>
1926       </INTERRUPTINFO>
1927     </MODULE>
1928     <MODULE FULLNAME="/mdm_1" HWVERSION="3.2" INSTANCE="mdm_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="DEBUG" MODTYPE="mdm" VLNV="xilinx.com:ip:mdm:3.2">
1929       <DOCUMENTS>
1930         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=mdm;v=v3_2;d=pg115-mdm.pdf"/>
1931       </DOCUMENTS>
1932       <PARAMETERS>
1933         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
1934         <PARAMETER NAME="C_JTAG_CHAIN" VALUE="2"/>
1935         <PARAMETER NAME="C_USE_BSCAN" VALUE="0"/>
1936         <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
1937         <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
1938         <PARAMETER NAME="C_MB_DBG_PORTS" VALUE="1"/>
1939         <PARAMETER NAME="C_USE_UART" VALUE="0"/>
1940         <PARAMETER NAME="C_DBG_REG_ACCESS" VALUE="0"/>
1941         <PARAMETER NAME="C_DBG_MEM_ACCESS" VALUE="0"/>
1942         <PARAMETER NAME="C_USE_CROSS_TRIGGER" VALUE="0"/>
1943         <PARAMETER NAME="C_TRACE_OUTPUT" VALUE="0"/>
1944         <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
1945         <PARAMETER NAME="C_TRACE_CLK_FREQ_HZ" VALUE="200000000"/>
1946         <PARAMETER NAME="C_TRACE_CLK_OUT_PHASE" VALUE="90"/>
1947         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
1948         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
1949         <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
1950         <PARAMETER NAME="C_M_AXI_ADDR_WIDTH" VALUE="32"/>
1951         <PARAMETER NAME="C_M_AXI_DATA_WIDTH" VALUE="32"/>
1952         <PARAMETER NAME="C_M_AXI_THREAD_ID_WIDTH" VALUE="1"/>
1953         <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
1954         <PARAMETER NAME="C_M_AXIS_DATA_WIDTH" VALUE="32"/>
1955         <PARAMETER NAME="C_M_AXIS_ID_WIDTH" VALUE="7"/>
1956         <PARAMETER NAME="C_XMTC" VALUE="0"/>
1957         <PARAMETER NAME="C_BRK" VALUE="0"/>
1958         <PARAMETER NAME="C_TRIG_IN_PORTS" VALUE="1"/>
1959         <PARAMETER NAME="C_TRIG_OUT_PORTS" VALUE="1"/>
1960         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mdm_1_0"/>
1961         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
1962       </PARAMETERS>
1963       <PORTS>
1964         <PORT DIR="O" NAME="Debug_SYS_Rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
1965           <CONNECTIONS>
1966             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_debug_sys_rst"/>
1967           </CONNECTIONS>
1968         </PORT>
1969         <PORT DIR="O" NAME="Dbg_Clk_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
1970           <CONNECTIONS>
1971             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Clk"/>
1972           </CONNECTIONS>
1973         </PORT>
1974         <PORT DIR="O" NAME="Dbg_TDI_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
1975           <CONNECTIONS>
1976             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDI"/>
1977           </CONNECTIONS>
1978         </PORT>
1979         <PORT DIR="I" NAME="Dbg_TDO_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
1980           <CONNECTIONS>
1981             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDO"/>
1982           </CONNECTIONS>
1983         </PORT>
1984         <PORT DIR="O" LEFT="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
1985           <CONNECTIONS>
1986             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Reg_En"/>
1987           </CONNECTIONS>
1988         </PORT>
1989         <PORT DIR="O" NAME="Dbg_Capture_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
1990           <CONNECTIONS>
1991             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Capture"/>
1992           </CONNECTIONS>
1993         </PORT>
1994         <PORT DIR="O" NAME="Dbg_Shift_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
1995           <CONNECTIONS>
1996             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Shift"/>
1997           </CONNECTIONS>
1998         </PORT>
1999         <PORT DIR="O" NAME="Dbg_Update_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
2000           <CONNECTIONS>
2001             <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Update"/>
2002           </CONNECTIONS>
2003         </PORT>
2004         <PORT DIR="O" NAME="Dbg_Rst_0" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
2005           <CONNECTIONS>
2006             <CONNECTION INSTANCE="microblaze_0" PORT="Debug_Rst"/>
2007           </CONNECTIONS>
2008         </PORT>
2009       </PORTS>
2010       <BUSINTERFACES>
2011         <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="MBDEBUG_0" TYPE="INITIATOR">
2012           <PORTMAPS>
2013             <PORTMAP PHYSICAL="Dbg_Capture_0"/>
2014             <PORTMAP PHYSICAL="Dbg_Clk_0"/>
2015             <PORTMAP PHYSICAL="Dbg_Reg_En_0"/>
2016             <PORTMAP PHYSICAL="Dbg_Rst_0"/>
2017             <PORTMAP PHYSICAL="Dbg_Shift_0"/>
2018             <PORTMAP PHYSICAL="Dbg_TDI_0"/>
2019             <PORTMAP PHYSICAL="Dbg_TDO_0"/>
2020             <PORTMAP PHYSICAL="Dbg_Update_0"/>
2021           </PORTMAPS>
2022         </BUSINTERFACE>
2023       </BUSINTERFACES>
2024       <MEMORYMAP/>
2025       <PERIPHERALS>
2026         <PERIPHERAL INSTANCE="microblaze_0"/>
2027       </PERIPHERALS>
2028     </MODULE>
2029     <MODULE FULLNAME="/microblaze_0" HWVERSION="9.4" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" IS_ENABLE="1" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="microblaze" VLNV="xilinx.com:ip:microblaze:9.4">
2030       <DOCUMENTS>
2031         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/rdoc?v=2014.3;d=ug984-vivado-microblaze-ref.pdf"/>
2032       </DOCUMENTS>
2033       <PARAMETERS>
2034         <PARAMETER NAME="C_SCO" VALUE="0"/>
2035         <PARAMETER NAME="C_FREQ" VALUE="100000000"/>
2036         <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
2037         <PARAMETER NAME="C_NUM_SYNC_FF_CLK" VALUE="2"/>
2038         <PARAMETER NAME="C_NUM_SYNC_FF_CLK_IRQ" VALUE="1"/>
2039         <PARAMETER NAME="C_NUM_SYNC_FF_CLK_DEBUG" VALUE="2"/>
2040         <PARAMETER NAME="C_NUM_SYNC_FF_DBG_CLK" VALUE="1"/>
2041         <PARAMETER NAME="C_FAULT_TOLERANT" VALUE="0"/>
2042         <PARAMETER NAME="C_ECC_USE_CE_EXCEPTION" VALUE="0"/>
2043         <PARAMETER NAME="C_LOCKSTEP_SLAVE" VALUE="0"/>
2044         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
2045         <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
2046         <PARAMETER NAME="C_INSTANCE" VALUE="base_microblaze_design_microblaze_0_0"/>
2047         <PARAMETER NAME="C_AVOID_PRIMITIVES" VALUE="0"/>
2048         <PARAMETER NAME="C_AREA_OPTIMIZED" VALUE="0"/>
2049         <PARAMETER NAME="C_OPTIMIZATION" VALUE="0"/>
2050         <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
2051         <PARAMETER NAME="C_BASE_VECTORS" VALUE="0x00000000"/>
2052         <PARAMETER NAME="C_M_AXI_DP_THREAD_ID_WIDTH" VALUE="1"/>
2053         <PARAMETER NAME="C_M_AXI_DP_DATA_WIDTH" VALUE="32"/>
2054         <PARAMETER NAME="C_M_AXI_DP_ADDR_WIDTH" VALUE="32"/>
2055         <PARAMETER NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" VALUE="0"/>
2056         <PARAMETER NAME="C_M_AXI_D_BUS_EXCEPTION" VALUE="1"/>
2057         <PARAMETER NAME="C_M_AXI_IP_THREAD_ID_WIDTH" VALUE="1"/>
2058         <PARAMETER NAME="C_M_AXI_IP_DATA_WIDTH" VALUE="32"/>
2059         <PARAMETER NAME="C_M_AXI_IP_ADDR_WIDTH" VALUE="32"/>
2060         <PARAMETER NAME="C_M_AXI_I_BUS_EXCEPTION" VALUE="1"/>
2061         <PARAMETER NAME="C_D_LMB" VALUE="1"/>
2062         <PARAMETER NAME="C_D_AXI" VALUE="1"/>
2063         <PARAMETER NAME="C_I_LMB" VALUE="1"/>
2064         <PARAMETER NAME="C_I_AXI" VALUE="0"/>
2065         <PARAMETER NAME="C_USE_MSR_INSTR" VALUE="1"/>
2066         <PARAMETER NAME="C_USE_PCMP_INSTR" VALUE="1"/>
2067         <PARAMETER NAME="C_USE_BARREL" VALUE="1"/>
2068         <PARAMETER NAME="C_USE_DIV" VALUE="1"/>
2069         <PARAMETER NAME="C_USE_HW_MUL" VALUE="2"/>
2070         <PARAMETER NAME="C_USE_FPU" VALUE="2"/>
2071         <PARAMETER NAME="C_USE_REORDER_INSTR" VALUE="1"/>
2072         <PARAMETER NAME="C_UNALIGNED_EXCEPTIONS" VALUE="1"/>
2073         <PARAMETER NAME="C_ILL_OPCODE_EXCEPTION" VALUE="1"/>
2074         <PARAMETER NAME="C_DIV_ZERO_EXCEPTION" VALUE="1"/>
2075         <PARAMETER NAME="C_FPU_EXCEPTION" VALUE="1"/>
2076         <PARAMETER NAME="C_FSL_LINKS" VALUE="0"/>
2077         <PARAMETER NAME="C_USE_EXTENDED_FSL_INSTR" VALUE="0"/>
2078         <PARAMETER NAME="C_FSL_EXCEPTION" VALUE="0"/>
2079         <PARAMETER NAME="C_USE_STACK_PROTECTION" VALUE="1"/>
2080         <PARAMETER NAME="C_USE_INTERRUPT" VALUE="1"/>
2081         <PARAMETER NAME="C_USE_EXT_BRK" VALUE="0"/>
2082         <PARAMETER NAME="C_USE_EXT_NM_BRK" VALUE="0"/>
2083         <PARAMETER NAME="C_USE_MMU" VALUE="0"/>
2084         <PARAMETER NAME="C_MMU_DTLB_SIZE" VALUE="4"/>
2085         <PARAMETER NAME="C_MMU_ITLB_SIZE" VALUE="2"/>
2086         <PARAMETER NAME="C_MMU_TLB_ACCESS" VALUE="3"/>
2087         <PARAMETER NAME="C_MMU_ZONES" VALUE="2"/>
2088         <PARAMETER NAME="C_MMU_PRIVILEGED_INSTR" VALUE="0"/>
2089         <PARAMETER NAME="C_USE_BRANCH_TARGET_CACHE" VALUE="1"/>
2090         <PARAMETER NAME="C_BRANCH_TARGET_CACHE_SIZE" VALUE="0"/>
2091         <PARAMETER NAME="C_PC_WIDTH" VALUE="32"/>
2092         <PARAMETER NAME="C_PVR" VALUE="0"/>
2093         <PARAMETER NAME="C_PVR_USER1" VALUE="0x00"/>
2094         <PARAMETER NAME="C_PVR_USER2" VALUE="0x00000000"/>
2095         <PARAMETER NAME="C_DYNAMIC_BUS_SIZING" VALUE="0"/>
2096         <PARAMETER NAME="C_RESET_MSR" VALUE="0x00000000"/>
2097         <PARAMETER NAME="C_OPCODE_0x0_ILLEGAL" VALUE="1"/>
2098         <PARAMETER NAME="C_DEBUG_ENABLED" VALUE="1"/>
2099         <PARAMETER NAME="C_NUMBER_OF_PC_BRK" VALUE="8"/>
2100         <PARAMETER NAME="C_NUMBER_OF_RD_ADDR_BRK" VALUE="2"/>
2101         <PARAMETER NAME="C_NUMBER_OF_WR_ADDR_BRK" VALUE="2"/>
2102         <PARAMETER NAME="C_DEBUG_EVENT_COUNTERS" VALUE="5"/>
2103         <PARAMETER NAME="C_DEBUG_LATENCY_COUNTERS" VALUE="1"/>
2104         <PARAMETER NAME="C_DEBUG_COUNTER_WIDTH" VALUE="32"/>
2105         <PARAMETER NAME="C_DEBUG_TRACE_SIZE" VALUE="8192"/>
2106         <PARAMETER NAME="C_DEBUG_EXTERNAL_TRACE" VALUE="0"/>
2107         <PARAMETER NAME="C_DEBUG_PROFILE_SIZE" VALUE="0"/>
2108         <PARAMETER NAME="C_INTERRUPT_IS_EDGE" VALUE="0"/>
2109         <PARAMETER NAME="C_EDGE_IS_POSITIVE" VALUE="1"/>
2110         <PARAMETER NAME="C_ASYNC_INTERRUPT" VALUE="1"/>
2111         <PARAMETER NAME="C_M0_AXIS_DATA_WIDTH" VALUE="32"/>
2112         <PARAMETER NAME="C_S0_AXIS_DATA_WIDTH" VALUE="32"/>
2113         <PARAMETER NAME="C_M1_AXIS_DATA_WIDTH" VALUE="32"/>
2114         <PARAMETER NAME="C_S1_AXIS_DATA_WIDTH" VALUE="32"/>
2115         <PARAMETER NAME="C_M2_AXIS_DATA_WIDTH" VALUE="32"/>
2116         <PARAMETER NAME="C_S2_AXIS_DATA_WIDTH" VALUE="32"/>
2117         <PARAMETER NAME="C_M3_AXIS_DATA_WIDTH" VALUE="32"/>
2118         <PARAMETER NAME="C_S3_AXIS_DATA_WIDTH" VALUE="32"/>
2119         <PARAMETER NAME="C_M4_AXIS_DATA_WIDTH" VALUE="32"/>
2120         <PARAMETER NAME="C_S4_AXIS_DATA_WIDTH" VALUE="32"/>
2121         <PARAMETER NAME="C_M5_AXIS_DATA_WIDTH" VALUE="32"/>
2122         <PARAMETER NAME="C_S5_AXIS_DATA_WIDTH" VALUE="32"/>
2123         <PARAMETER NAME="C_M6_AXIS_DATA_WIDTH" VALUE="32"/>
2124         <PARAMETER NAME="C_S6_AXIS_DATA_WIDTH" VALUE="32"/>
2125         <PARAMETER NAME="C_M7_AXIS_DATA_WIDTH" VALUE="32"/>
2126         <PARAMETER NAME="C_S7_AXIS_DATA_WIDTH" VALUE="32"/>
2127         <PARAMETER NAME="C_M8_AXIS_DATA_WIDTH" VALUE="32"/>
2128         <PARAMETER NAME="C_S8_AXIS_DATA_WIDTH" VALUE="32"/>
2129         <PARAMETER NAME="C_M9_AXIS_DATA_WIDTH" VALUE="32"/>
2130         <PARAMETER NAME="C_S9_AXIS_DATA_WIDTH" VALUE="32"/>
2131         <PARAMETER NAME="C_M10_AXIS_DATA_WIDTH" VALUE="32"/>
2132         <PARAMETER NAME="C_S10_AXIS_DATA_WIDTH" VALUE="32"/>
2133         <PARAMETER NAME="C_M11_AXIS_DATA_WIDTH" VALUE="32"/>
2134         <PARAMETER NAME="C_S11_AXIS_DATA_WIDTH" VALUE="32"/>
2135         <PARAMETER NAME="C_M12_AXIS_DATA_WIDTH" VALUE="32"/>
2136         <PARAMETER NAME="C_S12_AXIS_DATA_WIDTH" VALUE="32"/>
2137         <PARAMETER NAME="C_M13_AXIS_DATA_WIDTH" VALUE="32"/>
2138         <PARAMETER NAME="C_S13_AXIS_DATA_WIDTH" VALUE="32"/>
2139         <PARAMETER NAME="C_M14_AXIS_DATA_WIDTH" VALUE="32"/>
2140         <PARAMETER NAME="C_S14_AXIS_DATA_WIDTH" VALUE="32"/>
2141         <PARAMETER NAME="C_M15_AXIS_DATA_WIDTH" VALUE="32"/>
2142         <PARAMETER NAME="C_S15_AXIS_DATA_WIDTH" VALUE="32"/>
2143         <PARAMETER NAME="C_ICACHE_BASEADDR" VALUE="0x80000000"/>
2144         <PARAMETER NAME="C_ICACHE_HIGHADDR" VALUE="0xbfffffff"/>
2145         <PARAMETER NAME="C_USE_ICACHE" VALUE="1"/>
2146         <PARAMETER NAME="C_ALLOW_ICACHE_WR" VALUE="1"/>
2147         <PARAMETER NAME="C_ADDR_TAG_BITS" VALUE="15"/>
2148         <PARAMETER NAME="C_CACHE_BYTE_SIZE" VALUE="32768"/>
2149         <PARAMETER NAME="C_ICACHE_LINE_LEN" VALUE="8"/>
2150         <PARAMETER NAME="C_ICACHE_ALWAYS_USED" VALUE="1"/>
2151         <PARAMETER NAME="C_ICACHE_STREAMS" VALUE="1"/>
2152         <PARAMETER NAME="C_ICACHE_VICTIMS" VALUE="8"/>
2153         <PARAMETER NAME="C_ICACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
2154         <PARAMETER NAME="C_ICACHE_DATA_WIDTH" VALUE="0"/>
2155         <PARAMETER NAME="C_M_AXI_IC_THREAD_ID_WIDTH" VALUE="1"/>
2156         <PARAMETER NAME="C_M_AXI_IC_DATA_WIDTH" VALUE="32"/>
2157         <PARAMETER NAME="C_M_AXI_IC_ADDR_WIDTH" VALUE="32"/>
2158         <PARAMETER NAME="C_M_AXI_IC_USER_VALUE" VALUE="31"/>
2159         <PARAMETER NAME="C_M_AXI_IC_AWUSER_WIDTH" VALUE="5"/>
2160         <PARAMETER NAME="C_M_AXI_IC_ARUSER_WIDTH" VALUE="5"/>
2161         <PARAMETER NAME="C_M_AXI_IC_WUSER_WIDTH" VALUE="1"/>
2162         <PARAMETER NAME="C_M_AXI_IC_RUSER_WIDTH" VALUE="1"/>
2163         <PARAMETER NAME="C_M_AXI_IC_BUSER_WIDTH" VALUE="1"/>
2164         <PARAMETER NAME="C_DCACHE_BASEADDR" VALUE="0x80000000"/>
2165         <PARAMETER NAME="C_DCACHE_HIGHADDR" VALUE="0xbfffffff"/>
2166         <PARAMETER NAME="C_USE_DCACHE" VALUE="1"/>
2167         <PARAMETER NAME="C_ALLOW_DCACHE_WR" VALUE="1"/>
2168         <PARAMETER NAME="C_DCACHE_ADDR_TAG" VALUE="15"/>
2169         <PARAMETER NAME="C_DCACHE_BYTE_SIZE" VALUE="32768"/>
2170         <PARAMETER NAME="C_DCACHE_LINE_LEN" VALUE="8"/>
2171         <PARAMETER NAME="C_DCACHE_ALWAYS_USED" VALUE="1"/>
2172         <PARAMETER NAME="C_DCACHE_USE_WRITEBACK" VALUE="1"/>
2173         <PARAMETER NAME="C_DCACHE_VICTIMS" VALUE="8"/>
2174         <PARAMETER NAME="C_DCACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
2175         <PARAMETER NAME="C_DCACHE_DATA_WIDTH" VALUE="0"/>
2176         <PARAMETER NAME="C_M_AXI_DC_THREAD_ID_WIDTH" VALUE="1"/>
2177         <PARAMETER NAME="C_M_AXI_DC_DATA_WIDTH" VALUE="32"/>
2178         <PARAMETER NAME="C_M_AXI_DC_ADDR_WIDTH" VALUE="32"/>
2179         <PARAMETER NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" VALUE="0"/>
2180         <PARAMETER NAME="C_M_AXI_DC_USER_VALUE" VALUE="31"/>
2181         <PARAMETER NAME="C_M_AXI_DC_AWUSER_WIDTH" VALUE="5"/>
2182         <PARAMETER NAME="C_M_AXI_DC_ARUSER_WIDTH" VALUE="5"/>
2183         <PARAMETER NAME="C_M_AXI_DC_WUSER_WIDTH" VALUE="1"/>
2184         <PARAMETER NAME="C_M_AXI_DC_RUSER_WIDTH" VALUE="1"/>
2185         <PARAMETER NAME="C_M_AXI_DC_BUSER_WIDTH" VALUE="1"/>
2186         <PARAMETER NAME="C_TRACE" VALUE="1"/>
2187         <PARAMETER NAME="C_LOCKSTEP_SELECT" VALUE="0"/>
2188         <PARAMETER NAME="C_ENABLE_DISCRETE_PORTS" VALUE="0"/>
2189         <PARAMETER NAME="C_M_AXI_DC_USER_SIGNALS" VALUE="0"/>
2190         <PARAMETER NAME="C_M_AXI_IC_USER_SIGNALS" VALUE="0"/>
2191         <PARAMETER NAME="G_TEMPLATE_LIST" VALUE="2"/>
2192         <PARAMETER NAME="G_USE_EXCEPTIONS" VALUE="1"/>
2193         <PARAMETER NAME="C_M0_AXIS_PROTOCOL" VALUE="GENERIC"/>
2194         <PARAMETER NAME="C_S0_AXIS_PROTOCOL" VALUE="GENERIC"/>
2195         <PARAMETER NAME="C_M1_AXIS_PROTOCOL" VALUE="GENERIC"/>
2196         <PARAMETER NAME="C_S1_AXIS_PROTOCOL" VALUE="GENERIC"/>
2197         <PARAMETER NAME="C_M2_AXIS_PROTOCOL" VALUE="GENERIC"/>
2198         <PARAMETER NAME="C_S2_AXIS_PROTOCOL" VALUE="GENERIC"/>
2199         <PARAMETER NAME="C_M3_AXIS_PROTOCOL" VALUE="GENERIC"/>
2200         <PARAMETER NAME="C_S3_AXIS_PROTOCOL" VALUE="GENERIC"/>
2201         <PARAMETER NAME="C_M4_AXIS_PROTOCOL" VALUE="GENERIC"/>
2202         <PARAMETER NAME="C_S4_AXIS_PROTOCOL" VALUE="GENERIC"/>
2203         <PARAMETER NAME="C_M5_AXIS_PROTOCOL" VALUE="GENERIC"/>
2204         <PARAMETER NAME="C_S5_AXIS_PROTOCOL" VALUE="GENERIC"/>
2205         <PARAMETER NAME="C_M6_AXIS_PROTOCOL" VALUE="GENERIC"/>
2206         <PARAMETER NAME="C_S6_AXIS_PROTOCOL" VALUE="GENERIC"/>
2207         <PARAMETER NAME="C_M7_AXIS_PROTOCOL" VALUE="GENERIC"/>
2208         <PARAMETER NAME="C_S7_AXIS_PROTOCOL" VALUE="GENERIC"/>
2209         <PARAMETER NAME="C_M8_AXIS_PROTOCOL" VALUE="GENERIC"/>
2210         <PARAMETER NAME="C_S8_AXIS_PROTOCOL" VALUE="GENERIC"/>
2211         <PARAMETER NAME="C_M9_AXIS_PROTOCOL" VALUE="GENERIC"/>
2212         <PARAMETER NAME="C_S9_AXIS_PROTOCOL" VALUE="GENERIC"/>
2213         <PARAMETER NAME="C_M10_AXIS_PROTOCOL" VALUE="GENERIC"/>
2214         <PARAMETER NAME="C_S10_AXIS_PROTOCOL" VALUE="GENERIC"/>
2215         <PARAMETER NAME="C_M11_AXIS_PROTOCOL" VALUE="GENERIC"/>
2216         <PARAMETER NAME="C_S11_AXIS_PROTOCOL" VALUE="GENERIC"/>
2217         <PARAMETER NAME="C_M12_AXIS_PROTOCOL" VALUE="GENERIC"/>
2218         <PARAMETER NAME="C_S12_AXIS_PROTOCOL" VALUE="GENERIC"/>
2219         <PARAMETER NAME="C_M13_AXIS_PROTOCOL" VALUE="GENERIC"/>
2220         <PARAMETER NAME="C_S13_AXIS_PROTOCOL" VALUE="GENERIC"/>
2221         <PARAMETER NAME="C_M14_AXIS_PROTOCOL" VALUE="GENERIC"/>
2222         <PARAMETER NAME="C_S14_AXIS_PROTOCOL" VALUE="GENERIC"/>
2223         <PARAMETER NAME="C_M15_AXIS_PROTOCOL" VALUE="GENERIC"/>
2224         <PARAMETER NAME="C_S15_AXIS_PROTOCOL" VALUE="GENERIC"/>
2225         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_0"/>
2226         <PARAMETER NAME="C_ENDIANNESS" VALUE="1"/>
2227         <PARAMETER NAME="EDK_IPTYPE" VALUE="PROCESSOR"/>
2228         <PARAMETER NAME="EDK_SPECIAL" VALUE="microblaze"/>
2229       </PARAMETERS>
2230       <PORTS>
2231         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
2232           <CONNECTIONS>
2233             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
2234           </CONNECTIONS>
2235         </PORT>
2236         <PORT DIR="I" NAME="Reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
2237           <CONNECTIONS>
2238             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="mb_reset"/>
2239           </CONNECTIONS>
2240         </PORT>
2241         <PORT DIR="I" NAME="Interrupt" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
2242           <CONNECTIONS>
2243             <CONNECTION INSTANCE="axi_intc_0" PORT="irq"/>
2244           </CONNECTIONS>
2245         </PORT>
2246         <PORT DIR="I" LEFT="0" NAME="Interrupt_Address" RIGHT="31" SIGIS="undef"/>
2247         <PORT DIR="O" LEFT="0" NAME="Interrupt_Ack" RIGHT="1" SIGIS="undef"/>
2248         <PORT DIR="O" LEFT="0" NAME="Instr_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
2249           <CONNECTIONS>
2250             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ABus"/>
2251           </CONNECTIONS>
2252         </PORT>
2253         <PORT DIR="I" LEFT="0" NAME="Instr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
2254           <CONNECTIONS>
2255             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadDBus"/>
2256           </CONNECTIONS>
2257         </PORT>
2258         <PORT DIR="O" NAME="IFetch" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
2259           <CONNECTIONS>
2260             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_ReadStrobe"/>
2261           </CONNECTIONS>
2262         </PORT>
2263         <PORT DIR="O" NAME="I_AS" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
2264           <CONNECTIONS>
2265             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="M_AddrStrobe"/>
2266           </CONNECTIONS>
2267         </PORT>
2268         <PORT DIR="I" NAME="IReady" SIGIS="undef" SIGNAME="microblaze_0_IReady">
2269           <CONNECTIONS>
2270             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Ready"/>
2271           </CONNECTIONS>
2272         </PORT>
2273         <PORT DIR="I" NAME="IWAIT" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
2274           <CONNECTIONS>
2275             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Wait"/>
2276           </CONNECTIONS>
2277         </PORT>
2278         <PORT DIR="I" NAME="ICE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
2279           <CONNECTIONS>
2280             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_CE"/>
2281           </CONNECTIONS>
2282         </PORT>
2283         <PORT DIR="I" NAME="IUE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
2284           <CONNECTIONS>
2285             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_UE"/>
2286           </CONNECTIONS>
2287         </PORT>
2288         <PORT DIR="O" LEFT="0" NAME="Data_Addr" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
2289           <CONNECTIONS>
2290             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ABus"/>
2291           </CONNECTIONS>
2292         </PORT>
2293         <PORT DIR="I" LEFT="0" NAME="Data_Read" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
2294           <CONNECTIONS>
2295             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadDBus"/>
2296           </CONNECTIONS>
2297         </PORT>
2298         <PORT DIR="O" LEFT="0" NAME="Data_Write" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
2299           <CONNECTIONS>
2300             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_DBus"/>
2301           </CONNECTIONS>
2302         </PORT>
2303         <PORT DIR="O" NAME="D_AS" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
2304           <CONNECTIONS>
2305             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_AddrStrobe"/>
2306           </CONNECTIONS>
2307         </PORT>
2308         <PORT DIR="O" NAME="Read_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
2309           <CONNECTIONS>
2310             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_ReadStrobe"/>
2311           </CONNECTIONS>
2312         </PORT>
2313         <PORT DIR="O" NAME="Write_Strobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
2314           <CONNECTIONS>
2315             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_WriteStrobe"/>
2316           </CONNECTIONS>
2317         </PORT>
2318         <PORT DIR="I" NAME="DReady" SIGIS="undef" SIGNAME="microblaze_0_DReady">
2319           <CONNECTIONS>
2320             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Ready"/>
2321           </CONNECTIONS>
2322         </PORT>
2323         <PORT DIR="I" NAME="DWait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
2324           <CONNECTIONS>
2325             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Wait"/>
2326           </CONNECTIONS>
2327         </PORT>
2328         <PORT DIR="I" NAME="DCE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
2329           <CONNECTIONS>
2330             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_CE"/>
2331           </CONNECTIONS>
2332         </PORT>
2333         <PORT DIR="I" NAME="DUE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
2334           <CONNECTIONS>
2335             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_UE"/>
2336           </CONNECTIONS>
2337         </PORT>
2338         <PORT DIR="O" LEFT="0" NAME="Byte_Enable" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
2339           <CONNECTIONS>
2340             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="M_BE"/>
2341           </CONNECTIONS>
2342         </PORT>
2343         <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
2344           <CONNECTIONS>
2345             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awaddr"/>
2346           </CONNECTIONS>
2347         </PORT>
2348         <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
2349           <CONNECTIONS>
2350             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awprot"/>
2351           </CONNECTIONS>
2352         </PORT>
2353         <PORT DIR="O" NAME="M_AXI_DP_AWVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
2354           <CONNECTIONS>
2355             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awvalid"/>
2356           </CONNECTIONS>
2357         </PORT>
2358         <PORT DIR="I" NAME="M_AXI_DP_AWREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
2359           <CONNECTIONS>
2360             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_awready"/>
2361           </CONNECTIONS>
2362         </PORT>
2363         <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
2364           <CONNECTIONS>
2365             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wdata"/>
2366           </CONNECTIONS>
2367         </PORT>
2368         <PORT DIR="O" LEFT="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
2369           <CONNECTIONS>
2370             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wstrb"/>
2371           </CONNECTIONS>
2372         </PORT>
2373         <PORT DIR="O" NAME="M_AXI_DP_WVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
2374           <CONNECTIONS>
2375             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wvalid"/>
2376           </CONNECTIONS>
2377         </PORT>
2378         <PORT DIR="I" NAME="M_AXI_DP_WREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
2379           <CONNECTIONS>
2380             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_wready"/>
2381           </CONNECTIONS>
2382         </PORT>
2383         <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
2384           <CONNECTIONS>
2385             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bresp"/>
2386           </CONNECTIONS>
2387         </PORT>
2388         <PORT DIR="I" NAME="M_AXI_DP_BVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
2389           <CONNECTIONS>
2390             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bvalid"/>
2391           </CONNECTIONS>
2392         </PORT>
2393         <PORT DIR="O" NAME="M_AXI_DP_BREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
2394           <CONNECTIONS>
2395             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_bready"/>
2396           </CONNECTIONS>
2397         </PORT>
2398         <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
2399           <CONNECTIONS>
2400             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_araddr"/>
2401           </CONNECTIONS>
2402         </PORT>
2403         <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
2404           <CONNECTIONS>
2405             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arprot"/>
2406           </CONNECTIONS>
2407         </PORT>
2408         <PORT DIR="O" NAME="M_AXI_DP_ARVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
2409           <CONNECTIONS>
2410             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arvalid"/>
2411           </CONNECTIONS>
2412         </PORT>
2413         <PORT DIR="I" NAME="M_AXI_DP_ARREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
2414           <CONNECTIONS>
2415             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_arready"/>
2416           </CONNECTIONS>
2417         </PORT>
2418         <PORT DIR="I" LEFT="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
2419           <CONNECTIONS>
2420             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rdata"/>
2421           </CONNECTIONS>
2422         </PORT>
2423         <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
2424           <CONNECTIONS>
2425             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rresp"/>
2426           </CONNECTIONS>
2427         </PORT>
2428         <PORT DIR="I" NAME="M_AXI_DP_RVALID" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
2429           <CONNECTIONS>
2430             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rvalid"/>
2431           </CONNECTIONS>
2432         </PORT>
2433         <PORT DIR="O" NAME="M_AXI_DP_RREADY" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
2434           <CONNECTIONS>
2435             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_AXI_rready"/>
2436           </CONNECTIONS>
2437         </PORT>
2438         <PORT DIR="I" NAME="Dbg_Clk" SIGIS="undef" SIGNAME="mdm_1_Dbg_Clk_0">
2439           <CONNECTIONS>
2440             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Clk_0"/>
2441           </CONNECTIONS>
2442         </PORT>
2443         <PORT DIR="I" NAME="Dbg_TDI" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDI_0">
2444           <CONNECTIONS>
2445             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDI_0"/>
2446           </CONNECTIONS>
2447         </PORT>
2448         <PORT DIR="O" NAME="Dbg_TDO" SIGIS="undef" SIGNAME="mdm_1_Dbg_TDO_0">
2449           <CONNECTIONS>
2450             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_TDO_0"/>
2451           </CONNECTIONS>
2452         </PORT>
2453         <PORT DIR="I" LEFT="0" NAME="Dbg_Reg_En" RIGHT="7" SIGIS="undef" SIGNAME="mdm_1_Dbg_Reg_En_0">
2454           <CONNECTIONS>
2455             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Reg_En_0"/>
2456           </CONNECTIONS>
2457         </PORT>
2458         <PORT DIR="I" NAME="Dbg_Shift" SIGIS="undef" SIGNAME="mdm_1_Dbg_Shift_0">
2459           <CONNECTIONS>
2460             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Shift_0"/>
2461           </CONNECTIONS>
2462         </PORT>
2463         <PORT DIR="I" NAME="Dbg_Capture" SIGIS="undef" SIGNAME="mdm_1_Dbg_Capture_0">
2464           <CONNECTIONS>
2465             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Capture_0"/>
2466           </CONNECTIONS>
2467         </PORT>
2468         <PORT DIR="I" NAME="Dbg_Update" SIGIS="undef" SIGNAME="mdm_1_Dbg_Update_0">
2469           <CONNECTIONS>
2470             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Update_0"/>
2471           </CONNECTIONS>
2472         </PORT>
2473         <PORT DIR="I" NAME="Debug_Rst" SIGIS="undef" SIGNAME="mdm_1_Dbg_Rst_0">
2474           <CONNECTIONS>
2475             <CONNECTION INSTANCE="mdm_1" PORT="Dbg_Rst_0"/>
2476           </CONNECTIONS>
2477         </PORT>
2478         <PORT DIR="O" LEFT="0" NAME="Trace_Instruction" RIGHT="31" SIGIS="undef"/>
2479         <PORT DIR="O" NAME="Trace_Valid_Instr" SIGIS="undef"/>
2480         <PORT DIR="O" LEFT="0" NAME="Trace_PC" RIGHT="31" SIGIS="undef"/>
2481         <PORT DIR="O" NAME="Trace_Reg_Write" SIGIS="undef"/>
2482         <PORT DIR="O" LEFT="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGIS="undef"/>
2483         <PORT DIR="O" LEFT="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGIS="undef"/>
2484         <PORT DIR="O" LEFT="0" NAME="Trace_PID_Reg" RIGHT="7" SIGIS="undef"/>
2485         <PORT DIR="O" LEFT="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGIS="undef"/>
2486         <PORT DIR="O" NAME="Trace_Exception_Taken" SIGIS="undef"/>
2487         <PORT DIR="O" LEFT="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGIS="undef"/>
2488         <PORT DIR="O" NAME="Trace_Jump_Taken" SIGIS="undef"/>
2489         <PORT DIR="O" NAME="Trace_Delay_Slot" SIGIS="undef"/>
2490         <PORT DIR="O" LEFT="0" NAME="Trace_Data_Address" RIGHT="31" SIGIS="undef"/>
2491         <PORT DIR="O" LEFT="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGIS="undef"/>
2492         <PORT DIR="O" LEFT="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGIS="undef"/>
2493         <PORT DIR="O" NAME="Trace_Data_Access" SIGIS="undef"/>
2494         <PORT DIR="O" NAME="Trace_Data_Read" SIGIS="undef"/>
2495         <PORT DIR="O" NAME="Trace_Data_Write" SIGIS="undef"/>
2496         <PORT DIR="O" NAME="Trace_DCache_Req" SIGIS="undef"/>
2497         <PORT DIR="O" NAME="Trace_DCache_Hit" SIGIS="undef"/>
2498         <PORT DIR="O" NAME="Trace_DCache_Rdy" SIGIS="undef"/>
2499         <PORT DIR="O" NAME="Trace_DCache_Read" SIGIS="undef"/>
2500         <PORT DIR="O" NAME="Trace_ICache_Req" SIGIS="undef"/>
2501         <PORT DIR="O" NAME="Trace_ICache_Hit" SIGIS="undef"/>
2502         <PORT DIR="O" NAME="Trace_ICache_Rdy" SIGIS="undef"/>
2503         <PORT DIR="O" NAME="Trace_OF_PipeRun" SIGIS="undef"/>
2504         <PORT DIR="O" NAME="Trace_EX_PipeRun" SIGIS="undef"/>
2505         <PORT DIR="O" NAME="Trace_MEM_PipeRun" SIGIS="undef"/>
2506         <PORT DIR="O" NAME="Trace_MB_Halted" SIGIS="undef"/>
2507         <PORT DIR="O" NAME="Trace_Jump_Hit" SIGIS="undef"/>
2508         <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awid">
2509           <CONNECTIONS>
2510             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awid"/>
2511           </CONNECTIONS>
2512         </PORT>
2513         <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awaddr">
2514           <CONNECTIONS>
2515             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awaddr"/>
2516           </CONNECTIONS>
2517         </PORT>
2518         <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlen">
2519           <CONNECTIONS>
2520             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlen"/>
2521           </CONNECTIONS>
2522         </PORT>
2523         <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awsize">
2524           <CONNECTIONS>
2525             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awsize"/>
2526           </CONNECTIONS>
2527         </PORT>
2528         <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awburst">
2529           <CONNECTIONS>
2530             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awburst"/>
2531           </CONNECTIONS>
2532         </PORT>
2533         <PORT DIR="O" NAME="M_AXI_IC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awlock">
2534           <CONNECTIONS>
2535             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlock"/>
2536           </CONNECTIONS>
2537         </PORT>
2538         <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awcache">
2539           <CONNECTIONS>
2540             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awcache"/>
2541           </CONNECTIONS>
2542         </PORT>
2543         <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awprot">
2544           <CONNECTIONS>
2545             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awprot"/>
2546           </CONNECTIONS>
2547         </PORT>
2548         <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awqos">
2549           <CONNECTIONS>
2550             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awqos"/>
2551           </CONNECTIONS>
2552         </PORT>
2553         <PORT DIR="O" NAME="M_AXI_IC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awvalid">
2554           <CONNECTIONS>
2555             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awvalid"/>
2556           </CONNECTIONS>
2557         </PORT>
2558         <PORT DIR="I" NAME="M_AXI_IC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_awready">
2559           <CONNECTIONS>
2560             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awready"/>
2561           </CONNECTIONS>
2562         </PORT>
2563         <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wdata">
2564           <CONNECTIONS>
2565             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wdata"/>
2566           </CONNECTIONS>
2567         </PORT>
2568         <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wstrb">
2569           <CONNECTIONS>
2570             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wstrb"/>
2571           </CONNECTIONS>
2572         </PORT>
2573         <PORT DIR="O" NAME="M_AXI_IC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wlast">
2574           <CONNECTIONS>
2575             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wlast"/>
2576           </CONNECTIONS>
2577         </PORT>
2578         <PORT DIR="O" NAME="M_AXI_IC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wvalid">
2579           <CONNECTIONS>
2580             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wvalid"/>
2581           </CONNECTIONS>
2582         </PORT>
2583         <PORT DIR="I" NAME="M_AXI_IC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_wready">
2584           <CONNECTIONS>
2585             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wready"/>
2586           </CONNECTIONS>
2587         </PORT>
2588         <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bid">
2589           <CONNECTIONS>
2590             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bid"/>
2591           </CONNECTIONS>
2592         </PORT>
2593         <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bresp">
2594           <CONNECTIONS>
2595             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bresp"/>
2596           </CONNECTIONS>
2597         </PORT>
2598         <PORT DIR="I" NAME="M_AXI_IC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bvalid">
2599           <CONNECTIONS>
2600             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bvalid"/>
2601           </CONNECTIONS>
2602         </PORT>
2603         <PORT DIR="O" NAME="M_AXI_IC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_bready">
2604           <CONNECTIONS>
2605             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bready"/>
2606           </CONNECTIONS>
2607         </PORT>
2608         <PORT DIR="O" LEFT="0" NAME="M_AXI_IC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arid">
2609           <CONNECTIONS>
2610             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arid"/>
2611           </CONNECTIONS>
2612         </PORT>
2613         <PORT DIR="O" LEFT="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_araddr">
2614           <CONNECTIONS>
2615             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_araddr"/>
2616           </CONNECTIONS>
2617         </PORT>
2618         <PORT DIR="O" LEFT="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlen">
2619           <CONNECTIONS>
2620             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlen"/>
2621           </CONNECTIONS>
2622         </PORT>
2623         <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arsize">
2624           <CONNECTIONS>
2625             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arsize"/>
2626           </CONNECTIONS>
2627         </PORT>
2628         <PORT DIR="O" LEFT="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arburst">
2629           <CONNECTIONS>
2630             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arburst"/>
2631           </CONNECTIONS>
2632         </PORT>
2633         <PORT DIR="O" NAME="M_AXI_IC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arlock">
2634           <CONNECTIONS>
2635             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arlock"/>
2636           </CONNECTIONS>
2637         </PORT>
2638         <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arcache">
2639           <CONNECTIONS>
2640             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arcache"/>
2641           </CONNECTIONS>
2642         </PORT>
2643         <PORT DIR="O" LEFT="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arprot">
2644           <CONNECTIONS>
2645             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arprot"/>
2646           </CONNECTIONS>
2647         </PORT>
2648         <PORT DIR="O" LEFT="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arqos">
2649           <CONNECTIONS>
2650             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arqos"/>
2651           </CONNECTIONS>
2652         </PORT>
2653         <PORT DIR="O" NAME="M_AXI_IC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arvalid">
2654           <CONNECTIONS>
2655             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arvalid"/>
2656           </CONNECTIONS>
2657         </PORT>
2658         <PORT DIR="I" NAME="M_AXI_IC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_arready">
2659           <CONNECTIONS>
2660             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_arready"/>
2661           </CONNECTIONS>
2662         </PORT>
2663         <PORT DIR="I" LEFT="0" NAME="M_AXI_IC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rid">
2664           <CONNECTIONS>
2665             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rid"/>
2666           </CONNECTIONS>
2667         </PORT>
2668         <PORT DIR="I" LEFT="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rdata">
2669           <CONNECTIONS>
2670             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rdata"/>
2671           </CONNECTIONS>
2672         </PORT>
2673         <PORT DIR="I" LEFT="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rresp">
2674           <CONNECTIONS>
2675             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rresp"/>
2676           </CONNECTIONS>
2677         </PORT>
2678         <PORT DIR="I" NAME="M_AXI_IC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rlast">
2679           <CONNECTIONS>
2680             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rlast"/>
2681           </CONNECTIONS>
2682         </PORT>
2683         <PORT DIR="I" NAME="M_AXI_IC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rvalid">
2684           <CONNECTIONS>
2685             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rvalid"/>
2686           </CONNECTIONS>
2687         </PORT>
2688         <PORT DIR="O" NAME="M_AXI_IC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S01_AXI_rready">
2689           <CONNECTIONS>
2690             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_rready"/>
2691           </CONNECTIONS>
2692         </PORT>
2693         <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awid">
2694           <CONNECTIONS>
2695             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awid"/>
2696           </CONNECTIONS>
2697         </PORT>
2698         <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awaddr">
2699           <CONNECTIONS>
2700             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awaddr"/>
2701           </CONNECTIONS>
2702         </PORT>
2703         <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlen">
2704           <CONNECTIONS>
2705             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlen"/>
2706           </CONNECTIONS>
2707         </PORT>
2708         <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awsize">
2709           <CONNECTIONS>
2710             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awsize"/>
2711           </CONNECTIONS>
2712         </PORT>
2713         <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awburst">
2714           <CONNECTIONS>
2715             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awburst"/>
2716           </CONNECTIONS>
2717         </PORT>
2718         <PORT DIR="O" NAME="M_AXI_DC_AWLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awlock">
2719           <CONNECTIONS>
2720             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awlock"/>
2721           </CONNECTIONS>
2722         </PORT>
2723         <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awcache">
2724           <CONNECTIONS>
2725             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awcache"/>
2726           </CONNECTIONS>
2727         </PORT>
2728         <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awprot">
2729           <CONNECTIONS>
2730             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awprot"/>
2731           </CONNECTIONS>
2732         </PORT>
2733         <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awqos">
2734           <CONNECTIONS>
2735             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awqos"/>
2736           </CONNECTIONS>
2737         </PORT>
2738         <PORT DIR="O" NAME="M_AXI_DC_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awvalid">
2739           <CONNECTIONS>
2740             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awvalid"/>
2741           </CONNECTIONS>
2742         </PORT>
2743         <PORT DIR="I" NAME="M_AXI_DC_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_awready">
2744           <CONNECTIONS>
2745             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_awready"/>
2746           </CONNECTIONS>
2747         </PORT>
2748         <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wdata">
2749           <CONNECTIONS>
2750             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wdata"/>
2751           </CONNECTIONS>
2752         </PORT>
2753         <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wstrb">
2754           <CONNECTIONS>
2755             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wstrb"/>
2756           </CONNECTIONS>
2757         </PORT>
2758         <PORT DIR="O" NAME="M_AXI_DC_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wlast">
2759           <CONNECTIONS>
2760             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wlast"/>
2761           </CONNECTIONS>
2762         </PORT>
2763         <PORT DIR="O" NAME="M_AXI_DC_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wvalid">
2764           <CONNECTIONS>
2765             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wvalid"/>
2766           </CONNECTIONS>
2767         </PORT>
2768         <PORT DIR="I" NAME="M_AXI_DC_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_wready">
2769           <CONNECTIONS>
2770             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_wready"/>
2771           </CONNECTIONS>
2772         </PORT>
2773         <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bresp">
2774           <CONNECTIONS>
2775             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bresp"/>
2776           </CONNECTIONS>
2777         </PORT>
2778         <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bid">
2779           <CONNECTIONS>
2780             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bid"/>
2781           </CONNECTIONS>
2782         </PORT>
2783         <PORT DIR="I" NAME="M_AXI_DC_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bvalid">
2784           <CONNECTIONS>
2785             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bvalid"/>
2786           </CONNECTIONS>
2787         </PORT>
2788         <PORT DIR="O" NAME="M_AXI_DC_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_bready">
2789           <CONNECTIONS>
2790             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_bready"/>
2791           </CONNECTIONS>
2792         </PORT>
2793         <PORT DIR="O" LEFT="0" NAME="M_AXI_DC_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arid">
2794           <CONNECTIONS>
2795             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arid"/>
2796           </CONNECTIONS>
2797         </PORT>
2798         <PORT DIR="O" LEFT="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_araddr">
2799           <CONNECTIONS>
2800             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_araddr"/>
2801           </CONNECTIONS>
2802         </PORT>
2803         <PORT DIR="O" LEFT="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlen">
2804           <CONNECTIONS>
2805             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlen"/>
2806           </CONNECTIONS>
2807         </PORT>
2808         <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arsize">
2809           <CONNECTIONS>
2810             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arsize"/>
2811           </CONNECTIONS>
2812         </PORT>
2813         <PORT DIR="O" LEFT="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arburst">
2814           <CONNECTIONS>
2815             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arburst"/>
2816           </CONNECTIONS>
2817         </PORT>
2818         <PORT DIR="O" NAME="M_AXI_DC_ARLOCK" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arlock">
2819           <CONNECTIONS>
2820             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlock"/>
2821           </CONNECTIONS>
2822         </PORT>
2823         <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arcache">
2824           <CONNECTIONS>
2825             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arcache"/>
2826           </CONNECTIONS>
2827         </PORT>
2828         <PORT DIR="O" LEFT="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arprot">
2829           <CONNECTIONS>
2830             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arprot"/>
2831           </CONNECTIONS>
2832         </PORT>
2833         <PORT DIR="O" LEFT="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arqos">
2834           <CONNECTIONS>
2835             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arqos"/>
2836           </CONNECTIONS>
2837         </PORT>
2838         <PORT DIR="O" NAME="M_AXI_DC_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arvalid">
2839           <CONNECTIONS>
2840             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arvalid"/>
2841           </CONNECTIONS>
2842         </PORT>
2843         <PORT DIR="I" NAME="M_AXI_DC_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_arready">
2844           <CONNECTIONS>
2845             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arready"/>
2846           </CONNECTIONS>
2847         </PORT>
2848         <PORT DIR="I" LEFT="0" NAME="M_AXI_DC_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rid">
2849           <CONNECTIONS>
2850             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rid"/>
2851           </CONNECTIONS>
2852         </PORT>
2853         <PORT DIR="I" LEFT="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rdata">
2854           <CONNECTIONS>
2855             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rdata"/>
2856           </CONNECTIONS>
2857         </PORT>
2858         <PORT DIR="I" LEFT="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rresp">
2859           <CONNECTIONS>
2860             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rresp"/>
2861           </CONNECTIONS>
2862         </PORT>
2863         <PORT DIR="I" NAME="M_AXI_DC_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rlast">
2864           <CONNECTIONS>
2865             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rlast"/>
2866           </CONNECTIONS>
2867         </PORT>
2868         <PORT DIR="I" NAME="M_AXI_DC_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rvalid">
2869           <CONNECTIONS>
2870             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rvalid"/>
2871           </CONNECTIONS>
2872         </PORT>
2873         <PORT DIR="O" NAME="M_AXI_DC_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_S00_AXI_rready">
2874           <CONNECTIONS>
2875             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rready"/>
2876           </CONNECTIONS>
2877         </PORT>
2878       </PORTS>
2879       <BUSINTERFACES>
2880         <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="INTERRUPT" TYPE="TARGET">
2881           <PORTMAPS>
2882             <PORTMAP PHYSICAL="Interrupt_Ack"/>
2883             <PORTMAP PHYSICAL="Interrupt_Address"/>
2884             <PORTMAP PHYSICAL="Interrupt"/>
2885           </PORTMAPS>
2886         </BUSINTERFACE>
2887         <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="DLMB" TYPE="MASTER">
2888           <PORTMAPS>
2889             <PORTMAP PHYSICAL="Data_Addr"/>
2890             <PORTMAP PHYSICAL="D_AS"/>
2891             <PORTMAP PHYSICAL="Byte_Enable"/>
2892             <PORTMAP PHYSICAL="DCE"/>
2893             <PORTMAP PHYSICAL="Data_Read"/>
2894             <PORTMAP PHYSICAL="Read_Strobe"/>
2895             <PORTMAP PHYSICAL="DReady"/>
2896             <PORTMAP PHYSICAL="DUE"/>
2897             <PORTMAP PHYSICAL="DWait"/>
2898             <PORTMAP PHYSICAL="Data_Write"/>
2899             <PORTMAP PHYSICAL="Write_Strobe"/>
2900           </PORTMAPS>
2901         </BUSINTERFACE>
2902         <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="ILMB" TYPE="MASTER">
2903           <PORTMAPS>
2904             <PORTMAP PHYSICAL="Instr_Addr"/>
2905             <PORTMAP PHYSICAL="I_AS"/>
2906             <PORTMAP PHYSICAL="ICE"/>
2907             <PORTMAP PHYSICAL="Instr"/>
2908             <PORTMAP PHYSICAL="IFetch"/>
2909             <PORTMAP PHYSICAL="IReady"/>
2910             <PORTMAP PHYSICAL="IUE"/>
2911             <PORTMAP PHYSICAL="IWAIT"/>
2912           </PORTMAPS>
2913         </BUSINTERFACE>
2914         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="M_AXI_DP" TYPE="MASTER">
2915           <PORTMAPS>
2916             <PORTMAP PHYSICAL="M_AXI_DP_ARADDR"/>
2917             <PORTMAP PHYSICAL="M_AXI_DP_ARPROT"/>
2918             <PORTMAP PHYSICAL="M_AXI_DP_ARREADY"/>
2919             <PORTMAP PHYSICAL="M_AXI_DP_ARVALID"/>
2920             <PORTMAP PHYSICAL="M_AXI_DP_AWADDR"/>
2921             <PORTMAP PHYSICAL="M_AXI_DP_AWPROT"/>
2922             <PORTMAP PHYSICAL="M_AXI_DP_AWREADY"/>
2923             <PORTMAP PHYSICAL="M_AXI_DP_AWVALID"/>
2924             <PORTMAP PHYSICAL="M_AXI_DP_BREADY"/>
2925             <PORTMAP PHYSICAL="M_AXI_DP_BRESP"/>
2926             <PORTMAP PHYSICAL="M_AXI_DP_BVALID"/>
2927             <PORTMAP PHYSICAL="M_AXI_DP_RDATA"/>
2928             <PORTMAP PHYSICAL="M_AXI_DP_RREADY"/>
2929             <PORTMAP PHYSICAL="M_AXI_DP_RRESP"/>
2930             <PORTMAP PHYSICAL="M_AXI_DP_RVALID"/>
2931             <PORTMAP PHYSICAL="M_AXI_DP_WDATA"/>
2932             <PORTMAP PHYSICAL="M_AXI_DP_WREADY"/>
2933             <PORTMAP PHYSICAL="M_AXI_DP_WSTRB"/>
2934             <PORTMAP PHYSICAL="M_AXI_DP_WVALID"/>
2935           </PORTMAPS>
2936         </BUSINTERFACE>
2937         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DC" NAME="M_AXI_DC" TYPE="MASTER">
2938           <PORTMAPS>
2939             <PORTMAP PHYSICAL="M_AXI_DC_ARADDR"/>
2940             <PORTMAP PHYSICAL="M_AXI_DC_ARBURST"/>
2941             <PORTMAP PHYSICAL="M_AXI_DC_ARCACHE"/>
2942             <PORTMAP PHYSICAL="M_AXI_DC_ARID"/>
2943             <PORTMAP PHYSICAL="M_AXI_DC_ARLEN"/>
2944             <PORTMAP PHYSICAL="M_AXI_DC_ARLOCK"/>
2945             <PORTMAP PHYSICAL="M_AXI_DC_ARPROT"/>
2946             <PORTMAP PHYSICAL="M_AXI_DC_ARQOS"/>
2947             <PORTMAP PHYSICAL="M_AXI_DC_ARREADY"/>
2948             <PORTMAP PHYSICAL="M_AXI_DC_ARSIZE"/>
2949             <PORTMAP PHYSICAL="M_AXI_DC_ARVALID"/>
2950             <PORTMAP PHYSICAL="M_AXI_DC_AWADDR"/>
2951             <PORTMAP PHYSICAL="M_AXI_DC_AWBURST"/>
2952             <PORTMAP PHYSICAL="M_AXI_DC_AWCACHE"/>
2953             <PORTMAP PHYSICAL="M_AXI_DC_AWID"/>
2954             <PORTMAP PHYSICAL="M_AXI_DC_AWLEN"/>
2955             <PORTMAP PHYSICAL="M_AXI_DC_AWLOCK"/>
2956             <PORTMAP PHYSICAL="M_AXI_DC_AWPROT"/>
2957             <PORTMAP PHYSICAL="M_AXI_DC_AWQOS"/>
2958             <PORTMAP PHYSICAL="M_AXI_DC_AWREADY"/>
2959             <PORTMAP PHYSICAL="M_AXI_DC_AWSIZE"/>
2960             <PORTMAP PHYSICAL="M_AXI_DC_AWVALID"/>
2961             <PORTMAP PHYSICAL="M_AXI_DC_BID"/>
2962             <PORTMAP PHYSICAL="M_AXI_DC_BREADY"/>
2963             <PORTMAP PHYSICAL="M_AXI_DC_BRESP"/>
2964             <PORTMAP PHYSICAL="M_AXI_DC_BVALID"/>
2965             <PORTMAP PHYSICAL="M_AXI_DC_RDATA"/>
2966             <PORTMAP PHYSICAL="M_AXI_DC_RID"/>
2967             <PORTMAP PHYSICAL="M_AXI_DC_RLAST"/>
2968             <PORTMAP PHYSICAL="M_AXI_DC_RREADY"/>
2969             <PORTMAP PHYSICAL="M_AXI_DC_RRESP"/>
2970             <PORTMAP PHYSICAL="M_AXI_DC_RVALID"/>
2971             <PORTMAP PHYSICAL="M_AXI_DC_WDATA"/>
2972             <PORTMAP PHYSICAL="M_AXI_DC_WLAST"/>
2973             <PORTMAP PHYSICAL="M_AXI_DC_WREADY"/>
2974             <PORTMAP PHYSICAL="M_AXI_DC_WSTRB"/>
2975             <PORTMAP PHYSICAL="M_AXI_DC_WVALID"/>
2976           </PORTMAPS>
2977         </BUSINTERFACE>
2978         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_IC" NAME="M_AXI_IC" TYPE="MASTER">
2979           <PORTMAPS>
2980             <PORTMAP PHYSICAL="M_AXI_IC_ARADDR"/>
2981             <PORTMAP PHYSICAL="M_AXI_IC_ARBURST"/>
2982             <PORTMAP PHYSICAL="M_AXI_IC_ARCACHE"/>
2983             <PORTMAP PHYSICAL="M_AXI_IC_ARID"/>
2984             <PORTMAP PHYSICAL="M_AXI_IC_ARLEN"/>
2985             <PORTMAP PHYSICAL="M_AXI_IC_ARLOCK"/>
2986             <PORTMAP PHYSICAL="M_AXI_IC_ARPROT"/>
2987             <PORTMAP PHYSICAL="M_AXI_IC_ARQOS"/>
2988             <PORTMAP PHYSICAL="M_AXI_IC_ARREADY"/>
2989             <PORTMAP PHYSICAL="M_AXI_IC_ARSIZE"/>
2990             <PORTMAP PHYSICAL="M_AXI_IC_ARVALID"/>
2991             <PORTMAP PHYSICAL="M_AXI_IC_AWADDR"/>
2992             <PORTMAP PHYSICAL="M_AXI_IC_AWBURST"/>
2993             <PORTMAP PHYSICAL="M_AXI_IC_AWCACHE"/>
2994             <PORTMAP PHYSICAL="M_AXI_IC_AWID"/>
2995             <PORTMAP PHYSICAL="M_AXI_IC_AWLEN"/>
2996             <PORTMAP PHYSICAL="M_AXI_IC_AWLOCK"/>
2997             <PORTMAP PHYSICAL="M_AXI_IC_AWPROT"/>
2998             <PORTMAP PHYSICAL="M_AXI_IC_AWQOS"/>
2999             <PORTMAP PHYSICAL="M_AXI_IC_AWREADY"/>
3000             <PORTMAP PHYSICAL="M_AXI_IC_AWSIZE"/>
3001             <PORTMAP PHYSICAL="M_AXI_IC_AWVALID"/>
3002             <PORTMAP PHYSICAL="M_AXI_IC_BID"/>
3003             <PORTMAP PHYSICAL="M_AXI_IC_BREADY"/>
3004             <PORTMAP PHYSICAL="M_AXI_IC_BRESP"/>
3005             <PORTMAP PHYSICAL="M_AXI_IC_BVALID"/>
3006             <PORTMAP PHYSICAL="M_AXI_IC_RDATA"/>
3007             <PORTMAP PHYSICAL="M_AXI_IC_RID"/>
3008             <PORTMAP PHYSICAL="M_AXI_IC_RLAST"/>
3009             <PORTMAP PHYSICAL="M_AXI_IC_RREADY"/>
3010             <PORTMAP PHYSICAL="M_AXI_IC_RRESP"/>
3011             <PORTMAP PHYSICAL="M_AXI_IC_RVALID"/>
3012             <PORTMAP PHYSICAL="M_AXI_IC_WDATA"/>
3013             <PORTMAP PHYSICAL="M_AXI_IC_WLAST"/>
3014             <PORTMAP PHYSICAL="M_AXI_IC_WREADY"/>
3015             <PORTMAP PHYSICAL="M_AXI_IC_WSTRB"/>
3016             <PORTMAP PHYSICAL="M_AXI_IC_WVALID"/>
3017           </PORTMAPS>
3018         </BUSINTERFACE>
3019         <BUSINTERFACE BUSNAME="mdm_1_MBDEBUG_0" NAME="DEBUG" TYPE="TARGET">
3020           <PORTMAPS>
3021             <PORTMAP PHYSICAL="Dbg_Capture"/>
3022             <PORTMAP PHYSICAL="Dbg_Clk"/>
3023             <PORTMAP PHYSICAL="Dbg_Reg_En"/>
3024             <PORTMAP PHYSICAL="Debug_Rst"/>
3025             <PORTMAP PHYSICAL="Dbg_Shift"/>
3026             <PORTMAP PHYSICAL="Dbg_TDI"/>
3027             <PORTMAP PHYSICAL="Dbg_TDO"/>
3028             <PORTMAP PHYSICAL="Dbg_Update"/>
3029           </PORTMAPS>
3030         </BUSINTERFACE>
3031         <BUSINTERFACE BUSNAME="__NOC__" NAME="TRACE" TYPE="INITIATOR">
3032           <PORTMAPS>
3033             <PORTMAP PHYSICAL="Trace_Data_Access"/>
3034             <PORTMAP PHYSICAL="Trace_Data_Address"/>
3035             <PORTMAP PHYSICAL="Trace_Data_Byte_Enable"/>
3036             <PORTMAP PHYSICAL="Trace_Data_Read"/>
3037             <PORTMAP PHYSICAL="Trace_Data_Write"/>
3038             <PORTMAP PHYSICAL="Trace_Data_Write_Value"/>
3039             <PORTMAP PHYSICAL="Trace_DCache_Hit"/>
3040             <PORTMAP PHYSICAL="Trace_DCache_Rdy"/>
3041             <PORTMAP PHYSICAL="Trace_DCache_Read"/>
3042             <PORTMAP PHYSICAL="Trace_DCache_Req"/>
3043             <PORTMAP PHYSICAL="Trace_Delay_Slot"/>
3044             <PORTMAP PHYSICAL="Trace_EX_PipeRun"/>
3045             <PORTMAP PHYSICAL="Trace_Exception_Kind"/>
3046             <PORTMAP PHYSICAL="Trace_Exception_Taken"/>
3047             <PORTMAP PHYSICAL="Trace_ICache_Hit"/>
3048             <PORTMAP PHYSICAL="Trace_ICache_Rdy"/>
3049             <PORTMAP PHYSICAL="Trace_ICache_Req"/>
3050             <PORTMAP PHYSICAL="Trace_Instruction"/>
3051             <PORTMAP PHYSICAL="Trace_Jump_Hit"/>
3052             <PORTMAP PHYSICAL="Trace_Jump_Taken"/>
3053             <PORTMAP PHYSICAL="Trace_MB_Halted"/>
3054             <PORTMAP PHYSICAL="Trace_MEM_PipeRun"/>
3055             <PORTMAP PHYSICAL="Trace_MSR_Reg"/>
3056             <PORTMAP PHYSICAL="Trace_New_Reg_Value"/>
3057             <PORTMAP PHYSICAL="Trace_OF_PipeRun"/>
3058             <PORTMAP PHYSICAL="Trace_PC"/>
3059             <PORTMAP PHYSICAL="Trace_PID_Reg"/>
3060             <PORTMAP PHYSICAL="Trace_Reg_Addr"/>
3061             <PORTMAP PHYSICAL="Trace_Reg_Write"/>
3062             <PORTMAP PHYSICAL="Trace_Valid_Instr"/>
3063           </PORTMAPS>
3064         </BUSINTERFACE>
3065       </BUSINTERFACES>
3066       <MEMORYMAP>
3067         <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
3068         <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0003FFFF" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
3069         <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="axi_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
3070         <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060FFFF" INSTANCE="axi_uartlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
3071         <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40E0FFFF" INSTANCE="axi_ethernetlite_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
3072         <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120FFFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
3073         <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41C00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41C0FFFF" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="REGISTER"/>
3074         <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MEMTYPE="MEMORY"/>
3075         <MEMRANGE ADDRESSBLOCK="memaddr" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xBFFFFFFF" INSTANCE="mig_7series_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MEMTYPE="MEMORY"/>
3076       </MEMORYMAP>
3077       <PERIPHERALS>
3078         <PERIPHERAL INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr"/>
3079         <PERIPHERAL INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr"/>
3080         <PERIPHERAL INSTANCE="axi_gpio_0"/>
3081         <PERIPHERAL INSTANCE="axi_uartlite_0"/>
3082         <PERIPHERAL INSTANCE="axi_ethernetlite_0"/>
3083         <PERIPHERAL INSTANCE="axi_intc_0"/>
3084         <PERIPHERAL INSTANCE="axi_timer_0"/>
3085         <PERIPHERAL INSTANCE="mig_7series_0"/>
3086       </PERIPHERALS>
3087     </MODULE>
3088     <MODULE FULLNAME="/microblaze_0_axi_periph" HWVERSION="2.1" INSTANCE="microblaze_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
3089       <DOCUMENTS>
3090         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
3091       </DOCUMENTS>
3092       <PARAMETERS>
3093         <PARAMETER NAME="NUM_SI" VALUE="1"/>
3094         <PARAMETER NAME="NUM_MI" VALUE="5"/>
3095         <PARAMETER NAME="STRATEGY" VALUE="0"/>
3096         <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
3097         <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
3098         <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
3099         <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
3100         <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
3101         <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
3102         <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
3103         <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
3104         <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
3105         <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
3106         <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
3107         <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
3108         <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
3109         <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
3110         <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
3111         <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
3112         <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
3113         <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
3114         <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
3115         <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
3116         <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
3117         <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
3118         <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
3119         <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
3120         <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
3121         <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
3122         <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
3123         <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
3124         <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
3125         <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
3126         <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
3127         <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
3128         <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
3129         <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
3130         <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
3131         <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
3132         <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
3133         <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
3134         <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
3135         <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
3136         <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
3137         <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
3138         <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
3139         <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
3140         <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
3141         <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
3142         <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
3143         <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
3144         <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
3145         <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
3146         <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
3147         <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
3148         <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
3149         <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
3150         <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
3151         <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
3152         <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
3153         <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
3154         <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
3155         <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
3156         <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
3157         <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
3158         <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
3159         <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
3160         <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
3161         <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
3162         <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
3163         <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
3164         <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
3165         <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
3166         <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
3167         <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
3168         <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
3169         <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
3170         <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
3171         <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
3172         <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
3173         <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
3174         <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
3175         <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
3176         <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
3177         <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
3178         <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
3179         <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
3180         <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
3181         <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
3182         <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
3183         <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
3184         <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
3185         <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
3186         <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
3187         <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
3188         <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
3189         <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
3190         <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
3191         <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
3192         <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
3193         <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
3194         <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
3195         <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
3196         <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
3197         <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
3198         <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
3199         <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
3200         <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
3201         <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
3202         <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
3203         <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
3204         <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
3205         <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
3206         <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
3207         <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
3208         <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
3209         <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
3210         <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
3211         <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
3212         <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
3213         <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
3214         <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
3215         <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
3216         <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
3217         <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
3218         <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
3219         <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
3220         <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
3221         <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
3222         <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
3223         <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
3224         <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
3225         <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
3226         <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
3227         <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
3228         <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
3229         <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
3230         <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
3231         <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
3232         <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
3233         <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
3234         <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
3235         <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
3236         <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
3237         <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
3238         <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
3239         <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
3240         <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
3241         <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
3242         <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
3243         <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
3244         <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
3245         <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
3246         <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
3247         <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
3248         <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
3249         <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
3250         <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
3251         <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
3252         <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
3253         <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
3254         <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
3255         <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
3256         <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
3257         <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
3258         <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
3259         <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
3260         <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
3261         <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
3262         <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
3263         <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
3264         <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
3265         <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
3266         <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
3267         <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
3268         <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
3269         <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
3270         <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
3271         <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
3272         <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
3273         <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
3274         <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
3275         <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
3276         <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
3277         <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
3278         <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
3279         <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
3280         <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
3281         <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
3282         <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
3283         <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
3284         <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
3285         <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
3286         <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
3287         <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
3288         <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
3289         <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
3290         <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
3291         <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
3292         <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
3293         <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
3294         <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
3295         <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
3296         <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
3297         <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
3298         <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
3299         <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
3300         <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
3301         <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
3302         <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
3303         <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
3304         <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
3305         <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
3306         <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
3307         <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
3308         <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
3309         <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
3310         <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
3311         <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
3312         <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
3313         <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
3314         <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
3315         <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
3316         <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
3317         <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
3318         <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
3319         <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
3320         <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
3321         <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
3322         <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
3323         <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
3324         <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
3325         <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
3326         <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
3327         <PARAMETER NAME="M00_SECURE" VALUE="0"/>
3328         <PARAMETER NAME="M01_SECURE" VALUE="0"/>
3329         <PARAMETER NAME="M02_SECURE" VALUE="0"/>
3330         <PARAMETER NAME="M03_SECURE" VALUE="0"/>
3331         <PARAMETER NAME="M04_SECURE" VALUE="0"/>
3332         <PARAMETER NAME="M05_SECURE" VALUE="0"/>
3333         <PARAMETER NAME="M06_SECURE" VALUE="0"/>
3334         <PARAMETER NAME="M07_SECURE" VALUE="0"/>
3335         <PARAMETER NAME="M08_SECURE" VALUE="0"/>
3336         <PARAMETER NAME="M09_SECURE" VALUE="0"/>
3337         <PARAMETER NAME="M10_SECURE" VALUE="0"/>
3338         <PARAMETER NAME="M11_SECURE" VALUE="0"/>
3339         <PARAMETER NAME="M12_SECURE" VALUE="0"/>
3340         <PARAMETER NAME="M13_SECURE" VALUE="0"/>
3341         <PARAMETER NAME="M14_SECURE" VALUE="0"/>
3342         <PARAMETER NAME="M15_SECURE" VALUE="0"/>
3343         <PARAMETER NAME="M16_SECURE" VALUE="0"/>
3344         <PARAMETER NAME="M17_SECURE" VALUE="0"/>
3345         <PARAMETER NAME="M18_SECURE" VALUE="0"/>
3346         <PARAMETER NAME="M19_SECURE" VALUE="0"/>
3347         <PARAMETER NAME="M20_SECURE" VALUE="0"/>
3348         <PARAMETER NAME="M21_SECURE" VALUE="0"/>
3349         <PARAMETER NAME="M22_SECURE" VALUE="0"/>
3350         <PARAMETER NAME="M23_SECURE" VALUE="0"/>
3351         <PARAMETER NAME="M24_SECURE" VALUE="0"/>
3352         <PARAMETER NAME="M25_SECURE" VALUE="0"/>
3353         <PARAMETER NAME="M26_SECURE" VALUE="0"/>
3354         <PARAMETER NAME="M27_SECURE" VALUE="0"/>
3355         <PARAMETER NAME="M28_SECURE" VALUE="0"/>
3356         <PARAMETER NAME="M29_SECURE" VALUE="0"/>
3357         <PARAMETER NAME="M30_SECURE" VALUE="0"/>
3358         <PARAMETER NAME="M31_SECURE" VALUE="0"/>
3359         <PARAMETER NAME="M32_SECURE" VALUE="0"/>
3360         <PARAMETER NAME="M33_SECURE" VALUE="0"/>
3361         <PARAMETER NAME="M34_SECURE" VALUE="0"/>
3362         <PARAMETER NAME="M35_SECURE" VALUE="0"/>
3363         <PARAMETER NAME="M36_SECURE" VALUE="0"/>
3364         <PARAMETER NAME="M37_SECURE" VALUE="0"/>
3365         <PARAMETER NAME="M38_SECURE" VALUE="0"/>
3366         <PARAMETER NAME="M39_SECURE" VALUE="0"/>
3367         <PARAMETER NAME="M40_SECURE" VALUE="0"/>
3368         <PARAMETER NAME="M41_SECURE" VALUE="0"/>
3369         <PARAMETER NAME="M42_SECURE" VALUE="0"/>
3370         <PARAMETER NAME="M43_SECURE" VALUE="0"/>
3371         <PARAMETER NAME="M44_SECURE" VALUE="0"/>
3372         <PARAMETER NAME="M45_SECURE" VALUE="0"/>
3373         <PARAMETER NAME="M46_SECURE" VALUE="0"/>
3374         <PARAMETER NAME="M47_SECURE" VALUE="0"/>
3375         <PARAMETER NAME="M48_SECURE" VALUE="0"/>
3376         <PARAMETER NAME="M49_SECURE" VALUE="0"/>
3377         <PARAMETER NAME="M50_SECURE" VALUE="0"/>
3378         <PARAMETER NAME="M51_SECURE" VALUE="0"/>
3379         <PARAMETER NAME="M52_SECURE" VALUE="0"/>
3380         <PARAMETER NAME="M53_SECURE" VALUE="0"/>
3381         <PARAMETER NAME="M54_SECURE" VALUE="0"/>
3382         <PARAMETER NAME="M55_SECURE" VALUE="0"/>
3383         <PARAMETER NAME="M56_SECURE" VALUE="0"/>
3384         <PARAMETER NAME="M57_SECURE" VALUE="0"/>
3385         <PARAMETER NAME="M58_SECURE" VALUE="0"/>
3386         <PARAMETER NAME="M59_SECURE" VALUE="0"/>
3387         <PARAMETER NAME="M60_SECURE" VALUE="0"/>
3388         <PARAMETER NAME="M61_SECURE" VALUE="0"/>
3389         <PARAMETER NAME="M62_SECURE" VALUE="0"/>
3390         <PARAMETER NAME="M63_SECURE" VALUE="0"/>
3391         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_microblaze_0_axi_periph_0"/>
3392         <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
3393       </PARAMETERS>
3394       <PORTS>
3395         <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3396           <CONNECTIONS>
3397             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3398           </CONNECTIONS>
3399         </PORT>
3400         <PORT DIR="I" LEFT="0" NAME="ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
3401           <CONNECTIONS>
3402             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="interconnect_aresetn"/>
3403           </CONNECTIONS>
3404         </PORT>
3405         <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3406           <CONNECTIONS>
3407             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3408           </CONNECTIONS>
3409         </PORT>
3410         <PORT DIR="I" LEFT="0" NAME="S00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3411           <CONNECTIONS>
3412             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3413           </CONNECTIONS>
3414         </PORT>
3415         <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3416           <CONNECTIONS>
3417             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3418           </CONNECTIONS>
3419         </PORT>
3420         <PORT DIR="I" LEFT="0" NAME="M00_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3421           <CONNECTIONS>
3422             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3423           </CONNECTIONS>
3424         </PORT>
3425         <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3426           <CONNECTIONS>
3427             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3428           </CONNECTIONS>
3429         </PORT>
3430         <PORT DIR="I" LEFT="0" NAME="M01_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3431           <CONNECTIONS>
3432             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3433           </CONNECTIONS>
3434         </PORT>
3435         <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3436           <CONNECTIONS>
3437             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3438           </CONNECTIONS>
3439         </PORT>
3440         <PORT DIR="I" LEFT="0" NAME="M02_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3441           <CONNECTIONS>
3442             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3443           </CONNECTIONS>
3444         </PORT>
3445         <PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3446           <CONNECTIONS>
3447             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3448           </CONNECTIONS>
3449         </PORT>
3450         <PORT DIR="I" LEFT="0" NAME="M03_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3451           <CONNECTIONS>
3452             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3453           </CONNECTIONS>
3454         </PORT>
3455         <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
3456           <CONNECTIONS>
3457             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
3458           </CONNECTIONS>
3459         </PORT>
3460         <PORT DIR="I" LEFT="0" NAME="M04_ARESETN" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
3461           <CONNECTIONS>
3462             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
3463           </CONNECTIONS>
3464         </PORT>
3465         <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARADDR">
3466           <CONNECTIONS>
3467             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
3468           </CONNECTIONS>
3469         </PORT>
3470         <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARPROT">
3471           <CONNECTIONS>
3472             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
3473           </CONNECTIONS>
3474         </PORT>
3475         <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARREADY">
3476           <CONNECTIONS>
3477             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
3478           </CONNECTIONS>
3479         </PORT>
3480         <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_ARVALID">
3481           <CONNECTIONS>
3482             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
3483           </CONNECTIONS>
3484         </PORT>
3485         <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWADDR">
3486           <CONNECTIONS>
3487             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
3488           </CONNECTIONS>
3489         </PORT>
3490         <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWPROT">
3491           <CONNECTIONS>
3492             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
3493           </CONNECTIONS>
3494         </PORT>
3495         <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWREADY">
3496           <CONNECTIONS>
3497             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
3498           </CONNECTIONS>
3499         </PORT>
3500         <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_AWVALID">
3501           <CONNECTIONS>
3502             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
3503           </CONNECTIONS>
3504         </PORT>
3505         <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BREADY">
3506           <CONNECTIONS>
3507             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
3508           </CONNECTIONS>
3509         </PORT>
3510         <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BRESP">
3511           <CONNECTIONS>
3512             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
3513           </CONNECTIONS>
3514         </PORT>
3515         <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_BVALID">
3516           <CONNECTIONS>
3517             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
3518           </CONNECTIONS>
3519         </PORT>
3520         <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RDATA">
3521           <CONNECTIONS>
3522             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
3523           </CONNECTIONS>
3524         </PORT>
3525         <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RREADY">
3526           <CONNECTIONS>
3527             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
3528           </CONNECTIONS>
3529         </PORT>
3530         <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RRESP">
3531           <CONNECTIONS>
3532             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
3533           </CONNECTIONS>
3534         </PORT>
3535         <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_RVALID">
3536           <CONNECTIONS>
3537             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
3538           </CONNECTIONS>
3539         </PORT>
3540         <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WDATA">
3541           <CONNECTIONS>
3542             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
3543           </CONNECTIONS>
3544         </PORT>
3545         <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WREADY">
3546           <CONNECTIONS>
3547             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
3548           </CONNECTIONS>
3549         </PORT>
3550         <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WSTRB">
3551           <CONNECTIONS>
3552             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
3553           </CONNECTIONS>
3554         </PORT>
3555         <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_M_AXI_DP_WVALID">
3556           <CONNECTIONS>
3557             <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
3558           </CONNECTIONS>
3559         </PORT>
3560         <PORT DIR="O" LEFT="3" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_araddr">
3561           <CONNECTIONS>
3562             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_araddr"/>
3563           </CONNECTIONS>
3564         </PORT>
3565         <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arready">
3566           <CONNECTIONS>
3567             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arready"/>
3568           </CONNECTIONS>
3569         </PORT>
3570         <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_arvalid">
3571           <CONNECTIONS>
3572             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_arvalid"/>
3573           </CONNECTIONS>
3574         </PORT>
3575         <PORT DIR="O" LEFT="3" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awaddr">
3576           <CONNECTIONS>
3577             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awaddr"/>
3578           </CONNECTIONS>
3579         </PORT>
3580         <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awready">
3581           <CONNECTIONS>
3582             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awready"/>
3583           </CONNECTIONS>
3584         </PORT>
3585         <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_awvalid">
3586           <CONNECTIONS>
3587             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_awvalid"/>
3588           </CONNECTIONS>
3589         </PORT>
3590         <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bready">
3591           <CONNECTIONS>
3592             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bready"/>
3593           </CONNECTIONS>
3594         </PORT>
3595         <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bresp">
3596           <CONNECTIONS>
3597             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bresp"/>
3598           </CONNECTIONS>
3599         </PORT>
3600         <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_bvalid">
3601           <CONNECTIONS>
3602             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_bvalid"/>
3603           </CONNECTIONS>
3604         </PORT>
3605         <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rdata">
3606           <CONNECTIONS>
3607             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rdata"/>
3608           </CONNECTIONS>
3609         </PORT>
3610         <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rready">
3611           <CONNECTIONS>
3612             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rready"/>
3613           </CONNECTIONS>
3614         </PORT>
3615         <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rresp">
3616           <CONNECTIONS>
3617             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rresp"/>
3618           </CONNECTIONS>
3619         </PORT>
3620         <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_rvalid">
3621           <CONNECTIONS>
3622             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_rvalid"/>
3623           </CONNECTIONS>
3624         </PORT>
3625         <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wdata">
3626           <CONNECTIONS>
3627             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wdata"/>
3628           </CONNECTIONS>
3629         </PORT>
3630         <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wready">
3631           <CONNECTIONS>
3632             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wready"/>
3633           </CONNECTIONS>
3634         </PORT>
3635         <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wstrb">
3636           <CONNECTIONS>
3637             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wstrb"/>
3638           </CONNECTIONS>
3639         </PORT>
3640         <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_uartlite_0_s_axi_wvalid">
3641           <CONNECTIONS>
3642             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_wvalid"/>
3643           </CONNECTIONS>
3644         </PORT>
3645         <PORT DIR="O" LEFT="8" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
3646           <CONNECTIONS>
3647             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_araddr"/>
3648           </CONNECTIONS>
3649         </PORT>
3650         <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
3651           <CONNECTIONS>
3652             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arready"/>
3653           </CONNECTIONS>
3654         </PORT>
3655         <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
3656           <CONNECTIONS>
3657             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arvalid"/>
3658           </CONNECTIONS>
3659         </PORT>
3660         <PORT DIR="O" LEFT="8" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
3661           <CONNECTIONS>
3662             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awaddr"/>
3663           </CONNECTIONS>
3664         </PORT>
3665         <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
3666           <CONNECTIONS>
3667             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awready"/>
3668           </CONNECTIONS>
3669         </PORT>
3670         <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
3671           <CONNECTIONS>
3672             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awvalid"/>
3673           </CONNECTIONS>
3674         </PORT>
3675         <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
3676           <CONNECTIONS>
3677             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bready"/>
3678           </CONNECTIONS>
3679         </PORT>
3680         <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
3681           <CONNECTIONS>
3682             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bresp"/>
3683           </CONNECTIONS>
3684         </PORT>
3685         <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
3686           <CONNECTIONS>
3687             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bvalid"/>
3688           </CONNECTIONS>
3689         </PORT>
3690         <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
3691           <CONNECTIONS>
3692             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rdata"/>
3693           </CONNECTIONS>
3694         </PORT>
3695         <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
3696           <CONNECTIONS>
3697             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rready"/>
3698           </CONNECTIONS>
3699         </PORT>
3700         <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
3701           <CONNECTIONS>
3702             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rresp"/>
3703           </CONNECTIONS>
3704         </PORT>
3705         <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
3706           <CONNECTIONS>
3707             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rvalid"/>
3708           </CONNECTIONS>
3709         </PORT>
3710         <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
3711           <CONNECTIONS>
3712             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wdata"/>
3713           </CONNECTIONS>
3714         </PORT>
3715         <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
3716           <CONNECTIONS>
3717             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wready"/>
3718           </CONNECTIONS>
3719         </PORT>
3720         <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
3721           <CONNECTIONS>
3722             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wstrb"/>
3723           </CONNECTIONS>
3724         </PORT>
3725         <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
3726           <CONNECTIONS>
3727             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wvalid"/>
3728           </CONNECTIONS>
3729         </PORT>
3730         <PORT DIR="O" LEFT="4" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_araddr">
3731           <CONNECTIONS>
3732             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_araddr"/>
3733           </CONNECTIONS>
3734         </PORT>
3735         <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arready">
3736           <CONNECTIONS>
3737             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arready"/>
3738           </CONNECTIONS>
3739         </PORT>
3740         <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_arvalid">
3741           <CONNECTIONS>
3742             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arvalid"/>
3743           </CONNECTIONS>
3744         </PORT>
3745         <PORT DIR="O" LEFT="4" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awaddr">
3746           <CONNECTIONS>
3747             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awaddr"/>
3748           </CONNECTIONS>
3749         </PORT>
3750         <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awready">
3751           <CONNECTIONS>
3752             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awready"/>
3753           </CONNECTIONS>
3754         </PORT>
3755         <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_awvalid">
3756           <CONNECTIONS>
3757             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awvalid"/>
3758           </CONNECTIONS>
3759         </PORT>
3760         <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bready">
3761           <CONNECTIONS>
3762             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bready"/>
3763           </CONNECTIONS>
3764         </PORT>
3765         <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bresp">
3766           <CONNECTIONS>
3767             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bresp"/>
3768           </CONNECTIONS>
3769         </PORT>
3770         <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_bvalid">
3771           <CONNECTIONS>
3772             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bvalid"/>
3773           </CONNECTIONS>
3774         </PORT>
3775         <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rdata">
3776           <CONNECTIONS>
3777             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rdata"/>
3778           </CONNECTIONS>
3779         </PORT>
3780         <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rready">
3781           <CONNECTIONS>
3782             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rready"/>
3783           </CONNECTIONS>
3784         </PORT>
3785         <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rresp">
3786           <CONNECTIONS>
3787             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rresp"/>
3788           </CONNECTIONS>
3789         </PORT>
3790         <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_rvalid">
3791           <CONNECTIONS>
3792             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rvalid"/>
3793           </CONNECTIONS>
3794         </PORT>
3795         <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wdata">
3796           <CONNECTIONS>
3797             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wdata"/>
3798           </CONNECTIONS>
3799         </PORT>
3800         <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wready">
3801           <CONNECTIONS>
3802             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wready"/>
3803           </CONNECTIONS>
3804         </PORT>
3805         <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wstrb">
3806           <CONNECTIONS>
3807             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wstrb"/>
3808           </CONNECTIONS>
3809         </PORT>
3810         <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_timer_0_s_axi_wvalid">
3811           <CONNECTIONS>
3812             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wvalid"/>
3813           </CONNECTIONS>
3814         </PORT>
3815         <PORT DIR="O" LEFT="8" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
3816           <CONNECTIONS>
3817             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
3818           </CONNECTIONS>
3819         </PORT>
3820         <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
3821           <CONNECTIONS>
3822             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
3823           </CONNECTIONS>
3824         </PORT>
3825         <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
3826           <CONNECTIONS>
3827             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
3828           </CONNECTIONS>
3829         </PORT>
3830         <PORT DIR="O" LEFT="8" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
3831           <CONNECTIONS>
3832             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
3833           </CONNECTIONS>
3834         </PORT>
3835         <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
3836           <CONNECTIONS>
3837             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
3838           </CONNECTIONS>
3839         </PORT>
3840         <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
3841           <CONNECTIONS>
3842             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
3843           </CONNECTIONS>
3844         </PORT>
3845         <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
3846           <CONNECTIONS>
3847             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
3848           </CONNECTIONS>
3849         </PORT>
3850         <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
3851           <CONNECTIONS>
3852             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
3853           </CONNECTIONS>
3854         </PORT>
3855         <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
3856           <CONNECTIONS>
3857             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
3858           </CONNECTIONS>
3859         </PORT>
3860         <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
3861           <CONNECTIONS>
3862             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
3863           </CONNECTIONS>
3864         </PORT>
3865         <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
3866           <CONNECTIONS>
3867             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
3868           </CONNECTIONS>
3869         </PORT>
3870         <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
3871           <CONNECTIONS>
3872             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
3873           </CONNECTIONS>
3874         </PORT>
3875         <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
3876           <CONNECTIONS>
3877             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
3878           </CONNECTIONS>
3879         </PORT>
3880         <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
3881           <CONNECTIONS>
3882             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
3883           </CONNECTIONS>
3884         </PORT>
3885         <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
3886           <CONNECTIONS>
3887             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
3888           </CONNECTIONS>
3889         </PORT>
3890         <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
3891           <CONNECTIONS>
3892             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
3893           </CONNECTIONS>
3894         </PORT>
3895         <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
3896           <CONNECTIONS>
3897             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
3898           </CONNECTIONS>
3899         </PORT>
3900         <PORT DIR="O" LEFT="12" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_araddr">
3901           <CONNECTIONS>
3902             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_araddr"/>
3903           </CONNECTIONS>
3904         </PORT>
3905         <PORT DIR="I" NAME="M04_AXI_arready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arready">
3906           <CONNECTIONS>
3907             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arready"/>
3908           </CONNECTIONS>
3909         </PORT>
3910         <PORT DIR="O" NAME="M04_AXI_arvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_arvalid">
3911           <CONNECTIONS>
3912             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_arvalid"/>
3913           </CONNECTIONS>
3914         </PORT>
3915         <PORT DIR="O" LEFT="12" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awaddr">
3916           <CONNECTIONS>
3917             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awaddr"/>
3918           </CONNECTIONS>
3919         </PORT>
3920         <PORT DIR="I" NAME="M04_AXI_awready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awready">
3921           <CONNECTIONS>
3922             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awready"/>
3923           </CONNECTIONS>
3924         </PORT>
3925         <PORT DIR="O" NAME="M04_AXI_awvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_awvalid">
3926           <CONNECTIONS>
3927             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_awvalid"/>
3928           </CONNECTIONS>
3929         </PORT>
3930         <PORT DIR="O" NAME="M04_AXI_bready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bready">
3931           <CONNECTIONS>
3932             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bready"/>
3933           </CONNECTIONS>
3934         </PORT>
3935         <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bresp">
3936           <CONNECTIONS>
3937             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bresp"/>
3938           </CONNECTIONS>
3939         </PORT>
3940         <PORT DIR="I" NAME="M04_AXI_bvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_bvalid">
3941           <CONNECTIONS>
3942             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_bvalid"/>
3943           </CONNECTIONS>
3944         </PORT>
3945         <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rdata">
3946           <CONNECTIONS>
3947             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rdata"/>
3948           </CONNECTIONS>
3949         </PORT>
3950         <PORT DIR="O" NAME="M04_AXI_rready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rready">
3951           <CONNECTIONS>
3952             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rready"/>
3953           </CONNECTIONS>
3954         </PORT>
3955         <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rresp">
3956           <CONNECTIONS>
3957             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rresp"/>
3958           </CONNECTIONS>
3959         </PORT>
3960         <PORT DIR="I" NAME="M04_AXI_rvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_rvalid">
3961           <CONNECTIONS>
3962             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_rvalid"/>
3963           </CONNECTIONS>
3964         </PORT>
3965         <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wdata">
3966           <CONNECTIONS>
3967             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wdata"/>
3968           </CONNECTIONS>
3969         </PORT>
3970         <PORT DIR="I" NAME="M04_AXI_wready" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wready">
3971           <CONNECTIONS>
3972             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wready"/>
3973           </CONNECTIONS>
3974         </PORT>
3975         <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wstrb">
3976           <CONNECTIONS>
3977             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wstrb"/>
3978           </CONNECTIONS>
3979         </PORT>
3980         <PORT DIR="O" NAME="M04_AXI_wvalid" SIGIS="undef" SIGNAME="axi_ethernetlite_0_s_axi_wvalid">
3981           <CONNECTIONS>
3982             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_wvalid"/>
3983           </CONNECTIONS>
3984         </PORT>
3985       </PORTS>
3986       <BUSINTERFACES>
3987         <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" NAME="S00_AXI" TYPE="SLAVE">
3988           <PORTMAPS>
3989             <PORTMAP PHYSICAL="S00_AXI_araddr"/>
3990             <PORTMAP PHYSICAL="S00_AXI_arprot"/>
3991             <PORTMAP PHYSICAL="S00_AXI_arready"/>
3992             <PORTMAP PHYSICAL="S00_AXI_arvalid"/>
3993             <PORTMAP PHYSICAL="S00_AXI_awaddr"/>
3994             <PORTMAP PHYSICAL="S00_AXI_awprot"/>
3995             <PORTMAP PHYSICAL="S00_AXI_awready"/>
3996             <PORTMAP PHYSICAL="S00_AXI_awvalid"/>
3997             <PORTMAP PHYSICAL="S00_AXI_bready"/>
3998             <PORTMAP PHYSICAL="S00_AXI_bresp"/>
3999             <PORTMAP PHYSICAL="S00_AXI_bvalid"/>
4000             <PORTMAP PHYSICAL="S00_AXI_rdata"/>
4001             <PORTMAP PHYSICAL="S00_AXI_rready"/>
4002             <PORTMAP PHYSICAL="S00_AXI_rresp"/>
4003             <PORTMAP PHYSICAL="S00_AXI_rvalid"/>
4004             <PORTMAP PHYSICAL="S00_AXI_wdata"/>
4005             <PORTMAP PHYSICAL="S00_AXI_wready"/>
4006             <PORTMAP PHYSICAL="S00_AXI_wstrb"/>
4007             <PORTMAP PHYSICAL="S00_AXI_wvalid"/>
4008           </PORTMAPS>
4009         </BUSINTERFACE>
4010         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M00_AXI" NAME="M00_AXI" TYPE="MASTER">
4011           <PORTMAPS>
4012             <PORTMAP PHYSICAL="M00_AXI_araddr"/>
4013             <PORTMAP PHYSICAL="M00_AXI_arready"/>
4014             <PORTMAP PHYSICAL="M00_AXI_arvalid"/>
4015             <PORTMAP PHYSICAL="M00_AXI_awaddr"/>
4016             <PORTMAP PHYSICAL="M00_AXI_awready"/>
4017             <PORTMAP PHYSICAL="M00_AXI_awvalid"/>
4018             <PORTMAP PHYSICAL="M00_AXI_bready"/>
4019             <PORTMAP PHYSICAL="M00_AXI_bresp"/>
4020             <PORTMAP PHYSICAL="M00_AXI_bvalid"/>
4021             <PORTMAP PHYSICAL="M00_AXI_rdata"/>
4022             <PORTMAP PHYSICAL="M00_AXI_rready"/>
4023             <PORTMAP PHYSICAL="M00_AXI_rresp"/>
4024             <PORTMAP PHYSICAL="M00_AXI_rvalid"/>
4025             <PORTMAP PHYSICAL="M00_AXI_wdata"/>
4026             <PORTMAP PHYSICAL="M00_AXI_wready"/>
4027             <PORTMAP PHYSICAL="M00_AXI_wstrb"/>
4028             <PORTMAP PHYSICAL="M00_AXI_wvalid"/>
4029           </PORTMAPS>
4030         </BUSINTERFACE>
4031         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M01_AXI" NAME="M01_AXI" TYPE="MASTER">
4032           <PORTMAPS>
4033             <PORTMAP PHYSICAL="M01_AXI_araddr"/>
4034             <PORTMAP PHYSICAL="M01_AXI_arready"/>
4035             <PORTMAP PHYSICAL="M01_AXI_arvalid"/>
4036             <PORTMAP PHYSICAL="M01_AXI_awaddr"/>
4037             <PORTMAP PHYSICAL="M01_AXI_awready"/>
4038             <PORTMAP PHYSICAL="M01_AXI_awvalid"/>
4039             <PORTMAP PHYSICAL="M01_AXI_bready"/>
4040             <PORTMAP PHYSICAL="M01_AXI_bresp"/>
4041             <PORTMAP PHYSICAL="M01_AXI_bvalid"/>
4042             <PORTMAP PHYSICAL="M01_AXI_rdata"/>
4043             <PORTMAP PHYSICAL="M01_AXI_rready"/>
4044             <PORTMAP PHYSICAL="M01_AXI_rresp"/>
4045             <PORTMAP PHYSICAL="M01_AXI_rvalid"/>
4046             <PORTMAP PHYSICAL="M01_AXI_wdata"/>
4047             <PORTMAP PHYSICAL="M01_AXI_wready"/>
4048             <PORTMAP PHYSICAL="M01_AXI_wstrb"/>
4049             <PORTMAP PHYSICAL="M01_AXI_wvalid"/>
4050           </PORTMAPS>
4051         </BUSINTERFACE>
4052         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M02_AXI" NAME="M02_AXI" TYPE="MASTER">
4053           <PORTMAPS>
4054             <PORTMAP PHYSICAL="M02_AXI_araddr"/>
4055             <PORTMAP PHYSICAL="M02_AXI_arready"/>
4056             <PORTMAP PHYSICAL="M02_AXI_arvalid"/>
4057             <PORTMAP PHYSICAL="M02_AXI_awaddr"/>
4058             <PORTMAP PHYSICAL="M02_AXI_awready"/>
4059             <PORTMAP PHYSICAL="M02_AXI_awvalid"/>
4060             <PORTMAP PHYSICAL="M02_AXI_bready"/>
4061             <PORTMAP PHYSICAL="M02_AXI_bresp"/>
4062             <PORTMAP PHYSICAL="M02_AXI_bvalid"/>
4063             <PORTMAP PHYSICAL="M02_AXI_rdata"/>
4064             <PORTMAP PHYSICAL="M02_AXI_rready"/>
4065             <PORTMAP PHYSICAL="M02_AXI_rresp"/>
4066             <PORTMAP PHYSICAL="M02_AXI_rvalid"/>
4067             <PORTMAP PHYSICAL="M02_AXI_wdata"/>
4068             <PORTMAP PHYSICAL="M02_AXI_wready"/>
4069             <PORTMAP PHYSICAL="M02_AXI_wstrb"/>
4070             <PORTMAP PHYSICAL="M02_AXI_wvalid"/>
4071           </PORTMAPS>
4072         </BUSINTERFACE>
4073         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M03_AXI" NAME="M03_AXI" TYPE="MASTER">
4074           <PORTMAPS>
4075             <PORTMAP PHYSICAL="M03_AXI_araddr"/>
4076             <PORTMAP PHYSICAL="M03_AXI_arready"/>
4077             <PORTMAP PHYSICAL="M03_AXI_arvalid"/>
4078             <PORTMAP PHYSICAL="M03_AXI_awaddr"/>
4079             <PORTMAP PHYSICAL="M03_AXI_awready"/>
4080             <PORTMAP PHYSICAL="M03_AXI_awvalid"/>
4081             <PORTMAP PHYSICAL="M03_AXI_bready"/>
4082             <PORTMAP PHYSICAL="M03_AXI_bresp"/>
4083             <PORTMAP PHYSICAL="M03_AXI_bvalid"/>
4084             <PORTMAP PHYSICAL="M03_AXI_rdata"/>
4085             <PORTMAP PHYSICAL="M03_AXI_rready"/>
4086             <PORTMAP PHYSICAL="M03_AXI_rresp"/>
4087             <PORTMAP PHYSICAL="M03_AXI_rvalid"/>
4088             <PORTMAP PHYSICAL="M03_AXI_wdata"/>
4089             <PORTMAP PHYSICAL="M03_AXI_wready"/>
4090             <PORTMAP PHYSICAL="M03_AXI_wstrb"/>
4091             <PORTMAP PHYSICAL="M03_AXI_wvalid"/>
4092           </PORTMAPS>
4093         </BUSINTERFACE>
4094         <BUSINTERFACE BUSNAME="microblaze_0_axi_periph_M04_AXI" NAME="M04_AXI" TYPE="MASTER">
4095           <PORTMAPS>
4096             <PORTMAP PHYSICAL="M04_AXI_araddr"/>
4097             <PORTMAP PHYSICAL="M04_AXI_arready"/>
4098             <PORTMAP PHYSICAL="M04_AXI_arvalid"/>
4099             <PORTMAP PHYSICAL="M04_AXI_awaddr"/>
4100             <PORTMAP PHYSICAL="M04_AXI_awready"/>
4101             <PORTMAP PHYSICAL="M04_AXI_awvalid"/>
4102             <PORTMAP PHYSICAL="M04_AXI_bready"/>
4103             <PORTMAP PHYSICAL="M04_AXI_bresp"/>
4104             <PORTMAP PHYSICAL="M04_AXI_bvalid"/>
4105             <PORTMAP PHYSICAL="M04_AXI_rdata"/>
4106             <PORTMAP PHYSICAL="M04_AXI_rready"/>
4107             <PORTMAP PHYSICAL="M04_AXI_rresp"/>
4108             <PORTMAP PHYSICAL="M04_AXI_rvalid"/>
4109             <PORTMAP PHYSICAL="M04_AXI_wdata"/>
4110             <PORTMAP PHYSICAL="M04_AXI_wready"/>
4111             <PORTMAP PHYSICAL="M04_AXI_wstrb"/>
4112             <PORTMAP PHYSICAL="M04_AXI_wvalid"/>
4113           </PORTMAPS>
4114         </BUSINTERFACE>
4115       </BUSINTERFACES>
4116     </MODULE>
4117     <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
4118       <DOCUMENTS>
4119         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
4120       </DOCUMENTS>
4121       <PARAMETERS>
4122         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
4123         <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
4124         <PARAMETER NAME="C_MASK" VALUE="0xc0000000"/>
4125         <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
4126         <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
4127         <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
4128         <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
4129         <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
4130         <PARAMETER NAME="C_ECC" VALUE="0"/>
4131         <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
4132         <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
4133         <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
4134         <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
4135         <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
4136         <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
4137         <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
4138         <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
4139         <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
4140         <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
4141         <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
4142         <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
4143         <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
4144         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_bram_if_cntlr_0"/>
4145         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
4146         <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
4147         <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
4148         <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
4149       </PARAMETERS>
4150       <PORTS>
4151         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
4152           <CONNECTIONS>
4153             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
4154           </CONNECTIONS>
4155         </PORT>
4156         <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
4157           <CONNECTIONS>
4158             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
4159           </CONNECTIONS>
4160         </PORT>
4161         <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
4162           <CONNECTIONS>
4163             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ABus"/>
4164           </CONNECTIONS>
4165         </PORT>
4166         <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
4167           <CONNECTIONS>
4168             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteDBus"/>
4169           </CONNECTIONS>
4170         </PORT>
4171         <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
4172           <CONNECTIONS>
4173             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_AddrStrobe"/>
4174           </CONNECTIONS>
4175         </PORT>
4176         <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
4177           <CONNECTIONS>
4178             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_ReadStrobe"/>
4179           </CONNECTIONS>
4180         </PORT>
4181         <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
4182           <CONNECTIONS>
4183             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_WriteStrobe"/>
4184           </CONNECTIONS>
4185         </PORT>
4186         <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
4187           <CONNECTIONS>
4188             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_BE"/>
4189           </CONNECTIONS>
4190         </PORT>
4191         <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
4192           <CONNECTIONS>
4193             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_DBus"/>
4194           </CONNECTIONS>
4195         </PORT>
4196         <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
4197           <CONNECTIONS>
4198             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Ready"/>
4199           </CONNECTIONS>
4200         </PORT>
4201         <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
4202           <CONNECTIONS>
4203             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_Wait"/>
4204           </CONNECTIONS>
4205         </PORT>
4206         <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
4207           <CONNECTIONS>
4208             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_UE"/>
4209           </CONNECTIONS>
4210         </PORT>
4211         <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
4212           <CONNECTIONS>
4213             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="Sl_CE"/>
4214           </CONNECTIONS>
4215         </PORT>
4216         <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
4217           <CONNECTIONS>
4218             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rsta"/>
4219           </CONNECTIONS>
4220         </PORT>
4221         <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
4222           <CONNECTIONS>
4223             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clka"/>
4224           </CONNECTIONS>
4225         </PORT>
4226         <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
4227           <CONNECTIONS>
4228             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addra"/>
4229           </CONNECTIONS>
4230         </PORT>
4231         <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
4232           <CONNECTIONS>
4233             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="ena"/>
4234           </CONNECTIONS>
4235         </PORT>
4236         <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
4237           <CONNECTIONS>
4238             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="wea"/>
4239           </CONNECTIONS>
4240         </PORT>
4241         <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
4242           <CONNECTIONS>
4243             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dina"/>
4244           </CONNECTIONS>
4245         </PORT>
4246         <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
4247           <CONNECTIONS>
4248             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="douta"/>
4249           </CONNECTIONS>
4250         </PORT>
4251       </PORTS>
4252       <BUSINTERFACES>
4253         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
4254           <PORTMAPS>
4255             <PORTMAP PHYSICAL="LMB_ABus"/>
4256             <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
4257             <PORTMAP PHYSICAL="LMB_BE"/>
4258             <PORTMAP PHYSICAL="Sl_CE"/>
4259             <PORTMAP PHYSICAL="Sl_DBus"/>
4260             <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
4261             <PORTMAP PHYSICAL="Sl_Ready"/>
4262             <PORTMAP PHYSICAL="Sl_UE"/>
4263             <PORTMAP PHYSICAL="Sl_Wait"/>
4264             <PORTMAP PHYSICAL="LMB_WriteDBus"/>
4265             <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
4266           </PORTMAPS>
4267         </BUSINTERFACE>
4268         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
4269           <PORTMAPS>
4270             <PORTMAP PHYSICAL="BRAM_Addr_A"/>
4271             <PORTMAP PHYSICAL="BRAM_Clk_A"/>
4272             <PORTMAP PHYSICAL="BRAM_Dout_A"/>
4273             <PORTMAP PHYSICAL="BRAM_Din_A"/>
4274             <PORTMAP PHYSICAL="BRAM_EN_A"/>
4275             <PORTMAP PHYSICAL="BRAM_Rst_A"/>
4276             <PORTMAP PHYSICAL="BRAM_WEN_A"/>
4277           </PORTMAPS>
4278         </BUSINTERFACE>
4279       </BUSINTERFACES>
4280     </MODULE>
4281     <MODULE FULLNAME="/microblaze_0_local_memory/dlmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_dlmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
4282       <DOCUMENTS>
4283         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
4284       </DOCUMENTS>
4285       <PARAMETERS>
4286         <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
4287         <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
4288         <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
4289         <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
4290         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_dlmb_v10_0"/>
4291         <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
4292       </PARAMETERS>
4293       <PORTS>
4294         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
4295           <CONNECTIONS>
4296             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
4297           </CONNECTIONS>
4298         </PORT>
4299         <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
4300           <CONNECTIONS>
4301             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
4302           </CONNECTIONS>
4303         </PORT>
4304         <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
4305         <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Addr">
4306           <CONNECTIONS>
4307             <CONNECTION INSTANCE="microblaze_0" PORT="Data_Addr"/>
4308           </CONNECTIONS>
4309         </PORT>
4310         <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_Read_Strobe">
4311           <CONNECTIONS>
4312             <CONNECTION INSTANCE="microblaze_0" PORT="Read_Strobe"/>
4313           </CONNECTIONS>
4314         </PORT>
4315         <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_Write_Strobe">
4316           <CONNECTIONS>
4317             <CONNECTION INSTANCE="microblaze_0" PORT="Write_Strobe"/>
4318           </CONNECTIONS>
4319         </PORT>
4320         <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_D_AS">
4321           <CONNECTIONS>
4322             <CONNECTION INSTANCE="microblaze_0" PORT="D_AS"/>
4323           </CONNECTIONS>
4324         </PORT>
4325         <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Write">
4326           <CONNECTIONS>
4327             <CONNECTION INSTANCE="microblaze_0" PORT="Data_Write"/>
4328           </CONNECTIONS>
4329         </PORT>
4330         <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_Byte_Enable">
4331           <CONNECTIONS>
4332             <CONNECTION INSTANCE="microblaze_0" PORT="Byte_Enable"/>
4333           </CONNECTIONS>
4334         </PORT>
4335         <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_DBus">
4336           <CONNECTIONS>
4337             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_DBus"/>
4338           </CONNECTIONS>
4339         </PORT>
4340         <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Ready">
4341           <CONNECTIONS>
4342             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Ready"/>
4343           </CONNECTIONS>
4344         </PORT>
4345         <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_Wait">
4346           <CONNECTIONS>
4347             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_Wait"/>
4348           </CONNECTIONS>
4349         </PORT>
4350         <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_UE">
4351           <CONNECTIONS>
4352             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_UE"/>
4353           </CONNECTIONS>
4354         </PORT>
4355         <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_Sl_CE">
4356           <CONNECTIONS>
4357             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="Sl_CE"/>
4358           </CONNECTIONS>
4359         </PORT>
4360         <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ABus">
4361           <CONNECTIONS>
4362             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ABus"/>
4363           </CONNECTIONS>
4364         </PORT>
4365         <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_ReadStrobe">
4366           <CONNECTIONS>
4367             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
4368           </CONNECTIONS>
4369         </PORT>
4370         <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteStrobe">
4371           <CONNECTIONS>
4372             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
4373           </CONNECTIONS>
4374         </PORT>
4375         <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_AddrStrobe">
4376           <CONNECTIONS>
4377             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
4378           </CONNECTIONS>
4379         </PORT>
4380         <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Data_Read">
4381           <CONNECTIONS>
4382             <CONNECTION INSTANCE="microblaze_0" PORT="Data_Read"/>
4383           </CONNECTIONS>
4384         </PORT>
4385         <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_WriteDBus">
4386           <CONNECTIONS>
4387             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
4388           </CONNECTIONS>
4389         </PORT>
4390         <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_DReady">
4391           <CONNECTIONS>
4392             <CONNECTION INSTANCE="microblaze_0" PORT="DReady"/>
4393           </CONNECTIONS>
4394         </PORT>
4395         <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_DWait">
4396           <CONNECTIONS>
4397             <CONNECTION INSTANCE="microblaze_0" PORT="DWait"/>
4398           </CONNECTIONS>
4399         </PORT>
4400         <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_DUE">
4401           <CONNECTIONS>
4402             <CONNECTION INSTANCE="microblaze_0" PORT="DUE"/>
4403           </CONNECTIONS>
4404         </PORT>
4405         <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_DCE">
4406           <CONNECTIONS>
4407             <CONNECTION INSTANCE="microblaze_0" PORT="DCE"/>
4408           </CONNECTIONS>
4409         </PORT>
4410         <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_LMB_BE">
4411           <CONNECTIONS>
4412             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_BE"/>
4413           </CONNECTIONS>
4414         </PORT>
4415       </PORTS>
4416       <BUSINTERFACES>
4417         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
4418           <PORTMAPS>
4419             <PORTMAP PHYSICAL="LMB_ABus"/>
4420             <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
4421             <PORTMAP PHYSICAL="LMB_BE"/>
4422             <PORTMAP PHYSICAL="Sl_CE"/>
4423             <PORTMAP PHYSICAL="Sl_DBus"/>
4424             <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
4425             <PORTMAP PHYSICAL="Sl_Ready"/>
4426             <PORTMAP PHYSICAL="LMB_Rst"/>
4427             <PORTMAP PHYSICAL="Sl_UE"/>
4428             <PORTMAP PHYSICAL="Sl_Wait"/>
4429             <PORTMAP PHYSICAL="LMB_WriteDBus"/>
4430             <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
4431           </PORTMAPS>
4432         </BUSINTERFACE>
4433         <BUSINTERFACE BUSNAME="microblaze_0_DLMB" NAME="LMB_M" TYPE="SLAVE">
4434           <PORTMAPS>
4435             <PORTMAP PHYSICAL="M_ABus"/>
4436             <PORTMAP PHYSICAL="M_AddrStrobe"/>
4437             <PORTMAP PHYSICAL="M_BE"/>
4438             <PORTMAP PHYSICAL="LMB_CE"/>
4439             <PORTMAP PHYSICAL="LMB_ReadDBus"/>
4440             <PORTMAP PHYSICAL="M_ReadStrobe"/>
4441             <PORTMAP PHYSICAL="LMB_Ready"/>
4442             <PORTMAP PHYSICAL="LMB_Rst"/>
4443             <PORTMAP PHYSICAL="LMB_UE"/>
4444             <PORTMAP PHYSICAL="LMB_Wait"/>
4445             <PORTMAP PHYSICAL="M_DBus"/>
4446             <PORTMAP PHYSICAL="M_WriteStrobe"/>
4447           </PORTMAPS>
4448         </BUSINTERFACE>
4449       </BUSINTERFACES>
4450     </MODULE>
4451     <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_bram_if_cntlr" HWVERSION="4.0" INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
4452       <DOCUMENTS>
4453         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
4454       </DOCUMENTS>
4455       <PARAMETERS>
4456         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
4457         <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
4458         <PARAMETER NAME="C_MASK" VALUE="0x80000000"/>
4459         <PARAMETER NAME="C_MASK1" VALUE="0x00800000"/>
4460         <PARAMETER NAME="C_MASK2" VALUE="0x00800000"/>
4461         <PARAMETER NAME="C_MASK3" VALUE="0x00800000"/>
4462         <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
4463         <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
4464         <PARAMETER NAME="C_ECC" VALUE="0"/>
4465         <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
4466         <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
4467         <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
4468         <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
4469         <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
4470         <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
4471         <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
4472         <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
4473         <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
4474         <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
4475         <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
4476         <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
4477         <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
4478         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_bram_if_cntlr_0"/>
4479         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
4480         <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
4481         <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
4482         <PARAMETER NAME="C_HIGHADDR" VALUE="0x0003FFFF"/>
4483       </PARAMETERS>
4484       <PORTS>
4485         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
4486           <CONNECTIONS>
4487             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
4488           </CONNECTIONS>
4489         </PORT>
4490         <PORT DIR="I" NAME="LMB_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
4491           <CONNECTIONS>
4492             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
4493           </CONNECTIONS>
4494         </PORT>
4495         <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
4496           <CONNECTIONS>
4497             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ABus"/>
4498           </CONNECTIONS>
4499         </PORT>
4500         <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
4501           <CONNECTIONS>
4502             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteDBus"/>
4503           </CONNECTIONS>
4504         </PORT>
4505         <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
4506           <CONNECTIONS>
4507             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_AddrStrobe"/>
4508           </CONNECTIONS>
4509         </PORT>
4510         <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
4511           <CONNECTIONS>
4512             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_ReadStrobe"/>
4513           </CONNECTIONS>
4514         </PORT>
4515         <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
4516           <CONNECTIONS>
4517             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_WriteStrobe"/>
4518           </CONNECTIONS>
4519         </PORT>
4520         <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
4521           <CONNECTIONS>
4522             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_BE"/>
4523           </CONNECTIONS>
4524         </PORT>
4525         <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
4526           <CONNECTIONS>
4527             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_DBus"/>
4528           </CONNECTIONS>
4529         </PORT>
4530         <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
4531           <CONNECTIONS>
4532             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Ready"/>
4533           </CONNECTIONS>
4534         </PORT>
4535         <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
4536           <CONNECTIONS>
4537             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_Wait"/>
4538           </CONNECTIONS>
4539         </PORT>
4540         <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
4541           <CONNECTIONS>
4542             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_UE"/>
4543           </CONNECTIONS>
4544         </PORT>
4545         <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
4546           <CONNECTIONS>
4547             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="Sl_CE"/>
4548           </CONNECTIONS>
4549         </PORT>
4550         <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
4551           <CONNECTIONS>
4552             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="rstb"/>
4553           </CONNECTIONS>
4554         </PORT>
4555         <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
4556           <CONNECTIONS>
4557             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="clkb"/>
4558           </CONNECTIONS>
4559         </PORT>
4560         <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
4561           <CONNECTIONS>
4562             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="addrb"/>
4563           </CONNECTIONS>
4564         </PORT>
4565         <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
4566           <CONNECTIONS>
4567             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="enb"/>
4568           </CONNECTIONS>
4569         </PORT>
4570         <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
4571           <CONNECTIONS>
4572             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="web"/>
4573           </CONNECTIONS>
4574         </PORT>
4575         <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
4576           <CONNECTIONS>
4577             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="dinb"/>
4578           </CONNECTIONS>
4579         </PORT>
4580         <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
4581           <CONNECTIONS>
4582             <CONNECTION INSTANCE="microblaze_0_local_memory_lmb_bram" PORT="doutb"/>
4583           </CONNECTIONS>
4584         </PORT>
4585       </PORTS>
4586       <BUSINTERFACES>
4587         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="SLMB" TYPE="SLAVE">
4588           <PORTMAPS>
4589             <PORTMAP PHYSICAL="LMB_ABus"/>
4590             <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
4591             <PORTMAP PHYSICAL="LMB_BE"/>
4592             <PORTMAP PHYSICAL="Sl_CE"/>
4593             <PORTMAP PHYSICAL="Sl_DBus"/>
4594             <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
4595             <PORTMAP PHYSICAL="Sl_Ready"/>
4596             <PORTMAP PHYSICAL="Sl_UE"/>
4597             <PORTMAP PHYSICAL="Sl_Wait"/>
4598             <PORTMAP PHYSICAL="LMB_WriteDBus"/>
4599             <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
4600           </PORTMAPS>
4601         </BUSINTERFACE>
4602         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR">
4603           <PORTMAPS>
4604             <PORTMAP PHYSICAL="BRAM_Addr_A"/>
4605             <PORTMAP PHYSICAL="BRAM_Clk_A"/>
4606             <PORTMAP PHYSICAL="BRAM_Dout_A"/>
4607             <PORTMAP PHYSICAL="BRAM_Din_A"/>
4608             <PORTMAP PHYSICAL="BRAM_EN_A"/>
4609             <PORTMAP PHYSICAL="BRAM_Rst_A"/>
4610             <PORTMAP PHYSICAL="BRAM_WEN_A"/>
4611           </PORTMAPS>
4612         </BUSINTERFACE>
4613       </BUSINTERFACES>
4614     </MODULE>
4615     <MODULE FULLNAME="/microblaze_0_local_memory/ilmb_v10" HWVERSION="3.0" INSTANCE="microblaze_0_local_memory_ilmb_v10" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
4616       <DOCUMENTS>
4617         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
4618       </DOCUMENTS>
4619       <PARAMETERS>
4620         <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
4621         <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
4622         <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
4623         <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
4624         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_ilmb_v10_0"/>
4625         <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
4626       </PARAMETERS>
4627       <PORTS>
4628         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
4629           <CONNECTIONS>
4630             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
4631           </CONNECTIONS>
4632         </PORT>
4633         <PORT DIR="I" NAME="SYS_Rst" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
4634           <CONNECTIONS>
4635             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="bus_struct_reset"/>
4636           </CONNECTIONS>
4637         </PORT>
4638         <PORT DIR="O" NAME="LMB_Rst" SIGIS="undef"/>
4639         <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr_Addr">
4640           <CONNECTIONS>
4641             <CONNECTION INSTANCE="microblaze_0" PORT="Instr_Addr"/>
4642           </CONNECTIONS>
4643         </PORT>
4644         <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_IFetch">
4645           <CONNECTIONS>
4646             <CONNECTION INSTANCE="microblaze_0" PORT="IFetch"/>
4647           </CONNECTIONS>
4648         </PORT>
4649         <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef"/>
4650         <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_I_AS">
4651           <CONNECTIONS>
4652             <CONNECTION INSTANCE="microblaze_0" PORT="I_AS"/>
4653           </CONNECTIONS>
4654         </PORT>
4655         <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef"/>
4656         <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef"/>
4657         <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_DBus">
4658           <CONNECTIONS>
4659             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_DBus"/>
4660           </CONNECTIONS>
4661         </PORT>
4662         <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Ready">
4663           <CONNECTIONS>
4664             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Ready"/>
4665           </CONNECTIONS>
4666         </PORT>
4667         <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_Wait">
4668           <CONNECTIONS>
4669             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_Wait"/>
4670           </CONNECTIONS>
4671         </PORT>
4672         <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_UE">
4673           <CONNECTIONS>
4674             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_UE"/>
4675           </CONNECTIONS>
4676         </PORT>
4677         <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_Sl_CE">
4678           <CONNECTIONS>
4679             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="Sl_CE"/>
4680           </CONNECTIONS>
4681         </PORT>
4682         <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ABus">
4683           <CONNECTIONS>
4684             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ABus"/>
4685           </CONNECTIONS>
4686         </PORT>
4687         <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_ReadStrobe">
4688           <CONNECTIONS>
4689             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_ReadStrobe"/>
4690           </CONNECTIONS>
4691         </PORT>
4692         <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteStrobe">
4693           <CONNECTIONS>
4694             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteStrobe"/>
4695           </CONNECTIONS>
4696         </PORT>
4697         <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_AddrStrobe">
4698           <CONNECTIONS>
4699             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_AddrStrobe"/>
4700           </CONNECTIONS>
4701         </PORT>
4702         <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_Instr">
4703           <CONNECTIONS>
4704             <CONNECTION INSTANCE="microblaze_0" PORT="Instr"/>
4705           </CONNECTIONS>
4706         </PORT>
4707         <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_WriteDBus">
4708           <CONNECTIONS>
4709             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_WriteDBus"/>
4710           </CONNECTIONS>
4711         </PORT>
4712         <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="microblaze_0_IReady">
4713           <CONNECTIONS>
4714             <CONNECTION INSTANCE="microblaze_0" PORT="IReady"/>
4715           </CONNECTIONS>
4716         </PORT>
4717         <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="microblaze_0_IWAIT">
4718           <CONNECTIONS>
4719             <CONNECTION INSTANCE="microblaze_0" PORT="IWAIT"/>
4720           </CONNECTIONS>
4721         </PORT>
4722         <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="microblaze_0_IUE">
4723           <CONNECTIONS>
4724             <CONNECTION INSTANCE="microblaze_0" PORT="IUE"/>
4725           </CONNECTIONS>
4726         </PORT>
4727         <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="microblaze_0_ICE">
4728           <CONNECTIONS>
4729             <CONNECTION INSTANCE="microblaze_0" PORT="ICE"/>
4730           </CONNECTIONS>
4731         </PORT>
4732         <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_LMB_BE">
4733           <CONNECTIONS>
4734             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_BE"/>
4735           </CONNECTIONS>
4736         </PORT>
4737       </PORTS>
4738       <BUSINTERFACES>
4739         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_v10_LMB_Sl_0" NAME="LMB_Sl_0" TYPE="SLAVE">
4740           <PORTMAPS>
4741             <PORTMAP PHYSICAL="LMB_ABus"/>
4742             <PORTMAP PHYSICAL="LMB_AddrStrobe"/>
4743             <PORTMAP PHYSICAL="LMB_BE"/>
4744             <PORTMAP PHYSICAL="Sl_CE"/>
4745             <PORTMAP PHYSICAL="Sl_DBus"/>
4746             <PORTMAP PHYSICAL="LMB_ReadStrobe"/>
4747             <PORTMAP PHYSICAL="Sl_Ready"/>
4748             <PORTMAP PHYSICAL="LMB_Rst"/>
4749             <PORTMAP PHYSICAL="Sl_UE"/>
4750             <PORTMAP PHYSICAL="Sl_Wait"/>
4751             <PORTMAP PHYSICAL="LMB_WriteDBus"/>
4752             <PORTMAP PHYSICAL="LMB_WriteStrobe"/>
4753           </PORTMAPS>
4754         </BUSINTERFACE>
4755         <BUSINTERFACE BUSNAME="microblaze_0_ILMB" NAME="LMB_M" TYPE="SLAVE">
4756           <PORTMAPS>
4757             <PORTMAP PHYSICAL="M_ABus"/>
4758             <PORTMAP PHYSICAL="M_AddrStrobe"/>
4759             <PORTMAP PHYSICAL="M_BE"/>
4760             <PORTMAP PHYSICAL="LMB_CE"/>
4761             <PORTMAP PHYSICAL="LMB_ReadDBus"/>
4762             <PORTMAP PHYSICAL="M_ReadStrobe"/>
4763             <PORTMAP PHYSICAL="LMB_Ready"/>
4764             <PORTMAP PHYSICAL="LMB_Rst"/>
4765             <PORTMAP PHYSICAL="LMB_UE"/>
4766             <PORTMAP PHYSICAL="LMB_Wait"/>
4767             <PORTMAP PHYSICAL="M_DBus"/>
4768             <PORTMAP PHYSICAL="M_WriteStrobe"/>
4769           </PORTMAPS>
4770         </BUSINTERFACE>
4771       </BUSINTERFACES>
4772     </MODULE>
4773     <MODULE FULLNAME="/microblaze_0_local_memory/lmb_bram" HWVERSION="8.2" INSTANCE="microblaze_0_local_memory_lmb_bram" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY" MODTYPE="blk_mem_gen" VLNV="xilinx.com:ip:blk_mem_gen:8.2">
4774       <DOCUMENTS>
4775         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=blk_mem_gen;v=v8_2;d=pg058-blk-mem-gen.pdf"/>
4776       </DOCUMENTS>
4777       <PARAMETERS>
4778         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
4779         <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="kintex7"/>
4780         <PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
4781         <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
4782         <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
4783         <PARAMETER NAME="C_AXI_SLAVE_TYPE" VALUE="0"/>
4784         <PARAMETER NAME="C_USE_BRAM_BLOCK" VALUE="1"/>
4785         <PARAMETER NAME="C_ENABLE_32BIT_ADDRESS" VALUE="1"/>
4786         <PARAMETER NAME="C_CTRL_ECC_ALGO" VALUE="NONE"/>
4787         <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
4788         <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="4"/>
4789         <PARAMETER NAME="C_MEM_TYPE" VALUE="2"/>
4790         <PARAMETER NAME="C_BYTE_SIZE" VALUE="8"/>
4791         <PARAMETER NAME="C_ALGORITHM" VALUE="1"/>
4792         <PARAMETER NAME="C_PRIM_TYPE" VALUE="1"/>
4793         <PARAMETER NAME="C_LOAD_INIT_FILE" VALUE="0"/>
4794         <PARAMETER NAME="C_INIT_FILE_NAME" VALUE="no_coe_file_loaded"/>
4795         <PARAMETER NAME="C_INIT_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
4796         <PARAMETER NAME="C_USE_DEFAULT_DATA" VALUE="0"/>
4797         <PARAMETER NAME="C_DEFAULT_DATA" VALUE="0"/>
4798         <PARAMETER NAME="C_HAS_RSTA" VALUE="1"/>
4799         <PARAMETER NAME="C_RST_PRIORITY_A" VALUE="CE"/>
4800         <PARAMETER NAME="C_RSTRAM_A" VALUE="0"/>
4801         <PARAMETER NAME="C_INITA_VAL" VALUE="0"/>
4802         <PARAMETER NAME="C_HAS_ENA" VALUE="1"/>
4803         <PARAMETER NAME="C_HAS_REGCEA" VALUE="0"/>
4804         <PARAMETER NAME="C_USE_BYTE_WEA" VALUE="1"/>
4805         <PARAMETER NAME="C_WEA_WIDTH" VALUE="4"/>
4806         <PARAMETER NAME="C_WRITE_MODE_A" VALUE="WRITE_FIRST"/>
4807         <PARAMETER NAME="C_WRITE_WIDTH_A" VALUE="32"/>
4808         <PARAMETER NAME="C_READ_WIDTH_A" VALUE="32"/>
4809         <PARAMETER NAME="C_WRITE_DEPTH_A" VALUE="65536"/>
4810         <PARAMETER NAME="C_READ_DEPTH_A" VALUE="65536"/>
4811         <PARAMETER NAME="C_ADDRA_WIDTH" VALUE="32"/>
4812         <PARAMETER NAME="C_HAS_RSTB" VALUE="1"/>
4813         <PARAMETER NAME="C_RST_PRIORITY_B" VALUE="CE"/>
4814         <PARAMETER NAME="C_RSTRAM_B" VALUE="0"/>
4815         <PARAMETER NAME="C_INITB_VAL" VALUE="0"/>
4816         <PARAMETER NAME="C_HAS_ENB" VALUE="1"/>
4817         <PARAMETER NAME="C_HAS_REGCEB" VALUE="0"/>
4818         <PARAMETER NAME="C_USE_BYTE_WEB" VALUE="1"/>
4819         <PARAMETER NAME="C_WEB_WIDTH" VALUE="4"/>
4820         <PARAMETER NAME="C_WRITE_MODE_B" VALUE="WRITE_FIRST"/>
4821         <PARAMETER NAME="C_WRITE_WIDTH_B" VALUE="32"/>
4822         <PARAMETER NAME="C_READ_WIDTH_B" VALUE="32"/>
4823         <PARAMETER NAME="C_WRITE_DEPTH_B" VALUE="65536"/>
4824         <PARAMETER NAME="C_READ_DEPTH_B" VALUE="65536"/>
4825         <PARAMETER NAME="C_ADDRB_WIDTH" VALUE="32"/>
4826         <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_A" VALUE="0"/>
4827         <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_B" VALUE="0"/>
4828         <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_A" VALUE="0"/>
4829         <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_B" VALUE="0"/>
4830         <PARAMETER NAME="C_MUX_PIPELINE_STAGES" VALUE="0"/>
4831         <PARAMETER NAME="C_HAS_SOFTECC_INPUT_REGS_A" VALUE="0"/>
4832         <PARAMETER NAME="C_HAS_SOFTECC_OUTPUT_REGS_B" VALUE="0"/>
4833         <PARAMETER NAME="C_USE_SOFTECC" VALUE="0"/>
4834         <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
4835         <PARAMETER NAME="C_EN_ECC_PIPE" VALUE="0"/>
4836         <PARAMETER NAME="C_HAS_INJECTERR" VALUE="0"/>
4837         <PARAMETER NAME="C_SIM_COLLISION_CHECK" VALUE="ALL"/>
4838         <PARAMETER NAME="C_COMMON_CLK" VALUE="0"/>
4839         <PARAMETER NAME="C_DISABLE_WARN_BHV_COLL" VALUE="0"/>
4840         <PARAMETER NAME="C_EN_SLEEP_PIN" VALUE="0"/>
4841         <PARAMETER NAME="C_DISABLE_WARN_BHV_RANGE" VALUE="0"/>
4842         <PARAMETER NAME="C_COUNT_36K_BRAM" VALUE="64"/>
4843         <PARAMETER NAME="C_COUNT_18K_BRAM" VALUE="0"/>
4844         <PARAMETER NAME="C_EST_POWER_SUMMARY" VALUE="Estimated Power for IP     :     20.388004 mW"/>
4845         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_lmb_bram_0"/>
4846         <PARAMETER NAME="Interface_Type" VALUE="Native"/>
4847         <PARAMETER NAME="AXI_Type" VALUE="AXI4_Full"/>
4848         <PARAMETER NAME="AXI_Slave_Type" VALUE="Memory_Slave"/>
4849         <PARAMETER NAME="Use_AXI_ID" VALUE="false"/>
4850         <PARAMETER NAME="AXI_ID_Width" VALUE="4"/>
4851         <PARAMETER NAME="Memory_Type" VALUE="True_Dual_Port_RAM"/>
4852         <PARAMETER NAME="Enable_32bit_Address" VALUE="true"/>
4853         <PARAMETER NAME="ecctype" VALUE="No_ECC"/>
4854         <PARAMETER NAME="ECC" VALUE="false"/>
4855         <PARAMETER NAME="softecc" VALUE="false"/>
4856         <PARAMETER NAME="EN_SLEEP_PIN" VALUE="false"/>
4857         <PARAMETER NAME="EN_ECC_PIPE" VALUE="false"/>
4858         <PARAMETER NAME="Use_Error_Injection_Pins" VALUE="false"/>
4859         <PARAMETER NAME="Error_Injection_Type" VALUE="Single_Bit_Error_Injection"/>
4860         <PARAMETER NAME="Use_Byte_Write_Enable" VALUE="true"/>
4861         <PARAMETER NAME="Byte_Size" VALUE="8"/>
4862         <PARAMETER NAME="Algorithm" VALUE="Minimum_Area"/>
4863         <PARAMETER NAME="Primitive" VALUE="8kx2"/>
4864         <PARAMETER NAME="Assume_Synchronous_Clk" VALUE="false"/>
4865         <PARAMETER NAME="Write_Width_A" VALUE="32"/>
4866         <PARAMETER NAME="Write_Depth_A" VALUE="65536"/>
4867         <PARAMETER NAME="Read_Width_A" VALUE="32"/>
4868         <PARAMETER NAME="Operating_Mode_A" VALUE="WRITE_FIRST"/>
4869         <PARAMETER NAME="Enable_A" VALUE="Use_ENA_Pin"/>
4870         <PARAMETER NAME="Write_Width_B" VALUE="32"/>
4871         <PARAMETER NAME="Read_Width_B" VALUE="32"/>
4872         <PARAMETER NAME="Operating_Mode_B" VALUE="WRITE_FIRST"/>
4873         <PARAMETER NAME="Enable_B" VALUE="Use_ENB_Pin"/>
4874         <PARAMETER NAME="Register_PortA_Output_of_Memory_Primitives" VALUE="false"/>
4875         <PARAMETER NAME="Register_PortA_Output_of_Memory_Core" VALUE="false"/>
4876         <PARAMETER NAME="Use_REGCEA_Pin" VALUE="false"/>
4877         <PARAMETER NAME="Register_PortB_Output_of_Memory_Primitives" VALUE="false"/>
4878         <PARAMETER NAME="Register_PortB_Output_of_Memory_Core" VALUE="false"/>
4879         <PARAMETER NAME="Use_REGCEB_Pin" VALUE="false"/>
4880         <PARAMETER NAME="register_porta_input_of_softecc" VALUE="false"/>
4881         <PARAMETER NAME="register_portb_output_of_softecc" VALUE="false"/>
4882         <PARAMETER NAME="Pipeline_Stages" VALUE="0"/>
4883         <PARAMETER NAME="Load_Init_File" VALUE="false"/>
4884         <PARAMETER NAME="Coe_File" VALUE="no_coe_file_loaded"/>
4885         <PARAMETER NAME="Fill_Remaining_Memory_Locations" VALUE="false"/>
4886         <PARAMETER NAME="Remaining_Memory_Locations" VALUE="0"/>
4887         <PARAMETER NAME="Use_RSTA_Pin" VALUE="true"/>
4888         <PARAMETER NAME="Reset_Memory_Latch_A" VALUE="false"/>
4889         <PARAMETER NAME="Reset_Priority_A" VALUE="CE"/>
4890         <PARAMETER NAME="Output_Reset_Value_A" VALUE="0"/>
4891         <PARAMETER NAME="Use_RSTB_Pin" VALUE="true"/>
4892         <PARAMETER NAME="Reset_Memory_Latch_B" VALUE="false"/>
4893         <PARAMETER NAME="Reset_Priority_B" VALUE="CE"/>
4894         <PARAMETER NAME="Output_Reset_Value_B" VALUE="0"/>
4895         <PARAMETER NAME="Reset_Type" VALUE="SYNC"/>
4896         <PARAMETER NAME="Additional_Inputs_for_Power_Estimation" VALUE="false"/>
4897         <PARAMETER NAME="Port_A_Clock" VALUE="100"/>
4898         <PARAMETER NAME="Port_A_Write_Rate" VALUE="50"/>
4899         <PARAMETER NAME="Port_B_Clock" VALUE="100"/>
4900         <PARAMETER NAME="Port_B_Write_Rate" VALUE="50"/>
4901         <PARAMETER NAME="Port_A_Enable_Rate" VALUE="100"/>
4902         <PARAMETER NAME="Port_B_Enable_Rate" VALUE="100"/>
4903         <PARAMETER NAME="Collision_Warnings" VALUE="ALL"/>
4904         <PARAMETER NAME="Disable_Collision_Warnings" VALUE="false"/>
4905         <PARAMETER NAME="Disable_Out_of_Range_Warnings" VALUE="false"/>
4906         <PARAMETER NAME="use_bram_block" VALUE="BRAM_Controller"/>
4907         <PARAMETER NAME="MEM_FILE" VALUE="base_microblaze_design_lmb_bram_0.mem"/>
4908         <PARAMETER NAME="CTRL_ECC_ALGO" VALUE="NONE"/>
4909         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
4910       </PARAMETERS>
4911       <PORTS>
4912         <PORT DIR="I" NAME="clka" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Clk_A">
4913           <CONNECTIONS>
4914             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
4915           </CONNECTIONS>
4916         </PORT>
4917         <PORT DIR="I" NAME="rsta" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Rst_A">
4918           <CONNECTIONS>
4919             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
4920           </CONNECTIONS>
4921         </PORT>
4922         <PORT DIR="I" NAME="ena" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_EN_A">
4923           <CONNECTIONS>
4924             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
4925           </CONNECTIONS>
4926         </PORT>
4927         <PORT DIR="I" LEFT="3" NAME="wea" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_WEN_A">
4928           <CONNECTIONS>
4929             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
4930           </CONNECTIONS>
4931         </PORT>
4932         <PORT DIR="I" LEFT="31" NAME="addra" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Addr_A">
4933           <CONNECTIONS>
4934             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
4935           </CONNECTIONS>
4936         </PORT>
4937         <PORT DIR="I" LEFT="31" NAME="dina" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Dout_A">
4938           <CONNECTIONS>
4939             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
4940           </CONNECTIONS>
4941         </PORT>
4942         <PORT DIR="O" LEFT="31" NAME="douta" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_Din_A">
4943           <CONNECTIONS>
4944             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
4945           </CONNECTIONS>
4946         </PORT>
4947         <PORT DIR="I" NAME="clkb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Clk_A">
4948           <CONNECTIONS>
4949             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Clk_A"/>
4950           </CONNECTIONS>
4951         </PORT>
4952         <PORT DIR="I" NAME="rstb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Rst_A">
4953           <CONNECTIONS>
4954             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Rst_A"/>
4955           </CONNECTIONS>
4956         </PORT>
4957         <PORT DIR="I" NAME="enb" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_EN_A">
4958           <CONNECTIONS>
4959             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_EN_A"/>
4960           </CONNECTIONS>
4961         </PORT>
4962         <PORT DIR="I" LEFT="3" NAME="web" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_WEN_A">
4963           <CONNECTIONS>
4964             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_WEN_A"/>
4965           </CONNECTIONS>
4966         </PORT>
4967         <PORT DIR="I" LEFT="31" NAME="addrb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Addr_A">
4968           <CONNECTIONS>
4969             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Addr_A"/>
4970           </CONNECTIONS>
4971         </PORT>
4972         <PORT DIR="I" LEFT="31" NAME="dinb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Dout_A">
4973           <CONNECTIONS>
4974             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Dout_A"/>
4975           </CONNECTIONS>
4976         </PORT>
4977         <PORT DIR="O" LEFT="31" NAME="doutb" RIGHT="0" SIGIS="undef" SIGNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_Din_A">
4978           <CONNECTIONS>
4979             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="BRAM_Din_A"/>
4980           </CONNECTIONS>
4981         </PORT>
4982       </PORTS>
4983       <BUSINTERFACES>
4984         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_dlmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTA" TYPE="TARGET">
4985           <PORTMAPS>
4986             <PORTMAP PHYSICAL="addra"/>
4987             <PORTMAP PHYSICAL="clka"/>
4988             <PORTMAP PHYSICAL="dina"/>
4989             <PORTMAP PHYSICAL="douta"/>
4990             <PORTMAP PHYSICAL="ena"/>
4991             <PORTMAP PHYSICAL="rsta"/>
4992             <PORTMAP PHYSICAL="wea"/>
4993           </PORTMAPS>
4994         </BUSINTERFACE>
4995         <BUSINTERFACE BUSNAME="microblaze_0_local_memory_ilmb_bram_if_cntlr_BRAM_PORT" NAME="BRAM_PORTB" TYPE="TARGET">
4996           <PORTMAPS>
4997             <PORTMAP PHYSICAL="addrb"/>
4998             <PORTMAP PHYSICAL="clkb"/>
4999             <PORTMAP PHYSICAL="dinb"/>
5000             <PORTMAP PHYSICAL="doutb"/>
5001             <PORTMAP PHYSICAL="enb"/>
5002             <PORTMAP PHYSICAL="rstb"/>
5003             <PORTMAP PHYSICAL="web"/>
5004           </PORTMAPS>
5005         </BUSINTERFACE>
5006       </BUSINTERFACES>
5007     </MODULE>
5008     <MODULE FULLNAME="/mig_7series_0" HWVERSION="2.3" INSTANCE="mig_7series_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="mig_7series" VLNV="xilinx.com:ip:mig_7series:2.3">
5009       <DOCUMENTS/>
5010       <PARAMETERS>
5011         <PARAMETER NAME="NoOfControllers" VALUE="1"/>
5012         <PARAMETER NAME="COMBINED_INTERFACE" VALUE="0"/>
5013         <PARAMETER NAME="REFCLK_TYPE" VALUE="NONE"/>
5014         <PARAMETER NAME="MEM_TYPE" VALUE="DDR3"/>
5015         <PARAMETER NAME="TEMP_MON_CONTROL" VALUE="INTERNAL"/>
5016         <PARAMETER NAME="POLARITY" VALUE="ACTIVE_HIGH"/>
5017         <PARAMETER NAME="IS_CLK_SHARED" VALUE="FALSE"/>
5018         <PARAMETER NAME="SYSCLK_TYPE" VALUE="DIFF"/>
5019         <PARAMETER NAME="USE_AXI" VALUE="1"/>
5020         <PARAMETER NAME="ECC" VALUE="OFF"/>
5021         <PARAMETER NAME="DDR3_DQ_WIDTH" VALUE="64"/>
5022         <PARAMETER NAME="DDR3_DQS_WIDTH" VALUE="8"/>
5023         <PARAMETER NAME="DDR3_ROW_WIDTH" VALUE="14"/>
5024         <PARAMETER NAME="DDR3_BANK_WIDTH" VALUE="3"/>
5025         <PARAMETER NAME="DDR3_CK_WIDTH" VALUE="1"/>
5026         <PARAMETER NAME="DDR3_CKE_WIDTH" VALUE="1"/>
5027         <PARAMETER NAME="DDR3_CS_WIDTH" VALUE="1"/>
5028         <PARAMETER NAME="DDR3_nCS_PER_RANK" VALUE="1"/>
5029         <PARAMETER NAME="DDR3_DM_WIDTH" VALUE="8"/>
5030         <PARAMETER NAME="DDR3_ODT_WIDTH" VALUE="1"/>
5031         <PARAMETER NAME="DDR3_USE_CS_PORT" VALUE="1"/>
5032         <PARAMETER NAME="DDR3_USE_DM_PORT" VALUE="1"/>
5033         <PARAMETER NAME="DDR3_USE_ODT_PORT" VALUE="1"/>
5034         <PARAMETER NAME="DDR3_REG_CTRL" VALUE="OFF"/>
5035         <PARAMETER NAME="DDR3_DQS_CNT_WIDTH" VALUE="3"/>
5036         <PARAMETER NAME="DDR3_DEBUG_PORT" VALUE="OFF"/>
5037         <PARAMETER NAME="DDR2_DQ_WIDTH" VALUE="8"/>
5038         <PARAMETER NAME="DDR2_DQS_WIDTH" VALUE="1"/>
5039         <PARAMETER NAME="DDR2_ROW_WIDTH" VALUE="14"/>
5040         <PARAMETER NAME="DDR2_BANK_WIDTH" VALUE="3"/>
5041         <PARAMETER NAME="DDR2_CK_WIDTH" VALUE="1"/>
5042         <PARAMETER NAME="DDR2_CKE_WIDTH" VALUE="1"/>
5043         <PARAMETER NAME="DDR2_CS_WIDTH" VALUE="1"/>
5044         <PARAMETER NAME="DDR2_nCS_PER_RANK" VALUE="1"/>
5045         <PARAMETER NAME="DDR2_DM_WIDTH" VALUE="1"/>
5046         <PARAMETER NAME="DDR2_ODT_WIDTH" VALUE="1"/>
5047         <PARAMETER NAME="DDR2_USE_CS_PORT" VALUE="1"/>
5048         <PARAMETER NAME="DDR2_USE_DM_PORT" VALUE="1"/>
5049         <PARAMETER NAME="DDR2_USE_ODT_PORT" VALUE="1"/>
5050         <PARAMETER NAME="DDR2_REG_CTRL" VALUE="OFF"/>
5051         <PARAMETER NAME="DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5052         <PARAMETER NAME="DDR2_DEBUG_PORT" VALUE="OFF"/>
5053         <PARAMETER NAME="LPDDR2_DQ_WIDTH" VALUE="8"/>
5054         <PARAMETER NAME="LPDDR2_DQS_WIDTH" VALUE="1"/>
5055         <PARAMETER NAME="LPDDR2_ROW_WIDTH" VALUE="14"/>
5056         <PARAMETER NAME="LPDDR2_BANK_WIDTH" VALUE="3"/>
5057         <PARAMETER NAME="LPDDR2_CK_WIDTH" VALUE="1"/>
5058         <PARAMETER NAME="LPDDR2_CKE_WIDTH" VALUE="1"/>
5059         <PARAMETER NAME="LPDDR2_CS_WIDTH" VALUE="1"/>
5060         <PARAMETER NAME="LPDDR2_nCS_PER_RANK" VALUE="1"/>
5061         <PARAMETER NAME="LPDDR2_DM_WIDTH" VALUE="1"/>
5062         <PARAMETER NAME="LPDDR2_USE_CS_PORT" VALUE="1"/>
5063         <PARAMETER NAME="LPDDR2_USE_DM_PORT" VALUE="1"/>
5064         <PARAMETER NAME="LPDDR2_USE_ODT_PORT" VALUE="1"/>
5065         <PARAMETER NAME="LPDDR2_REG_CTRL" VALUE="OFF"/>
5066         <PARAMETER NAME="LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5067         <PARAMETER NAME="LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5068         <PARAMETER NAME="DQS_CNT_WIDTH" VALUE="1"/>
5069         <PARAMETER NAME="DEBUG_PORT" VALUE="OFF"/>
5070         <PARAMETER NAME="DDRX_ADDR_WIDTH" VALUE="8"/>
5071         <PARAMETER NAME="DDRX_nCK_PER_CLK" VALUE="2"/>
5072         <PARAMETER NAME="DDRX_DATA_WIDTH" VALUE="8"/>
5073         <PARAMETER NAME="DDR3_ADDR_WIDTH" VALUE="28"/>
5074         <PARAMETER NAME="DDR3_nCK_PER_CLK" VALUE="4"/>
5075         <PARAMETER NAME="DDR3_DATA_WIDTH" VALUE="64"/>
5076         <PARAMETER NAME="DDR2_ADDR_WIDTH" VALUE="8"/>
5077         <PARAMETER NAME="DDR2_nCK_PER_CLK" VALUE="2"/>
5078         <PARAMETER NAME="DDR2_DATA_WIDTH" VALUE="8"/>
5079         <PARAMETER NAME="LPDDR2_ADDR_WIDTH" VALUE="8"/>
5080         <PARAMETER NAME="LPDDR2_nCK_PER_CLK" VALUE="2"/>
5081         <PARAMETER NAME="LPDDR2_DATA_WIDTH" VALUE="8"/>
5082         <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
5083         <PARAMETER NAME="PHASE" VALUE="0.000"/>
5084         <PARAMETER NAME="UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5085         <PARAMETER NAME="MMCM_VCO" VALUE="800"/>
5086         <PARAMETER NAME="MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5087         <PARAMETER NAME="MMCM_CLKOUT1_FREQ" VALUE="10"/>
5088         <PARAMETER NAME="MMCM_CLKOUT2_FREQ" VALUE="10"/>
5089         <PARAMETER NAME="MMCM_CLKOUT3_FREQ" VALUE="10"/>
5090         <PARAMETER NAME="MMCM_CLKOUT4_FREQ" VALUE="10"/>
5091         <PARAMETER NAME="MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5092         <PARAMETER NAME="MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5093         <PARAMETER NAME="MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5094         <PARAMETER NAME="MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5095         <PARAMETER NAME="MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5096         <PARAMETER NAME="C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5097         <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5098         <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5099         <PARAMETER NAME="C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5100         <PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="1"/>
5101         <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
5102         <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5103         <PARAMETER NAME="C_S_AXI_MEM_SIZE" VALUE="1073741824"/>
5104         <PARAMETER NAME="QDRIIP_NUM_DEVICES" VALUE="1"/>
5105         <PARAMETER NAME="QDRIIP_DATA_WIDTH" VALUE="18"/>
5106         <PARAMETER NAME="QDRIIP_ADDR_WIDTH" VALUE="29"/>
5107         <PARAMETER NAME="QDRIIP_BW_WIDTH" VALUE="8"/>
5108         <PARAMETER NAME="QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5109         <PARAMETER NAME="QDRIIP_BURST_LEN" VALUE="1"/>
5110         <PARAMETER NAME="RLDII_NUM_DEVICES" VALUE="1"/>
5111         <PARAMETER NAME="RLDII_DATA_WIDTH" VALUE="18"/>
5112         <PARAMETER NAME="RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5113         <PARAMETER NAME="RLDII_QK_WIDTH" VALUE="8"/>
5114         <PARAMETER NAME="RLDII_CK_WIDTH" VALUE="1"/>
5115         <PARAMETER NAME="RLDII_DK_WIDTH" VALUE="1"/>
5116         <PARAMETER NAME="RLDII_DM_WIDTH" VALUE="1"/>
5117         <PARAMETER NAME="RLDII_BANK_WIDTH" VALUE="2"/>
5118         <PARAMETER NAME="RLDII_QVLD_WIDTH" VALUE="1"/>
5119         <PARAMETER NAME="RLDII_DEBUG_PORT" VALUE="OFF"/>
5120         <PARAMETER NAME="RLDIII_NUM_DEVICES" VALUE="1"/>
5121         <PARAMETER NAME="RLDIII_DATA_WIDTH" VALUE="18"/>
5122         <PARAMETER NAME="RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5123         <PARAMETER NAME="RLDIII_QK_WIDTH" VALUE="8"/>
5124         <PARAMETER NAME="RLDIII_CK_WIDTH" VALUE="1"/>
5125         <PARAMETER NAME="RLDIII_DK_WIDTH" VALUE="1"/>
5126         <PARAMETER NAME="RLDIII_DM_WIDTH" VALUE="1"/>
5127         <PARAMETER NAME="RLDIII_BANK_WIDTH" VALUE="2"/>
5128         <PARAMETER NAME="RLDIII_QVLD_WIDTH" VALUE="1"/>
5129         <PARAMETER NAME="RLDIII_DEBUG_PORT" VALUE="OFF"/>
5130         <PARAMETER NAME="RLDX_CMD_PER_CLK" VALUE="1"/>
5131         <PARAMETER NAME="RLDX_DATA_WIDTH" VALUE="18"/>
5132         <PARAMETER NAME="RLDX_ADDR_WIDTH" VALUE="29"/>
5133         <PARAMETER NAME="RLDX_BANK_WIDTH" VALUE="2"/>
5134         <PARAMETER NAME="RLDX_nCK_PER_CLK" VALUE="1"/>
5135         <PARAMETER NAME="RLDX_DM_WIDTH" VALUE="1"/>
5136         <PARAMETER NAME="RLDII_CMD_PER_CLK" VALUE="1"/>
5137         <PARAMETER NAME="RLDII_ADDR_WIDTH" VALUE="29"/>
5138         <PARAMETER NAME="RLDII_nCK_PER_CLK" VALUE="1"/>
5139         <PARAMETER NAME="RLDIII_CMD_PER_CLK" VALUE="1"/>
5140         <PARAMETER NAME="RLDIII_ADDR_WIDTH" VALUE="29"/>
5141         <PARAMETER NAME="RLDIII_nCK_PER_CLK" VALUE="1"/>
5142         <PARAMETER NAME="C0_MEM_TYPE" VALUE="DDR3"/>
5143         <PARAMETER NAME="C0_IS_CLK_SHARED" VALUE="FALSE"/>
5144         <PARAMETER NAME="C0_SYSCLK_TYPE" VALUE="DIFF"/>
5145         <PARAMETER NAME="C0_USE_AXI" VALUE="0"/>
5146         <PARAMETER NAME="C0_ECC" VALUE="OFF"/>
5147         <PARAMETER NAME="C0_DDR3_DQ_WIDTH" VALUE="8"/>
5148         <PARAMETER NAME="C0_DDR3_DQS_WIDTH" VALUE="1"/>
5149         <PARAMETER NAME="C0_DDR3_ROW_WIDTH" VALUE="14"/>
5150         <PARAMETER NAME="C0_DDR3_BANK_WIDTH" VALUE="3"/>
5151         <PARAMETER NAME="C0_DDR3_CK_WIDTH" VALUE="1"/>
5152         <PARAMETER NAME="C0_DDR3_CKE_WIDTH" VALUE="1"/>
5153         <PARAMETER NAME="C0_DDR3_CS_WIDTH" VALUE="1"/>
5154         <PARAMETER NAME="C0_DDR3_nCS_PER_RANK" VALUE="1"/>
5155         <PARAMETER NAME="C0_DDR3_DM_WIDTH" VALUE="1"/>
5156         <PARAMETER NAME="C0_DDR3_ODT_WIDTH" VALUE="1"/>
5157         <PARAMETER NAME="C0_DDR3_USE_CS_PORT" VALUE="1"/>
5158         <PARAMETER NAME="C0_DDR3_USE_DM_PORT" VALUE="1"/>
5159         <PARAMETER NAME="C0_DDR3_USE_ODT_PORT" VALUE="1"/>
5160         <PARAMETER NAME="C0_DDR3_REG_CTRL" VALUE="OFF"/>
5161         <PARAMETER NAME="C0_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5162         <PARAMETER NAME="C0_DDR3_DEBUG_PORT" VALUE="OFF"/>
5163         <PARAMETER NAME="C0_DDR2_DQ_WIDTH" VALUE="8"/>
5164         <PARAMETER NAME="C0_DDR2_DQS_WIDTH" VALUE="1"/>
5165         <PARAMETER NAME="C0_DDR2_ROW_WIDTH" VALUE="14"/>
5166         <PARAMETER NAME="C0_DDR2_BANK_WIDTH" VALUE="3"/>
5167         <PARAMETER NAME="C0_DDR2_CK_WIDTH" VALUE="1"/>
5168         <PARAMETER NAME="C0_DDR2_CKE_WIDTH" VALUE="1"/>
5169         <PARAMETER NAME="C0_DDR2_CS_WIDTH" VALUE="1"/>
5170         <PARAMETER NAME="C0_DDR2_nCS_PER_RANK" VALUE="1"/>
5171         <PARAMETER NAME="C0_DDR2_DM_WIDTH" VALUE="1"/>
5172         <PARAMETER NAME="C0_DDR2_ODT_WIDTH" VALUE="1"/>
5173         <PARAMETER NAME="C0_DDR2_USE_CS_PORT" VALUE="1"/>
5174         <PARAMETER NAME="C0_DDR2_USE_DM_PORT" VALUE="1"/>
5175         <PARAMETER NAME="C0_DDR2_USE_ODT_PORT" VALUE="1"/>
5176         <PARAMETER NAME="C0_DDR2_REG_CTRL" VALUE="OFF"/>
5177         <PARAMETER NAME="C0_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5178         <PARAMETER NAME="C0_DDR2_DEBUG_PORT" VALUE="OFF"/>
5179         <PARAMETER NAME="C0_LPDDR2_DQ_WIDTH" VALUE="8"/>
5180         <PARAMETER NAME="C0_LPDDR2_DQS_WIDTH" VALUE="1"/>
5181         <PARAMETER NAME="C0_LPDDR2_ROW_WIDTH" VALUE="14"/>
5182         <PARAMETER NAME="C0_LPDDR2_BANK_WIDTH" VALUE="3"/>
5183         <PARAMETER NAME="C0_LPDDR2_CK_WIDTH" VALUE="1"/>
5184         <PARAMETER NAME="C0_LPDDR2_CKE_WIDTH" VALUE="1"/>
5185         <PARAMETER NAME="C0_LPDDR2_CS_WIDTH" VALUE="1"/>
5186         <PARAMETER NAME="C0_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5187         <PARAMETER NAME="C0_LPDDR2_DM_WIDTH" VALUE="1"/>
5188         <PARAMETER NAME="C0_LPDDR2_USE_CS_PORT" VALUE="1"/>
5189         <PARAMETER NAME="C0_LPDDR2_USE_DM_PORT" VALUE="1"/>
5190         <PARAMETER NAME="C0_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5191         <PARAMETER NAME="C0_LPDDR2_REG_CTRL" VALUE="OFF"/>
5192         <PARAMETER NAME="C0_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5193         <PARAMETER NAME="C0_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5194         <PARAMETER NAME="C0_DQS_CNT_WIDTH" VALUE="1"/>
5195         <PARAMETER NAME="C0_DEBUG_PORT" VALUE="OFF"/>
5196         <PARAMETER NAME="C0_DDRX_ADDR_WIDTH" VALUE="8"/>
5197         <PARAMETER NAME="C0_DDRX_nCK_PER_CLK" VALUE="2"/>
5198         <PARAMETER NAME="C0_DDRX_DATA_WIDTH" VALUE="8"/>
5199         <PARAMETER NAME="C0_DDR3_ADDR_WIDTH" VALUE="8"/>
5200         <PARAMETER NAME="C0_DDR3_nCK_PER_CLK" VALUE="2"/>
5201         <PARAMETER NAME="C0_DDR3_DATA_WIDTH" VALUE="8"/>
5202         <PARAMETER NAME="C0_DDR2_ADDR_WIDTH" VALUE="8"/>
5203         <PARAMETER NAME="C0_DDR2_nCK_PER_CLK" VALUE="2"/>
5204         <PARAMETER NAME="C0_DDR2_DATA_WIDTH" VALUE="8"/>
5205         <PARAMETER NAME="C0_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5206         <PARAMETER NAME="C0_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5207         <PARAMETER NAME="C0_LPDDR2_DATA_WIDTH" VALUE="8"/>
5208         <PARAMETER NAME="C0_FREQ_HZ" VALUE="100.0"/>
5209         <PARAMETER NAME="C0_PHASE" VALUE="0.000"/>
5210         <PARAMETER NAME="C0_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5211         <PARAMETER NAME="C0_MMCM_VCO" VALUE="1200.0"/>
5212         <PARAMETER NAME="C0_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5213         <PARAMETER NAME="C0_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5214         <PARAMETER NAME="C0_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5215         <PARAMETER NAME="C0_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5216         <PARAMETER NAME="C0_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5217         <PARAMETER NAME="C0_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5218         <PARAMETER NAME="C0_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5219         <PARAMETER NAME="C0_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5220         <PARAMETER NAME="C0_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5221         <PARAMETER NAME="C0_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5222         <PARAMETER NAME="C0_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5223         <PARAMETER NAME="C0_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5224         <PARAMETER NAME="C0_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5225         <PARAMETER NAME="C0_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5226         <PARAMETER NAME="C0_C_S_AXI_ID_WIDTH" VALUE="4"/>
5227         <PARAMETER NAME="C0_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5228         <PARAMETER NAME="C0_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5229         <PARAMETER NAME="C0_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5230         <PARAMETER NAME="C0_QDRIIP_NUM_DEVICES" VALUE="1"/>
5231         <PARAMETER NAME="C0_QDRIIP_DATA_WIDTH" VALUE="18"/>
5232         <PARAMETER NAME="C0_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5233         <PARAMETER NAME="C0_QDRIIP_BW_WIDTH" VALUE="8"/>
5234         <PARAMETER NAME="C0_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5235         <PARAMETER NAME="C0_QDRIIP_BURST_LEN" VALUE="1"/>
5236         <PARAMETER NAME="C0_RLDII_NUM_DEVICES" VALUE="1"/>
5237         <PARAMETER NAME="C0_RLDII_DATA_WIDTH" VALUE="18"/>
5238         <PARAMETER NAME="C0_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5239         <PARAMETER NAME="C0_RLDII_QK_WIDTH" VALUE="8"/>
5240         <PARAMETER NAME="C0_RLDII_CK_WIDTH" VALUE="1"/>
5241         <PARAMETER NAME="C0_RLDII_DK_WIDTH" VALUE="1"/>
5242         <PARAMETER NAME="C0_RLDII_DM_WIDTH" VALUE="1"/>
5243         <PARAMETER NAME="C0_RLDII_BANK_WIDTH" VALUE="2"/>
5244         <PARAMETER NAME="C0_RLDII_QVLD_WIDTH" VALUE="1"/>
5245         <PARAMETER NAME="C0_RLDII_DEBUG_PORT" VALUE="OFF"/>
5246         <PARAMETER NAME="C0_RLDIII_NUM_DEVICES" VALUE="1"/>
5247         <PARAMETER NAME="C0_RLDIII_DATA_WIDTH" VALUE="18"/>
5248         <PARAMETER NAME="C0_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5249         <PARAMETER NAME="C0_RLDIII_QK_WIDTH" VALUE="8"/>
5250         <PARAMETER NAME="C0_RLDIII_CK_WIDTH" VALUE="1"/>
5251         <PARAMETER NAME="C0_RLDIII_DK_WIDTH" VALUE="1"/>
5252         <PARAMETER NAME="C0_RLDIII_DM_WIDTH" VALUE="1"/>
5253         <PARAMETER NAME="C0_RLDIII_BANK_WIDTH" VALUE="2"/>
5254         <PARAMETER NAME="C0_RLDIII_QVLD_WIDTH" VALUE="1"/>
5255         <PARAMETER NAME="C0_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5256         <PARAMETER NAME="C0_RLDX_CMD_PER_CLK" VALUE="1"/>
5257         <PARAMETER NAME="C0_RLDX_DATA_WIDTH" VALUE="18"/>
5258         <PARAMETER NAME="C0_RLDX_ADDR_WIDTH" VALUE="29"/>
5259         <PARAMETER NAME="C0_RLDX_BANK_WIDTH" VALUE="2"/>
5260         <PARAMETER NAME="C0_RLDX_nCK_PER_CLK" VALUE="1"/>
5261         <PARAMETER NAME="C0_RLDX_DM_WIDTH" VALUE="1"/>
5262         <PARAMETER NAME="C0_RLDII_CMD_PER_CLK" VALUE="1"/>
5263         <PARAMETER NAME="C0_RLDII_ADDR_WIDTH" VALUE="29"/>
5264         <PARAMETER NAME="C0_RLDII_nCK_PER_CLK" VALUE="1"/>
5265         <PARAMETER NAME="C0_RLDIII_CMD_PER_CLK" VALUE="1"/>
5266         <PARAMETER NAME="C0_RLDIII_ADDR_WIDTH" VALUE="29"/>
5267         <PARAMETER NAME="C0_RLDIII_nCK_PER_CLK" VALUE="1"/>
5268         <PARAMETER NAME="C0_POLARITY" VALUE="ACTIVE_LOW"/>
5269         <PARAMETER NAME="C1_MEM_TYPE" VALUE="DDR3"/>
5270         <PARAMETER NAME="C1_IS_CLK_SHARED" VALUE="FALSE"/>
5271         <PARAMETER NAME="C1_SYSCLK_TYPE" VALUE="DIFF"/>
5272         <PARAMETER NAME="C1_USE_AXI" VALUE="0"/>
5273         <PARAMETER NAME="C1_ECC" VALUE="OFF"/>
5274         <PARAMETER NAME="C1_DDR3_DQ_WIDTH" VALUE="8"/>
5275         <PARAMETER NAME="C1_DDR3_DQS_WIDTH" VALUE="1"/>
5276         <PARAMETER NAME="C1_DDR3_ROW_WIDTH" VALUE="14"/>
5277         <PARAMETER NAME="C1_DDR3_BANK_WIDTH" VALUE="3"/>
5278         <PARAMETER NAME="C1_DDR3_CK_WIDTH" VALUE="1"/>
5279         <PARAMETER NAME="C1_DDR3_CKE_WIDTH" VALUE="1"/>
5280         <PARAMETER NAME="C1_DDR3_CS_WIDTH" VALUE="1"/>
5281         <PARAMETER NAME="C1_DDR3_nCS_PER_RANK" VALUE="1"/>
5282         <PARAMETER NAME="C1_DDR3_DM_WIDTH" VALUE="1"/>
5283         <PARAMETER NAME="C1_DDR3_ODT_WIDTH" VALUE="1"/>
5284         <PARAMETER NAME="C1_DDR3_USE_CS_PORT" VALUE="1"/>
5285         <PARAMETER NAME="C1_DDR3_USE_DM_PORT" VALUE="1"/>
5286         <PARAMETER NAME="C1_DDR3_USE_ODT_PORT" VALUE="1"/>
5287         <PARAMETER NAME="C1_DDR3_REG_CTRL" VALUE="OFF"/>
5288         <PARAMETER NAME="C1_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5289         <PARAMETER NAME="C1_DDR3_DEBUG_PORT" VALUE="OFF"/>
5290         <PARAMETER NAME="C1_DDR2_DQ_WIDTH" VALUE="8"/>
5291         <PARAMETER NAME="C1_DDR2_DQS_WIDTH" VALUE="1"/>
5292         <PARAMETER NAME="C1_DDR2_ROW_WIDTH" VALUE="14"/>
5293         <PARAMETER NAME="C1_DDR2_BANK_WIDTH" VALUE="3"/>
5294         <PARAMETER NAME="C1_DDR2_CK_WIDTH" VALUE="1"/>
5295         <PARAMETER NAME="C1_DDR2_CKE_WIDTH" VALUE="1"/>
5296         <PARAMETER NAME="C1_DDR2_CS_WIDTH" VALUE="1"/>
5297         <PARAMETER NAME="C1_DDR2_nCS_PER_RANK" VALUE="1"/>
5298         <PARAMETER NAME="C1_DDR2_DM_WIDTH" VALUE="1"/>
5299         <PARAMETER NAME="C1_DDR2_ODT_WIDTH" VALUE="1"/>
5300         <PARAMETER NAME="C1_DDR2_USE_CS_PORT" VALUE="1"/>
5301         <PARAMETER NAME="C1_DDR2_USE_DM_PORT" VALUE="1"/>
5302         <PARAMETER NAME="C1_DDR2_USE_ODT_PORT" VALUE="1"/>
5303         <PARAMETER NAME="C1_DDR2_REG_CTRL" VALUE="OFF"/>
5304         <PARAMETER NAME="C1_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5305         <PARAMETER NAME="C1_DDR2_DEBUG_PORT" VALUE="OFF"/>
5306         <PARAMETER NAME="C1_LPDDR2_DQ_WIDTH" VALUE="8"/>
5307         <PARAMETER NAME="C1_LPDDR2_DQS_WIDTH" VALUE="1"/>
5308         <PARAMETER NAME="C1_LPDDR2_ROW_WIDTH" VALUE="14"/>
5309         <PARAMETER NAME="C1_LPDDR2_BANK_WIDTH" VALUE="3"/>
5310         <PARAMETER NAME="C1_LPDDR2_CK_WIDTH" VALUE="1"/>
5311         <PARAMETER NAME="C1_LPDDR2_CKE_WIDTH" VALUE="1"/>
5312         <PARAMETER NAME="C1_LPDDR2_CS_WIDTH" VALUE="1"/>
5313         <PARAMETER NAME="C1_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5314         <PARAMETER NAME="C1_LPDDR2_DM_WIDTH" VALUE="1"/>
5315         <PARAMETER NAME="C1_LPDDR2_USE_CS_PORT" VALUE="1"/>
5316         <PARAMETER NAME="C1_LPDDR2_USE_DM_PORT" VALUE="1"/>
5317         <PARAMETER NAME="C1_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5318         <PARAMETER NAME="C1_LPDDR2_REG_CTRL" VALUE="OFF"/>
5319         <PARAMETER NAME="C1_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5320         <PARAMETER NAME="C1_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5321         <PARAMETER NAME="C1_DQS_CNT_WIDTH" VALUE="1"/>
5322         <PARAMETER NAME="C1_DEBUG_PORT" VALUE="OFF"/>
5323         <PARAMETER NAME="C1_DDRX_ADDR_WIDTH" VALUE="8"/>
5324         <PARAMETER NAME="C1_DDRX_nCK_PER_CLK" VALUE="2"/>
5325         <PARAMETER NAME="C1_DDRX_DATA_WIDTH" VALUE="8"/>
5326         <PARAMETER NAME="C1_DDR3_ADDR_WIDTH" VALUE="8"/>
5327         <PARAMETER NAME="C1_DDR3_nCK_PER_CLK" VALUE="2"/>
5328         <PARAMETER NAME="C1_DDR3_DATA_WIDTH" VALUE="8"/>
5329         <PARAMETER NAME="C1_DDR2_ADDR_WIDTH" VALUE="8"/>
5330         <PARAMETER NAME="C1_DDR2_nCK_PER_CLK" VALUE="2"/>
5331         <PARAMETER NAME="C1_DDR2_DATA_WIDTH" VALUE="8"/>
5332         <PARAMETER NAME="C1_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5333         <PARAMETER NAME="C1_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5334         <PARAMETER NAME="C1_LPDDR2_DATA_WIDTH" VALUE="8"/>
5335         <PARAMETER NAME="C1_FREQ_HZ" VALUE="100.0"/>
5336         <PARAMETER NAME="C1_PHASE" VALUE="0.000"/>
5337         <PARAMETER NAME="C1_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5338         <PARAMETER NAME="C1_MMCM_VCO" VALUE="1200.0"/>
5339         <PARAMETER NAME="C1_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5340         <PARAMETER NAME="C1_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5341         <PARAMETER NAME="C1_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5342         <PARAMETER NAME="C1_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5343         <PARAMETER NAME="C1_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5344         <PARAMETER NAME="C1_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5345         <PARAMETER NAME="C1_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5346         <PARAMETER NAME="C1_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5347         <PARAMETER NAME="C1_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5348         <PARAMETER NAME="C1_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5349         <PARAMETER NAME="C1_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5350         <PARAMETER NAME="C1_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5351         <PARAMETER NAME="C1_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5352         <PARAMETER NAME="C1_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5353         <PARAMETER NAME="C1_C_S_AXI_ID_WIDTH" VALUE="4"/>
5354         <PARAMETER NAME="C1_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5355         <PARAMETER NAME="C1_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5356         <PARAMETER NAME="C1_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5357         <PARAMETER NAME="C1_QDRIIP_NUM_DEVICES" VALUE="1"/>
5358         <PARAMETER NAME="C1_QDRIIP_DATA_WIDTH" VALUE="18"/>
5359         <PARAMETER NAME="C1_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5360         <PARAMETER NAME="C1_QDRIIP_BW_WIDTH" VALUE="8"/>
5361         <PARAMETER NAME="C1_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5362         <PARAMETER NAME="C1_QDRIIP_BURST_LEN" VALUE="1"/>
5363         <PARAMETER NAME="C1_RLDII_NUM_DEVICES" VALUE="1"/>
5364         <PARAMETER NAME="C1_RLDII_DATA_WIDTH" VALUE="18"/>
5365         <PARAMETER NAME="C1_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5366         <PARAMETER NAME="C1_RLDII_QK_WIDTH" VALUE="8"/>
5367         <PARAMETER NAME="C1_RLDII_CK_WIDTH" VALUE="1"/>
5368         <PARAMETER NAME="C1_RLDII_DK_WIDTH" VALUE="1"/>
5369         <PARAMETER NAME="C1_RLDII_DM_WIDTH" VALUE="1"/>
5370         <PARAMETER NAME="C1_RLDII_BANK_WIDTH" VALUE="2"/>
5371         <PARAMETER NAME="C1_RLDII_QVLD_WIDTH" VALUE="1"/>
5372         <PARAMETER NAME="C1_RLDII_DEBUG_PORT" VALUE="OFF"/>
5373         <PARAMETER NAME="C1_RLDIII_NUM_DEVICES" VALUE="1"/>
5374         <PARAMETER NAME="C1_RLDIII_DATA_WIDTH" VALUE="18"/>
5375         <PARAMETER NAME="C1_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5376         <PARAMETER NAME="C1_RLDIII_QK_WIDTH" VALUE="8"/>
5377         <PARAMETER NAME="C1_RLDIII_CK_WIDTH" VALUE="1"/>
5378         <PARAMETER NAME="C1_RLDIII_DK_WIDTH" VALUE="1"/>
5379         <PARAMETER NAME="C1_RLDIII_DM_WIDTH" VALUE="1"/>
5380         <PARAMETER NAME="C1_RLDIII_BANK_WIDTH" VALUE="2"/>
5381         <PARAMETER NAME="C1_RLDIII_QVLD_WIDTH" VALUE="1"/>
5382         <PARAMETER NAME="C1_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5383         <PARAMETER NAME="C1_RLDX_CMD_PER_CLK" VALUE="1"/>
5384         <PARAMETER NAME="C1_RLDX_DATA_WIDTH" VALUE="18"/>
5385         <PARAMETER NAME="C1_RLDX_ADDR_WIDTH" VALUE="29"/>
5386         <PARAMETER NAME="C1_RLDX_BANK_WIDTH" VALUE="2"/>
5387         <PARAMETER NAME="C1_RLDX_nCK_PER_CLK" VALUE="1"/>
5388         <PARAMETER NAME="C1_RLDX_DM_WIDTH" VALUE="1"/>
5389         <PARAMETER NAME="C1_RLDII_CMD_PER_CLK" VALUE="1"/>
5390         <PARAMETER NAME="C1_RLDII_ADDR_WIDTH" VALUE="29"/>
5391         <PARAMETER NAME="C1_RLDII_nCK_PER_CLK" VALUE="1"/>
5392         <PARAMETER NAME="C1_RLDIII_CMD_PER_CLK" VALUE="1"/>
5393         <PARAMETER NAME="C1_RLDIII_ADDR_WIDTH" VALUE="29"/>
5394         <PARAMETER NAME="C1_RLDIII_nCK_PER_CLK" VALUE="1"/>
5395         <PARAMETER NAME="C1_POLARITY" VALUE="ACTIVE_LOW"/>
5396         <PARAMETER NAME="C2_MEM_TYPE" VALUE="DDR3"/>
5397         <PARAMETER NAME="C2_IS_CLK_SHARED" VALUE="FALSE"/>
5398         <PARAMETER NAME="C2_SYSCLK_TYPE" VALUE="DIFF"/>
5399         <PARAMETER NAME="C2_USE_AXI" VALUE="0"/>
5400         <PARAMETER NAME="C2_ECC" VALUE="OFF"/>
5401         <PARAMETER NAME="C2_DDR3_DQ_WIDTH" VALUE="8"/>
5402         <PARAMETER NAME="C2_DDR3_DQS_WIDTH" VALUE="1"/>
5403         <PARAMETER NAME="C2_DDR3_ROW_WIDTH" VALUE="14"/>
5404         <PARAMETER NAME="C2_DDR3_BANK_WIDTH" VALUE="3"/>
5405         <PARAMETER NAME="C2_DDR3_CK_WIDTH" VALUE="1"/>
5406         <PARAMETER NAME="C2_DDR3_CKE_WIDTH" VALUE="1"/>
5407         <PARAMETER NAME="C2_DDR3_CS_WIDTH" VALUE="1"/>
5408         <PARAMETER NAME="C2_DDR3_nCS_PER_RANK" VALUE="1"/>
5409         <PARAMETER NAME="C2_DDR3_DM_WIDTH" VALUE="1"/>
5410         <PARAMETER NAME="C2_DDR3_ODT_WIDTH" VALUE="1"/>
5411         <PARAMETER NAME="C2_DDR3_USE_CS_PORT" VALUE="1"/>
5412         <PARAMETER NAME="C2_DDR3_USE_DM_PORT" VALUE="1"/>
5413         <PARAMETER NAME="C2_DDR3_USE_ODT_PORT" VALUE="1"/>
5414         <PARAMETER NAME="C2_DDR3_REG_CTRL" VALUE="OFF"/>
5415         <PARAMETER NAME="C2_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5416         <PARAMETER NAME="C2_DDR3_DEBUG_PORT" VALUE="OFF"/>
5417         <PARAMETER NAME="C2_DDR2_DQ_WIDTH" VALUE="8"/>
5418         <PARAMETER NAME="C2_DDR2_DQS_WIDTH" VALUE="1"/>
5419         <PARAMETER NAME="C2_DDR2_ROW_WIDTH" VALUE="14"/>
5420         <PARAMETER NAME="C2_DDR2_BANK_WIDTH" VALUE="3"/>
5421         <PARAMETER NAME="C2_DDR2_CK_WIDTH" VALUE="1"/>
5422         <PARAMETER NAME="C2_DDR2_CKE_WIDTH" VALUE="1"/>
5423         <PARAMETER NAME="C2_DDR2_CS_WIDTH" VALUE="1"/>
5424         <PARAMETER NAME="C2_DDR2_nCS_PER_RANK" VALUE="1"/>
5425         <PARAMETER NAME="C2_DDR2_DM_WIDTH" VALUE="1"/>
5426         <PARAMETER NAME="C2_DDR2_ODT_WIDTH" VALUE="1"/>
5427         <PARAMETER NAME="C2_DDR2_USE_CS_PORT" VALUE="1"/>
5428         <PARAMETER NAME="C2_DDR2_USE_DM_PORT" VALUE="1"/>
5429         <PARAMETER NAME="C2_DDR2_USE_ODT_PORT" VALUE="1"/>
5430         <PARAMETER NAME="C2_DDR2_REG_CTRL" VALUE="OFF"/>
5431         <PARAMETER NAME="C2_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5432         <PARAMETER NAME="C2_DDR2_DEBUG_PORT" VALUE="OFF"/>
5433         <PARAMETER NAME="C2_LPDDR2_DQ_WIDTH" VALUE="8"/>
5434         <PARAMETER NAME="C2_LPDDR2_DQS_WIDTH" VALUE="1"/>
5435         <PARAMETER NAME="C2_LPDDR2_ROW_WIDTH" VALUE="14"/>
5436         <PARAMETER NAME="C2_LPDDR2_BANK_WIDTH" VALUE="3"/>
5437         <PARAMETER NAME="C2_LPDDR2_CK_WIDTH" VALUE="1"/>
5438         <PARAMETER NAME="C2_LPDDR2_CKE_WIDTH" VALUE="1"/>
5439         <PARAMETER NAME="C2_LPDDR2_CS_WIDTH" VALUE="1"/>
5440         <PARAMETER NAME="C2_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5441         <PARAMETER NAME="C2_LPDDR2_DM_WIDTH" VALUE="1"/>
5442         <PARAMETER NAME="C2_LPDDR2_USE_CS_PORT" VALUE="1"/>
5443         <PARAMETER NAME="C2_LPDDR2_USE_DM_PORT" VALUE="1"/>
5444         <PARAMETER NAME="C2_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5445         <PARAMETER NAME="C2_LPDDR2_REG_CTRL" VALUE="OFF"/>
5446         <PARAMETER NAME="C2_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5447         <PARAMETER NAME="C2_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5448         <PARAMETER NAME="C2_DQS_CNT_WIDTH" VALUE="1"/>
5449         <PARAMETER NAME="C2_DEBUG_PORT" VALUE="OFF"/>
5450         <PARAMETER NAME="C2_DDRX_ADDR_WIDTH" VALUE="8"/>
5451         <PARAMETER NAME="C2_DDRX_nCK_PER_CLK" VALUE="2"/>
5452         <PARAMETER NAME="C2_DDRX_DATA_WIDTH" VALUE="8"/>
5453         <PARAMETER NAME="C2_DDR3_ADDR_WIDTH" VALUE="8"/>
5454         <PARAMETER NAME="C2_DDR3_nCK_PER_CLK" VALUE="2"/>
5455         <PARAMETER NAME="C2_DDR3_DATA_WIDTH" VALUE="8"/>
5456         <PARAMETER NAME="C2_DDR2_ADDR_WIDTH" VALUE="8"/>
5457         <PARAMETER NAME="C2_DDR2_nCK_PER_CLK" VALUE="2"/>
5458         <PARAMETER NAME="C2_DDR2_DATA_WIDTH" VALUE="8"/>
5459         <PARAMETER NAME="C2_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5460         <PARAMETER NAME="C2_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5461         <PARAMETER NAME="C2_LPDDR2_DATA_WIDTH" VALUE="8"/>
5462         <PARAMETER NAME="C2_FREQ_HZ" VALUE="100.0"/>
5463         <PARAMETER NAME="C2_PHASE" VALUE="0.000"/>
5464         <PARAMETER NAME="C2_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5465         <PARAMETER NAME="C2_MMCM_VCO" VALUE="1200.0"/>
5466         <PARAMETER NAME="C2_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5467         <PARAMETER NAME="C2_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5468         <PARAMETER NAME="C2_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5469         <PARAMETER NAME="C2_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5470         <PARAMETER NAME="C2_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5471         <PARAMETER NAME="C2_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5472         <PARAMETER NAME="C2_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5473         <PARAMETER NAME="C2_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5474         <PARAMETER NAME="C2_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5475         <PARAMETER NAME="C2_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5476         <PARAMETER NAME="C2_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5477         <PARAMETER NAME="C2_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5478         <PARAMETER NAME="C2_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5479         <PARAMETER NAME="C2_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5480         <PARAMETER NAME="C2_C_S_AXI_ID_WIDTH" VALUE="4"/>
5481         <PARAMETER NAME="C2_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5482         <PARAMETER NAME="C2_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5483         <PARAMETER NAME="C2_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5484         <PARAMETER NAME="C2_QDRIIP_NUM_DEVICES" VALUE="1"/>
5485         <PARAMETER NAME="C2_QDRIIP_DATA_WIDTH" VALUE="18"/>
5486         <PARAMETER NAME="C2_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5487         <PARAMETER NAME="C2_QDRIIP_BW_WIDTH" VALUE="8"/>
5488         <PARAMETER NAME="C2_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5489         <PARAMETER NAME="C2_QDRIIP_BURST_LEN" VALUE="1"/>
5490         <PARAMETER NAME="C2_RLDII_NUM_DEVICES" VALUE="1"/>
5491         <PARAMETER NAME="C2_RLDII_DATA_WIDTH" VALUE="18"/>
5492         <PARAMETER NAME="C2_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5493         <PARAMETER NAME="C2_RLDII_QK_WIDTH" VALUE="8"/>
5494         <PARAMETER NAME="C2_RLDII_CK_WIDTH" VALUE="1"/>
5495         <PARAMETER NAME="C2_RLDII_DK_WIDTH" VALUE="1"/>
5496         <PARAMETER NAME="C2_RLDII_DM_WIDTH" VALUE="1"/>
5497         <PARAMETER NAME="C2_RLDII_BANK_WIDTH" VALUE="2"/>
5498         <PARAMETER NAME="C2_RLDII_QVLD_WIDTH" VALUE="1"/>
5499         <PARAMETER NAME="C2_RLDII_DEBUG_PORT" VALUE="OFF"/>
5500         <PARAMETER NAME="C2_RLDIII_NUM_DEVICES" VALUE="1"/>
5501         <PARAMETER NAME="C2_RLDIII_DATA_WIDTH" VALUE="18"/>
5502         <PARAMETER NAME="C2_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5503         <PARAMETER NAME="C2_RLDIII_QK_WIDTH" VALUE="8"/>
5504         <PARAMETER NAME="C2_RLDIII_CK_WIDTH" VALUE="1"/>
5505         <PARAMETER NAME="C2_RLDIII_DK_WIDTH" VALUE="1"/>
5506         <PARAMETER NAME="C2_RLDIII_DM_WIDTH" VALUE="1"/>
5507         <PARAMETER NAME="C2_RLDIII_BANK_WIDTH" VALUE="2"/>
5508         <PARAMETER NAME="C2_RLDIII_QVLD_WIDTH" VALUE="1"/>
5509         <PARAMETER NAME="C2_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5510         <PARAMETER NAME="C2_RLDX_CMD_PER_CLK" VALUE="1"/>
5511         <PARAMETER NAME="C2_RLDX_DATA_WIDTH" VALUE="18"/>
5512         <PARAMETER NAME="C2_RLDX_ADDR_WIDTH" VALUE="29"/>
5513         <PARAMETER NAME="C2_RLDX_BANK_WIDTH" VALUE="2"/>
5514         <PARAMETER NAME="C2_RLDX_nCK_PER_CLK" VALUE="1"/>
5515         <PARAMETER NAME="C2_RLDX_DM_WIDTH" VALUE="1"/>
5516         <PARAMETER NAME="C2_RLDII_CMD_PER_CLK" VALUE="1"/>
5517         <PARAMETER NAME="C2_RLDII_ADDR_WIDTH" VALUE="29"/>
5518         <PARAMETER NAME="C2_RLDII_nCK_PER_CLK" VALUE="1"/>
5519         <PARAMETER NAME="C2_RLDIII_CMD_PER_CLK" VALUE="1"/>
5520         <PARAMETER NAME="C2_RLDIII_ADDR_WIDTH" VALUE="29"/>
5521         <PARAMETER NAME="C2_RLDIII_nCK_PER_CLK" VALUE="1"/>
5522         <PARAMETER NAME="C2_POLARITY" VALUE="ACTIVE_LOW"/>
5523         <PARAMETER NAME="C3_MEM_TYPE" VALUE="DDR3"/>
5524         <PARAMETER NAME="C3_IS_CLK_SHARED" VALUE="FALSE"/>
5525         <PARAMETER NAME="C3_SYSCLK_TYPE" VALUE="DIFF"/>
5526         <PARAMETER NAME="C3_USE_AXI" VALUE="0"/>
5527         <PARAMETER NAME="C3_ECC" VALUE="OFF"/>
5528         <PARAMETER NAME="C3_DDR3_DQ_WIDTH" VALUE="8"/>
5529         <PARAMETER NAME="C3_DDR3_DQS_WIDTH" VALUE="1"/>
5530         <PARAMETER NAME="C3_DDR3_ROW_WIDTH" VALUE="14"/>
5531         <PARAMETER NAME="C3_DDR3_BANK_WIDTH" VALUE="3"/>
5532         <PARAMETER NAME="C3_DDR3_CK_WIDTH" VALUE="1"/>
5533         <PARAMETER NAME="C3_DDR3_CKE_WIDTH" VALUE="1"/>
5534         <PARAMETER NAME="C3_DDR3_CS_WIDTH" VALUE="1"/>
5535         <PARAMETER NAME="C3_DDR3_nCS_PER_RANK" VALUE="1"/>
5536         <PARAMETER NAME="C3_DDR3_DM_WIDTH" VALUE="1"/>
5537         <PARAMETER NAME="C3_DDR3_ODT_WIDTH" VALUE="1"/>
5538         <PARAMETER NAME="C3_DDR3_USE_CS_PORT" VALUE="1"/>
5539         <PARAMETER NAME="C3_DDR3_USE_DM_PORT" VALUE="1"/>
5540         <PARAMETER NAME="C3_DDR3_USE_ODT_PORT" VALUE="1"/>
5541         <PARAMETER NAME="C3_DDR3_REG_CTRL" VALUE="OFF"/>
5542         <PARAMETER NAME="C3_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5543         <PARAMETER NAME="C3_DDR3_DEBUG_PORT" VALUE="OFF"/>
5544         <PARAMETER NAME="C3_DDR2_DQ_WIDTH" VALUE="8"/>
5545         <PARAMETER NAME="C3_DDR2_DQS_WIDTH" VALUE="1"/>
5546         <PARAMETER NAME="C3_DDR2_ROW_WIDTH" VALUE="14"/>
5547         <PARAMETER NAME="C3_DDR2_BANK_WIDTH" VALUE="3"/>
5548         <PARAMETER NAME="C3_DDR2_CK_WIDTH" VALUE="1"/>
5549         <PARAMETER NAME="C3_DDR2_CKE_WIDTH" VALUE="1"/>
5550         <PARAMETER NAME="C3_DDR2_CS_WIDTH" VALUE="1"/>
5551         <PARAMETER NAME="C3_DDR2_nCS_PER_RANK" VALUE="1"/>
5552         <PARAMETER NAME="C3_DDR2_DM_WIDTH" VALUE="1"/>
5553         <PARAMETER NAME="C3_DDR2_ODT_WIDTH" VALUE="1"/>
5554         <PARAMETER NAME="C3_DDR2_USE_CS_PORT" VALUE="1"/>
5555         <PARAMETER NAME="C3_DDR2_USE_DM_PORT" VALUE="1"/>
5556         <PARAMETER NAME="C3_DDR2_USE_ODT_PORT" VALUE="1"/>
5557         <PARAMETER NAME="C3_DDR2_REG_CTRL" VALUE="OFF"/>
5558         <PARAMETER NAME="C3_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5559         <PARAMETER NAME="C3_DDR2_DEBUG_PORT" VALUE="OFF"/>
5560         <PARAMETER NAME="C3_LPDDR2_DQ_WIDTH" VALUE="8"/>
5561         <PARAMETER NAME="C3_LPDDR2_DQS_WIDTH" VALUE="1"/>
5562         <PARAMETER NAME="C3_LPDDR2_ROW_WIDTH" VALUE="14"/>
5563         <PARAMETER NAME="C3_LPDDR2_BANK_WIDTH" VALUE="3"/>
5564         <PARAMETER NAME="C3_LPDDR2_CK_WIDTH" VALUE="1"/>
5565         <PARAMETER NAME="C3_LPDDR2_CKE_WIDTH" VALUE="1"/>
5566         <PARAMETER NAME="C3_LPDDR2_CS_WIDTH" VALUE="1"/>
5567         <PARAMETER NAME="C3_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5568         <PARAMETER NAME="C3_LPDDR2_DM_WIDTH" VALUE="1"/>
5569         <PARAMETER NAME="C3_LPDDR2_USE_CS_PORT" VALUE="1"/>
5570         <PARAMETER NAME="C3_LPDDR2_USE_DM_PORT" VALUE="1"/>
5571         <PARAMETER NAME="C3_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5572         <PARAMETER NAME="C3_LPDDR2_REG_CTRL" VALUE="OFF"/>
5573         <PARAMETER NAME="C3_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5574         <PARAMETER NAME="C3_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5575         <PARAMETER NAME="C3_DQS_CNT_WIDTH" VALUE="1"/>
5576         <PARAMETER NAME="C3_DEBUG_PORT" VALUE="OFF"/>
5577         <PARAMETER NAME="C3_DDRX_ADDR_WIDTH" VALUE="8"/>
5578         <PARAMETER NAME="C3_DDRX_nCK_PER_CLK" VALUE="2"/>
5579         <PARAMETER NAME="C3_DDRX_DATA_WIDTH" VALUE="8"/>
5580         <PARAMETER NAME="C3_DDR3_ADDR_WIDTH" VALUE="8"/>
5581         <PARAMETER NAME="C3_DDR3_nCK_PER_CLK" VALUE="2"/>
5582         <PARAMETER NAME="C3_DDR3_DATA_WIDTH" VALUE="8"/>
5583         <PARAMETER NAME="C3_DDR2_ADDR_WIDTH" VALUE="8"/>
5584         <PARAMETER NAME="C3_DDR2_nCK_PER_CLK" VALUE="2"/>
5585         <PARAMETER NAME="C3_DDR2_DATA_WIDTH" VALUE="8"/>
5586         <PARAMETER NAME="C3_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5587         <PARAMETER NAME="C3_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5588         <PARAMETER NAME="C3_LPDDR2_DATA_WIDTH" VALUE="8"/>
5589         <PARAMETER NAME="C3_FREQ_HZ" VALUE="100.0"/>
5590         <PARAMETER NAME="C3_PHASE" VALUE="0.000"/>
5591         <PARAMETER NAME="C3_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5592         <PARAMETER NAME="C3_MMCM_VCO" VALUE="1200.0"/>
5593         <PARAMETER NAME="C3_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5594         <PARAMETER NAME="C3_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5595         <PARAMETER NAME="C3_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5596         <PARAMETER NAME="C3_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5597         <PARAMETER NAME="C3_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5598         <PARAMETER NAME="C3_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5599         <PARAMETER NAME="C3_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5600         <PARAMETER NAME="C3_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5601         <PARAMETER NAME="C3_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5602         <PARAMETER NAME="C3_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5603         <PARAMETER NAME="C3_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5604         <PARAMETER NAME="C3_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5605         <PARAMETER NAME="C3_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5606         <PARAMETER NAME="C3_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5607         <PARAMETER NAME="C3_C_S_AXI_ID_WIDTH" VALUE="4"/>
5608         <PARAMETER NAME="C3_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5609         <PARAMETER NAME="C3_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5610         <PARAMETER NAME="C3_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5611         <PARAMETER NAME="C3_QDRIIP_NUM_DEVICES" VALUE="1"/>
5612         <PARAMETER NAME="C3_QDRIIP_DATA_WIDTH" VALUE="18"/>
5613         <PARAMETER NAME="C3_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5614         <PARAMETER NAME="C3_QDRIIP_BW_WIDTH" VALUE="8"/>
5615         <PARAMETER NAME="C3_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5616         <PARAMETER NAME="C3_QDRIIP_BURST_LEN" VALUE="1"/>
5617         <PARAMETER NAME="C3_RLDII_NUM_DEVICES" VALUE="1"/>
5618         <PARAMETER NAME="C3_RLDII_DATA_WIDTH" VALUE="18"/>
5619         <PARAMETER NAME="C3_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5620         <PARAMETER NAME="C3_RLDII_QK_WIDTH" VALUE="8"/>
5621         <PARAMETER NAME="C3_RLDII_CK_WIDTH" VALUE="1"/>
5622         <PARAMETER NAME="C3_RLDII_DK_WIDTH" VALUE="1"/>
5623         <PARAMETER NAME="C3_RLDII_DM_WIDTH" VALUE="1"/>
5624         <PARAMETER NAME="C3_RLDII_BANK_WIDTH" VALUE="2"/>
5625         <PARAMETER NAME="C3_RLDII_QVLD_WIDTH" VALUE="1"/>
5626         <PARAMETER NAME="C3_RLDII_DEBUG_PORT" VALUE="OFF"/>
5627         <PARAMETER NAME="C3_RLDIII_NUM_DEVICES" VALUE="1"/>
5628         <PARAMETER NAME="C3_RLDIII_DATA_WIDTH" VALUE="18"/>
5629         <PARAMETER NAME="C3_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5630         <PARAMETER NAME="C3_RLDIII_QK_WIDTH" VALUE="8"/>
5631         <PARAMETER NAME="C3_RLDIII_CK_WIDTH" VALUE="1"/>
5632         <PARAMETER NAME="C3_RLDIII_DK_WIDTH" VALUE="1"/>
5633         <PARAMETER NAME="C3_RLDIII_DM_WIDTH" VALUE="1"/>
5634         <PARAMETER NAME="C3_RLDIII_BANK_WIDTH" VALUE="2"/>
5635         <PARAMETER NAME="C3_RLDIII_QVLD_WIDTH" VALUE="1"/>
5636         <PARAMETER NAME="C3_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5637         <PARAMETER NAME="C3_RLDX_CMD_PER_CLK" VALUE="1"/>
5638         <PARAMETER NAME="C3_RLDX_DATA_WIDTH" VALUE="18"/>
5639         <PARAMETER NAME="C3_RLDX_ADDR_WIDTH" VALUE="29"/>
5640         <PARAMETER NAME="C3_RLDX_BANK_WIDTH" VALUE="2"/>
5641         <PARAMETER NAME="C3_RLDX_nCK_PER_CLK" VALUE="1"/>
5642         <PARAMETER NAME="C3_RLDX_DM_WIDTH" VALUE="1"/>
5643         <PARAMETER NAME="C3_RLDII_CMD_PER_CLK" VALUE="1"/>
5644         <PARAMETER NAME="C3_RLDII_ADDR_WIDTH" VALUE="29"/>
5645         <PARAMETER NAME="C3_RLDII_nCK_PER_CLK" VALUE="1"/>
5646         <PARAMETER NAME="C3_RLDIII_CMD_PER_CLK" VALUE="1"/>
5647         <PARAMETER NAME="C3_RLDIII_ADDR_WIDTH" VALUE="29"/>
5648         <PARAMETER NAME="C3_RLDIII_nCK_PER_CLK" VALUE="1"/>
5649         <PARAMETER NAME="C3_POLARITY" VALUE="ACTIVE_LOW"/>
5650         <PARAMETER NAME="C4_MEM_TYPE" VALUE="DDR3"/>
5651         <PARAMETER NAME="C4_IS_CLK_SHARED" VALUE="FALSE"/>
5652         <PARAMETER NAME="C4_SYSCLK_TYPE" VALUE="DIFF"/>
5653         <PARAMETER NAME="C4_USE_AXI" VALUE="0"/>
5654         <PARAMETER NAME="C4_ECC" VALUE="OFF"/>
5655         <PARAMETER NAME="C4_DDR3_DQ_WIDTH" VALUE="8"/>
5656         <PARAMETER NAME="C4_DDR3_DQS_WIDTH" VALUE="1"/>
5657         <PARAMETER NAME="C4_DDR3_ROW_WIDTH" VALUE="14"/>
5658         <PARAMETER NAME="C4_DDR3_BANK_WIDTH" VALUE="3"/>
5659         <PARAMETER NAME="C4_DDR3_CK_WIDTH" VALUE="1"/>
5660         <PARAMETER NAME="C4_DDR3_CKE_WIDTH" VALUE="1"/>
5661         <PARAMETER NAME="C4_DDR3_CS_WIDTH" VALUE="1"/>
5662         <PARAMETER NAME="C4_DDR3_nCS_PER_RANK" VALUE="1"/>
5663         <PARAMETER NAME="C4_DDR3_DM_WIDTH" VALUE="1"/>
5664         <PARAMETER NAME="C4_DDR3_ODT_WIDTH" VALUE="1"/>
5665         <PARAMETER NAME="C4_DDR3_USE_CS_PORT" VALUE="1"/>
5666         <PARAMETER NAME="C4_DDR3_USE_DM_PORT" VALUE="1"/>
5667         <PARAMETER NAME="C4_DDR3_USE_ODT_PORT" VALUE="1"/>
5668         <PARAMETER NAME="C4_DDR3_REG_CTRL" VALUE="OFF"/>
5669         <PARAMETER NAME="C4_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5670         <PARAMETER NAME="C4_DDR3_DEBUG_PORT" VALUE="OFF"/>
5671         <PARAMETER NAME="C4_DDR2_DQ_WIDTH" VALUE="8"/>
5672         <PARAMETER NAME="C4_DDR2_DQS_WIDTH" VALUE="1"/>
5673         <PARAMETER NAME="C4_DDR2_ROW_WIDTH" VALUE="14"/>
5674         <PARAMETER NAME="C4_DDR2_BANK_WIDTH" VALUE="3"/>
5675         <PARAMETER NAME="C4_DDR2_CK_WIDTH" VALUE="1"/>
5676         <PARAMETER NAME="C4_DDR2_CKE_WIDTH" VALUE="1"/>
5677         <PARAMETER NAME="C4_DDR2_CS_WIDTH" VALUE="1"/>
5678         <PARAMETER NAME="C4_DDR2_nCS_PER_RANK" VALUE="1"/>
5679         <PARAMETER NAME="C4_DDR2_DM_WIDTH" VALUE="1"/>
5680         <PARAMETER NAME="C4_DDR2_ODT_WIDTH" VALUE="1"/>
5681         <PARAMETER NAME="C4_DDR2_USE_CS_PORT" VALUE="1"/>
5682         <PARAMETER NAME="C4_DDR2_USE_DM_PORT" VALUE="1"/>
5683         <PARAMETER NAME="C4_DDR2_USE_ODT_PORT" VALUE="1"/>
5684         <PARAMETER NAME="C4_DDR2_REG_CTRL" VALUE="OFF"/>
5685         <PARAMETER NAME="C4_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5686         <PARAMETER NAME="C4_DDR2_DEBUG_PORT" VALUE="OFF"/>
5687         <PARAMETER NAME="C4_LPDDR2_DQ_WIDTH" VALUE="8"/>
5688         <PARAMETER NAME="C4_LPDDR2_DQS_WIDTH" VALUE="1"/>
5689         <PARAMETER NAME="C4_LPDDR2_ROW_WIDTH" VALUE="14"/>
5690         <PARAMETER NAME="C4_LPDDR2_BANK_WIDTH" VALUE="3"/>
5691         <PARAMETER NAME="C4_LPDDR2_CK_WIDTH" VALUE="1"/>
5692         <PARAMETER NAME="C4_LPDDR2_CKE_WIDTH" VALUE="1"/>
5693         <PARAMETER NAME="C4_LPDDR2_CS_WIDTH" VALUE="1"/>
5694         <PARAMETER NAME="C4_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5695         <PARAMETER NAME="C4_LPDDR2_DM_WIDTH" VALUE="1"/>
5696         <PARAMETER NAME="C4_LPDDR2_USE_CS_PORT" VALUE="1"/>
5697         <PARAMETER NAME="C4_LPDDR2_USE_DM_PORT" VALUE="1"/>
5698         <PARAMETER NAME="C4_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5699         <PARAMETER NAME="C4_LPDDR2_REG_CTRL" VALUE="OFF"/>
5700         <PARAMETER NAME="C4_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5701         <PARAMETER NAME="C4_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5702         <PARAMETER NAME="C4_DQS_CNT_WIDTH" VALUE="1"/>
5703         <PARAMETER NAME="C4_DEBUG_PORT" VALUE="OFF"/>
5704         <PARAMETER NAME="C4_DDRX_ADDR_WIDTH" VALUE="8"/>
5705         <PARAMETER NAME="C4_DDRX_nCK_PER_CLK" VALUE="2"/>
5706         <PARAMETER NAME="C4_DDRX_DATA_WIDTH" VALUE="8"/>
5707         <PARAMETER NAME="C4_DDR3_ADDR_WIDTH" VALUE="8"/>
5708         <PARAMETER NAME="C4_DDR3_nCK_PER_CLK" VALUE="2"/>
5709         <PARAMETER NAME="C4_DDR3_DATA_WIDTH" VALUE="8"/>
5710         <PARAMETER NAME="C4_DDR2_ADDR_WIDTH" VALUE="8"/>
5711         <PARAMETER NAME="C4_DDR2_nCK_PER_CLK" VALUE="2"/>
5712         <PARAMETER NAME="C4_DDR2_DATA_WIDTH" VALUE="8"/>
5713         <PARAMETER NAME="C4_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5714         <PARAMETER NAME="C4_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5715         <PARAMETER NAME="C4_LPDDR2_DATA_WIDTH" VALUE="8"/>
5716         <PARAMETER NAME="C4_FREQ_HZ" VALUE="100.0"/>
5717         <PARAMETER NAME="C4_PHASE" VALUE="0.000"/>
5718         <PARAMETER NAME="C4_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5719         <PARAMETER NAME="C4_MMCM_VCO" VALUE="1200.0"/>
5720         <PARAMETER NAME="C4_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5721         <PARAMETER NAME="C4_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5722         <PARAMETER NAME="C4_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5723         <PARAMETER NAME="C4_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5724         <PARAMETER NAME="C4_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5725         <PARAMETER NAME="C4_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5726         <PARAMETER NAME="C4_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5727         <PARAMETER NAME="C4_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5728         <PARAMETER NAME="C4_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5729         <PARAMETER NAME="C4_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5730         <PARAMETER NAME="C4_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5731         <PARAMETER NAME="C4_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5732         <PARAMETER NAME="C4_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5733         <PARAMETER NAME="C4_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5734         <PARAMETER NAME="C4_C_S_AXI_ID_WIDTH" VALUE="4"/>
5735         <PARAMETER NAME="C4_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5736         <PARAMETER NAME="C4_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5737         <PARAMETER NAME="C4_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5738         <PARAMETER NAME="C4_QDRIIP_NUM_DEVICES" VALUE="1"/>
5739         <PARAMETER NAME="C4_QDRIIP_DATA_WIDTH" VALUE="18"/>
5740         <PARAMETER NAME="C4_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5741         <PARAMETER NAME="C4_QDRIIP_BW_WIDTH" VALUE="8"/>
5742         <PARAMETER NAME="C4_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5743         <PARAMETER NAME="C4_QDRIIP_BURST_LEN" VALUE="1"/>
5744         <PARAMETER NAME="C4_RLDII_NUM_DEVICES" VALUE="1"/>
5745         <PARAMETER NAME="C4_RLDII_DATA_WIDTH" VALUE="18"/>
5746         <PARAMETER NAME="C4_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5747         <PARAMETER NAME="C4_RLDII_QK_WIDTH" VALUE="8"/>
5748         <PARAMETER NAME="C4_RLDII_CK_WIDTH" VALUE="1"/>
5749         <PARAMETER NAME="C4_RLDII_DK_WIDTH" VALUE="1"/>
5750         <PARAMETER NAME="C4_RLDII_DM_WIDTH" VALUE="1"/>
5751         <PARAMETER NAME="C4_RLDII_BANK_WIDTH" VALUE="2"/>
5752         <PARAMETER NAME="C4_RLDII_QVLD_WIDTH" VALUE="1"/>
5753         <PARAMETER NAME="C4_RLDII_DEBUG_PORT" VALUE="OFF"/>
5754         <PARAMETER NAME="C4_RLDIII_NUM_DEVICES" VALUE="1"/>
5755         <PARAMETER NAME="C4_RLDIII_DATA_WIDTH" VALUE="18"/>
5756         <PARAMETER NAME="C4_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5757         <PARAMETER NAME="C4_RLDIII_QK_WIDTH" VALUE="8"/>
5758         <PARAMETER NAME="C4_RLDIII_CK_WIDTH" VALUE="1"/>
5759         <PARAMETER NAME="C4_RLDIII_DK_WIDTH" VALUE="1"/>
5760         <PARAMETER NAME="C4_RLDIII_DM_WIDTH" VALUE="1"/>
5761         <PARAMETER NAME="C4_RLDIII_BANK_WIDTH" VALUE="2"/>
5762         <PARAMETER NAME="C4_RLDIII_QVLD_WIDTH" VALUE="1"/>
5763         <PARAMETER NAME="C4_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5764         <PARAMETER NAME="C4_RLDX_CMD_PER_CLK" VALUE="1"/>
5765         <PARAMETER NAME="C4_RLDX_DATA_WIDTH" VALUE="18"/>
5766         <PARAMETER NAME="C4_RLDX_ADDR_WIDTH" VALUE="29"/>
5767         <PARAMETER NAME="C4_RLDX_BANK_WIDTH" VALUE="2"/>
5768         <PARAMETER NAME="C4_RLDX_nCK_PER_CLK" VALUE="1"/>
5769         <PARAMETER NAME="C4_RLDX_DM_WIDTH" VALUE="1"/>
5770         <PARAMETER NAME="C4_RLDII_CMD_PER_CLK" VALUE="1"/>
5771         <PARAMETER NAME="C4_RLDII_ADDR_WIDTH" VALUE="29"/>
5772         <PARAMETER NAME="C4_RLDII_nCK_PER_CLK" VALUE="1"/>
5773         <PARAMETER NAME="C4_RLDIII_CMD_PER_CLK" VALUE="1"/>
5774         <PARAMETER NAME="C4_RLDIII_ADDR_WIDTH" VALUE="29"/>
5775         <PARAMETER NAME="C4_RLDIII_nCK_PER_CLK" VALUE="1"/>
5776         <PARAMETER NAME="C4_POLARITY" VALUE="ACTIVE_LOW"/>
5777         <PARAMETER NAME="C5_MEM_TYPE" VALUE="DDR3"/>
5778         <PARAMETER NAME="C5_IS_CLK_SHARED" VALUE="FALSE"/>
5779         <PARAMETER NAME="C5_SYSCLK_TYPE" VALUE="DIFF"/>
5780         <PARAMETER NAME="C5_USE_AXI" VALUE="0"/>
5781         <PARAMETER NAME="C5_ECC" VALUE="OFF"/>
5782         <PARAMETER NAME="C5_DDR3_DQ_WIDTH" VALUE="8"/>
5783         <PARAMETER NAME="C5_DDR3_DQS_WIDTH" VALUE="1"/>
5784         <PARAMETER NAME="C5_DDR3_ROW_WIDTH" VALUE="14"/>
5785         <PARAMETER NAME="C5_DDR3_BANK_WIDTH" VALUE="3"/>
5786         <PARAMETER NAME="C5_DDR3_CK_WIDTH" VALUE="1"/>
5787         <PARAMETER NAME="C5_DDR3_CKE_WIDTH" VALUE="1"/>
5788         <PARAMETER NAME="C5_DDR3_CS_WIDTH" VALUE="1"/>
5789         <PARAMETER NAME="C5_DDR3_nCS_PER_RANK" VALUE="1"/>
5790         <PARAMETER NAME="C5_DDR3_DM_WIDTH" VALUE="1"/>
5791         <PARAMETER NAME="C5_DDR3_ODT_WIDTH" VALUE="1"/>
5792         <PARAMETER NAME="C5_DDR3_USE_CS_PORT" VALUE="1"/>
5793         <PARAMETER NAME="C5_DDR3_USE_DM_PORT" VALUE="1"/>
5794         <PARAMETER NAME="C5_DDR3_USE_ODT_PORT" VALUE="1"/>
5795         <PARAMETER NAME="C5_DDR3_REG_CTRL" VALUE="OFF"/>
5796         <PARAMETER NAME="C5_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5797         <PARAMETER NAME="C5_DDR3_DEBUG_PORT" VALUE="OFF"/>
5798         <PARAMETER NAME="C5_DDR2_DQ_WIDTH" VALUE="8"/>
5799         <PARAMETER NAME="C5_DDR2_DQS_WIDTH" VALUE="1"/>
5800         <PARAMETER NAME="C5_DDR2_ROW_WIDTH" VALUE="14"/>
5801         <PARAMETER NAME="C5_DDR2_BANK_WIDTH" VALUE="3"/>
5802         <PARAMETER NAME="C5_DDR2_CK_WIDTH" VALUE="1"/>
5803         <PARAMETER NAME="C5_DDR2_CKE_WIDTH" VALUE="1"/>
5804         <PARAMETER NAME="C5_DDR2_CS_WIDTH" VALUE="1"/>
5805         <PARAMETER NAME="C5_DDR2_nCS_PER_RANK" VALUE="1"/>
5806         <PARAMETER NAME="C5_DDR2_DM_WIDTH" VALUE="1"/>
5807         <PARAMETER NAME="C5_DDR2_ODT_WIDTH" VALUE="1"/>
5808         <PARAMETER NAME="C5_DDR2_USE_CS_PORT" VALUE="1"/>
5809         <PARAMETER NAME="C5_DDR2_USE_DM_PORT" VALUE="1"/>
5810         <PARAMETER NAME="C5_DDR2_USE_ODT_PORT" VALUE="1"/>
5811         <PARAMETER NAME="C5_DDR2_REG_CTRL" VALUE="OFF"/>
5812         <PARAMETER NAME="C5_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5813         <PARAMETER NAME="C5_DDR2_DEBUG_PORT" VALUE="OFF"/>
5814         <PARAMETER NAME="C5_LPDDR2_DQ_WIDTH" VALUE="8"/>
5815         <PARAMETER NAME="C5_LPDDR2_DQS_WIDTH" VALUE="1"/>
5816         <PARAMETER NAME="C5_LPDDR2_ROW_WIDTH" VALUE="14"/>
5817         <PARAMETER NAME="C5_LPDDR2_BANK_WIDTH" VALUE="3"/>
5818         <PARAMETER NAME="C5_LPDDR2_CK_WIDTH" VALUE="1"/>
5819         <PARAMETER NAME="C5_LPDDR2_CKE_WIDTH" VALUE="1"/>
5820         <PARAMETER NAME="C5_LPDDR2_CS_WIDTH" VALUE="1"/>
5821         <PARAMETER NAME="C5_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5822         <PARAMETER NAME="C5_LPDDR2_DM_WIDTH" VALUE="1"/>
5823         <PARAMETER NAME="C5_LPDDR2_USE_CS_PORT" VALUE="1"/>
5824         <PARAMETER NAME="C5_LPDDR2_USE_DM_PORT" VALUE="1"/>
5825         <PARAMETER NAME="C5_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5826         <PARAMETER NAME="C5_LPDDR2_REG_CTRL" VALUE="OFF"/>
5827         <PARAMETER NAME="C5_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5828         <PARAMETER NAME="C5_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5829         <PARAMETER NAME="C5_DQS_CNT_WIDTH" VALUE="1"/>
5830         <PARAMETER NAME="C5_DEBUG_PORT" VALUE="OFF"/>
5831         <PARAMETER NAME="C5_DDRX_ADDR_WIDTH" VALUE="8"/>
5832         <PARAMETER NAME="C5_DDRX_nCK_PER_CLK" VALUE="2"/>
5833         <PARAMETER NAME="C5_DDRX_DATA_WIDTH" VALUE="8"/>
5834         <PARAMETER NAME="C5_DDR3_ADDR_WIDTH" VALUE="8"/>
5835         <PARAMETER NAME="C5_DDR3_nCK_PER_CLK" VALUE="2"/>
5836         <PARAMETER NAME="C5_DDR3_DATA_WIDTH" VALUE="8"/>
5837         <PARAMETER NAME="C5_DDR2_ADDR_WIDTH" VALUE="8"/>
5838         <PARAMETER NAME="C5_DDR2_nCK_PER_CLK" VALUE="2"/>
5839         <PARAMETER NAME="C5_DDR2_DATA_WIDTH" VALUE="8"/>
5840         <PARAMETER NAME="C5_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5841         <PARAMETER NAME="C5_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5842         <PARAMETER NAME="C5_LPDDR2_DATA_WIDTH" VALUE="8"/>
5843         <PARAMETER NAME="C5_FREQ_HZ" VALUE="100.0"/>
5844         <PARAMETER NAME="C5_PHASE" VALUE="0.000"/>
5845         <PARAMETER NAME="C5_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5846         <PARAMETER NAME="C5_MMCM_VCO" VALUE="1200.0"/>
5847         <PARAMETER NAME="C5_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5848         <PARAMETER NAME="C5_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5849         <PARAMETER NAME="C5_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5850         <PARAMETER NAME="C5_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5851         <PARAMETER NAME="C5_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5852         <PARAMETER NAME="C5_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5853         <PARAMETER NAME="C5_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5854         <PARAMETER NAME="C5_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5855         <PARAMETER NAME="C5_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5856         <PARAMETER NAME="C5_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5857         <PARAMETER NAME="C5_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5858         <PARAMETER NAME="C5_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5859         <PARAMETER NAME="C5_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5860         <PARAMETER NAME="C5_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5861         <PARAMETER NAME="C5_C_S_AXI_ID_WIDTH" VALUE="4"/>
5862         <PARAMETER NAME="C5_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5863         <PARAMETER NAME="C5_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5864         <PARAMETER NAME="C5_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5865         <PARAMETER NAME="C5_QDRIIP_NUM_DEVICES" VALUE="1"/>
5866         <PARAMETER NAME="C5_QDRIIP_DATA_WIDTH" VALUE="18"/>
5867         <PARAMETER NAME="C5_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5868         <PARAMETER NAME="C5_QDRIIP_BW_WIDTH" VALUE="8"/>
5869         <PARAMETER NAME="C5_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5870         <PARAMETER NAME="C5_QDRIIP_BURST_LEN" VALUE="1"/>
5871         <PARAMETER NAME="C5_RLDII_NUM_DEVICES" VALUE="1"/>
5872         <PARAMETER NAME="C5_RLDII_DATA_WIDTH" VALUE="18"/>
5873         <PARAMETER NAME="C5_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
5874         <PARAMETER NAME="C5_RLDII_QK_WIDTH" VALUE="8"/>
5875         <PARAMETER NAME="C5_RLDII_CK_WIDTH" VALUE="1"/>
5876         <PARAMETER NAME="C5_RLDII_DK_WIDTH" VALUE="1"/>
5877         <PARAMETER NAME="C5_RLDII_DM_WIDTH" VALUE="1"/>
5878         <PARAMETER NAME="C5_RLDII_BANK_WIDTH" VALUE="2"/>
5879         <PARAMETER NAME="C5_RLDII_QVLD_WIDTH" VALUE="1"/>
5880         <PARAMETER NAME="C5_RLDII_DEBUG_PORT" VALUE="OFF"/>
5881         <PARAMETER NAME="C5_RLDIII_NUM_DEVICES" VALUE="1"/>
5882         <PARAMETER NAME="C5_RLDIII_DATA_WIDTH" VALUE="18"/>
5883         <PARAMETER NAME="C5_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
5884         <PARAMETER NAME="C5_RLDIII_QK_WIDTH" VALUE="8"/>
5885         <PARAMETER NAME="C5_RLDIII_CK_WIDTH" VALUE="1"/>
5886         <PARAMETER NAME="C5_RLDIII_DK_WIDTH" VALUE="1"/>
5887         <PARAMETER NAME="C5_RLDIII_DM_WIDTH" VALUE="1"/>
5888         <PARAMETER NAME="C5_RLDIII_BANK_WIDTH" VALUE="2"/>
5889         <PARAMETER NAME="C5_RLDIII_QVLD_WIDTH" VALUE="1"/>
5890         <PARAMETER NAME="C5_RLDIII_DEBUG_PORT" VALUE="OFF"/>
5891         <PARAMETER NAME="C5_RLDX_CMD_PER_CLK" VALUE="1"/>
5892         <PARAMETER NAME="C5_RLDX_DATA_WIDTH" VALUE="18"/>
5893         <PARAMETER NAME="C5_RLDX_ADDR_WIDTH" VALUE="29"/>
5894         <PARAMETER NAME="C5_RLDX_BANK_WIDTH" VALUE="2"/>
5895         <PARAMETER NAME="C5_RLDX_nCK_PER_CLK" VALUE="1"/>
5896         <PARAMETER NAME="C5_RLDX_DM_WIDTH" VALUE="1"/>
5897         <PARAMETER NAME="C5_RLDII_CMD_PER_CLK" VALUE="1"/>
5898         <PARAMETER NAME="C5_RLDII_ADDR_WIDTH" VALUE="29"/>
5899         <PARAMETER NAME="C5_RLDII_nCK_PER_CLK" VALUE="1"/>
5900         <PARAMETER NAME="C5_RLDIII_CMD_PER_CLK" VALUE="1"/>
5901         <PARAMETER NAME="C5_RLDIII_ADDR_WIDTH" VALUE="29"/>
5902         <PARAMETER NAME="C5_RLDIII_nCK_PER_CLK" VALUE="1"/>
5903         <PARAMETER NAME="C5_POLARITY" VALUE="ACTIVE_LOW"/>
5904         <PARAMETER NAME="C6_MEM_TYPE" VALUE="DDR3"/>
5905         <PARAMETER NAME="C6_IS_CLK_SHARED" VALUE="FALSE"/>
5906         <PARAMETER NAME="C6_SYSCLK_TYPE" VALUE="DIFF"/>
5907         <PARAMETER NAME="C6_USE_AXI" VALUE="0"/>
5908         <PARAMETER NAME="C6_ECC" VALUE="OFF"/>
5909         <PARAMETER NAME="C6_DDR3_DQ_WIDTH" VALUE="8"/>
5910         <PARAMETER NAME="C6_DDR3_DQS_WIDTH" VALUE="1"/>
5911         <PARAMETER NAME="C6_DDR3_ROW_WIDTH" VALUE="14"/>
5912         <PARAMETER NAME="C6_DDR3_BANK_WIDTH" VALUE="3"/>
5913         <PARAMETER NAME="C6_DDR3_CK_WIDTH" VALUE="1"/>
5914         <PARAMETER NAME="C6_DDR3_CKE_WIDTH" VALUE="1"/>
5915         <PARAMETER NAME="C6_DDR3_CS_WIDTH" VALUE="1"/>
5916         <PARAMETER NAME="C6_DDR3_nCS_PER_RANK" VALUE="1"/>
5917         <PARAMETER NAME="C6_DDR3_DM_WIDTH" VALUE="1"/>
5918         <PARAMETER NAME="C6_DDR3_ODT_WIDTH" VALUE="1"/>
5919         <PARAMETER NAME="C6_DDR3_USE_CS_PORT" VALUE="1"/>
5920         <PARAMETER NAME="C6_DDR3_USE_DM_PORT" VALUE="1"/>
5921         <PARAMETER NAME="C6_DDR3_USE_ODT_PORT" VALUE="1"/>
5922         <PARAMETER NAME="C6_DDR3_REG_CTRL" VALUE="OFF"/>
5923         <PARAMETER NAME="C6_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
5924         <PARAMETER NAME="C6_DDR3_DEBUG_PORT" VALUE="OFF"/>
5925         <PARAMETER NAME="C6_DDR2_DQ_WIDTH" VALUE="8"/>
5926         <PARAMETER NAME="C6_DDR2_DQS_WIDTH" VALUE="1"/>
5927         <PARAMETER NAME="C6_DDR2_ROW_WIDTH" VALUE="14"/>
5928         <PARAMETER NAME="C6_DDR2_BANK_WIDTH" VALUE="3"/>
5929         <PARAMETER NAME="C6_DDR2_CK_WIDTH" VALUE="1"/>
5930         <PARAMETER NAME="C6_DDR2_CKE_WIDTH" VALUE="1"/>
5931         <PARAMETER NAME="C6_DDR2_CS_WIDTH" VALUE="1"/>
5932         <PARAMETER NAME="C6_DDR2_nCS_PER_RANK" VALUE="1"/>
5933         <PARAMETER NAME="C6_DDR2_DM_WIDTH" VALUE="1"/>
5934         <PARAMETER NAME="C6_DDR2_ODT_WIDTH" VALUE="1"/>
5935         <PARAMETER NAME="C6_DDR2_USE_CS_PORT" VALUE="1"/>
5936         <PARAMETER NAME="C6_DDR2_USE_DM_PORT" VALUE="1"/>
5937         <PARAMETER NAME="C6_DDR2_USE_ODT_PORT" VALUE="1"/>
5938         <PARAMETER NAME="C6_DDR2_REG_CTRL" VALUE="OFF"/>
5939         <PARAMETER NAME="C6_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
5940         <PARAMETER NAME="C6_DDR2_DEBUG_PORT" VALUE="OFF"/>
5941         <PARAMETER NAME="C6_LPDDR2_DQ_WIDTH" VALUE="8"/>
5942         <PARAMETER NAME="C6_LPDDR2_DQS_WIDTH" VALUE="1"/>
5943         <PARAMETER NAME="C6_LPDDR2_ROW_WIDTH" VALUE="14"/>
5944         <PARAMETER NAME="C6_LPDDR2_BANK_WIDTH" VALUE="3"/>
5945         <PARAMETER NAME="C6_LPDDR2_CK_WIDTH" VALUE="1"/>
5946         <PARAMETER NAME="C6_LPDDR2_CKE_WIDTH" VALUE="1"/>
5947         <PARAMETER NAME="C6_LPDDR2_CS_WIDTH" VALUE="1"/>
5948         <PARAMETER NAME="C6_LPDDR2_nCS_PER_RANK" VALUE="1"/>
5949         <PARAMETER NAME="C6_LPDDR2_DM_WIDTH" VALUE="1"/>
5950         <PARAMETER NAME="C6_LPDDR2_USE_CS_PORT" VALUE="1"/>
5951         <PARAMETER NAME="C6_LPDDR2_USE_DM_PORT" VALUE="1"/>
5952         <PARAMETER NAME="C6_LPDDR2_USE_ODT_PORT" VALUE="1"/>
5953         <PARAMETER NAME="C6_LPDDR2_REG_CTRL" VALUE="OFF"/>
5954         <PARAMETER NAME="C6_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
5955         <PARAMETER NAME="C6_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
5956         <PARAMETER NAME="C6_DQS_CNT_WIDTH" VALUE="1"/>
5957         <PARAMETER NAME="C6_DEBUG_PORT" VALUE="OFF"/>
5958         <PARAMETER NAME="C6_DDRX_ADDR_WIDTH" VALUE="8"/>
5959         <PARAMETER NAME="C6_DDRX_nCK_PER_CLK" VALUE="2"/>
5960         <PARAMETER NAME="C6_DDRX_DATA_WIDTH" VALUE="8"/>
5961         <PARAMETER NAME="C6_DDR3_ADDR_WIDTH" VALUE="8"/>
5962         <PARAMETER NAME="C6_DDR3_nCK_PER_CLK" VALUE="2"/>
5963         <PARAMETER NAME="C6_DDR3_DATA_WIDTH" VALUE="8"/>
5964         <PARAMETER NAME="C6_DDR2_ADDR_WIDTH" VALUE="8"/>
5965         <PARAMETER NAME="C6_DDR2_nCK_PER_CLK" VALUE="2"/>
5966         <PARAMETER NAME="C6_DDR2_DATA_WIDTH" VALUE="8"/>
5967         <PARAMETER NAME="C6_LPDDR2_ADDR_WIDTH" VALUE="8"/>
5968         <PARAMETER NAME="C6_LPDDR2_nCK_PER_CLK" VALUE="2"/>
5969         <PARAMETER NAME="C6_LPDDR2_DATA_WIDTH" VALUE="8"/>
5970         <PARAMETER NAME="C6_FREQ_HZ" VALUE="100.0"/>
5971         <PARAMETER NAME="C6_PHASE" VALUE="0.000"/>
5972         <PARAMETER NAME="C6_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
5973         <PARAMETER NAME="C6_MMCM_VCO" VALUE="1200.0"/>
5974         <PARAMETER NAME="C6_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
5975         <PARAMETER NAME="C6_MMCM_CLKOUT1_FREQ" VALUE="10"/>
5976         <PARAMETER NAME="C6_MMCM_CLKOUT2_FREQ" VALUE="10"/>
5977         <PARAMETER NAME="C6_MMCM_CLKOUT3_FREQ" VALUE="10"/>
5978         <PARAMETER NAME="C6_MMCM_CLKOUT4_FREQ" VALUE="10"/>
5979         <PARAMETER NAME="C6_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
5980         <PARAMETER NAME="C6_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
5981         <PARAMETER NAME="C6_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
5982         <PARAMETER NAME="C6_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
5983         <PARAMETER NAME="C6_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
5984         <PARAMETER NAME="C6_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
5985         <PARAMETER NAME="C6_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
5986         <PARAMETER NAME="C6_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
5987         <PARAMETER NAME="C6_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
5988         <PARAMETER NAME="C6_C_S_AXI_ID_WIDTH" VALUE="4"/>
5989         <PARAMETER NAME="C6_C_S_AXI_DATA_WIDTH" VALUE="32"/>
5990         <PARAMETER NAME="C6_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
5991         <PARAMETER NAME="C6_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
5992         <PARAMETER NAME="C6_QDRIIP_NUM_DEVICES" VALUE="1"/>
5993         <PARAMETER NAME="C6_QDRIIP_DATA_WIDTH" VALUE="18"/>
5994         <PARAMETER NAME="C6_QDRIIP_ADDR_WIDTH" VALUE="29"/>
5995         <PARAMETER NAME="C6_QDRIIP_BW_WIDTH" VALUE="8"/>
5996         <PARAMETER NAME="C6_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
5997         <PARAMETER NAME="C6_QDRIIP_BURST_LEN" VALUE="1"/>
5998         <PARAMETER NAME="C6_RLDII_NUM_DEVICES" VALUE="1"/>
5999         <PARAMETER NAME="C6_RLDII_DATA_WIDTH" VALUE="18"/>
6000         <PARAMETER NAME="C6_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
6001         <PARAMETER NAME="C6_RLDII_QK_WIDTH" VALUE="8"/>
6002         <PARAMETER NAME="C6_RLDII_CK_WIDTH" VALUE="1"/>
6003         <PARAMETER NAME="C6_RLDII_DK_WIDTH" VALUE="1"/>
6004         <PARAMETER NAME="C6_RLDII_DM_WIDTH" VALUE="1"/>
6005         <PARAMETER NAME="C6_RLDII_BANK_WIDTH" VALUE="2"/>
6006         <PARAMETER NAME="C6_RLDII_QVLD_WIDTH" VALUE="1"/>
6007         <PARAMETER NAME="C6_RLDII_DEBUG_PORT" VALUE="OFF"/>
6008         <PARAMETER NAME="C6_RLDIII_NUM_DEVICES" VALUE="1"/>
6009         <PARAMETER NAME="C6_RLDIII_DATA_WIDTH" VALUE="18"/>
6010         <PARAMETER NAME="C6_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
6011         <PARAMETER NAME="C6_RLDIII_QK_WIDTH" VALUE="8"/>
6012         <PARAMETER NAME="C6_RLDIII_CK_WIDTH" VALUE="1"/>
6013         <PARAMETER NAME="C6_RLDIII_DK_WIDTH" VALUE="1"/>
6014         <PARAMETER NAME="C6_RLDIII_DM_WIDTH" VALUE="1"/>
6015         <PARAMETER NAME="C6_RLDIII_BANK_WIDTH" VALUE="2"/>
6016         <PARAMETER NAME="C6_RLDIII_QVLD_WIDTH" VALUE="1"/>
6017         <PARAMETER NAME="C6_RLDIII_DEBUG_PORT" VALUE="OFF"/>
6018         <PARAMETER NAME="C6_RLDX_CMD_PER_CLK" VALUE="1"/>
6019         <PARAMETER NAME="C6_RLDX_DATA_WIDTH" VALUE="18"/>
6020         <PARAMETER NAME="C6_RLDX_ADDR_WIDTH" VALUE="29"/>
6021         <PARAMETER NAME="C6_RLDX_BANK_WIDTH" VALUE="2"/>
6022         <PARAMETER NAME="C6_RLDX_nCK_PER_CLK" VALUE="1"/>
6023         <PARAMETER NAME="C6_RLDX_DM_WIDTH" VALUE="1"/>
6024         <PARAMETER NAME="C6_RLDII_CMD_PER_CLK" VALUE="1"/>
6025         <PARAMETER NAME="C6_RLDII_ADDR_WIDTH" VALUE="29"/>
6026         <PARAMETER NAME="C6_RLDII_nCK_PER_CLK" VALUE="1"/>
6027         <PARAMETER NAME="C6_RLDIII_CMD_PER_CLK" VALUE="1"/>
6028         <PARAMETER NAME="C6_RLDIII_ADDR_WIDTH" VALUE="29"/>
6029         <PARAMETER NAME="C6_RLDIII_nCK_PER_CLK" VALUE="1"/>
6030         <PARAMETER NAME="C6_POLARITY" VALUE="ACTIVE_LOW"/>
6031         <PARAMETER NAME="C7_MEM_TYPE" VALUE="DDR3"/>
6032         <PARAMETER NAME="C7_IS_CLK_SHARED" VALUE="FALSE"/>
6033         <PARAMETER NAME="C7_SYSCLK_TYPE" VALUE="DIFF"/>
6034         <PARAMETER NAME="C7_USE_AXI" VALUE="0"/>
6035         <PARAMETER NAME="C7_ECC" VALUE="OFF"/>
6036         <PARAMETER NAME="C7_DDR3_DQ_WIDTH" VALUE="8"/>
6037         <PARAMETER NAME="C7_DDR3_DQS_WIDTH" VALUE="1"/>
6038         <PARAMETER NAME="C7_DDR3_ROW_WIDTH" VALUE="14"/>
6039         <PARAMETER NAME="C7_DDR3_BANK_WIDTH" VALUE="3"/>
6040         <PARAMETER NAME="C7_DDR3_CK_WIDTH" VALUE="1"/>
6041         <PARAMETER NAME="C7_DDR3_CKE_WIDTH" VALUE="1"/>
6042         <PARAMETER NAME="C7_DDR3_CS_WIDTH" VALUE="1"/>
6043         <PARAMETER NAME="C7_DDR3_nCS_PER_RANK" VALUE="1"/>
6044         <PARAMETER NAME="C7_DDR3_DM_WIDTH" VALUE="1"/>
6045         <PARAMETER NAME="C7_DDR3_ODT_WIDTH" VALUE="1"/>
6046         <PARAMETER NAME="C7_DDR3_USE_CS_PORT" VALUE="1"/>
6047         <PARAMETER NAME="C7_DDR3_USE_DM_PORT" VALUE="1"/>
6048         <PARAMETER NAME="C7_DDR3_USE_ODT_PORT" VALUE="1"/>
6049         <PARAMETER NAME="C7_DDR3_REG_CTRL" VALUE="OFF"/>
6050         <PARAMETER NAME="C7_DDR3_DQS_CNT_WIDTH" VALUE="1"/>
6051         <PARAMETER NAME="C7_DDR3_DEBUG_PORT" VALUE="OFF"/>
6052         <PARAMETER NAME="C7_DDR2_DQ_WIDTH" VALUE="8"/>
6053         <PARAMETER NAME="C7_DDR2_DQS_WIDTH" VALUE="1"/>
6054         <PARAMETER NAME="C7_DDR2_ROW_WIDTH" VALUE="14"/>
6055         <PARAMETER NAME="C7_DDR2_BANK_WIDTH" VALUE="3"/>
6056         <PARAMETER NAME="C7_DDR2_CK_WIDTH" VALUE="1"/>
6057         <PARAMETER NAME="C7_DDR2_CKE_WIDTH" VALUE="1"/>
6058         <PARAMETER NAME="C7_DDR2_CS_WIDTH" VALUE="1"/>
6059         <PARAMETER NAME="C7_DDR2_nCS_PER_RANK" VALUE="1"/>
6060         <PARAMETER NAME="C7_DDR2_DM_WIDTH" VALUE="1"/>
6061         <PARAMETER NAME="C7_DDR2_ODT_WIDTH" VALUE="1"/>
6062         <PARAMETER NAME="C7_DDR2_USE_CS_PORT" VALUE="1"/>
6063         <PARAMETER NAME="C7_DDR2_USE_DM_PORT" VALUE="1"/>
6064         <PARAMETER NAME="C7_DDR2_USE_ODT_PORT" VALUE="1"/>
6065         <PARAMETER NAME="C7_DDR2_REG_CTRL" VALUE="OFF"/>
6066         <PARAMETER NAME="C7_DDR2_DQS_CNT_WIDTH" VALUE="1"/>
6067         <PARAMETER NAME="C7_DDR2_DEBUG_PORT" VALUE="OFF"/>
6068         <PARAMETER NAME="C7_LPDDR2_DQ_WIDTH" VALUE="8"/>
6069         <PARAMETER NAME="C7_LPDDR2_DQS_WIDTH" VALUE="1"/>
6070         <PARAMETER NAME="C7_LPDDR2_ROW_WIDTH" VALUE="14"/>
6071         <PARAMETER NAME="C7_LPDDR2_BANK_WIDTH" VALUE="3"/>
6072         <PARAMETER NAME="C7_LPDDR2_CK_WIDTH" VALUE="1"/>
6073         <PARAMETER NAME="C7_LPDDR2_CKE_WIDTH" VALUE="1"/>
6074         <PARAMETER NAME="C7_LPDDR2_CS_WIDTH" VALUE="1"/>
6075         <PARAMETER NAME="C7_LPDDR2_nCS_PER_RANK" VALUE="1"/>
6076         <PARAMETER NAME="C7_LPDDR2_DM_WIDTH" VALUE="1"/>
6077         <PARAMETER NAME="C7_LPDDR2_USE_CS_PORT" VALUE="1"/>
6078         <PARAMETER NAME="C7_LPDDR2_USE_DM_PORT" VALUE="1"/>
6079         <PARAMETER NAME="C7_LPDDR2_USE_ODT_PORT" VALUE="1"/>
6080         <PARAMETER NAME="C7_LPDDR2_REG_CTRL" VALUE="OFF"/>
6081         <PARAMETER NAME="C7_LPDDR2_DQS_CNT_WIDTH" VALUE="1"/>
6082         <PARAMETER NAME="C7_LPDDR2_DEBUG_PORT" VALUE="OFF"/>
6083         <PARAMETER NAME="C7_DQS_CNT_WIDTH" VALUE="1"/>
6084         <PARAMETER NAME="C7_DEBUG_PORT" VALUE="OFF"/>
6085         <PARAMETER NAME="C7_DDRX_ADDR_WIDTH" VALUE="8"/>
6086         <PARAMETER NAME="C7_DDRX_nCK_PER_CLK" VALUE="2"/>
6087         <PARAMETER NAME="C7_DDRX_DATA_WIDTH" VALUE="8"/>
6088         <PARAMETER NAME="C7_DDR3_ADDR_WIDTH" VALUE="8"/>
6089         <PARAMETER NAME="C7_DDR3_nCK_PER_CLK" VALUE="2"/>
6090         <PARAMETER NAME="C7_DDR3_DATA_WIDTH" VALUE="8"/>
6091         <PARAMETER NAME="C7_DDR2_ADDR_WIDTH" VALUE="8"/>
6092         <PARAMETER NAME="C7_DDR2_nCK_PER_CLK" VALUE="2"/>
6093         <PARAMETER NAME="C7_DDR2_DATA_WIDTH" VALUE="8"/>
6094         <PARAMETER NAME="C7_LPDDR2_ADDR_WIDTH" VALUE="8"/>
6095         <PARAMETER NAME="C7_LPDDR2_nCK_PER_CLK" VALUE="2"/>
6096         <PARAMETER NAME="C7_LPDDR2_DATA_WIDTH" VALUE="8"/>
6097         <PARAMETER NAME="C7_FREQ_HZ" VALUE="100.0"/>
6098         <PARAMETER NAME="C7_PHASE" VALUE="0.000"/>
6099         <PARAMETER NAME="C7_UI_EXTRA_CLOCKS" VALUE="FALSE"/>
6100         <PARAMETER NAME="C7_MMCM_VCO" VALUE="1200.0"/>
6101         <PARAMETER NAME="C7_MMCM_CLKOUT0_FREQ" VALUE="10.0"/>
6102         <PARAMETER NAME="C7_MMCM_CLKOUT1_FREQ" VALUE="10"/>
6103         <PARAMETER NAME="C7_MMCM_CLKOUT2_FREQ" VALUE="10"/>
6104         <PARAMETER NAME="C7_MMCM_CLKOUT3_FREQ" VALUE="10"/>
6105         <PARAMETER NAME="C7_MMCM_CLKOUT4_FREQ" VALUE="10"/>
6106         <PARAMETER NAME="C7_MMCM_CLKOUT0_EN" VALUE="FALSE"/>
6107         <PARAMETER NAME="C7_MMCM_CLKOUT2_EN" VALUE="FALSE"/>
6108         <PARAMETER NAME="C7_MMCM_CLKOUT1_EN" VALUE="FALSE"/>
6109         <PARAMETER NAME="C7_MMCM_CLKOUT3_EN" VALUE="FALSE"/>
6110         <PARAMETER NAME="C7_MMCM_CLKOUT4_EN" VALUE="FALSE"/>
6111         <PARAMETER NAME="C7_C_S_AXI_CTRL_ID_WIDTH" VALUE="4"/>
6112         <PARAMETER NAME="C7_C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
6113         <PARAMETER NAME="C7_C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
6114         <PARAMETER NAME="C7_C_S_AXI_CTRL_MEM_SIZE" VALUE="1048576"/>
6115         <PARAMETER NAME="C7_C_S_AXI_ID_WIDTH" VALUE="4"/>
6116         <PARAMETER NAME="C7_C_S_AXI_DATA_WIDTH" VALUE="32"/>
6117         <PARAMETER NAME="C7_C_S_AXI_ADDR_WIDTH" VALUE="32"/>
6118         <PARAMETER NAME="C7_C_S_AXI_MEM_SIZE" VALUE="1048576"/>
6119         <PARAMETER NAME="C7_QDRIIP_NUM_DEVICES" VALUE="1"/>
6120         <PARAMETER NAME="C7_QDRIIP_DATA_WIDTH" VALUE="18"/>
6121         <PARAMETER NAME="C7_QDRIIP_ADDR_WIDTH" VALUE="29"/>
6122         <PARAMETER NAME="C7_QDRIIP_BW_WIDTH" VALUE="8"/>
6123         <PARAMETER NAME="C7_QDRIIP_DEBUG_PORT" VALUE="OFF"/>
6124         <PARAMETER NAME="C7_QDRIIP_BURST_LEN" VALUE="1"/>
6125         <PARAMETER NAME="C7_RLDII_NUM_DEVICES" VALUE="1"/>
6126         <PARAMETER NAME="C7_RLDII_DATA_WIDTH" VALUE="18"/>
6127         <PARAMETER NAME="C7_RLDII_RLD_ADDR_WIDTH" VALUE="29"/>
6128         <PARAMETER NAME="C7_RLDII_QK_WIDTH" VALUE="8"/>
6129         <PARAMETER NAME="C7_RLDII_CK_WIDTH" VALUE="1"/>
6130         <PARAMETER NAME="C7_RLDII_DK_WIDTH" VALUE="1"/>
6131         <PARAMETER NAME="C7_RLDII_DM_WIDTH" VALUE="1"/>
6132         <PARAMETER NAME="C7_RLDII_BANK_WIDTH" VALUE="2"/>
6133         <PARAMETER NAME="C7_RLDII_QVLD_WIDTH" VALUE="1"/>
6134         <PARAMETER NAME="C7_RLDII_DEBUG_PORT" VALUE="OFF"/>
6135         <PARAMETER NAME="C7_RLDIII_NUM_DEVICES" VALUE="1"/>
6136         <PARAMETER NAME="C7_RLDIII_DATA_WIDTH" VALUE="18"/>
6137         <PARAMETER NAME="C7_RLDIII_RLD_ADDR_WIDTH" VALUE="29"/>
6138         <PARAMETER NAME="C7_RLDIII_QK_WIDTH" VALUE="8"/>
6139         <PARAMETER NAME="C7_RLDIII_CK_WIDTH" VALUE="1"/>
6140         <PARAMETER NAME="C7_RLDIII_DK_WIDTH" VALUE="1"/>
6141         <PARAMETER NAME="C7_RLDIII_DM_WIDTH" VALUE="1"/>
6142         <PARAMETER NAME="C7_RLDIII_BANK_WIDTH" VALUE="2"/>
6143         <PARAMETER NAME="C7_RLDIII_QVLD_WIDTH" VALUE="1"/>
6144         <PARAMETER NAME="C7_RLDIII_DEBUG_PORT" VALUE="OFF"/>
6145         <PARAMETER NAME="C7_RLDX_CMD_PER_CLK" VALUE="1"/>
6146         <PARAMETER NAME="C7_RLDX_DATA_WIDTH" VALUE="18"/>
6147         <PARAMETER NAME="C7_RLDX_ADDR_WIDTH" VALUE="29"/>
6148         <PARAMETER NAME="C7_RLDX_BANK_WIDTH" VALUE="2"/>
6149         <PARAMETER NAME="C7_RLDX_nCK_PER_CLK" VALUE="1"/>
6150         <PARAMETER NAME="C7_RLDX_DM_WIDTH" VALUE="1"/>
6151         <PARAMETER NAME="C7_RLDII_CMD_PER_CLK" VALUE="1"/>
6152         <PARAMETER NAME="C7_RLDII_ADDR_WIDTH" VALUE="29"/>
6153         <PARAMETER NAME="C7_RLDII_nCK_PER_CLK" VALUE="1"/>
6154         <PARAMETER NAME="C7_RLDIII_CMD_PER_CLK" VALUE="1"/>
6155         <PARAMETER NAME="C7_RLDIII_ADDR_WIDTH" VALUE="29"/>
6156         <PARAMETER NAME="C7_RLDIII_nCK_PER_CLK" VALUE="1"/>
6157         <PARAMETER NAME="C7_POLARITY" VALUE="ACTIVE_LOW"/>
6158         <PARAMETER NAME="XML_INPUT_FILE" VALUE="board.prj"/>
6159         <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="reset"/>
6160         <PARAMETER NAME="MIG_DONT_TOUCH_PARAM" VALUE="Custom"/>
6161         <PARAMETER NAME="BOARD_MIG_PARAM" VALUE="ddr3_sdram"/>
6162         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_mig_7series_0_0"/>
6163         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
6164         <PARAMETER NAME="EDK_SPECIAL" VALUE="MEMORY_CTRL"/>
6165         <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
6166         <PARAMETER NAME="C_HIGHADDR" VALUE="0xBFFFFFFF"/>
6167       </PARAMETERS>
6168       <PORTS>
6169         <PORT DIR="I" NAME="sys_rst" SIGIS="rst" SIGNAME="External_Ports_reset">
6170           <CONNECTIONS>
6171             <CONNECTION INSTANCE="External_Ports" PORT="reset"/>
6172           </CONNECTIONS>
6173         </PORT>
6174         <PORT DIR="IO" LEFT="63" NAME="ddr3_dq" RIGHT="0" SIGIS="undef"/>
6175         <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_p" RIGHT="0" SIGIS="undef"/>
6176         <PORT DIR="IO" LEFT="7" NAME="ddr3_dqs_n" RIGHT="0" SIGIS="undef"/>
6177         <PORT DIR="O" LEFT="13" NAME="ddr3_addr" RIGHT="0" SIGIS="undef"/>
6178         <PORT DIR="O" LEFT="2" NAME="ddr3_ba" RIGHT="0" SIGIS="undef"/>
6179         <PORT DIR="O" NAME="ddr3_ras_n" SIGIS="undef"/>
6180         <PORT DIR="O" NAME="ddr3_cas_n" SIGIS="undef"/>
6181         <PORT DIR="O" NAME="ddr3_we_n" SIGIS="undef"/>
6182         <PORT DIR="O" NAME="ddr3_reset_n" SIGIS="undef"/>
6183         <PORT DIR="O" LEFT="0" NAME="ddr3_ck_p" RIGHT="0" SIGIS="undef"/>
6184         <PORT DIR="O" LEFT="0" NAME="ddr3_ck_n" RIGHT="0" SIGIS="undef"/>
6185         <PORT DIR="O" LEFT="0" NAME="ddr3_cke" RIGHT="0" SIGIS="undef"/>
6186         <PORT DIR="O" LEFT="0" NAME="ddr3_cs_n" RIGHT="0" SIGIS="undef"/>
6187         <PORT DIR="O" LEFT="7" NAME="ddr3_dm" RIGHT="0" SIGIS="undef"/>
6188         <PORT DIR="O" LEFT="0" NAME="ddr3_odt" RIGHT="0" SIGIS="undef"/>
6189         <PORT DIR="O" NAME="ui_clk_sync_rst" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
6190           <CONNECTIONS>
6191             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="ext_reset_in"/>
6192           </CONNECTIONS>
6193         </PORT>
6194         <PORT CLKFREQUENCY="100000000" DIR="O" NAME="ui_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
6195           <CONNECTIONS>
6196             <CONNECTION INSTANCE="microblaze_0" PORT="Clk"/>
6197             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="LMB_Clk"/>
6198             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Clk"/>
6199             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="LMB_Clk"/>
6200             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Clk"/>
6201             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="slowest_sync_clk"/>
6202             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
6203             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
6204             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aclk"/>
6205             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
6206             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aclk"/>
6207             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ACLK"/>
6208             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ACLK"/>
6209             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ACLK"/>
6210             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ACLK"/>
6211             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ACLK"/>
6212             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ACLK"/>
6213             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ACLK"/>
6214             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ACLK"/>
6215             <CONNECTION INSTANCE="axi_mem_intercon" PORT="ACLK"/>
6216             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ACLK"/>
6217             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ACLK"/>
6218           </CONNECTIONS>
6219         </PORT>
6220         <PORT DIR="I" LEFT="0" NAME="s_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
6221           <CONNECTIONS>
6222             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awid"/>
6223           </CONNECTIONS>
6224         </PORT>
6225         <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
6226           <CONNECTIONS>
6227             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awaddr"/>
6228           </CONNECTIONS>
6229         </PORT>
6230         <PORT DIR="I" LEFT="7" NAME="s_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
6231           <CONNECTIONS>
6232             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlen"/>
6233           </CONNECTIONS>
6234         </PORT>
6235         <PORT DIR="I" LEFT="2" NAME="s_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
6236           <CONNECTIONS>
6237             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awsize"/>
6238           </CONNECTIONS>
6239         </PORT>
6240         <PORT DIR="I" LEFT="1" NAME="s_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
6241           <CONNECTIONS>
6242             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awburst"/>
6243           </CONNECTIONS>
6244         </PORT>
6245         <PORT DIR="I" NAME="s_axi_awlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
6246           <CONNECTIONS>
6247             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlock"/>
6248           </CONNECTIONS>
6249         </PORT>
6250         <PORT DIR="I" LEFT="3" NAME="s_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
6251           <CONNECTIONS>
6252             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awcache"/>
6253           </CONNECTIONS>
6254         </PORT>
6255         <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
6256           <CONNECTIONS>
6257             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awprot"/>
6258           </CONNECTIONS>
6259         </PORT>
6260         <PORT DIR="I" LEFT="3" NAME="s_axi_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
6261           <CONNECTIONS>
6262             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awqos"/>
6263           </CONNECTIONS>
6264         </PORT>
6265         <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
6266           <CONNECTIONS>
6267             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awvalid"/>
6268           </CONNECTIONS>
6269         </PORT>
6270         <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
6271           <CONNECTIONS>
6272             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awready"/>
6273           </CONNECTIONS>
6274         </PORT>
6275         <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
6276           <CONNECTIONS>
6277             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wdata"/>
6278           </CONNECTIONS>
6279         </PORT>
6280         <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
6281           <CONNECTIONS>
6282             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wstrb"/>
6283           </CONNECTIONS>
6284         </PORT>
6285         <PORT DIR="I" NAME="s_axi_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
6286           <CONNECTIONS>
6287             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wlast"/>
6288           </CONNECTIONS>
6289         </PORT>
6290         <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
6291           <CONNECTIONS>
6292             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wvalid"/>
6293           </CONNECTIONS>
6294         </PORT>
6295         <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
6296           <CONNECTIONS>
6297             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wready"/>
6298           </CONNECTIONS>
6299         </PORT>
6300         <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
6301           <CONNECTIONS>
6302             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bready"/>
6303           </CONNECTIONS>
6304         </PORT>
6305         <PORT DIR="O" LEFT="0" NAME="s_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
6306           <CONNECTIONS>
6307             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bid"/>
6308           </CONNECTIONS>
6309         </PORT>
6310         <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
6311           <CONNECTIONS>
6312             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bresp"/>
6313           </CONNECTIONS>
6314         </PORT>
6315         <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
6316           <CONNECTIONS>
6317             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bvalid"/>
6318           </CONNECTIONS>
6319         </PORT>
6320         <PORT DIR="I" LEFT="0" NAME="s_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
6321           <CONNECTIONS>
6322             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arid"/>
6323           </CONNECTIONS>
6324         </PORT>
6325         <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
6326           <CONNECTIONS>
6327             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_araddr"/>
6328           </CONNECTIONS>
6329         </PORT>
6330         <PORT DIR="I" LEFT="7" NAME="s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
6331           <CONNECTIONS>
6332             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlen"/>
6333           </CONNECTIONS>
6334         </PORT>
6335         <PORT DIR="I" LEFT="2" NAME="s_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
6336           <CONNECTIONS>
6337             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arsize"/>
6338           </CONNECTIONS>
6339         </PORT>
6340         <PORT DIR="I" LEFT="1" NAME="s_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
6341           <CONNECTIONS>
6342             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arburst"/>
6343           </CONNECTIONS>
6344         </PORT>
6345         <PORT DIR="I" NAME="s_axi_arlock" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
6346           <CONNECTIONS>
6347             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlock"/>
6348           </CONNECTIONS>
6349         </PORT>
6350         <PORT DIR="I" LEFT="3" NAME="s_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
6351           <CONNECTIONS>
6352             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arcache"/>
6353           </CONNECTIONS>
6354         </PORT>
6355         <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
6356           <CONNECTIONS>
6357             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arprot"/>
6358           </CONNECTIONS>
6359         </PORT>
6360         <PORT DIR="I" LEFT="3" NAME="s_axi_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
6361           <CONNECTIONS>
6362             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arqos"/>
6363           </CONNECTIONS>
6364         </PORT>
6365         <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
6366           <CONNECTIONS>
6367             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arvalid"/>
6368           </CONNECTIONS>
6369         </PORT>
6370         <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
6371           <CONNECTIONS>
6372             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arready"/>
6373           </CONNECTIONS>
6374         </PORT>
6375         <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
6376           <CONNECTIONS>
6377             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rready"/>
6378           </CONNECTIONS>
6379         </PORT>
6380         <PORT DIR="O" LEFT="0" NAME="s_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
6381           <CONNECTIONS>
6382             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rid"/>
6383           </CONNECTIONS>
6384         </PORT>
6385         <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
6386           <CONNECTIONS>
6387             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rdata"/>
6388           </CONNECTIONS>
6389         </PORT>
6390         <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
6391           <CONNECTIONS>
6392             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rresp"/>
6393           </CONNECTIONS>
6394         </PORT>
6395         <PORT DIR="O" NAME="s_axi_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
6396           <CONNECTIONS>
6397             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rlast"/>
6398           </CONNECTIONS>
6399         </PORT>
6400         <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
6401           <CONNECTIONS>
6402             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rvalid"/>
6403           </CONNECTIONS>
6404         </PORT>
6405         <PORT DIR="O" NAME="mmcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
6406           <CONNECTIONS>
6407             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="dcm_locked"/>
6408           </CONNECTIONS>
6409         </PORT>
6410         <PORT DIR="I" NAME="sys_clk_p" SIGIS="undef"/>
6411         <PORT DIR="I" NAME="sys_clk_n" SIGIS="undef"/>
6412         <PORT DIR="O" NAME="init_calib_complete" SIGIS="undef"/>
6413         <PORT DIR="I" NAME="aresetn" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
6414           <CONNECTIONS>
6415             <CONNECTION INSTANCE="rst_clk_wiz_1_100M" PORT="peripheral_aresetn"/>
6416           </CONNECTIONS>
6417         </PORT>
6418       </PORTS>
6419       <BUSINTERFACES>
6420         <BUSINTERFACE BUSNAME="mig_7series_0_DDR3" NAME="DDR3" TYPE="INITIATOR">
6421           <PORTMAPS>
6422             <PORTMAP PHYSICAL="ddr3_dq"/>
6423             <PORTMAP PHYSICAL="ddr3_dqs_p"/>
6424             <PORTMAP PHYSICAL="ddr3_dqs_n"/>
6425             <PORTMAP PHYSICAL="ddr3_addr"/>
6426             <PORTMAP PHYSICAL="ddr3_ba"/>
6427             <PORTMAP PHYSICAL="ddr3_ras_n"/>
6428             <PORTMAP PHYSICAL="ddr3_cas_n"/>
6429             <PORTMAP PHYSICAL="ddr3_we_n"/>
6430             <PORTMAP PHYSICAL="ddr3_reset_n"/>
6431             <PORTMAP PHYSICAL="ddr3_ck_p"/>
6432             <PORTMAP PHYSICAL="ddr3_ck_n"/>
6433             <PORTMAP PHYSICAL="ddr3_cke"/>
6434             <PORTMAP PHYSICAL="ddr3_cs_n"/>
6435             <PORTMAP PHYSICAL="ddr3_dm"/>
6436             <PORTMAP PHYSICAL="ddr3_odt"/>
6437           </PORTMAPS>
6438         </BUSINTERFACE>
6439         <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" NAME="S_AXI" TYPE="SLAVE">
6440           <PORTMAPS>
6441             <PORTMAP PHYSICAL="s_axi_awid"/>
6442             <PORTMAP PHYSICAL="s_axi_awaddr"/>
6443             <PORTMAP PHYSICAL="s_axi_awlen"/>
6444             <PORTMAP PHYSICAL="s_axi_awsize"/>
6445             <PORTMAP PHYSICAL="s_axi_awburst"/>
6446             <PORTMAP PHYSICAL="s_axi_awlock"/>
6447             <PORTMAP PHYSICAL="s_axi_awcache"/>
6448             <PORTMAP PHYSICAL="s_axi_awprot"/>
6449             <PORTMAP PHYSICAL="s_axi_awqos"/>
6450             <PORTMAP PHYSICAL="s_axi_awvalid"/>
6451             <PORTMAP PHYSICAL="s_axi_awready"/>
6452             <PORTMAP PHYSICAL="s_axi_wdata"/>
6453             <PORTMAP PHYSICAL="s_axi_wstrb"/>
6454             <PORTMAP PHYSICAL="s_axi_wlast"/>
6455             <PORTMAP PHYSICAL="s_axi_wvalid"/>
6456             <PORTMAP PHYSICAL="s_axi_wready"/>
6457             <PORTMAP PHYSICAL="s_axi_bready"/>
6458             <PORTMAP PHYSICAL="s_axi_bid"/>
6459             <PORTMAP PHYSICAL="s_axi_bresp"/>
6460             <PORTMAP PHYSICAL="s_axi_bvalid"/>
6461             <PORTMAP PHYSICAL="s_axi_arid"/>
6462             <PORTMAP PHYSICAL="s_axi_araddr"/>
6463             <PORTMAP PHYSICAL="s_axi_arlen"/>
6464             <PORTMAP PHYSICAL="s_axi_arsize"/>
6465             <PORTMAP PHYSICAL="s_axi_arburst"/>
6466             <PORTMAP PHYSICAL="s_axi_arlock"/>
6467             <PORTMAP PHYSICAL="s_axi_arcache"/>
6468             <PORTMAP PHYSICAL="s_axi_arprot"/>
6469             <PORTMAP PHYSICAL="s_axi_arqos"/>
6470             <PORTMAP PHYSICAL="s_axi_arvalid"/>
6471             <PORTMAP PHYSICAL="s_axi_arready"/>
6472             <PORTMAP PHYSICAL="s_axi_rready"/>
6473             <PORTMAP PHYSICAL="s_axi_rid"/>
6474             <PORTMAP PHYSICAL="s_axi_rdata"/>
6475             <PORTMAP PHYSICAL="s_axi_rresp"/>
6476             <PORTMAP PHYSICAL="s_axi_rlast"/>
6477             <PORTMAP PHYSICAL="s_axi_rvalid"/>
6478           </PORTMAPS>
6479         </BUSINTERFACE>
6480         <BUSINTERFACE BUSNAME="External_Interface_sys_diff_clock" NAME="SYS_CLK" TYPE="TARGET">
6481           <PORTMAPS>
6482             <PORTMAP PHYSICAL="sys_clk_p"/>
6483             <PORTMAP PHYSICAL="sys_clk_n"/>
6484           </PORTMAPS>
6485         </BUSINTERFACE>
6486       </BUSINTERFACES>
6487     </MODULE>
6488     <MODULE FULLNAME="/rst_clk_wiz_1_100M" HWVERSION="5.0" INSTANCE="rst_clk_wiz_1_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
6489       <DOCUMENTS>
6490         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
6491       </DOCUMENTS>
6492       <PARAMETERS>
6493         <PARAMETER NAME="C_FAMILY" VALUE="kintex7"/>
6494         <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
6495         <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
6496         <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
6497         <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
6498         <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
6499         <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
6500         <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
6501         <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
6502         <PARAMETER NAME="Component_Name" VALUE="base_microblaze_design_rst_clk_wiz_1_100M_0"/>
6503         <PARAMETER NAME="USE_BOARD_FLOW" VALUE="true"/>
6504         <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
6505         <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
6506       </PARAMETERS>
6507       <PORTS>
6508         <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="mig_7series_0_ui_clk">
6509           <CONNECTIONS>
6510             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk"/>
6511           </CONNECTIONS>
6512         </PORT>
6513         <PORT DIR="I" NAME="ext_reset_in" SIGIS="rst" SIGNAME="mig_7series_0_ui_clk_sync_rst">
6514           <CONNECTIONS>
6515             <CONNECTION INSTANCE="mig_7series_0" PORT="ui_clk_sync_rst"/>
6516           </CONNECTIONS>
6517         </PORT>
6518         <PORT DIR="I" NAME="aux_reset_in" SIGIS="rst"/>
6519         <PORT DIR="I" NAME="mb_debug_sys_rst" SIGIS="rst" SIGNAME="mdm_1_Debug_SYS_Rst">
6520           <CONNECTIONS>
6521             <CONNECTION INSTANCE="mdm_1" PORT="Debug_SYS_Rst"/>
6522           </CONNECTIONS>
6523         </PORT>
6524         <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="mig_7series_0_mmcm_locked">
6525           <CONNECTIONS>
6526             <CONNECTION INSTANCE="mig_7series_0" PORT="mmcm_locked"/>
6527           </CONNECTIONS>
6528         </PORT>
6529         <PORT DIR="O" NAME="mb_reset" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_mb_reset">
6530           <CONNECTIONS>
6531             <CONNECTION INSTANCE="microblaze_0" PORT="Reset"/>
6532           </CONNECTIONS>
6533         </PORT>
6534         <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_bus_struct_reset">
6535           <CONNECTIONS>
6536             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_v10" PORT="SYS_Rst"/>
6537             <CONNECTION INSTANCE="microblaze_0_local_memory_dlmb_bram_if_cntlr" PORT="LMB_Rst"/>
6538             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_v10" PORT="SYS_Rst"/>
6539             <CONNECTION INSTANCE="microblaze_0_local_memory_ilmb_bram_if_cntlr" PORT="LMB_Rst"/>
6540           </CONNECTIONS>
6541         </PORT>
6542         <PORT DIR="O" LEFT="0" NAME="peripheral_reset" RIGHT="0" SIGIS="rst"/>
6543         <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_interconnect_aresetn">
6544           <CONNECTIONS>
6545             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="ARESETN"/>
6546             <CONNECTION INSTANCE="axi_mem_intercon" PORT="ARESETN"/>
6547           </CONNECTIONS>
6548         </PORT>
6549         <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_clk_wiz_1_100M_peripheral_aresetn">
6550           <CONNECTIONS>
6551             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
6552             <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
6553             <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aresetn"/>
6554             <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
6555             <CONNECTION INSTANCE="axi_ethernetlite_0" PORT="s_axi_aresetn"/>
6556             <CONNECTION INSTANCE="mig_7series_0" PORT="aresetn"/>
6557             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="S00_ARESETN"/>
6558             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M00_ARESETN"/>
6559             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M01_ARESETN"/>
6560             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M02_ARESETN"/>
6561             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M03_ARESETN"/>
6562             <CONNECTION INSTANCE="microblaze_0_axi_periph" PORT="M04_ARESETN"/>
6563             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ARESETN"/>
6564             <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ARESETN"/>
6565             <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ARESETN"/>
6566           </CONNECTIONS>
6567         </PORT>
6568       </PORTS>
6569       <BUSINTERFACES/>
6570     </MODULE>
6571   </MODULES>
6572
6573   <REPOSITORIES/>
6574
6575 </EDKSYSTEM>