git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp

   1 #Please do not modify this file by hand\r
   2 XmpVersion: 13.1\r
   3 VerMgmt: 13.1\r
   4 IntStyle: default\r
   5 MHS File: system.mhs\r
   6 Architecture: spartan6\r
   7 Device: xc6slx45t\r
   8 Package: fgg484\r
   9 SpeedGrade: -3\r
  10 UserCmd1: \r
  11 UserCmd1Type: 0\r
  12 UserCmd2: \r
  13 UserCmd2Type: 0\r
  14 GenSimTB: 0\r
  15 SdkExportBmmBit: 1\r
  16 SdkExportDir: SDK/SDK_Export\r
  17 InsertNoPads: 0\r
  18 WarnForEAArch: 1\r
  19 HdlLang: VHDL\r
  20 SimModel: BEHAVIORAL\r
  21 UcfFile: data/system.ucf\r
  22 EnableParTimingError: 1\r
  23 ShowLicenseDialog: 1\r
  24 ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR\r
  25 ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR\r
  26 ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR\r
  27 ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR\r
  28 ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR\r
  29 ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR\r
  30 DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR\r
  31 DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR\r
  32 DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR\r
  33 DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR\r
  34 DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR\r
  35 DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR\r
  36 Processor: microblaze_0\r
  37 ElfImp: \r
  38 ElfSim: \r