2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * This file implements functions to access and manipulate the PIC32 hardware
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30 * without reliance on third party library functions that may be liable to
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34 /* FreeRTOS includes. */
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35 #include "FreeRTOS.h"
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37 /* Demo includes. */
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38 #include "ConfigPerformance.h"
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40 /* Hardware specific definitions. */
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41 #define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )
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42 #define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )
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43 #define hwMAX_FLASH_SPEED ( 30000000UL )
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44 #define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )
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45 #define hwUNLOCK_KEY_0 ( 0xAA996655UL )
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46 #define hwUNLOCK_KEY_1 ( 0x556699AAUL )
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47 #define hwLOCK_KEY ( 0x33333333UL )
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48 #define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )
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49 #define hwBEV_BIT ( 0x00400000 )
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50 #define hwEXL_BIT ( 0x00000002 )
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51 #define hwIV_BIT ( 0x00800000 )
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54 * Set the flash wait states for the configured CPU clock speed.
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56 static void prvConfigureWaitStates( void );
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59 * Use a divisor of 2 on the peripheral bus.
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61 static void prvConfigurePeripheralBus( void );
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66 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );
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68 /*-----------------------------------------------------------*/
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70 void vHardwareConfigurePerformance( void )
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72 unsigned long ulStatus;
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74 unsigned long ulCacheStatus;
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77 /* Disable interrupts - note taskDISABLE_INTERRUPTS() cannot be used here as
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78 FreeRTOS does not globally disable interrupt. */
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79 ulStatus = _CP0_GET_STATUS();
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80 _CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );
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82 prvConfigurePeripheralBus();
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83 prvConfigureWaitStates();
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85 /* Disable DRM wait state. */
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86 BMXCONCLR = _BMXCON_BMXWSDRM_MASK;
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90 /* Read the current CHECON value. */
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91 ulCacheStatus = CHECON;
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93 /* All the PREFEN bits are being set, so no need to clear first. */
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94 ulCacheStatus |= hwCHECON_PREFEN_BITS;
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96 /* Write back the new value. */
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97 CHECON = ulCacheStatus;
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102 /* Reset the status register back to its original value so the original
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103 interrupt enable status is retored. */
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104 _CP0_SET_STATUS( ulStatus );
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106 /*-----------------------------------------------------------*/
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108 void vHardwareUseMultiVectoredInterrupts( void )
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110 unsigned long ulStatus, ulCause;
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111 extern unsigned long _ebase_address[];
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113 /* Get current status. */
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114 ulStatus = _CP0_GET_STATUS();
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116 /* Disable interrupts. */
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117 ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;
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120 ulStatus |= hwBEV_BIT;
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122 /* Write status back. */
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123 _CP0_SET_STATUS( ulStatus );
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126 _CP0_SET_EBASE( ( unsigned long ) _ebase_address );
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128 /* Space vectors by 0x20 bytes. */
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129 _CP0_XCH_INTCTL( 0x20 );
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131 /* Set the IV bit in the CAUSE register. */
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132 ulCause = _CP0_GET_CAUSE();
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133 ulCause |= hwIV_BIT;
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134 _CP0_SET_CAUSE( ulCause );
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136 /* Clear BEV and EXL bits in status. */
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137 ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );
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138 _CP0_SET_STATUS( ulStatus );
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140 /* Set MVEC bit. */
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141 INTCONbits.MVEC = 1;
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143 /* Finally enable interrupts again. */
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144 ulStatus |= hwGLOBAL_INTERRUPT_BIT;
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145 _CP0_SET_STATUS( ulStatus );
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147 /*-----------------------------------------------------------*/
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149 static void prvConfigurePeripheralBus( void )
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151 unsigned long ulDMAStatus;
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152 __OSCCONbits_t xOSCCONBits;
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154 /* Unlock after suspending. */
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155 ulDMAStatus = DMACONbits.SUSPEND;
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156 if( ulDMAStatus == 0 )
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158 DMACONSET = _DMACON_SUSPEND_MASK;
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160 /* Wait until actually suspended. */
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161 while( DMACONbits.SUSPEND == 0 );
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165 SYSKEY = hwUNLOCK_KEY_0;
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166 SYSKEY = hwUNLOCK_KEY_1;
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168 /* Read to start in sync. */
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169 xOSCCONBits.w = OSCCON;
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170 xOSCCONBits.PBDIV = 0;
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171 xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;
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174 OSCCON = xOSCCONBits.w;
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176 /* Ensure the write occurred. */
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177 xOSCCONBits.w = OSCCON;
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180 SYSKEY = hwLOCK_KEY;
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182 /* Resume DMA activity. */
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183 if( ulDMAStatus == 0 )
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185 DMACONCLR=_DMACON_SUSPEND_MASK;
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188 /*-----------------------------------------------------------*/
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190 static void prvConfigureWaitStates( void )
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192 unsigned long ulSystemClock = configCPU_CLOCK_HZ - 1;
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193 unsigned long ulWaitStates, ulCHECONVal;
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195 /* 1 wait state for every hwMAX_FLASH_SPEED MHz. */
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198 while( ulSystemClock > hwMAX_FLASH_SPEED )
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201 ulSystemClock -= hwMAX_FLASH_SPEED;
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204 /* Obtain current CHECON value. */
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205 ulCHECONVal = CHECON;
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207 /* Clear the wait state bits, then set the calculated wait state bits. */
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208 ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;
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209 ulCHECONVal |= ulWaitStates;
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211 /* Write back the new value. */
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212 CHECON = ulWaitStates;
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214 /*-----------------------------------------------------------*/
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216 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )
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218 unsigned long ulValue;
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220 __asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );
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221 ulValue = ( ulValue & ~0x07) | 0x03;
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222 __asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );
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