2 FreeRTOS V7.4.1 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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76 * This file implements functions to access and manipulate the PIC32 hardware
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77 * without reliance on third party library functions that may be liable to
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81 /* FreeRTOS includes. */
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82 #include "FreeRTOS.h"
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84 /* Demo includes. */
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85 #include "ConfigPerformance.h"
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87 /* Hardware specific definitions. */
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88 #define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )
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89 #define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )
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90 #define hwMAX_FLASH_SPEED ( 30000000UL )
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91 #define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )
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92 #define hwUNLOCK_KEY_0 ( 0xAA996655UL )
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93 #define hwUNLOCK_KEY_1 ( 0x556699AAUL )
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94 #define hwLOCK_KEY ( 0x33333333UL )
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95 #define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )
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96 #define hwBEV_BIT ( 0x00400000 )
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97 #define hwEXL_BIT ( 0x00000002 )
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98 #define hwIV_BIT ( 0x00800000 )
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101 * Set the flash wait states for the configured CPU clock speed.
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103 static void prvConfigureWaitStates( void );
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106 * Use a divisor of 2 on the peripheral bus.
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108 static void prvConfigurePeripheralBus( void );
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111 * Enable the cache.
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113 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );
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115 /*-----------------------------------------------------------*/
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117 void vHardwareConfigurePerformance( void )
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119 unsigned long ulStatus;
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121 unsigned long ulCacheStatus;
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124 /* Disable interrupts - not taskDISABLE_INTERRUPTS() cannot be used here as
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125 FreeRTOS does not globally disable interrupt. */
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126 ulStatus = _CP0_GET_STATUS();
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127 _CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );
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129 prvConfigurePeripheralBus();
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130 prvConfigureWaitStates();
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132 /* Disable DRM wait state. */
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133 BMXCONCLR = _BMXCON_BMXWSDRM_MASK;
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137 /* Read the current CHECON value. */
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138 ulCacheStatus = CHECON;
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140 /* All the PREFEN bits are being set, so no need to clear first. */
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141 ulCacheStatus |= hwCHECON_PREFEN_BITS;
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143 /* Write back the new value. */
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144 CHECON = ulCacheStatus;
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149 /* Reset the status register back to its original value so the original
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150 interrupt enable status is retored. */
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151 _CP0_SET_STATUS( ulStatus );
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153 /*-----------------------------------------------------------*/
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155 void vHardwareUseMultiVectoredInterrupts( void )
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157 unsigned long ulStatus, ulCause;
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158 extern unsigned long _ebase_address[];
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160 /* Get current status. */
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161 ulStatus = _CP0_GET_STATUS();
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163 /* Disable interrupts. */
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164 ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;
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167 ulStatus |= hwBEV_BIT;
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169 /* Write status back. */
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170 _CP0_SET_STATUS( ulStatus );
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173 _CP0_SET_EBASE( ( unsigned long ) _ebase_address );
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175 /* Space vectors by 0x20 bytes. */
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176 _CP0_XCH_INTCTL( 0x20 );
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178 /* Set the IV bit in the CAUSE register. */
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179 ulCause = _CP0_GET_CAUSE();
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180 ulCause |= hwIV_BIT;
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181 _CP0_SET_CAUSE( ulCause );
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183 /* Clear BEV and EXL bits in status. */
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184 ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );
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185 _CP0_SET_STATUS( ulStatus );
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187 /* Set MVEC bit. */
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188 INTCONbits.MVEC = 1;
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190 /* Finally enable interrupts again. */
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191 ulStatus |= hwGLOBAL_INTERRUPT_BIT;
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192 _CP0_SET_STATUS( ulStatus );
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194 /*-----------------------------------------------------------*/
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196 static void prvConfigurePeripheralBus( void )
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198 unsigned long ulDMAStatus;
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199 __OSCCONbits_t xOSCCONBits;
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201 /* Unlock after suspending. */
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202 ulDMAStatus = DMACONbits.SUSPEND;
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203 if( ulDMAStatus == 0 )
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205 DMACONSET = _DMACON_SUSPEND_MASK;
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207 /* Wait until actually suspended. */
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208 while( DMACONbits.SUSPEND == 0 );
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212 SYSKEY = hwUNLOCK_KEY_0;
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213 SYSKEY = hwUNLOCK_KEY_1;
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215 /* Read to start in sync. */
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216 xOSCCONBits.w = OSCCON;
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217 xOSCCONBits.PBDIV = 0;
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218 xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;
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221 OSCCON = xOSCCONBits.w;
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223 /* Ensure the write occurred. */
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224 xOSCCONBits.w = OSCCON;
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227 SYSKEY = hwLOCK_KEY;
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229 /* Resume DMA activity. */
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230 if( ulDMAStatus == 0 )
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232 DMACONCLR=_DMACON_SUSPEND_MASK;
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235 /*-----------------------------------------------------------*/
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237 static void prvConfigureWaitStates( void )
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239 unsigned long ulInterruptStatus, ulSystemClock = configCPU_CLOCK_HZ - 1;
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240 unsigned long ulWaitStates, ulCHECONVal;
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242 /* 1 wait state for every hwMAX_FLASH_SPEED MHz. */
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245 while( ulSystemClock > hwMAX_FLASH_SPEED )
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248 ulSystemClock -= hwMAX_FLASH_SPEED;
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251 /* Obtain current CHECON value. */
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252 ulCHECONVal = CHECON;
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254 /* Clear the wait state bits, then set the calculated wait state bits. */
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255 ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;
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256 ulCHECONVal |= ulWaitStates;
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258 /* Write back the new value. */
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259 CHECON = ulWaitStates;
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261 /*-----------------------------------------------------------*/
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263 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )
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265 unsigned long ulValue;
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267 __asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );
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268 ulValue = ( ulValue & ~0x07) | 0x03;
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269 __asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );
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