2 FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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66 * This file implements functions to access and manipulate the PIC32 hardware
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67 * without reliance on third party library functions that may be liable to
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71 /* FreeRTOS includes. */
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72 #include "FreeRTOS.h"
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74 /* Demo includes. */
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75 #include "ConfigPerformance.h"
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77 /* Hardware specific definitions. */
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78 #define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )
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79 #define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )
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80 #define hwMAX_FLASH_SPEED ( 30000000UL )
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81 #define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )
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82 #define hwUNLOCK_KEY_0 ( 0xAA996655UL )
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83 #define hwUNLOCK_KEY_1 ( 0x556699AAUL )
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84 #define hwLOCK_KEY ( 0x33333333UL )
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85 #define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )
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86 #define hwBEV_BIT ( 0x00400000 )
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87 #define hwEXL_BIT ( 0x00000002 )
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88 #define hwIV_BIT ( 0x00800000 )
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91 * Set the flash wait states for the configured CPU clock speed.
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93 static void prvConfigureWaitStates( void );
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96 * Use a divisor of 2 on the peripheral bus.
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98 static void prvConfigurePeripheralBus( void );
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101 * Enable the cache.
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103 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );
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105 /*-----------------------------------------------------------*/
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107 void vHardwareConfigurePerformance( void )
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109 unsigned long ulStatus;
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111 unsigned long ulCacheStatus;
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114 /* Disable interrupts - not taskDISABLE_INTERRUPTS() cannot be used here as
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115 FreeRTOS does not globally disable interrupt. */
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116 ulStatus = _CP0_GET_STATUS();
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117 _CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );
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119 prvConfigurePeripheralBus();
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120 prvConfigureWaitStates();
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122 /* Disable DRM wait state. */
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123 BMXCONCLR = _BMXCON_BMXWSDRM_MASK;
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127 /* Read the current CHECON value. */
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128 ulCacheStatus = CHECON;
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130 /* All the PREFEN bits are being set, so no need to clear first. */
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131 ulCacheStatus |= hwCHECON_PREFEN_BITS;
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133 /* Write back the new value. */
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134 CHECON = ulCacheStatus;
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139 /* Reset the status register back to its original value so the original
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140 interrupt enable status is retored. */
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141 _CP0_SET_STATUS( ulStatus );
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143 /*-----------------------------------------------------------*/
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145 void vHardwareUseMultiVectoredInterrupts( void )
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147 unsigned long ulStatus, ulCause;
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148 extern unsigned long _ebase_address[];
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150 /* Get current status. */
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151 ulStatus = _CP0_GET_STATUS();
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153 /* Disable interrupts. */
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154 ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;
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157 ulStatus |= hwBEV_BIT;
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159 /* Write status back. */
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160 _CP0_SET_STATUS( ulStatus );
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163 _CP0_SET_EBASE( ( unsigned long ) _ebase_address );
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165 /* Space vectors by 0x20 bytes. */
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166 _CP0_XCH_INTCTL( 0x20 );
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168 /* Set the IV bit in the CAUSE register. */
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169 ulCause = _CP0_GET_CAUSE();
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170 ulCause |= hwIV_BIT;
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171 _CP0_SET_CAUSE( ulCause );
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173 /* Clear BEV and EXL bits in status. */
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174 ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );
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175 _CP0_SET_STATUS( ulStatus );
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177 /* Set MVEC bit. */
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178 INTCONbits.MVEC = 1;
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180 /* Finally enable interrupts again. */
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181 ulStatus |= hwGLOBAL_INTERRUPT_BIT;
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182 _CP0_SET_STATUS( ulStatus );
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184 /*-----------------------------------------------------------*/
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186 static void prvConfigurePeripheralBus( void )
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188 unsigned long ulDMAStatus;
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189 __OSCCONbits_t xOSCCONBits;
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191 /* Unlock after suspending. */
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192 ulDMAStatus = DMACONbits.SUSPEND;
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193 if( ulDMAStatus == 0 )
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195 DMACONSET = _DMACON_SUSPEND_MASK;
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197 /* Wait until actually suspended. */
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198 while( DMACONbits.SUSPEND == 0 );
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202 SYSKEY = hwUNLOCK_KEY_0;
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203 SYSKEY = hwUNLOCK_KEY_1;
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205 /* Read to start in sync. */
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206 xOSCCONBits.w = OSCCON;
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207 xOSCCONBits.PBDIV = 0;
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208 xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;
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211 OSCCON = xOSCCONBits.w;
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213 /* Ensure the write occurred. */
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214 xOSCCONBits.w = OSCCON;
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217 SYSKEY = hwLOCK_KEY;
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219 /* Resume DMA activity. */
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220 if( ulDMAStatus == 0 )
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222 DMACONCLR=_DMACON_SUSPEND_MASK;
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225 /*-----------------------------------------------------------*/
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227 static void prvConfigureWaitStates( void )
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229 unsigned long ulInterruptStatus, ulSystemClock = configCPU_CLOCK_HZ - 1;
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230 unsigned long ulWaitStates, ulCHECONVal;
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232 /* 1 wait state for every hwMAX_FLASH_SPEED MHz. */
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235 while( ulSystemClock > hwMAX_FLASH_SPEED )
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238 ulSystemClock -= hwMAX_FLASH_SPEED;
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241 /* Obtain current CHECON value. */
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242 ulCHECONVal = CHECON;
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244 /* Clear the wait state bits, then set the calculated wait state bits. */
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245 ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;
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246 ulCHECONVal |= ulWaitStates;
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248 /* Write back the new value. */
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249 CHECON = ulWaitStates;
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251 /*-----------------------------------------------------------*/
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253 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )
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255 unsigned long ulValue;
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257 __asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );
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258 ulValue = ( ulValue & ~0x07) | 0x03;
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259 __asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );
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