1 /*******************************************************************/
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3 /* This file is automatically generated by linker script generator.*/
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5 /* Version: Xilinx EDK 11.1 EDK_L.29.1 */
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7 /* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
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9 /* Description : PowerPC440 Linker Script */
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11 /*******************************************************************/
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13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
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14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
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16 /* Define Memories in the system */
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20 DDR2_SDRAM_C_MEM_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x10000000
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21 SRAM_C_MEM0_BASEADDR : ORIGIN = 0xF8000000, LENGTH = 0x00100000
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22 xps_bram_if_cntlr_1 : ORIGIN = 0xFFFFE000, LENGTH = 0x00001F00
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25 /* Specify the default entry point to the program */
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30 /* Define the sections, and where they are mapped in memory */
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35 __vectors_start = .;
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38 } > SRAM_C_MEM0_BASEADDR
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43 *(.gnu.linkonce.t.*)
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44 } > SRAM_C_MEM0_BASEADDR
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48 } > SRAM_C_MEM0_BASEADDR
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52 } > SRAM_C_MEM0_BASEADDR
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58 *(.gnu.linkonce.r.*)
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60 } > SRAM_C_MEM0_BASEADDR
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63 __rodata1_start = .;
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67 } > SRAM_C_MEM0_BASEADDR
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73 *(.gnu.linkonce.s2.*)
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75 } > SRAM_C_MEM0_BASEADDR
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81 *(.gnu.linkonce.sb2.*)
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83 } > SRAM_C_MEM0_BASEADDR
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89 *(.gnu.linkonce.d.*)
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91 } > SRAM_C_MEM0_BASEADDR
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98 } > SRAM_C_MEM0_BASEADDR
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102 } > SRAM_C_MEM0_BASEADDR
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106 } > SRAM_C_MEM0_BASEADDR
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110 } > SRAM_C_MEM0_BASEADDR
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114 ___CTORS_LIST___ = .;
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115 KEEP (*crtbegin.o(.ctors))
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116 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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117 KEEP (*(SORT(.ctors.*)))
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120 ___CTORS_END___ = .;
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121 } > SRAM_C_MEM0_BASEADDR
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125 ___DTORS_LIST___ = .;
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126 KEEP (*crtbegin.o(.dtors))
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127 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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128 KEEP (*(SORT(.dtors.*)))
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131 ___DTORS_END___ = .;
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132 } > SRAM_C_MEM0_BASEADDR
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138 } > SRAM_C_MEM0_BASEADDR
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142 } > SRAM_C_MEM0_BASEADDR
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146 } > SRAM_C_MEM0_BASEADDR
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148 .gcc_except_table : {
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149 *(.gcc_except_table)
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150 } > SRAM_C_MEM0_BASEADDR
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156 *(.gnu.linkonce.s.*)
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158 } > SRAM_C_MEM0_BASEADDR
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164 *(.gnu.linkonce.sb.*)
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167 } > SRAM_C_MEM0_BASEADDR
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173 *(.gnu.linkonce.td.*)
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175 } > SRAM_C_MEM0_BASEADDR
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181 *(.gnu.linkonce.tb.*)
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183 } > SRAM_C_MEM0_BASEADDR
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189 *(.gnu.linkonce.b.*)
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193 } > SRAM_C_MEM0_BASEADDR
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195 .boot0 0xFFFFFF00 : {
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201 .boot 0xFFFFFFFC : {
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207 /* Generate Stack and Heap Sections */
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214 } > SRAM_C_MEM0_BASEADDR
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223 } > SRAM_C_MEM0_BASEADDR
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