git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/system.log

   1 No logfile was found.\r
   2 \r
   3 Xilinx Platform Studio (XPS)\r
   4 Xilinx EDK 11.2 Build EDK_LS3.47
   5 \r
   6 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
   7 \r
   8 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!
   9 \r
  10 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!
  11 \r
  12 Generating Block Diagram to Buffer
  13 \r
  14 Generated Block Diagram SVG
  15 \r
  16 At Local date and time: Mon Jun 29 21:01:23 2009
  17  make -f system.make program started...
  18 \r
  19 *********************************************\r
  20 Creating software libraries...\r
  21 *********************************************\r
  22 libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss\r
  23 libgen\r\r
  24 Xilinx EDK 11.2 Build EDK_LS3.47\r\r
  25 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
  26 \r\r
  27 Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
  28 __xps/ise/xmsgprops.lst system.mss \r\r
  29 \r\r
  30 Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
  31 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
  32 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
  33    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  34    m.mhs line 251 - deprecated core for architecture 'virtex5fx'!\r\r
  35 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
  36    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  37    m.mhs line 296 - deprecated core for architecture 'virtex5fx'!\r\r
  38 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
  39    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  40    m.mhs line 251 - deprecated core for architecture 'virtex5fx'!\r\r
  41 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
  42    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  43    m.mhs line 296 - deprecated core for architecture 'virtex5fx'!\r\r
  44 \r\r
  45 Checking platform configuration ...\r\r
  46 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
  47 C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m\r\r
  48 hs line 107 - 1 master(s) : 12 slave(s)\r\r
  49 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
  50 C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m\r\r
  51 hs line 288 - 1 master(s) : 1 slave(s)\r\r
  52 \r\r
  53 Checking port drivers...\r\r
  54 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
  55    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  56    m.mhs line 446 - floating connection!\r\r
  57 \r\r
  58 Performing Clock DRCs...\r\r
  59 \r\r
  60 Performing Reset DRCs...\r\r
  61 \r\r
  62 Overriding system level properties...\r\r
  63 \r\r
  64 Running system level update procedures...\r\r
  65 \r\r
  66 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
  67 \r\r
  68 Running system level DRCs...\r\r
  69 \r\r
  70 Performing System level DRCs on properties...\r\r
  71 \r\r
  72 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
  73 WARNING:EDK:494 -\r\r
  74    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth\r\r
  75    esis\ not found.\r\r
  76 WARNING:EDK:2530 - Timing and Resource utilization information not added\r\r
  77 WARNING:EDK:411 - pcie -\r\r
  78    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  79    m.mss line 77 - deprecated driver!\r\r
  80 WARNING:EDK:411 - emaclite -\r\r
  81    C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste\r\r
  82    m.mss line 83 - deprecated driver!\r\r
  83 INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
  84   - DDR2_SDRAM\r\r
  85   - DIP_Switches_8Bit\r\r
  86   - Ethernet_MAC\r\r
  87   - IIC_EEPROM\r\r
  88   - LEDs_8Bit\r\r
  89   - LEDs_Positions\r\r
  90   - PCIe_Bridge\r\r
  91   - Push_Buttons_5Bit\r\r
  92   - RS232_Uart_1\r\r
  93   - SRAM\r\r
  94   - SysACE_CompactFlash\r\r
  95   - xps_bram_if_cntlr_1\r\r
  96   - xps_intc_0\r\r
  97 \r\r
  98 -- Generating libraries for processor: ppc440_0 --\r\r
  99 \r\r
 100 \r\r
 101 Staging source files.\r\r
 102 Running DRCs.\r\r
 103 Running generate.\r\r
 104 Running post_generate.\r\r
 105 Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
 106 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
 107 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
 108 \r\r
 109 Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
 110 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
 111 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
 112 Compiling common\r
 113 powerpc-eabi-ar: creating ../../../lib/libxil.a
 114 \r
 115 Compiling lldma\r
 116 Compiling standalone\r
 117 Compiling gpio\r
 118 Compiling emaclite\r
 119 Compiling iic\r
 120 Compiling pci\r
 121 Compiling uartlite\r
 122 Compiling sysace\r
 123 Compiling intc\r
 124 Compiling cpu_ppc440\r
 125 Running execs_generate.\r\r
 126 powerpc-eabi-gcc -O0 /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
 127     -mcpu=440  -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
 128 -D GCC_PPC440 -mregnames  \r
 129 powerpc-eabi-size RTOSDemo/executable.elf \r
 130    text    data     bss     dec     hex filename\r
 131   53754     372   86524  140650   2256a RTOSDemo/executable.elf\r
 132 \r
 133 \r
 134 Done!
 135 \r
 136 Writing filter settings....
 137 \r
 138 Done writing filter settings to:
 139         C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 140 \r
 141 Done writing Tab View settings to:
 142         C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
 143 \r
 144 Xilinx Platform Studio (XPS)\r
 145 Xilinx EDK 11.2 Build EDK_LS3.47
 146 \r
 147 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 148 \r
 149 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 150 \r
 151 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 152 \r
 153 Generating Block Diagram to Buffer
 154 \r
 155 Generated Block Diagram SVG
 156 \r
 157 At Local date and time: Tue Jun 30 18:32:58 2009
 158  make -f system.make hwclean started...
 159 \r
 160 rm -f implementation/system.ngc\r
 161 rm -f platgen.log\r
 162 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
 163 rm -f implementation/system.bmm\r
 164 rm -f implementation/system.bit\r
 165 rm -f implementation/system.ncd\r
 166 rm -f implementation/system_bd.bmm \r
 167 rm -f implementation/system_map.ncd \r
 168 rm -f __xps/system_routed\r
 169 rm -rf implementation synthesis xst hdl\r
 170 rm -rf xst.srp system.srp\r
 171 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
 172 \r
 173 \r
 174 Done!
 175 \r
 176 At Local date and time: Tue Jun 30 18:33:07 2009
 177  make -f system.make netlistclean started...
 178 \r
 179 rm -f implementation/system.ngc\r
 180 rm -f platgen.log\r
 181 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
 182 rm -f implementation/system.bmm\r
 183 \r
 184 \r
 185 Done!
 186 \r
 187 At Local date and time: Tue Jun 30 18:33:13 2009
 188  make -f system.make bitsclean started...
 189 \r
 190 rm -f implementation/system.bit\r
 191 rm -f implementation/system.ncd\r
 192 rm -f implementation/system_bd.bmm \r
 193 rm -f implementation/system_map.ncd \r
 194 rm -f __xps/system_routed\r
 195 \r
 196 \r
 197 Done!
 198 \r
 199 At Local date and time: Tue Jun 30 18:33:24 2009
 200  make -f system.make libsclean started...
 201 \r
 202 rm -rf ppc440_0/\r
 203 rm -f libgen.log\r
 204 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
 205 \r
 206 \r
 207 Done!
 208 \r
 209 At Local date and time: Tue Jun 30 18:33:31 2009
 210  make -f system.make programclean started...
 211 \r
 212 rm -f RTOSDemo/executable.elf \r
 213 \r
 214 \r
 215 Done!
 216 \r
 217 At Local date and time: Tue Jun 30 18:33:37 2009
 218  make -f system.make swclean started...
 219 \r
 220 rm -rf ppc440_0/\r
 221 rm -f libgen.log\r
 222 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
 223 rm -f RTOSDemo/executable.elf \r
 224 \r
 225 \r
 226 Done!
 227 \r
 228 Writing filter settings....
 229 \r
 230 Done writing filter settings to:
 231         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 232 \r
 233 Done writing Tab View settings to:
 234         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
 235 \r
 236 Xilinx Platform Studio (XPS)\r
 237 Xilinx EDK 11.2 Build EDK_LS3.47
 238 \r
 239 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 240 \r
 241 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 242 \r
 243 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 244 \r
 245 Generating Block Diagram to Buffer
 246 \r
 247 Generated Block Diagram SVG
 248 \r
 249 At Local date and time: Tue Jun 30 20:53:14 2009
 250  make -f system.make program started...
 251 \r
 252 *********************************************\r
 253 Creating software libraries...\r
 254 *********************************************\r
 255 libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss\r
 256 libgen\r\r
 257 Xilinx EDK 11.2 Build EDK_LS3.47\r\r
 258 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 259 \r\r
 260 Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
 261 __xps/ise/xmsgprops.lst system.mss \r\r
 262 \r\r
 263 Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
 264 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 265 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 266    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 267    251 - deprecated core for architecture 'virtex5fx'!\r\r
 268 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 269    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 270    296 - deprecated core for architecture 'virtex5fx'!\r\r
 271 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 272    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 273    251 - deprecated core for architecture 'virtex5fx'!\r\r
 274 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 275    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 276    296 - deprecated core for architecture 'virtex5fx'!\r\r
 277 \r\r
 278 Checking platform configuration ...\r\r
 279 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 280 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 281 107 - 1 master(s) : 12 slave(s)\r\r
 282 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 283 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 284 288 - 1 master(s) : 1 slave(s)\r\r
 285 \r\r
 286 Checking port drivers...\r\r
 287 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
 288    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 289    446 - floating connection!\r\r
 290 \r\r
 291 Performing Clock DRCs...\r\r
 292 \r\r
 293 Performing Reset DRCs...\r\r
 294 \r\r
 295 Overriding system level properties...\r\r
 296 \r\r
 297 Running system level update procedures...\r\r
 298 \r\r
 299 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
 300 \r\r
 301 Running system level DRCs...\r\r
 302 \r\r
 303 Performing System level DRCs on properties...\r\r
 304 \r\r
 305 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
 306 WARNING:EDK:494 -\r\r
 307    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not\r\r
 308    found.\r\r
 309 WARNING:EDK:2530 - Timing and Resource utilization information not added\r\r
 310 WARNING:EDK:411 - pcie -\r\r
 311    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
 312    77 - deprecated driver!\r\r
 313 WARNING:EDK:411 - emaclite -\r\r
 314    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line\r\r
 315    83 - deprecated driver!\r\r
 316 INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
 317   - DDR2_SDRAM\r\r
 318   - DIP_Switches_8Bit\r\r
 319   - Ethernet_MAC\r\r
 320   - IIC_EEPROM\r\r
 321   - LEDs_8Bit\r\r
 322   - LEDs_Positions\r\r
 323   - PCIe_Bridge\r\r
 324   - Push_Buttons_5Bit\r\r
 325   - RS232_Uart_1\r\r
 326   - SRAM\r\r
 327   - SysACE_CompactFlash\r\r
 328   - xps_bram_if_cntlr_1\r\r
 329   - xps_intc_0\r\r
 330 \r\r
 331 -- Generating libraries for processor: ppc440_0 --\r\r
 332 \r\r
 333 \r\r
 334 Staging source files.\r\r
 335 Running DRCs.\r\r
 336 Running generate.\r\r
 337 Running post_generate.\r\r
 338 Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
 339 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
 340 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
 341 \r\r
 342 Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
 343 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"\r\r
 344 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
 345 Compiling common\r
 346 powerpc-eabi-ar: creating ../../../lib/libxil.a
 347 \r
 348 Compiling lldma\r
 349 Compiling standalone\r
 350 Compiling gpio\r
 351 Compiling emaclite\r
 352 Compiling iic\r
 353 Compiling pci\r
 354 Compiling uartlite\r
 355 Compiling sysace\r
 356 Compiling intc\r
 357 Compiling cpu_ppc440\r
 358 Running execs_generate.\r\r
 359 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
 360     -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
 361 -D GCC_PPC440 -mregnames  \r
 362 powerpc-eabi-size RTOSDemo/executable.elf \r
 363    text    data     bss     dec     hex filename\r
 364   53754     372   86524  140650   2256a RTOSDemo/executable.elf\r
 365 \r
 366 \r
 367 Done!
 368 \r
 369 Writing filter settings....
 370 \r
 371 Done writing filter settings to:
 372         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 373 \r
 374 Done writing Tab View settings to:
 375         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
 376 \r
 377 Xilinx Platform Studio (XPS)\r
 378 Xilinx EDK 11.2 Build EDK_LS3.47
 379 \r
 380 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 381 \r
 382 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 383 \r
 384 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 385 \r
 386 Generating Block Diagram to Buffer
 387 \r
 388 Generated Block Diagram SVG
 389 \r
 390 At Local date and time: Tue Jun 30 21:05:40 2009
 391  make -f system.make bits started...
 392 \r
 393 ****************************************************\r
 394 Creating system netlist for hardware specification..\r
 395 ****************************************************\r
 396 platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs\r
 397 \r\r
 398 Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
 399  (nt)\r\r
 400 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 401 \r\r
 402 \r\r
 403 Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
 404 __xps/ise/xmsgprops.lst system.mhs \r\r
 405 \r\r
 406 Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs\r\r
 407 ...\r\r
 408 \r\r
 409 Read MPD definitions ...\r\r
 410 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 411    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 412    251 - deprecated core for architecture 'virtex5fx'!\r\r
 413 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 414    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 415    296 - deprecated core for architecture 'virtex5fx'!\r\r
 416 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 417    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 418    251 - deprecated core for architecture 'virtex5fx'!\r\r
 419 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 420    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 421    296 - deprecated core for architecture 'virtex5fx'!\r\r
 422 \r\r
 423 Overriding IP level properties ...\r\r
 424 \r\r
 425 Performing IP level DRCs on properties...\r\r
 426 \r\r
 427 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
 428 Address Map for Processor ppc440_0\r\r
 429   (0b0000000000-0b0011111111) ppc440_0  \r\r
 430   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
 431   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
 432   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
 433   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
 434   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
 435   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
 436   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
 437   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
 438   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
 439   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
 440   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
 441   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
 442   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
 443   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
 444   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
 445 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 446    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 447    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
 448    C_SPLB0_P2P value to 0\r\r
 449 \r\r
 450 Computing clock values...\r\r
 451 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 452    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
 453    performed for IPs connected to that clock port, unless they are connected\r\r
 454    through the clock generator IP. \r\r
 455 \r\r
 456 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 457    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
 458    performed for IPs connected to that clock port, unless they are connected\r\r
 459    through the clock generator IP. \r\r
 460 \r\r
 461 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 462    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 463    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 464    C_PLBV46_NUM_MASTERS value to 1\r\r
 465 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 466    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 467    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 468    C_PLBV46_NUM_SLAVES value to 12\r\r
 469 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 470    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 471    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 472    C_PLBV46_MID_WIDTH value to 1\r\r
 473 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 474    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 475    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 476    value to 128\r\r
 477 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 478    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 479    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
 480    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 481 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 482    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 483    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
 484    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
 485 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 486    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 487    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
 488    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
 489 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 490    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 491    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
 492    value to 0x2000\r\r
 493 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 494    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 495    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 496    C_PORT_DWIDTH value to 64\r\r
 497 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 498    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 499    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
 500    value to 8\r\r
 501 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
 502    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
 503    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
 504    C_SPLB_DWIDTH value to 128\r\r
 505 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
 506    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 507    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 508    value to 128\r\r
 509 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
 510    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 511    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 512    value to 128\r\r
 513 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
 514    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 515    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 516    value to 128\r\r
 517 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
 518    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 519    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 520    value to 128\r\r
 521 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
 522    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
 523    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 524    value to 128\r\r
 525 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 526    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 527    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
 528    C_SPLB_DWIDTH value to 128\r\r
 529 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 530    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 531    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
 532    C_SPLB_SMALLEST_MASTER value to 128\r\r
 533 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 534    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 535    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
 536    C_MPLB_DWIDTH value to 128\r\r
 537 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 538    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 539    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
 540    C_MPLB_SMALLEST_SLAVE value to 128\r\r
 541 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 542    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 543    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
 544    C_SPLB_MID_WIDTH value to 1\r\r
 545 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 546    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 547    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
 548    C_SPLB_NUM_MASTERS value to 1\r\r
 549 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 550    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 551    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
 552    C_SPLB_SMALLEST_MASTER value to 128\r\r
 553 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 554    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 555    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
 556    C_SPLB_DWIDTH value to 128\r\r
 557 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 558    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 559    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 560    C_PLBV46_NUM_MASTERS value to 1\r\r
 561 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 562    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 563    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 564    C_PLBV46_NUM_SLAVES value to 1\r\r
 565 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 566    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 567    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 568    C_PLBV46_MID_WIDTH value to 1\r\r
 569 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 570    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 571    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 572    value to 128\r\r
 573 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 574    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
 575    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
 576    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 577 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 578    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 579    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 580    C_SPLB_DWIDTH value to 128\r\r
 581 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 582    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 583    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
 584    C_SPLB_MID_WIDTH value to 1\r\r
 585 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 586    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 587    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
 588    C_SPLB_NUM_MASTERS value to 1\r\r
 589 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 590    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 591    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 592    value to 128\r\r
 593 \r\r
 594 Checking platform address map ...\r\r
 595 \r\r
 596 Checking platform configuration ...\r\r
 597 INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 598    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 599    296 - This design requires design constraints to guarantee performance.\r\r
 600    Please refer to the xps_ethernetlite_v2_00_a data sheet for details.  \r\r
 601    The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
 602    Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
 603    operation.\r\r
 604 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 605 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 606 107 - 1 master(s) : 12 slave(s)\r\r
 607 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 608 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 609 288 - 1 master(s) : 1 slave(s)\r\r
 610 \r\r
 611 Checking port drivers...\r\r
 612 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
 613    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 614    446 - floating connection!\r\r
 615 \r\r
 616 Performing Clock DRCs...\r\r
 617 \r\r
 618 Performing Reset DRCs...\r\r
 619 \r\r
 620 Overriding system level properties...\r\r
 621 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 622    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 623    01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
 624    C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
 625 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 626    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 627    01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
 628    C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
 629 INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
 630    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
 631    1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
 632    C_NUM_PPC_USED value to 1\r\r
 633 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 634    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 635    ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
 636    value to 0b00000000000000000000000000000001\r\r
 637 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 638    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 639    ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
 640    value to 0b00000000000000000000000000000001\r\r
 641 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 642    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 643    ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
 644    value to 0b00000000000000000000000000000000\r\r
 645 \r\r
 646 Running system level update procedures...\r\r
 647 \r\r
 648 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
 649 \r\r
 650 Running system level DRCs...\r\r
 651 \r\r
 652 Performing System level DRCs on properties...\r\r
 653 \r\r
 654 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
 655 \r\r
 656 Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
 657 INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
 658 implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
 659 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 660 \r\r
 661 \r\r\r
 662 \r\r
 663 INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
 664 implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
 665 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 666 \r\r
 667 \r\r\r
 668 \r\r
 669 INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
 670 implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
 671 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 672 \r\r
 673 \r\r\r
 674 \r\r
 675 \r\r
 676 Modify defaults ...\r\r
 677 \r\r
 678 Creating stub ...\r\r
 679 \r\r
 680 Processing licensed instances ...\r\r
 681 Completion time: 0.00 seconds\r\r
 682 \r\r
 683 Creating hardware output directories ...\r\r
 684 \r\r
 685 Managing hardware (BBD-specified) netlist files ...\r\r
 686 IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
 687 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 688 251 - Copying (BBD-specified) netlist files.\r\r
 689 IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
 690 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 691 296 - Copying (BBD-specified) netlist files.\r\r
 692 \r\r
 693 Managing cache ...\r\r
 694 \r\r
 695 Elaborating instances ...\r\r
 696 IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 697 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 698 129 - elaborating IP\r\r
 699 \r\r
 700 Writing HDL for elaborated instances ...\r\r
 701 \r\r
 702 Inserting wrapper level ...\r\r
 703 Completion time: 1.00 seconds\r\r
 704 \r\r
 705 Constructing platform-level connectivity ...\r\r
 706 Completion time: 1.00 seconds\r\r
 707 \r\r
 708 Writing (top-level) BMM ...\r\r
 709 \r\r
 710 Writing (top-level and wrappers) HDL ...\r\r
 711 \r\r
 712 Generating synthesis project file ...\r\r
 713 \r\r
 714 Running XST synthesis ...\r\r
 715 \r\r
 716 INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
 717    IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
 718    synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
 719 INSTANCE:ppc440_0 -\r\r
 720 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
 721 - Running XST synthesis\r\r
 722 INSTANCE:plb_v46_0 -\r\r
 723 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 724 107 - Running XST synthesis\r\r
 725 INSTANCE:xps_bram_if_cntlr_1 -\r\r
 726 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 727 116 - Running XST synthesis\r\r
 728 INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 729 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 730 129 - Running XST synthesis\r\r
 731 INSTANCE:rs232_uart_1 -\r\r
 732 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 733 136 - Running XST synthesis\r\r
 734 INSTANCE:leds_8bit -\r\r
 735 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 736 152 - Running XST synthesis\r\r
 737 INSTANCE:leds_positions -\r\r
 738 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 739 166 - Running XST synthesis\r\r
 740 INSTANCE:push_buttons_5bit -\r\r
 741 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 742 180 - Running XST synthesis\r\r
 743 INSTANCE:dip_switches_8bit -\r\r
 744 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 745 194 - Running XST synthesis\r\r
 746 INSTANCE:iic_eeprom -\r\r
 747 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 748 208 - Running XST synthesis\r\r
 749 INSTANCE:sram -\r\r
 750 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 751 221 - Running XST synthesis\r\r
 752 INSTANCE:pcie_bridge -\r\r
 753 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 754 251 - Running XST synthesis\r\r
 755 INSTANCE:ppc440_0_splb0 -\r\r
 756 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 757 288 - Running XST synthesis\r\r
 758 INSTANCE:ethernet_mac -\r\r
 759 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 760 296 - Running XST synthesis\r\r
 761 INSTANCE:ddr2_sdram -\r\r
 762 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 763 315 - Running XST synthesis\r\r
 764 INSTANCE:sysace_compactflash -\r\r
 765 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 766 375 - Running XST synthesis\r\r
 767 INSTANCE:clock_generator_0 -\r\r
 768 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 769 392 - Running XST synthesis\r\r
 770 INSTANCE:jtagppc_cntlr_inst -\r\r
 771 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 772 431 - Running XST synthesis\r\r
 773 INSTANCE:proc_sys_reset_0 -\r\r
 774 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 775 437 - Running XST synthesis\r\r
 776 INSTANCE:xps_intc_0 -\r\r
 777 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 778 449 - Running XST synthesis\r\r
 779 \r\r
 780 Running NGCBUILD ...\r\r
 781 IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
 782 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78\r\r
 783 - Running NGCBUILD\r\r
 784 PMSPEC -- Overriding Xilinx file\r\r
 785 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 786 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 787 \r\r
 788 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 789 xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
 790 ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
 791 \r\r
 792 Reading NGO file\r\r
 793 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp\r\r
 794 c440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
 795 \r\r
 796 Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
 797 \r\r
 798 Partition Implementation Status\r\r
 799 -------------------------------\r\r
 800 \r\r
 801   No Partitions were found in this design.\r\r
 802 \r\r
 803 -------------------------------\r\r
 804 \r\r
 805 NGCBUILD Design Results Summary:\r\r
 806   Number of errors:     0\r\r
 807   Number of warnings:   0\r\r
 808 \r\r
 809 Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
 810 Total REAL time to NGCBUILD completion:  7 sec\r\r
 811 Total CPU time to NGCBUILD completion:   6 sec\r\r
 812 \r\r
 813 Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
 814 \r\r
 815 NGCBUILD done.\r\r
 816 IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
 817 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 818 136 - Running NGCBUILD\r\r
 819 PMSPEC -- Overriding Xilinx file\r\r
 820 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 821 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 822 \r\r
 823 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 824 xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
 825 ../rs232_uart_1_wrapper.ngc\r\r
 826 \r\r
 827 Reading NGO file\r\r
 828 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/rs\r\r
 829 232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
 830 \r\r
 831 Partition Implementation Status\r\r
 832 -------------------------------\r\r
 833 \r\r
 834   No Partitions were found in this design.\r\r
 835 \r\r
 836 -------------------------------\r\r
 837 \r\r
 838 NGCBUILD Design Results Summary:\r\r
 839   Number of errors:     0\r\r
 840   Number of warnings:   0\r\r
 841 \r\r
 842 Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
 843 Total REAL time to NGCBUILD completion:  8 sec\r\r
 844 Total CPU time to NGCBUILD completion:   2 sec\r\r
 845 \r\r
 846 Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
 847 \r\r
 848 NGCBUILD done.\r\r
 849 IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
 850 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 851 251 - Running NGCBUILD\r\r
 852 PMSPEC -- Overriding Xilinx file\r\r
 853 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 854 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 855 \r\r
 856 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 857 xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
 858 pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
 859 \r\r
 860 Reading NGO file\r\r
 861 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc\r\r
 862 ie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
 863 Executing edif2ngd -noa\r\r
 864 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
 865 ie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
 866 "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
 867 Release 11.2 - edif2ngd L.46 (nt)\r\r
 868 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 869 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 870 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 871 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 872 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 873 Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 874 Loading design module\r\r
 875 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
 876 ie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 877 Loading design module\r\r
 878 "../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
 879 Loading design module\r\r
 880 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
 881 ie_bridge_wrapper/dpram_70_512.ngc"...\r\r
 882 Loading design module\r\r
 883 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc\r\r
 884 ie_bridge_wrapper/fifo_71x512.ngc"...\r\r
 885 \r\r
 886 Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
 887 \r\r
 888 Partition Implementation Status\r\r
 889 -------------------------------\r\r
 890 \r\r
 891   No Partitions were found in this design.\r\r
 892 \r\r
 893 -------------------------------\r\r
 894 \r\r
 895 NGCBUILD Design Results Summary:\r\r
 896   Number of errors:     0\r\r
 897   Number of warnings:   0\r\r
 898 \r\r
 899 Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
 900 Total REAL time to NGCBUILD completion:  13 sec\r\r
 901 Total CPU time to NGCBUILD completion:   9 sec\r\r
 902 \r\r
 903 Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
 904 \r\r
 905 NGCBUILD done.\r\r
 906 IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
 907 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 908 296 - Running NGCBUILD\r\r
 909 PMSPEC -- Overriding Xilinx file\r\r
 910 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 911 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 912 \r\r
 913 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 914 xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
 915 ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
 916 \r\r
 917 Reading NGO file\r\r
 918 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/et\r\r
 919 hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
 920 Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
 921 "ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
 922 Release 11.2 - edif2ngd L.46 (nt)\r\r
 923 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 924 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 925 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 926 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 927 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 928 Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 929 Loading design module\r\r
 930 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\et\r\r
 931 hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 932 \r\r
 933 Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
 934 \r\r
 935 Partition Implementation Status\r\r
 936 -------------------------------\r\r
 937 \r\r
 938   No Partitions were found in this design.\r\r
 939 \r\r
 940 -------------------------------\r\r
 941 \r\r
 942 NGCBUILD Design Results Summary:\r\r
 943   Number of errors:     0\r\r
 944   Number of warnings:   0\r\r
 945 \r\r
 946 Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
 947 Total REAL time to NGCBUILD completion:  9 sec\r\r
 948 Total CPU time to NGCBUILD completion:   6 sec\r\r
 949 \r\r
 950 Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
 951 \r\r
 952 NGCBUILD done.\r\r
 953 IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
 954 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 955 315 - Running NGCBUILD\r\r
 956 PMSPEC -- Overriding Xilinx file\r\r
 957 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 958 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 959 \r\r
 960 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 961 xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
 962 ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
 963 \r\r
 964 Reading NGO file\r\r
 965 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd\r\r
 966 r2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
 967 \r\r
 968 Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
 969 \r\r
 970 Partition Implementation Status\r\r
 971 -------------------------------\r\r
 972 \r\r
 973   No Partitions were found in this design.\r\r
 974 \r\r
 975 -------------------------------\r\r
 976 \r\r
 977 NGCBUILD Design Results Summary:\r\r
 978   Number of errors:     0\r\r
 979   Number of warnings:   0\r\r
 980 \r\r
 981 Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
 982 Total REAL time to NGCBUILD completion:  7 sec\r\r
 983 Total CPU time to NGCBUILD completion:   7 sec\r\r
 984 \r\r
 985 Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
 986 \r\r
 987 NGCBUILD done.\r\r
 988 IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
 989 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
 990 449 - Running NGCBUILD\r\r
 991 PMSPEC -- Overriding Xilinx file\r\r
 992 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 993 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 994 \r\r
 995 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 996 xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
 997 ../xps_intc_0_wrapper.ngc\r\r
 998 \r\r
 999 Reading NGO file\r\r
1000 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xp\r\r
1001 s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
1002 \r\r
1003 Partition Implementation Status\r\r
1004 -------------------------------\r\r
1005 \r\r
1006   No Partitions were found in this design.\r\r
1007 \r\r
1008 -------------------------------\r\r
1009 \r\r
1010 NGCBUILD Design Results Summary:\r\r
1011   Number of errors:     0\r\r
1012   Number of warnings:   0\r\r
1013 \r\r
1014 Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
1015 Total REAL time to NGCBUILD completion:  1 sec\r\r
1016 Total CPU time to NGCBUILD completion:   1 sec\r\r
1017 \r\r
1018 Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
1019 \r\r
1020 NGCBUILD done.\r\r
1021 \r\r
1022 Rebuilding cache ...\r\r
1023 \r\r
1024 Total run time: 1039.00 seconds\r\r
1025 Running synthesis...\r
1026 bash -c "cd synthesis; ./synthesis.sh"\r
1027 xst -ifn system_xst.scr -intstyle silent\r
1028 Running XST synthesis ...\r
1029 XST completed\r
1030 Release 11.2 - ngcbuild L.46 (nt)\r\r
1031 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
1032 Overriding Xilinx file <ngcflow.csf> with local file\r\r
1033 <c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
1034 \r\r
1035 Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
1036 ./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
1037 ../__xps/ise/system.ise\r\r
1038 \r\r
1039 Reading NGO file\r\r
1040 "c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/synthesis/system.\r\r
1041 ngc" ...\r\r
1042 Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
1043 Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
1044 Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
1045 Loading design module\r\r
1046 "../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
1047 Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
1048 Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
1049 Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
1050 Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
1051 Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
1052 Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
1053 Loading design module "../implementation/sram_wrapper.ngc"...\r\r
1054 Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
1055 Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
1056 Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
1057 Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
1058 Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
1059 Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
1060 Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
1061 Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
1062 Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
1063 \r\r
1064 Partition Implementation Status\r\r
1065 -------------------------------\r\r
1066 \r\r
1067   No Partitions were found in this design.\r\r
1068 \r\r
1069 -------------------------------\r\r
1070 \r\r
1071 NGCBUILD Design Results Summary:\r\r
1072   Number of errors:     0\r\r
1073   Number of warnings:   0\r\r
1074 \r\r
1075 Writing NGC file "../implementation/system.ngc" ...\r\r
1076 Total REAL time to NGCBUILD completion:  10 sec\r\r
1077 Total CPU time to NGCBUILD completion:   9 sec\r\r
1078 \r\r
1079 Writing NGCBUILD log file "../implementation/system.blc"...\r\r
1080 \r\r
1081 NGCBUILD done.\r\r
1082 *********************************************\r
1083 Running Xilinx Implementation tools..\r
1084 *********************************************\r
1085 xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
1086 Release 11.2 - Xflow L.46 (nt)\r\r
1087 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
1088 xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
1089 ../__xps/ise/system.ise system.ngc  \r\r
1090 PMSPEC -- Overriding Xilinx file\r\r
1091 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
1092 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
1093 .... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
1094 working directory\r\r
1095 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation \r\r
1096 \r\r
1097 Using Flow File:\r\r
1098 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/fpg\r\r
1099 a.flw \r\r
1100 Using Option File(s): \r\r
1101  C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xf\r\r
1102 low.opt \r\r
1103 \r\r
1104 Creating Script File ... \r\r
1105 \r\r
1106 #----------------------------------------------#\r\r
1107 # Starting program ngdbuild\r\r
1108 # ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
1109 system.bmm\r\r
1110 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
1111 stem.ngc" -uc system.ucf system.ngd \r\r
1112 #----------------------------------------------#\r\r
1113 Release 11.2 - ngdbuild L.46 (nt)\r\r
1114 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
1115 PMSPEC -- Overriding Xilinx file\r\r
1116 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
1117 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
1118 \r\r
1119 Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
1120 timestamp -bm system.bmm\r\r
1121 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sys\r\r
1122 tem.ngc -uc system.ucf system.ngd\r\r
1123 \r\r
1124 Reading NGO file\r\r
1125 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy\r\r
1126 stem.ngc" ...\r\r
1127 Gathering constraint information from source properties...\r\r
1128 Done.\r\r
1129 \r\r
1130 Applying constraints in "system.ucf" to the design...\r\r
1131 WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
1132    'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
1133    ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
1134    'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
1135    In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
1136    should be changed in this same manner in the source netlist or constraint\r\r
1137    file.\r\r
1138 Resolving constraint associations...\r\r
1139 Checking Constraint Associations...\r\r
1140 WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
1141    "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
1142    * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
1143    clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
1144    found.\r\r
1145 \r\r
1146 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
1147    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
1148    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
1149    The following new TNM groups and period specifications were generated at the\r\r
1150    PLL_ADV output(s): \r\r
1151    CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
1152    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
1153    1.25 PHASE 2 ns HIGH 50%>\r\r
1154 \r\r
1155 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
1156    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
1157    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
1158    The following new TNM groups and period specifications were generated at the\r\r
1159    PLL_ADV output(s): \r\r
1160    CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
1161    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
1162    1.25 HIGH 50%>\r\r
1163 \r\r
1164 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
1165    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
1166    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
1167    The following new TNM groups and period specifications were generated at the\r\r
1168    PLL_ADV output(s): \r\r
1169    CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
1170    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
1171    1.25 HIGH 50%>\r\r
1172 \r\r
1173 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
1174    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
1175    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
1176    The following new TNM groups and period specifications were generated at the\r\r
1177    PLL_ADV output(s): \r\r
1178    CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
1179    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
1180    2 HIGH 50%>\r\r
1181 \r\r
1182 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
1183    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
1184    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
1185    The following new TNM groups and period specifications were generated at the\r\r
1186    PLL_ADV output(s): \r\r
1187    CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
1188    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
1189    0.625 HIGH 50%>\r\r
1190 \r\r
1191 Done...\r\r
1192 Checking Partitions ...\r\r
1193 \r\r
1194 Processing BMM file ...\r\r
1195 \r\r
1196 WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
1197    (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
1198    "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
1199     This does not match the PERIOD constraint value (5 ns.).  The uncertainty\r\r
1200    calculation will use the non-default attribute value.  This could result in\r\r
1201    incorrect uncertainty calculated for DCM output clocks.\r\r
1202 Checking expanded design ...\r\r
1203 WARNING:NgdBuild:443 - SFF primitive\r\r
1204    'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
1205    ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
1206    has unconnected output pin\r\r
1207 WARNING:NgdBuild:443 - SFF primitive\r\r
1208    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
1209    unconnected output pin\r\r
1210 WARNING:NgdBuild:443 - SFF primitive\r\r
1211    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
1212    ALIGN_PIPE' has unconnected output pin\r\r
1213 WARNING:NgdBuild:443 - SFF primitive\r\r
1214    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1215    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
1216    has unconnected output pin\r\r
1217 WARNING:NgdBuild:443 - SFF primitive\r\r
1218    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1219    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
1220    has unconnected output pin\r\r
1221 WARNING:NgdBuild:443 - SFF primitive\r\r
1222    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1223    ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
1224    RE_I' has unconnected output pin\r\r
1225 WARNING:NgdBuild:443 - SFF primitive\r\r
1226    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1227    ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
1228    E_I' has unconnected output pin\r\r
1229 WARNING:NgdBuild:443 - SFF primitive\r\r
1230    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1231    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
1232    ' has unconnected output pin\r\r
1233 WARNING:NgdBuild:443 - SFF primitive\r\r
1234    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1235    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
1236    ' has unconnected output pin\r\r
1237 WARNING:NgdBuild:443 - SFF primitive\r\r
1238    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1239    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
1240    ' has unconnected output pin\r\r
1241 WARNING:NgdBuild:443 - SFF primitive\r\r
1242    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1243    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
1244    ' has unconnected output pin\r\r
1245 WARNING:NgdBuild:443 - SFF primitive\r\r
1246    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1247    ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
1248    has unconnected output pin\r\r
1249 WARNING:NgdBuild:443 - SFF primitive\r\r
1250    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1251    ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
1252    ' has unconnected output pin\r\r
1253 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
1254    "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
1255    v_i" of type "PLL_ADV".  This attribute will be ignored.\r\r
1256 WARNING:NgdBuild:443 - SFF primitive\r\r
1257    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1258    URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1259    unconnected output pin\r\r
1260 WARNING:NgdBuild:443 - SFF primitive\r\r
1261    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1262    URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1263    unconnected output pin\r\r
1264 WARNING:NgdBuild:443 - SFF primitive\r\r
1265    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1266    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1267    _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
1268 WARNING:NgdBuild:443 - SFF primitive\r\r
1269    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1270    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1271    _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
1272 WARNING:NgdBuild:443 - SFF primitive\r\r
1273    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1274    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1275    _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
1276 WARNING:NgdBuild:443 - SFF primitive\r\r
1277    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1278    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1279    _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
1280 WARNING:NgdBuild:443 - SFF primitive\r\r
1281    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1282    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
1283    E0to3' has unconnected output pin\r\r
1284 WARNING:NgdBuild:443 - SFF primitive\r\r
1285    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1286    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
1287    E0to3' has unconnected output pin\r\r
1288 WARNING:NgdBuild:443 - SFF primitive\r\r
1289    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1290    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
1291    E0to3' has unconnected output pin\r\r
1292 WARNING:NgdBuild:443 - SFF primitive\r\r
1293    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1294    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
1295    E0to3' has unconnected output pin\r\r
1296 WARNING:NgdBuild:443 - SFF primitive\r\r
1297    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1298    _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
1299 WARNING:NgdBuild:443 - SFF primitive\r\r
1300    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1301    _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
1302 WARNING:NgdBuild:443 - SFF primitive\r\r
1303    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1304    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
1305    output pin\r\r
1306 WARNING:NgdBuild:443 - SFF primitive\r\r
1307    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1308    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
1309    output pin\r\r
1310 WARNING:NgdBuild:443 - SFF primitive\r\r
1311    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1312    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
1313    output pin\r\r
1314 WARNING:NgdBuild:443 - SFF primitive\r\r
1315    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1316    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
1317    output pin\r\r
1318 WARNING:NgdBuild:443 - SFF primitive\r\r
1319    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1320    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
1321    output pin\r\r
1322 WARNING:NgdBuild:443 - SFF primitive\r\r
1323    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1324    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
1325    output pin\r\r
1326 WARNING:NgdBuild:443 - SFF primitive\r\r
1327    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1328    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
1329    output pin\r\r
1330 WARNING:NgdBuild:443 - SFF primitive\r\r
1331    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1332    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
1333    output pin\r\r
1334 WARNING:NgdBuild:443 - SFF primitive\r\r
1335    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1336    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
1337    output pin\r\r
1338 WARNING:NgdBuild:443 - SFF primitive\r\r
1339    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1340    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
1341    output pin\r\r
1342 WARNING:NgdBuild:443 - SFF primitive\r\r
1343    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1344    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
1345    output pin\r\r
1346 WARNING:NgdBuild:443 - SFF primitive\r\r
1347    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1348    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
1349    output pin\r\r
1350 WARNING:NgdBuild:443 - SFF primitive\r\r
1351    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1352    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
1353    output pin\r\r
1354 WARNING:NgdBuild:443 - SFF primitive\r\r
1355    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1356    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
1357    output pin\r\r
1358 WARNING:NgdBuild:443 - SFF primitive\r\r
1359    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1360    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
1361    output pin\r\r
1362 WARNING:NgdBuild:443 - SFF primitive\r\r
1363    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1364    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
1365    output pin\r\r
1366 WARNING:NgdBuild:443 - SFF primitive\r\r
1367    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1368    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
1369    output pin\r\r
1370 WARNING:NgdBuild:443 - SFF primitive\r\r
1371    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1372    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
1373    output pin\r\r
1374 WARNING:NgdBuild:443 - SFF primitive\r\r
1375    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1376    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
1377    output pin\r\r
1378 WARNING:NgdBuild:443 - SFF primitive\r\r
1379    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1380    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
1381    output pin\r\r
1382 WARNING:NgdBuild:443 - SFF primitive\r\r
1383    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1384    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
1385    output pin\r\r
1386 WARNING:NgdBuild:443 - SFF primitive\r\r
1387    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1388    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
1389    output pin\r\r
1390 WARNING:NgdBuild:443 - SFF primitive\r\r
1391    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1392    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
1393    output pin\r\r
1394 WARNING:NgdBuild:443 - SFF primitive\r\r
1395    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1396    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
1397    output pin\r\r
1398 WARNING:NgdBuild:443 - SFF primitive\r\r
1399    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1400    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
1401    output pin\r\r
1402 WARNING:NgdBuild:443 - SFF primitive\r\r
1403    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1404    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
1405    output pin\r\r
1406 WARNING:NgdBuild:443 - SFF primitive\r\r
1407    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1408    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
1409    output pin\r\r
1410 WARNING:NgdBuild:443 - SFF primitive\r\r
1411    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1412    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
1413    output pin\r\r
1414 WARNING:NgdBuild:443 - SFF primitive\r\r
1415    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1416    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
1417    output pin\r\r
1418 WARNING:NgdBuild:443 - SFF primitive\r\r
1419    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1420    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
1421    output pin\r\r
1422 WARNING:NgdBuild:443 - SFF primitive\r\r
1423    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1424    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
1425    output pin\r\r
1426 WARNING:NgdBuild:443 - SFF primitive\r\r
1427    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1428    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
1429    unconnected output pin\r\r
1430 WARNING:NgdBuild:443 - SFF primitive\r\r
1431    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1432    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
1433    unconnected output pin\r\r
1434 WARNING:NgdBuild:443 - SFF primitive\r\r
1435    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1436    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
1437    output pin\r\r
1438 WARNING:NgdBuild:443 - SFF primitive\r\r
1439    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1440    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
1441    unconnected output pin\r\r
1442 WARNING:NgdBuild:443 - SFF primitive\r\r
1443    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1444    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
1445    unconnected output pin\r\r
1446 WARNING:NgdBuild:443 - SFF primitive\r\r
1447    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1448    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
1449    output pin\r\r
1450 WARNING:NgdBuild:443 - SFF primitive\r\r
1451    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1452    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
1453    unconnected output pin\r\r
1454 WARNING:NgdBuild:443 - SFF primitive\r\r
1455    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1456    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
1457    unconnected output pin\r\r
1458 WARNING:NgdBuild:443 - SFF primitive\r\r
1459    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1460    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
1461    output pin\r\r
1462 WARNING:NgdBuild:443 - SFF primitive\r\r
1463    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1464    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
1465    unconnected output pin\r\r
1466 WARNING:NgdBuild:443 - SFF primitive\r\r
1467    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1468    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
1469    unconnected output pin\r\r
1470 WARNING:NgdBuild:443 - SFF primitive\r\r
1471    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1472    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
1473    output pin\r\r
1474 WARNING:NgdBuild:443 - SFF primitive\r\r
1475    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1476    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
1477    unconnected output pin\r\r
1478 WARNING:NgdBuild:443 - SFF primitive\r\r
1479    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1480    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
1481    unconnected output pin\r\r
1482 WARNING:NgdBuild:443 - SFF primitive\r\r
1483    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1484    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
1485    output pin\r\r
1486 WARNING:NgdBuild:443 - SFF primitive\r\r
1487    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1488    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
1489    unconnected output pin\r\r
1490 WARNING:NgdBuild:443 - SFF primitive\r\r
1491    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1492    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
1493    unconnected output pin\r\r
1494 WARNING:NgdBuild:443 - SFF primitive\r\r
1495    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1496    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
1497    output pin\r\r
1498 WARNING:NgdBuild:443 - SFF primitive\r\r
1499    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1500    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
1501    unconnected output pin\r\r
1502 WARNING:NgdBuild:443 - SFF primitive\r\r
1503    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1504    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
1505    unconnected output pin\r\r
1506 WARNING:NgdBuild:443 - SFF primitive\r\r
1507    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1508    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
1509    output pin\r\r
1510 WARNING:NgdBuild:443 - SFF primitive\r\r
1511    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1512    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
1513    unconnected output pin\r\r
1514 WARNING:NgdBuild:443 - SFF primitive\r\r
1515    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1516    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
1517    unconnected output pin\r\r
1518 WARNING:NgdBuild:443 - SFF primitive\r\r
1519    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1520    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
1521    output pin\r\r
1522 WARNING:NgdBuild:443 - SFF primitive\r\r
1523    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1524    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
1525    unconnected output pin\r\r
1526 WARNING:NgdBuild:443 - SFF primitive\r\r
1527    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1528    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
1529    unconnected output pin\r\r
1530 WARNING:NgdBuild:443 - SFF primitive\r\r
1531    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1532    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
1533    output pin\r\r
1534 WARNING:NgdBuild:443 - SFF primitive\r\r
1535    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1536    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
1537    unconnected output pin\r\r
1538 WARNING:NgdBuild:443 - SFF primitive\r\r
1539    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1540    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
1541    unconnected output pin\r\r
1542 WARNING:NgdBuild:443 - SFF primitive\r\r
1543    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1544    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
1545    output pin\r\r
1546 WARNING:NgdBuild:443 - SFF primitive\r\r
1547    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1548    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
1549    unconnected output pin\r\r
1550 WARNING:NgdBuild:443 - SFF primitive\r\r
1551    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1552    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
1553    unconnected output pin\r\r
1554 WARNING:NgdBuild:443 - SFF primitive\r\r
1555    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1556    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
1557    output pin\r\r
1558 WARNING:NgdBuild:443 - SFF primitive\r\r
1559    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1560    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
1561    unconnected output pin\r\r
1562 WARNING:NgdBuild:443 - SFF primitive\r\r
1563    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1564    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
1565    unconnected output pin\r\r
1566 WARNING:NgdBuild:443 - SFF primitive\r\r
1567    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1568    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
1569    output pin\r\r
1570 WARNING:NgdBuild:443 - SFF primitive\r\r
1571    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1572    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
1573    unconnected output pin\r\r
1574 WARNING:NgdBuild:443 - SFF primitive\r\r
1575    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1576    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
1577    unconnected output pin\r\r
1578 WARNING:NgdBuild:443 - SFF primitive\r\r
1579    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1580    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
1581    output pin\r\r
1582 WARNING:NgdBuild:443 - SFF primitive\r\r
1583    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1584    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
1585    unconnected output pin\r\r
1586 WARNING:NgdBuild:443 - SFF primitive\r\r
1587    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1588    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
1589    unconnected output pin\r\r
1590 WARNING:NgdBuild:443 - SFF primitive\r\r
1591    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1592    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
1593    output pin\r\r
1594 WARNING:NgdBuild:443 - SFF primitive\r\r
1595    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1596    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
1597    unconnected output pin\r\r
1598 WARNING:NgdBuild:443 - SFF primitive\r\r
1599    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1600    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
1601    unconnected output pin\r\r
1602 WARNING:NgdBuild:443 - SFF primitive\r\r
1603    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1604    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
1605    output pin\r\r
1606 WARNING:NgdBuild:443 - SFF primitive\r\r
1607    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1608    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
1609    unconnected output pin\r\r
1610 WARNING:NgdBuild:443 - SFF primitive\r\r
1611    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1612    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
1613    unconnected output pin\r\r
1614 WARNING:NgdBuild:443 - SFF primitive\r\r
1615    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1616    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
1617    output pin\r\r
1618 WARNING:NgdBuild:443 - SFF primitive\r\r
1619    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1620    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
1621    unconnected output pin\r\r
1622 WARNING:NgdBuild:443 - SFF primitive\r\r
1623    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1624    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
1625    unconnected output pin\r\r
1626 WARNING:NgdBuild:443 - SFF primitive\r\r
1627    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1628    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
1629    output pin\r\r
1630 WARNING:NgdBuild:443 - SFF primitive\r\r
1631    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1632    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
1633    unconnected output pin\r\r
1634 WARNING:NgdBuild:443 - SFF primitive\r\r
1635    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1636    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
1637    unconnected output pin\r\r
1638 WARNING:NgdBuild:443 - SFF primitive\r\r
1639    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1640    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
1641    output pin\r\r
1642 WARNING:NgdBuild:443 - SFF primitive\r\r
1643    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1644    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
1645    unconnected output pin\r\r
1646 WARNING:NgdBuild:443 - SFF primitive\r\r
1647    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1648    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
1649    unconnected output pin\r\r
1650 WARNING:NgdBuild:443 - SFF primitive\r\r
1651    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1652    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
1653    output pin\r\r
1654 WARNING:NgdBuild:443 - SFF primitive\r\r
1655    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1656    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
1657    unconnected output pin\r\r
1658 WARNING:NgdBuild:443 - SFF primitive\r\r
1659    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1660    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
1661    unconnected output pin\r\r
1662 WARNING:NgdBuild:443 - SFF primitive\r\r
1663    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1664    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
1665    output pin\r\r
1666 WARNING:NgdBuild:443 - SFF primitive\r\r
1667    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1668    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
1669    unconnected output pin\r\r
1670 WARNING:NgdBuild:443 - SFF primitive\r\r
1671    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1672    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
1673    unconnected output pin\r\r
1674 WARNING:NgdBuild:443 - SFF primitive\r\r
1675    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1676    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
1677    output pin\r\r
1678 WARNING:NgdBuild:443 - SFF primitive\r\r
1679    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1680    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
1681    unconnected output pin\r\r
1682 WARNING:NgdBuild:443 - SFF primitive\r\r
1683    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1684    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
1685    unconnected output pin\r\r
1686 WARNING:NgdBuild:443 - SFF primitive\r\r
1687    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1688    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
1689    output pin\r\r
1690 WARNING:NgdBuild:443 - SFF primitive\r\r
1691    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1692    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
1693    output pin\r\r
1694 WARNING:NgdBuild:443 - SFF primitive\r\r
1695    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1696    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
1697    output pin\r\r
1698 WARNING:NgdBuild:443 - SFF primitive\r\r
1699    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1700    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
1701    output pin\r\r
1702 WARNING:NgdBuild:443 - SFF primitive\r\r
1703    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1704    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
1705    output pin\r\r
1706 WARNING:NgdBuild:443 - SFF primitive\r\r
1707    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1708    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
1709    output pin\r\r
1710 WARNING:NgdBuild:443 - SFF primitive\r\r
1711    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1712    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
1713    output pin\r\r
1714 WARNING:NgdBuild:443 - SFF primitive\r\r
1715    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1716    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
1717    output pin\r\r
1718 WARNING:NgdBuild:443 - SFF primitive\r\r
1719    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1720    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
1721    output pin\r\r
1722 WARNING:NgdBuild:443 - SFF primitive\r\r
1723    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1724    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
1725    output pin\r\r
1726 WARNING:NgdBuild:443 - SFF primitive\r\r
1727    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1728    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
1729    output pin\r\r
1730 WARNING:NgdBuild:443 - SFF primitive\r\r
1731    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1732    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
1733    output pin\r\r
1734 WARNING:NgdBuild:443 - SFF primitive\r\r
1735    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1736    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
1737    output pin\r\r
1738 WARNING:NgdBuild:443 - SFF primitive\r\r
1739    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1740    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
1741    unconnected output pin\r\r
1742 WARNING:NgdBuild:443 - SFF primitive\r\r
1743    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1744    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
1745    unconnected output pin\r\r
1746 WARNING:NgdBuild:443 - SFF primitive\r\r
1747    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1748    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
1749    output pin\r\r
1750 WARNING:NgdBuild:443 - SFF primitive\r\r
1751    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1752    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
1753    unconnected output pin\r\r
1754 WARNING:NgdBuild:443 - SFF primitive\r\r
1755    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1756    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
1757    unconnected output pin\r\r
1758 WARNING:NgdBuild:443 - SFF primitive\r\r
1759    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1760    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
1761    output pin\r\r
1762 WARNING:NgdBuild:443 - SFF primitive\r\r
1763    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1764    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
1765    unconnected output pin\r\r
1766 WARNING:NgdBuild:443 - SFF primitive\r\r
1767    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1768    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
1769    unconnected output pin\r\r
1770 WARNING:NgdBuild:443 - SFF primitive\r\r
1771    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1772    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
1773    output pin\r\r
1774 WARNING:NgdBuild:443 - SFF primitive\r\r
1775    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1776    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
1777    unconnected output pin\r\r
1778 WARNING:NgdBuild:443 - SFF primitive\r\r
1779    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1780    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
1781    unconnected output pin\r\r
1782 WARNING:NgdBuild:443 - SFF primitive\r\r
1783    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1784    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
1785    output pin\r\r
1786 WARNING:NgdBuild:443 - SFF primitive\r\r
1787    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1788    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
1789    unconnected output pin\r\r
1790 WARNING:NgdBuild:443 - SFF primitive\r\r
1791    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1792    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
1793    unconnected output pin\r\r
1794 WARNING:NgdBuild:443 - SFF primitive\r\r
1795    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1796    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
1797    output pin\r\r
1798 WARNING:NgdBuild:443 - SFF primitive\r\r
1799    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1800    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
1801    unconnected output pin\r\r
1802 WARNING:NgdBuild:443 - SFF primitive\r\r
1803    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1804    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
1805    unconnected output pin\r\r
1806 WARNING:NgdBuild:443 - SFF primitive\r\r
1807    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1808    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
1809    output pin\r\r
1810 WARNING:NgdBuild:443 - SFF primitive\r\r
1811    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1812    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
1813    unconnected output pin\r\r
1814 WARNING:NgdBuild:443 - SFF primitive\r\r
1815    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1816    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
1817    unconnected output pin\r\r
1818 WARNING:NgdBuild:443 - SFF primitive\r\r
1819    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1820    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
1821    output pin\r\r
1822 WARNING:NgdBuild:443 - SFF primitive\r\r
1823    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1824    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
1825    unconnected output pin\r\r
1826 WARNING:NgdBuild:443 - SFF primitive\r\r
1827    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1828    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
1829    unconnected output pin\r\r
1830 WARNING:NgdBuild:443 - SFF primitive\r\r
1831    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1832    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
1833    output pin\r\r
1834 WARNING:NgdBuild:443 - SFF primitive\r\r
1835    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1836    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
1837    unconnected output pin\r\r
1838 WARNING:NgdBuild:443 - SFF primitive\r\r
1839    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1840    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
1841    unconnected output pin\r\r
1842 WARNING:NgdBuild:443 - SFF primitive\r\r
1843    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1844    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
1845    output pin\r\r
1846 WARNING:NgdBuild:443 - SFF primitive\r\r
1847    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1848    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
1849    unconnected output pin\r\r
1850 WARNING:NgdBuild:443 - SFF primitive\r\r
1851    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1852    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
1853    unconnected output pin\r\r
1854 WARNING:NgdBuild:443 - SFF primitive\r\r
1855    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1856    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
1857    output pin\r\r
1858 WARNING:NgdBuild:443 - SFF primitive\r\r
1859    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1860    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
1861    unconnected output pin\r\r
1862 WARNING:NgdBuild:443 - SFF primitive\r\r
1863    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1864    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
1865    unconnected output pin\r\r
1866 WARNING:NgdBuild:443 - SFF primitive\r\r
1867    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1868    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
1869    output pin\r\r
1870 WARNING:NgdBuild:443 - SFF primitive\r\r
1871    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1872    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
1873    unconnected output pin\r\r
1874 WARNING:NgdBuild:443 - SFF primitive\r\r
1875    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1876    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
1877    unconnected output pin\r\r
1878 WARNING:NgdBuild:443 - SFF primitive\r\r
1879    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1880    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
1881    output pin\r\r
1882 WARNING:NgdBuild:443 - SFF primitive\r\r
1883    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1884    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
1885    output pin\r\r
1886 WARNING:NgdBuild:443 - SFF primitive\r\r
1887    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1888    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
1889    output pin\r\r
1890 WARNING:NgdBuild:443 - SFF primitive\r\r
1891    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1892    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
1893    output pin\r\r
1894 WARNING:NgdBuild:443 - SFF primitive\r\r
1895    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1896    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
1897    output pin\r\r
1898 WARNING:NgdBuild:443 - SFF primitive\r\r
1899    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1900    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
1901    output pin\r\r
1902 WARNING:NgdBuild:443 - SFF primitive\r\r
1903    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1904    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
1905    unconnected output pin\r\r
1906 WARNING:NgdBuild:443 - SFF primitive\r\r
1907    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1908    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
1909    unconnected output pin\r\r
1910 WARNING:NgdBuild:443 - SFF primitive\r\r
1911    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1912    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
1913    output pin\r\r
1914 WARNING:NgdBuild:443 - SFF primitive\r\r
1915    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1916    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
1917    unconnected output pin\r\r
1918 WARNING:NgdBuild:443 - SFF primitive\r\r
1919    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1920    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
1921    unconnected output pin\r\r
1922 WARNING:NgdBuild:443 - SFF primitive\r\r
1923    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1924    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
1925    output pin\r\r
1926 WARNING:NgdBuild:443 - SFF primitive\r\r
1927    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1928    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
1929    unconnected output pin\r\r
1930 WARNING:NgdBuild:443 - SFF primitive\r\r
1931    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1932    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
1933    unconnected output pin\r\r
1934 WARNING:NgdBuild:443 - SFF primitive\r\r
1935    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1936    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
1937    output pin\r\r
1938 WARNING:NgdBuild:443 - SFF primitive\r\r
1939    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1940    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
1941    unconnected output pin\r\r
1942 WARNING:NgdBuild:443 - SFF primitive\r\r
1943    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1944    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
1945    unconnected output pin\r\r
1946 WARNING:NgdBuild:443 - SFF primitive\r\r
1947    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1948    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
1949    unconnected output pin\r\r
1950 WARNING:NgdBuild:443 - SFF primitive\r\r
1951    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1952    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
1953    unconnected output pin\r\r
1954 WARNING:NgdBuild:443 - SFF primitive\r\r
1955    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1956    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
1957    unconnected output pin\r\r
1958 WARNING:NgdBuild:443 - SFF primitive\r\r
1959    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1960    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
1961    unconnected output pin\r\r
1962 WARNING:NgdBuild:443 - SFF primitive\r\r
1963    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1964    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
1965    unconnected output pin\r\r
1966 WARNING:NgdBuild:443 - SFF primitive\r\r
1967    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1968    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
1969    unconnected output pin\r\r
1970 WARNING:NgdBuild:443 - SFF primitive\r\r
1971    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1972    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
1973    unconnected output pin\r\r
1974 WARNING:NgdBuild:443 - SFF primitive\r\r
1975    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1976    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
1977    unconnected output pin\r\r
1978 WARNING:NgdBuild:443 - SFF primitive\r\r
1979    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1980    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
1981    unconnected output pin\r\r
1982 WARNING:NgdBuild:443 - SFF primitive\r\r
1983    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1984    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
1985    unconnected output pin\r\r
1986 WARNING:NgdBuild:443 - SFF primitive\r\r
1987    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1988    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
1989    unconnected output pin\r\r
1990 WARNING:NgdBuild:443 - SFF primitive\r\r
1991    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1992    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
1993    unconnected output pin\r\r
1994 WARNING:NgdBuild:443 - SFF primitive\r\r
1995    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1996    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
1997    unconnected output pin\r\r
1998 WARNING:NgdBuild:443 - SFF primitive\r\r
1999    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2000    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
2001    unconnected output pin\r\r
2002 WARNING:NgdBuild:443 - SFF primitive\r\r
2003    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2004    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
2005    unconnected output pin\r\r
2006 WARNING:NgdBuild:443 - SFF primitive\r\r
2007    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2008    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
2009    unconnected output pin\r\r
2010 WARNING:NgdBuild:443 - SFF primitive\r\r
2011    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2012    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
2013    unconnected output pin\r\r
2014 WARNING:NgdBuild:443 - SFF primitive\r\r
2015    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2016    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
2017    unconnected output pin\r\r
2018 WARNING:NgdBuild:443 - SFF primitive\r\r
2019    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2020    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
2021    unconnected output pin\r\r
2022 WARNING:NgdBuild:443 - SFF primitive\r\r
2023    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2024    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
2025    unconnected output pin\r\r
2026 WARNING:NgdBuild:443 - SFF primitive\r\r
2027    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2028    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
2029    unconnected output pin\r\r
2030 WARNING:NgdBuild:443 - SFF primitive\r\r
2031    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2032    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
2033    unconnected output pin\r\r
2034 WARNING:NgdBuild:443 - SFF primitive\r\r
2035    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2036    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
2037    unconnected output pin\r\r
2038 WARNING:NgdBuild:443 - SFF primitive\r\r
2039    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2040    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
2041    unconnected output pin\r\r
2042 WARNING:NgdBuild:443 - SFF primitive\r\r
2043    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2044    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
2045    unconnected output pin\r\r
2046 WARNING:NgdBuild:443 - SFF primitive\r\r
2047    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2048    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
2049    unconnected output pin\r\r
2050 WARNING:NgdBuild:443 - SFF primitive\r\r
2051    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2052    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
2053    unconnected output pin\r\r
2054 WARNING:NgdBuild:443 - SFF primitive\r\r
2055    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2056    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
2057    unconnected output pin\r\r
2058 WARNING:NgdBuild:443 - SFF primitive\r\r
2059    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2060    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
2061    unconnected output pin\r\r
2062 WARNING:NgdBuild:443 - SFF primitive\r\r
2063    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2064    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
2065    unconnected output pin\r\r
2066 WARNING:NgdBuild:443 - SFF primitive\r\r
2067    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2068    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
2069    unconnected output pin\r\r
2070 WARNING:NgdBuild:443 - SFF primitive\r\r
2071    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2072    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
2073    unconnected output pin\r\r
2074 WARNING:NgdBuild:443 - SFF primitive\r\r
2075    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2076    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
2077    unconnected output pin\r\r
2078 WARNING:NgdBuild:443 - SFF primitive\r\r
2079    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2080    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
2081    unconnected output pin\r\r
2082 WARNING:NgdBuild:443 - SFF primitive\r\r
2083    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2084    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
2085    unconnected output pin\r\r
2086 WARNING:NgdBuild:443 - SFF primitive\r\r
2087    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2088    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
2089    unconnected output pin\r\r
2090 WARNING:NgdBuild:443 - SFF primitive\r\r
2091    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2092    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
2093 WARNING:NgdBuild:443 - SFF primitive\r\r
2094    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2095    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
2096 WARNING:NgdBuild:443 - SFF primitive\r\r
2097    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2098    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
2099    output pin\r\r
2100 WARNING:NgdBuild:443 - SFF primitive\r\r
2101    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2102    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
2103    unconnected output pin\r\r
2104 WARNING:NgdBuild:443 - SFF primitive\r\r
2105    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2106    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
2107    unconnected output pin\r\r
2108 WARNING:NgdBuild:443 - SFF primitive\r\r
2109    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2110    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
2111    output pin\r\r
2112 WARNING:NgdBuild:443 - SFF primitive\r\r
2113    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2114    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
2115    unconnected output pin\r\r
2116 WARNING:NgdBuild:443 - SFF primitive\r\r
2117    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
2118    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
2119    unconnected output pin\r\r
2120 WARNING:NgdBuild:443 - SFF primitive\r\r
2121    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
2122    SIZE2_REG0' has unconnected output pin\r\r
2123 WARNING:NgdBuild:443 - SFF primitive\r\r
2124    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
2125    SIZE2_REG1' has unconnected output pin\r\r
2126 WARNING:NgdBuild:443 - SFF primitive\r\r
2127    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
2128    SIZE2_REG2' has unconnected output pin\r\r
2129 WARNING:NgdBuild:443 - SFF primitive\r\r
2130    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
2131    unconnected output pin\r\r
2132 WARNING:NgdBuild:443 - SFF primitive\r\r
2133    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
2134    output pin\r\r
2135 WARNING:NgdBuild:440 - FF primitive\r\r
2136    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
2137    has unconnected output pin\r\r
2138 WARNING:NgdBuild:440 - FF primitive\r\r
2139    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
2140    has unconnected output pin\r\r
2141 WARNING:NgdBuild:440 - FF primitive\r\r
2142    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
2143    has unconnected output pin\r\r
2144 WARNING:NgdBuild:440 - FF primitive\r\r
2145    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
2146    has unconnected output pin\r\r
2147 WARNING:NgdBuild:440 - FF primitive\r\r
2148    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
2149    has unconnected output pin\r\r
2150 WARNING:NgdBuild:440 - FF primitive\r\r
2151    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
2152    has unconnected output pin\r\r
2153 WARNING:NgdBuild:440 - FF primitive\r\r
2154    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
2155    has unconnected output pin\r\r
2156 WARNING:NgdBuild:440 - FF primitive\r\r
2157    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
2158    has unconnected output pin\r\r
2159 WARNING:NgdBuild:440 - FF primitive\r\r
2160    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
2161    has unconnected output pin\r\r
2162 WARNING:NgdBuild:440 - FF primitive\r\r
2163    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
2164    has unconnected output pin\r\r
2165 WARNING:NgdBuild:440 - FF primitive\r\r
2166    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
2167    has unconnected output pin\r\r
2168 WARNING:NgdBuild:440 - FF primitive\r\r
2169    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
2170    has unconnected output pin\r\r
2171 WARNING:NgdBuild:440 - FF primitive\r\r
2172    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
2173    has unconnected output pin\r\r
2174 WARNING:NgdBuild:440 - FF primitive\r\r
2175    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
2176    has unconnected output pin\r\r
2177 WARNING:NgdBuild:440 - FF primitive\r\r
2178    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
2179    has unconnected output pin\r\r
2180 WARNING:NgdBuild:440 - FF primitive\r\r
2181    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
2182    has unconnected output pin\r\r
2183 WARNING:NgdBuild:440 - FF primitive\r\r
2184    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2185    /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
2186 WARNING:NgdBuild:440 - FF primitive\r\r
2187    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2188    /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
2189 WARNING:NgdBuild:440 - FF primitive\r\r
2190    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2191    /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
2192 WARNING:NgdBuild:440 - FF primitive\r\r
2193    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2194    /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
2195 WARNING:NgdBuild:440 - FF primitive\r\r
2196    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2197    /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
2198 WARNING:NgdBuild:440 - FF primitive\r\r
2199    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2200    /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
2201 WARNING:NgdBuild:440 - FF primitive\r\r
2202    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
2203    /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
2204 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
2205    "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
2206    of type "PLL_ADV".  This attribute will be ignored.\r\r
2207 WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
2208 WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
2209 WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
2210 WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
2211 WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
2212 WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
2213 WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
2214 WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
2215 WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
2216 WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
2217 WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
2218 WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
2219 WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
2220 WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
2221 WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
2222 WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
2223 WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
2224 WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
2225 WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
2226 WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
2227 WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
2228 WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
2229 WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
2230 WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
2231 WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
2232 WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
2233 WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
2234 WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
2235 WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
2236 WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
2237 WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
2238 WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
2239 WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
2240 WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
2241 WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
2242 WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
2243 WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
2244 WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
2245 WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
2246 WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
2247 WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
2248 WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
2249 WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
2250 WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
2251 WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
2252 WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
2253 WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
2254 WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
2255 WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
2256 WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
2257 WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
2258 WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
2259 WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
2260 WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
2261 WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
2262 WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
2263 WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
2264 WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
2265 WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
2266 WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
2267 WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
2268 WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
2269 WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
2270 WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
2271 WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
2272 WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
2273 WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
2274 WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
2275 WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
2276 WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
2277 WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
2278 WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
2279 WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
2280 WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
2281 WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
2282 WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
2283 WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
2284 WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
2285 WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
2286 WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
2287 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
2288    has no driver\r\r
2289 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
2290    has no driver\r\r
2291 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
2292    has no driver\r\r
2293 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
2294    has no driver\r\r
2295 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
2296    has no driver\r\r
2297 \r\r
2298 Partition Implementation Status\r\r
2299 -------------------------------\r\r
2300 \r\r
2301   No Partitions were found in this design.\r\r
2302 \r\r
2303 -------------------------------\r\r
2304 \r\r
2305 NGDBUILD Design Results Summary:\r\r
2306   Number of errors:     0\r\r
2307   Number of warnings: 348\r\r
2308 \r\r
2309 Writing NGD file "system.ngd" ...\r\r
2310 Total REAL time to NGDBUILD completion: 1 min  58 sec\r\r
2311 Total CPU time to NGDBUILD completion:  1 min  28 sec\r\r
2312 \r\r
2313 Writing NGDBUILD log file "system.bld"...\r\r
2314 \r\r
2315 NGDBUILD done.\r\r
2316 \r\r
2317 \r\r
2318 \r\r
2319 #----------------------------------------------#\r\r
2320 # Starting program map\r\r
2321 # map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
2322 system.ngd system.pcf \r\r
2323 #----------------------------------------------#\r\r
2324 Release 11.2 - Map L.46 (nt)\r\r
2325 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
2326 PMSPEC -- Overriding Xilinx file\r\r
2327 <C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
2328 <c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
2329 Using target part "5vfx70tff1136-1".\r\r
2330 WARNING:LIT:243 - Logical network N194 has no load.\r\r
2331 WARNING:LIT:395 - The above warning message is repeated 1200 more times for the\r\r
2332    following (max. 5 shown):\r\r
2333    N195,\r\r
2334    N196,\r\r
2335    N197,\r\r
2336    N198,\r\r
2337    N199\r\r
2338    To see the details of these warning messages, please use the -detail switch.\r\r
2339 Mapping design into LUTs...\r\r
2340 WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
2341    connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
2342    been removed.\r\r
2343 WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
2344    level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
2345 WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
2346    optimized out of the design.\r\r
2347 Writing file system_map.ngm...\r\r
2348 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2349    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2350    of frag REGCLKAU connected to power/ground net\r\r
2351    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
2352 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2353    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2354    of frag REGCLKAL connected to power/ground net\r\r
2355    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
2356 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2357    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2358    of frag REGCLKAU connected to power/ground net\r\r
2359    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
2360 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2361    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2362    of frag REGCLKAL connected to power/ground net\r\r
2363    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
2364 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2365    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2366    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2367    of frag REGCLKAU connected to power/ground net\r\r
2368    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2369    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2370 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2371    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2372    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2373    of frag REGCLKAL connected to power/ground net\r\r
2374    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2375    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2376 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2377    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2378    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2379    of frag REGCLKAU connected to power/ground net\r\r
2380    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2381    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2382 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2383    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2384    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2385    of frag REGCLKAL connected to power/ground net\r\r
2386    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2387    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2388 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2389    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2390    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2391    of frag RDRCLKU connected to power/ground net\r\r
2392    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2393    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
2394 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2395    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2396    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2397    of frag RDRCLKL connected to power/ground net\r\r
2398    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2399    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
2400 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2401    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2402    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2403    noeccerr.SDP\r\r
2404    of frag RDRCLKU connected to power/ground net\r\r
2405    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2406    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2407    noeccerr.SDP_RDRCLKU_tiesig\r\r
2408 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2409    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2410    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2411    noeccerr.SDP\r\r
2412    of frag RDRCLKL connected to power/ground net\r\r
2413    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2414    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2415    noeccerr.SDP_RDRCLKL_tiesig\r\r
2416 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2417    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2418    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2419    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2420    of frag RDRCLKU connected to power/ground net\r\r
2421    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2422    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2423    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2424 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2425    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2426    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2427    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2428    of frag RDRCLKL connected to power/ground net\r\r
2429    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2430    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2431    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2432 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2433    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2434    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2435    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2436    of frag RDRCLKU connected to power/ground net\r\r
2437    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2438    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2439    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2440 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2441    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2442    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2443    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2444    of frag RDRCLKL connected to power/ground net\r\r
2445    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2446    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2447    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2448 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2449    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2450    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2451    36.noeccerr.SDP\r\r
2452    of frag RDRCLKU connected to power/ground net\r\r
2453    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2454    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2455    36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2456 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2457    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2458    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2459    36.noeccerr.SDP\r\r
2460    of frag RDRCLKL connected to power/ground net\r\r
2461    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2462    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2463    36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2464 Running directed packing...\r\r
2465 Running delay-based LUT packing...\r\r
2466 Updating timing models...\r\r
2467 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
2468    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
2469    timing analysis.\r\r
2470 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
2471    (.mrp).\r\r
2472 Running timing-driven placement...\r\r
2473 Total REAL time at the beginning of Placer: 1 mins 55 secs \r\r
2474 Total CPU  time at the beginning of Placer: 1 mins 43 secs \r\r
2475 \r\r
2476 Phase 1.1  Initial Placement Analysis\r\r
2477 Phase 1.1  Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs \r\r
2478 \r\r
2479 Phase 2.7  Design Feasibility Check\r\r
2480 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2481    Components associated with this bus are as follows: \r\r
2482          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7>   IOSTANDARD = LVCMOS25\r\r
2483          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25\r\r
2484          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5>   IOSTANDARD = LVCMOS25\r\r
2485          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18\r\r
2486          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3>   IOSTANDARD = LVCMOS25\r\r
2487          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18\r\r
2488          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1>   IOSTANDARD = LVCMOS18\r\r
2489          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18\r\r
2490 \r\r
2491 \r\r
2492 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2493    Components associated with this bus are as follows: \r\r
2494          Comp: fpga_0_SRAM_Mem_DQ_pin<31>   IOSTANDARD = LVDCI_33\r\r
2495          Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33\r\r
2496          Comp: fpga_0_SRAM_Mem_DQ_pin<29>   IOSTANDARD = LVDCI_33\r\r
2497          Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33\r\r
2498          Comp: fpga_0_SRAM_Mem_DQ_pin<27>   IOSTANDARD = LVDCI_33\r\r
2499          Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33\r\r
2500          Comp: fpga_0_SRAM_Mem_DQ_pin<25>   IOSTANDARD = LVDCI_33\r\r
2501          Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33\r\r
2502          Comp: fpga_0_SRAM_Mem_DQ_pin<23>   IOSTANDARD = LVDCI_33\r\r
2503          Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33\r\r
2504          Comp: fpga_0_SRAM_Mem_DQ_pin<21>   IOSTANDARD = LVDCI_33\r\r
2505          Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33\r\r
2506          Comp: fpga_0_SRAM_Mem_DQ_pin<19>   IOSTANDARD = LVDCI_33\r\r
2507          Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33\r\r
2508          Comp: fpga_0_SRAM_Mem_DQ_pin<17>   IOSTANDARD = LVDCI_33\r\r
2509          Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33\r\r
2510          Comp: fpga_0_SRAM_Mem_DQ_pin<15>   IOSTANDARD = LVCMOS33\r\r
2511          Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33\r\r
2512          Comp: fpga_0_SRAM_Mem_DQ_pin<13>   IOSTANDARD = LVCMOS33\r\r
2513          Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33\r\r
2514          Comp: fpga_0_SRAM_Mem_DQ_pin<11>   IOSTANDARD = LVCMOS33\r\r
2515          Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33\r\r
2516          Comp: fpga_0_SRAM_Mem_DQ_pin<9>   IOSTANDARD = LVCMOS33\r\r
2517          Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33\r\r
2518          Comp: fpga_0_SRAM_Mem_DQ_pin<7>   IOSTANDARD = LVCMOS33\r\r
2519          Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33\r\r
2520          Comp: fpga_0_SRAM_Mem_DQ_pin<5>   IOSTANDARD = LVCMOS33\r\r
2521          Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33\r\r
2522          Comp: fpga_0_SRAM_Mem_DQ_pin<3>   IOSTANDARD = LVCMOS33\r\r
2523          Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33\r\r
2524          Comp: fpga_0_SRAM_Mem_DQ_pin<1>   IOSTANDARD = LVCMOS33\r\r
2525          Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33\r\r
2526 \r\r
2527 \r\r
2528 Phase 2.7  Design Feasibility Check (Checksum:150b88e2) REAL time: 2 mins 14 secs \r\r
2529 \r\r
2530 Phase 3.31  Local Placement Optimization\r\r
2531 Phase 3.31  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
2532 \r\r
2533 Phase 4.37  Local Placement Optimization\r\r
2534 Phase 4.37  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs \r\r
2535 \r\r
2536 Phase 5.33  Local Placement Optimization\r\r
2537 Phase 5.33  Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs \r\r
2538 \r\r
2539 Phase 6.32  Local Placement Optimization\r\r
2540 Phase 6.32  Local Placement Optimization (Checksum:f23945c2) REAL time: 9 mins 1 secs \r\r
2541 \r\r
2542 Phase 7.2  Initial Clock and IO Placement\r\r
2543 \r\r
2544 \r\r
2545 \r\r
2546 There are 16 clock regions on the target FPGA device:\r\r
2547 |------------------------------------------|------------------------------------------|\r\r
2548 | CLOCKREGION_X0Y7:                        | CLOCKREGION_X1Y7:                        |\r\r
2549 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2550 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2551 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2552 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2553 |                                          |                                          |\r\r
2554 |------------------------------------------|------------------------------------------|\r\r
2555 | CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |\r\r
2556 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2557 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2558 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2559 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2560 |                                          |                                          |\r\r
2561 |------------------------------------------|------------------------------------------|\r\r
2562 | CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |\r\r
2563 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2564 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2565 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2566 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2567 |                                          |                                          |\r\r
2568 |------------------------------------------|------------------------------------------|\r\r
2569 | CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |\r\r
2570 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2571 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2572 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2573 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2574 |                                          |                                          |\r\r
2575 |------------------------------------------|------------------------------------------|\r\r
2576 | CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |\r\r
2577 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2578 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2579 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2580 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2581 |                                          |                                          |\r\r
2582 |------------------------------------------|------------------------------------------|\r\r
2583 | CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |\r\r
2584 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2585 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2586 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2587 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2588 |                                          |                                          |\r\r
2589 |------------------------------------------|------------------------------------------|\r\r
2590 | CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |\r\r
2591 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2592 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use\r
2593       |\r\r
2594 |   4 edge BUFIOs available, 2 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2595 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2596 |                                          |                                          |\r\r
2597 |------------------------------------------|------------------------------------------|\r\r
2598 | CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |\r\r
2599 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2600 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2601 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2602 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2603 |                                          |                                          |\r\r
2604 |------------------------------------------|------------------------------------------|\r\r
2605 \r\r
2606 \r\r
2607 Clock-Region: <CLOCKREGION_X0Y1>\r\r
2608   key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2609 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2610 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2611 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2612 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2613 |       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2614 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2615 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2616 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2617 |       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2618 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2619 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2620 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2621 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2622 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
2623 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2624 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
2625 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2626 \r\r
2627 \r\r
2628 Clock-Region: <CLOCKREGION_X0Y2>\r\r
2629   key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2630 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2631 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2632 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2633 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2634 |       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region\r\r
2635 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2636 |       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2637 |-------|-------------|------|-----|----|--------|-------\r
2638 -|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2639 |       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2640 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2641 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2642 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2643 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2644 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
2645 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2646 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
2647 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2648 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
2649 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2650 \r\r
2651 \r\r
2652 Clock-Region: <CLOCKREGION_X0Y6>\r\r
2653   key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2654 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2655 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2656 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2657 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2658 |       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2659 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2660 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2661 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2662 |       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2663 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2664 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2665 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2666 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2667 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 | \r
2668     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
2669 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2670 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
2671 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2672 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
2673 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2674 \r\r
2675 \r\r
2676 \r\r
2677 \r\r
2678 ######################################################################################\r\r
2679 # REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
2680 #\r\r
2681 # Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)\r\r
2682 # Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
2683 # composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
2684 # \r\r
2685 ######################################################################################\r\r
2686 \r\r
2687 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
2688 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2689 "BUFIO_X0Y27" ;\r\r
2690 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
2691 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2692 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
2693 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2694 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
2695 CLOCKREGION_X0Y6;\r\r
2696 \r\r
2697 \r\r
2698 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
2699 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2700 "BUFIO_X0Y9" ;\r\r
2701 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
2702 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2703 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
2704 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2705 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
2706 CLOCKREGION_X0Y2;\r\r
2707 \r\r
2708 \r\r
2709 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
2710 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2711 "BUFIO_X0Y11" ;\r\r
2712 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
2713 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2714 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
2715 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2716 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
2717 CLOCKREGION_X0Y2;\r\r
2718 \r\r
2719 \r\r
2720 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
2721 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2722 "BUFIO_X0Y4" ;\r\r
2723 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
2724 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2725 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
2726 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2727 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
2728 CLOCKREGION_X0Y1;\r\r
2729 \r\r
2730 \r\r
2731 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
2732 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2733 "BUFIO_X0Y25" ;\r\r
2734 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
2735 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2736 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
2737 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2738 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
2739 CLOCKREGION_X0Y6;\r\r
2740 \r\r
2741 \r\r
2742 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
2743 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2744 "BUFIO_X0Y7" ;\r\r
2745 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
2746 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2747 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
2748 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2749 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
2750 CLOCKREGION_X0Y1;\r\r
2751 \r\r
2752 \r\r
2753 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
2754 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2755 "BUFIO_X0Y26" ;\r\r
2756 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
2757 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2758 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
2759 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2760 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
2761 CLOCKREGION_X0Y6;\r\r
2762 \r\r
2763 \r\r
2764 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
2765 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2766 "BUFIO_X0Y10" ;\r\r
2767 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
2768 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2769 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
2770 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2771 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
2772 CLOCKREGION_X0Y2;\r\r
2773 \r\r
2774 \r\r
2775 Phase 7.2  Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
2776 \r\r
2777 Phase 8.36  Local Placement Optimization\r\r
2778 Phase 8.36  Local Placement Optimization (Checksum:7e049af9) REAL time: 9 mins 19 secs \r\r
2779 \r\r
2780 ....................\r
2781 .................\r\r
2782 .....\r
2783 ......\r
2784 .....\r
2785 ......\r
2786 .....\r
2787 .....\r
2788 ......\r
2789 ......\r
2790 .......\r
2791 ......\r
2792 .......\r
2793 .......\r
2794 .......\r
2795 ..\r\r
2796 Phase 9.30  Global Clock Region Assignment\r\r
2797 \r\r
2798 \r\r
2799 ######################################################################################\r\r
2800 # GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
2801 #\r\r
2802 # Number of Global Clock Regions : 16\r\r
2803 # Number of Global Clock Networks: 15\r\r
2804 #\r\r
2805 # Clock Region Assignment: SUCCESSFUL\r\r
2806 \r\r
2807 # Location of Clock Components\r\r
2808 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
2809 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
2810 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
2811 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
2812 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
2813 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
2814 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
2815 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
2816 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
2817 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
2818 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
2819 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
2820 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
2821 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
2822 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
2823 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
2824 INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
2825 INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
2826 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
2827 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
2828 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
2829 INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
2830 INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
2831 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
2832 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
2833 INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
2834 INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
2835 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
2836 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
2837 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
2838 INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
2839 \r\r
2840 # clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
2841 NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
2842 TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
2843 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2844 \r\r
2845 # fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
2846 NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2847 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2848 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2849 \r\r
2850 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
2851 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2852 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2853 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2854 \r\r
2855 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
2856 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2857 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2858 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2859 \r\r
2860 # clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
2861 NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2862 TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2863 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2864 \r\r
2865 # clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
2866 NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2867 TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2868 AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;\r\r
2869 \r\r
2870 # PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
2871 NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
2872 TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
2873 AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2874 \r\r
2875 # fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
2876 NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2877 TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2878 AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
2879 \r\r
2880 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
2881 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2882 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2883 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2884 \r\r
2885 # clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
2886 NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
2887 TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
2888 AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2889 \r\r
2890 # fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
2891 NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2892 TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2893 AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
2894 \r\r
2895 # fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
2896 NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2897 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2898 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2899 \r\r
2900 # clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
2901 NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2902 TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2903 AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2904 \r\r
2905 # clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
2906 NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2907 TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2908 AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2909 \r\r
2910 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
2911 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2912 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2913 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2914 \r\r
2915 # NOTE: \r\r
2916 # This report is provided to help reproduce successful clock-region \r\r
2917 # assignments. The report provides range constraints for all global \r\r
2918 # clock networks, in a format that is directly usable in ucf files. \r\r
2919 #\r\r
2920 #END of Global Clock Net Distribution UCF Constraints\r\r
2921 ######################################################################################\r\r
2922 \r\r
2923 \r\r
2924 ######################################################################################\r\r
2925 GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
2926 \r\r
2927 Number of Global Clock Regions : 16\r\r
2928 Number of Global Clock Networks: 15\r\r
2929 \r\r
2930 Clock Region Assignment: SUCCESSFUL\r\r
2931 \r\r
2932 Clock-Region: <CLOCKREGION_X0Y0> \r\r
2933  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2934 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2935    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2936    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2937 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2938      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2939 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2940         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2941 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2942       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     44 |    548 |PCIe_Bridge/Bridge_Clk\r\r
2943       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    202 |clk_125_0000MHzPLL0_ADJUST\r\r
2944 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2945       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    750 | Total \r\r
2946 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2947 \r\r
2948 \r\r
2949 Clock-Region: <CLOCKREGION_X1Y0> \r\r
2950  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2951 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2952    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2953    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2954 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2955       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2956 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2957         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2958 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2959       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     38 |    934 |PCIe_Bridge/Bridge_Clk\r\r
2960       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2961 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2962       8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |     62 |    986 | Total \r\r
2963 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2964 \r\r
2965 \r\r
2966 Clock-Region: <CLOCKREGION_X0Y1> \r\r
2967  key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
2968 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2969    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2970    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2971 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2972      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2973 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2974         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2975 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2976       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     13 |    195 |PCIe_Bridge/Bridge_Clk\r\r
2977       0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clk_125_0000MHz90PLL0_ADJUST\r\r
2978       0 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    719 |clk_125_0000MHzPLL0_ADJUST\r\r
2979       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2980       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |clk_62_5000MHzPLL0_ADJUST\r\r
2981       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
2982 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2983       0 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     17 |    918 | Total \r\r
2984 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2985 \r\r
2986 \r\r
2987 Clock-Region: <CLOCKREGION_X1Y1> \r\r
2988  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2989 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2990    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2991    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2992 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2993       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2994 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2995         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2996 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2997       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    500 |PCIe_Bridge/Bridge_Clk\r\r
2998       1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2999       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |    364 |clk_125_0000MHzPLL0_ADJUST\r\r
3000       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
3001 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3002       1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |    884 | Total \r\r
3003 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3004 \r\r
3005 \r\r
3006 Clock-Region: <CLOCKREGION_X0Y2> \r\r
3007  key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
3008 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3009    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3010    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3011 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3012      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
3013 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3014         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3015 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3016       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/Bridge_Clk\r\r
3017       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |clk_125_0000MHz90PLL0_ADJUST\r\r
3018       5 |      0 |      0 |      0 |      9 |     15 |      0 |      0 |      0 |      0 |      0 |      0 |     58 |    913 |clk_125_0000MHzPLL0_ADJUST\r\r
3019       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
3020       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    142 |clk_62_5000MHzPLL0_ADJUST\r\r
3021 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3022       7 |      0 |      0 |      0 |      9 |     42 |      0 |      0 |      0 |      0 |      1 |      0 |     58 |   1072 | Total \r\r
3023 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3024 \r\r
3025 \r\r
3026 Clock-Region: <CLOCKREGION_X1Y2> \r\r
3027  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
3028 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3029    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3030    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3031 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3032       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3033 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3034         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3035 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3036       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     94 |    387 |PCIe_Bridge/Bridge_Clk\r\r
3037       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
3038       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
3039       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |    500 |clk_125_0000MHzPLL0_ADJUST\r\r
3040 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3041       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    130 |    970 | Total \r\r
3042 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3043 \r\r
3044 \r\r
3045 Clock-Region: <CLOCKREGION_X0Y3> \r\r
3046  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
3047 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3048    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3049    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3050 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3051       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
3052 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3053         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3054 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3055       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |clk_125_0000MHz90PLL0_ADJUST\r\r
3056       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     36 |    272 |clk_125_0000MHzPLL0_ADJUST\r\r
3057       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz\r\r
3058       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    154 |clk_62_5000MHzPLL0_ADJUST\r\r
3059 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3060       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     36 |    512 | Total \r\r
3061 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3062 \r\r
3063 \r\r
3064 Clock-Region: <CLOCKREGION_X1Y3> \r\r
3065  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
3066 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3067    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3068    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3069 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3070       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3071 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3072         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3073 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3074       3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     44 |    290 |PCIe_Bridge/Bridge_Clk\r\r
3075       6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    659 |clk_125_0000MHzPLL0_ADJUST\r\r
3076       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
3077 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3078       9 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     66 |    950 | Total \r\r
3079 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3080 \r\r
3081 \r\r
3082 Clock-Region: <CLOCKREGION_X0Y4> \r\r
3083  key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
3084 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3085    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3086    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3087 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3088       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
3089 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3090         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3091 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3092       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      1 |PCIe_Bridge/Bridge_Clk\r\r
3093       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |clk_125_0000MHz90PLL0_ADJUST\r\r
3094       4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    231 |clk_125_0000MHzPLL0_ADJUST\r\r
3095       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    200 |clk_62_5000MHzPLL0_ADJUST\r\r
3096       0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
3097 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3098       6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     18 |    466 | Total \r\r
3099 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3100 \r\r
3101 \r\r
3102 Clock-Region: <CLOCKREGION_X1Y4> \r\r
3103  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
3104 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3105    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3106    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3107 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3108      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3109 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3110         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3111 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3112       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     54 |    367 |PCIe_Bridge/Bridge_Clk\r\r
3113       3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |    602 |clk_125_0000MHzPLL0_ADJUST\r\r
3114       0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
3115 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3116       3 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     74 |    985 | Total \r\r
3117 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3118 \r\r
3119 \r\r
3120 Clock-Region: <CLOCKREGION_X0Y5> \r\r
3121  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
3122 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3123    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3124    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3125 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3126      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
3127 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3128         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3129 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3130       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |      2 |PCIe_Bridge/Bridge_Clk\r\r
3131       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST\r\r
3132       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    517 |clk_125_0000MHzPLL0_ADJUST\r\r
3133       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    206 |clk_62_5000MHzPLL0_ADJUST\r\r
3134 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3135       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    773 | Total \r\r
3136 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3137 \r\r
3138 \r\r
3139 Clock-Region: <CLOCKREGION_X1Y5> \r\r
3140  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
3141 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3142    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3143    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3144 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3145      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3146 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3147         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3148 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3149       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     68 |    285 |PCIe_Bridge/Bridge_Clk\r\r
3150       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     50 |    333 |clk_125_0000MHzPLL0_ADJUST\r\r
3151       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
3152 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3153       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    118 |    639 | Total \r\r
3154 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3155 \r\r
3156 \r\r
3157 Clock-Region: <CLOCKREGION_X0Y6> \r\r
3158  key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
3159 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3160    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3161    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3162 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3163      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
3164 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3165         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3166 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3167       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
3168       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
3169       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST\r\r
3170       0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    605 |clk_125_0000MHzPLL0_ADJUST\r\r
3171       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
3172       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    158 |clk_62_5000MHzPLL0_ADJUST\r\r
3173       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |     12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
3174 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3175       0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     27 |    777 | Total \r\r
3176 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3177 \r\r
3178 \r\r
3179 Clock-Region: <CLOCKREGION_X1Y6> \r\r
3180  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
3181 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3182    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3183    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3184 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3185       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3186 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3187         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3188 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3189       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    103 |PCIe_Bridge/Bridge_Clk\r\r
3190       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    413 |clk_125_0000MHzPLL0_ADJUST\r\r
3191 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3192       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     26 |    516 | Total \r\r
3193 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3194 \r\r
3195 \r\r
3196 Clock-Region: <CLOCKREGION_X0Y7> \r\r
3197  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
3198 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3199    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3200    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3201 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3202      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
3203 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3204         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3205 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3206       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    495 |clk_125_0000MHzPLL0_ADJUST\r\r
3207       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     19 |clk_62_5000MHzPLL0_ADJUST\r\r
3208 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3209       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    514 | Total \r\r
3210 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3211 \r\r
3212 \r\r
3213 Clock-Region: <CLOCKREGION_X1Y7> \r\r
3214  key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
3215 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3216    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
3217    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3218 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3219       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3220 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3221         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3222 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3223       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 |clk_125_0000MHzPLL0_ADJUST\r\r
3224 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3225       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 | Total \r\r
3226 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3227 \r\r
3228 NOTE:\r\r
3229 The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
3230 may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
3231 maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
3232 \r\r
3233 \r\r
3234 # END of Global Clock Net Loads Distribution Report:\r\r
3235 ######################################################################################\r\r
3236 \r\r
3237 \r\r
3238 Phase 9.30  Global Clock Region Assignment (Checksum:7e049af9) REAL time: 10 mins 42 secs \r\r
3239 \r\r
3240 Phase 10.3  Local Placement Optimization\r\r
3241 Phase 10.3  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs \r\r
3242 \r\r
3243 Phase 11.5  Local Placement Optimization\r\r
3244 Phase 11.5  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 45 secs \r\r
3245 \r\r
3246 Phase 12.8  Global Placement\r\r
3247 .............................\r
3248 ....\r\r
3249 .\r
3250 .......\r
3251 .....\r
3252 .......\r
3253 .......\r
3254 .......\r
3255 ......\r
3256 ........\r
3257 ........\r
3258 ........\r
3259 .........\r
3260 .........\r
3261 .........\r\r
3262 .\r
3263 .......\r
3264 ......\r
3265 ........\r
3266 .......\r
3267 .........\r
3268 ........\r
3269 .........\r
3270 .......\r\r
3271 .\r
3272 .......\r
3273 .....\r
3274 .......\r
3275 .\r
3276 ....\r
3277 ...\r
3278 ...\r
3279 ......\r
3280 ......\r
3281 ......\r
3282 ....\r
3283 .......\r
3284 ......\r
3285 ....\r
3286 .\r
3287 ......\r
3288 ......\r
3289 ......\r\r
3290 ....\r
3291 ......\r
3292 .\r
3293 ....\r
3294 ...\r
3295 ....\r
3296 .......\r
3297 ......\r
3298 ....\r
3299 ...\r
3300 .......\r
3301 .........\r\r
3302 ..\r
3303 .\r
3304 .....\r
3305 ..\r
3306 ...\r
3307 .......\r
3308 ......\r
3309 .....\r
3310 ......\r
3311 .....\r
3312 ......\r
3313 ......\r
3314 ......\r
3315 .....\r\r
3316 .\r
3317 .....\r
3318 ..\r
3319 .....\r
3320 ...\r\r
3321 ..\r
3322 ......\r
3323 .......\r
3324 .......\r
3325 ........\r
3326 ...\r\r
3327 Phase 12.8  Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
3328 \r\r
3329 Phase 13.29  Local Placement Optimization\r\r
3330 Phase 13.29  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 18 secs \r\r
3331 \r\r
3332 Phase 14.5  Local Placement Optimization\r\r
3333 Phase 14.5  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs \r\r
3334 \r\r
3335 Phase 15.18  Placement Optimization\r\r
3336 Phase 15.18  Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 1 secs \r\r
3337 \r\r
3338 Phase 16.5  Local Placement Optimization\r\r
3339 Phase 16.5  Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs \r\r
3340 \r\r
3341 Phase 17.34  Placement Validation\r\r
3342 Phase 17.34  Placement Validation (Checksum:f81b02a1) REAL time: 18 mins 5 secs \r\r
3343 \r\r
3344 Total REAL time to Placer completion: 18 mins 7 secs \r\r
3345 Total CPU  time to Placer completion: 17 mins 4 secs \r\r
3346 Running post-placement packing...\r\r
3347 Writing output files...\r\r
3348 \r\r
3349 Design Summary:\r\r
3350 Number of errors:      0\r\r
3351 Number of warnings:   50\r\r
3352 Slice Logic Utilization:\r\r
3353   Number of Slice Registers:                12,128 out of  44,800   27%\r\r
3354     Number used as Flip Flops:              12,127\r\r
3355     Number used as Latches:                      1\r\r
3356   Number of Slice LUTs:                     12,266 out of  44,800   27%\r\r
3357     Number used as logic:                   11,767 out of  44,800   26%\r\r
3358       Number using O6 output only:          10,791\r\r
3359       Number using O5 output only:             282\r\r
3360       Number using O5 and O6:                  694\r\r
3361     Number used as Memory:                     392 out of  13,120    2%\r\r
3362       Number used as Dual Port RAM:             56\r\r
3363         Number using O6 output only:            12\r\r
3364         Number using O5 and O6:                 44\r\r
3365       Number used as Single Port RAM:            4\r\r
3366         Number using O6 output only:             4\r\r
3367       Number used as Shift Register:           332\r\r
3368         Number using O6 output only:           332\r\r
3369     Number used as exclusive route-thru:       107\r\r
3370   Number of route-thrus:                       438\r\r
3371     Number using O6 output only:               382\r\r
3372     Number using O5 output only:                51\r\r
3373     Number using O5 and O6:                      5\r\r
3374 \r\r
3375 Slice Logic Distribution:\r\r
3376   Number of occupied Slices:                 6,488 out of  11,200   57%\r\r
3377   Number of LUT Flip Flop pairs used:       17,046\r\r
3378     Number with an unused Flip Flop:         4,918 out of  17,046   28%\r\r
3379     Number with an unused LUT:               4,780 out of  17,046   28%\r\r
3380     Number of fully used LUT-FF pairs:       7,348 out of  17,046   43%\r\r
3381     Number of unique control sets:           1,288\r\r
3382     Number of slice register sites lost\r\r
3383       to control set restrictions:           3,000 out of  44,800    6%\r\r
3384 \r\r
3385   A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
3386   one Flip Flop within a slice.  A control set is a unique combination of\r\r
3387   clock, reset, set, and enable signals for a registered element.\r\r
3388   The Slice Logic Distribution report is not meaningful if the design is\r\r
3389   over-mapped for a non-slice resource or if Placement fails.\r\r
3390   OVERMAPPING of BRAM resources should be ignored if the design is\r\r
3391   over-mapped for a non-BRAM resource or if placement fails.\r\r
3392 \r\r
3393 IO Utilization:\r\r
3394   Number of bonded IOBs:                       255 out of     640   39%\r\r
3395     Number of LOCed IOBs:                      255 out of     255  100%\r\r
3396     IOB Flip Flops:                            494\r\r
3397     Number of bonded IPADs:                      4 out of      50    8%\r\r
3398     Number of bonded OPADs:                      2 out of      32    6%\r\r
3399 \r\r
3400 Specific Feature Utilization:\r\r
3401   Number of BlockRAM/FIFO:                      23 out of     148   15%\r\r
3402     Number using BlockRAM only:                 21\r\r
3403     Number using FIFO only:                      2\r\r
3404     Total primitives used:\r\r
3405       Number of 36k BlockRAM used:              16\r\r
3406       Number of 18k BlockRAM used:               6\r\r
3407       Number of 36k FIFO used:                   2\r\r
3408     Total Memory used (KB):                    756 out of   5,328   14%\r\r
3409   Number of BUFG/BUFGCTRLs:                     15 out of      32   46%\r\r
3410     Number used as BUFGs:                       15\r\r
3411   Number of IDELAYCTRLs:                         3 out of      22   13%\r\r
3412   Number of BUFDSs:                              1 out of       8   12%\r\r
3413   Number of BUFIOs:                              8 out of      80   10%\r\r
3414   Number of DCM_ADVs:                            1 out of      12    8%\r\r
3415   Number of GTX_DUALs:                           1 out of       8   12%\r\r
3416   Number of PCIEs:                               1 out of       3   33%\r\r
3417     Number of LOCed PCIEs:                       1 out of       1  100%\r\r
3418   Number of PLL_ADVs:                            2 out of       6   33%\r\r
3419   Number of PPC440s:                             1 out of       1  100%\r\r
3420 \r\r
3421   Number of RPM macros:           64\r\r
3422 Average Fanout of Non-Clock Nets:                3.76\r\r
3423 \r\r
3424 Peak Memory Usage:  701 MB\r\r
3425 Total REAL time to MAP completion:  18 mins 45 secs \r\r
3426 Total CPU time to MAP completion:   17 mins 40 secs \r\r
3427 \r\r
3428 Mapping completed.\r\r
3429 See MAP report file "system_map.mrp" for details.\r\r
3430 \r\r
3431 \r\r
3432 \r\r
3433 #----------------------------------------------#\r\r
3434 # Starting program par\r\r
3435 # par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
3436 system.pcf \r\r
3437 #----------------------------------------------#\r\r
3438 Release 11.2 - par L.46 (nt)\r\r
3439 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3440 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
3441 <c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
3442 \r\r
3443 \r\r
3444 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3445 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3446    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3447 \r\r
3448 Constraints file: system.pcf.\r\r
3449    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3450 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]\r\r
3451    overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
3452 \r\r
3453 \r\r
3454 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
3455 Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
3456 \r\r
3457 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP       \r\r
3458    "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
3459 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please\r\r
3460    consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
3461 \r\r
3462 Device speed data version:  "PRODUCTION 1.65 2009-06-01".\r\r
3463 \r\r
3464 \r\r
3465 \r\r
3466 Device Utilization Summary:\r\r
3467 \r\r
3468    Number of BUFDSs                          1 out of 8      12%\r\r
3469    Number of BUFGs                          15 out of 32     46%\r\r
3470    Number of BUFIOs                          8 out of 80     10%\r\r
3471    Number of DCM_ADVs                        1 out of 12      8%\r\r
3472    Number of FIFO36_72_EXPs                  2 out of 148     1%\r\r
3473       Number of LOCed FIFO36_72_EXPs         2 out of 2     100%\r\r
3474 \r\r
3475    Number of GTX_DUALs                       1 out of 8      12%\r\r
3476    Number of IDELAYCTRLs                     3 out of 22     13%\r\r
3477       Number of LOCed IDELAYCTRLs            3 out of 3     100%\r\r
3478 \r\r
3479    Number of ILOGICs                       131 out of 800    16%\r\r
3480       Number of LOCed ILOGICs                8 out of 131     6%\r\r
3481 \r\r
3482    Number of External IOBs                 255 out of 640    39%\r\r
3483       Number of LOCed IOBs                 255 out of 255   100%\r\r
3484 \r\r
3485    Number of IODELAYs                       80 out of 800    10%\r\r
3486       Number of LOCed IODELAYs               8 out of 80     10%\r\r
3487 \r\r
3488    Number of External IPADs                  4 out of 690     1%\r\r
3489       Number of LOCed IPADs                  4 out of 4     100%\r\r
3490 \r\r
3491    Number of JTAGPPCs                        1 out of 1     100%\r\r
3492    Number of OLOGICs                       236 out of 800    29%\r\r
3493    Number of External OPADs                  2 out of 32      6%\r\r
3494       Number of LOCed OPADs                  2 out of 2     100%\r\r
3495 \r\r
3496    Number of PCIEs                           1 out of 3      33%\r\r
3497       Number of LOCed PCIEs                  1 out of 1     100%\r\r
3498 \r\r
3499    Number of PLL_ADVs                        2 out of 6      33%\r\r
3500    Number of PPC440s                         1 out of 1     100%\r\r
3501    Number of RAMB18X2SDPs                    5 out of 148     3%\r\r
3502    Number of RAMB36SDP_EXPs                  6 out of 148     4%\r\r
3503       Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%\r\r
3504 \r\r
3505    Number of RAMB36_EXPs                    10 out of 148     6%\r\r
3506       Number of LOCed RAMB36_EXPs            6 out of 10     60%\r\r
3507 \r\r
3508    Number of Slice Registers             12128 out of 44800  27%\r\r
3509       Number used as Flip Flops          12127\r\r
3510       Number used as Latches                 1\r\r
3511       Number used as LatchThrus              0\r\r
3512 \r\r
3513    Number of Slice LUTS                  12266 out of 44800  27%\r\r
3514    Number of Slice LUT-Flip Flop pairs   17046 out of 44800  38%\r\r
3515 \r\r
3516 \r\r
3517 Overall effort level (-ol):   High \r\r
3518 Router effort level (-rl):    High \r\r
3519 \r\r
3520 Starting initial Timing Analysis.  REAL time: 51 secs \r\r
3521 Finished initial Timing Analysis.  REAL time: 52 secs \r\r
3522 \r\r
3523 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this\r\r
3524    signal.\r\r
3525 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this\r\r
3526    signal.\r\r
3527 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this\r\r
3528    signal.\r\r
3529 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this\r\r
3530    signal.\r\r
3531 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this\r\r
3532    signal.\r\r
3533 Starting Router\r\r
3534 \r\r
3535 INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
3536    that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
3537    verify that the same connectivity is available in the target device for this implementation. \r\r
3538 \r\r
3539 Phase  1  : 82160 unrouted;      REAL time: 1 mins 9 secs \r\r
3540 \r\r
3541 Phase  2  : 72970 unrouted;      REAL time: 1 mins 22 secs \r\r
3542 \r\r
3543 Phase  3  : 28783 unrouted;      REAL time: 3 mins 31 secs \r\r
3544 \r\r
3545 Phase  4  : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0)     REAL time: 3 mins 57 secs \r\r
3546 \r\r
3547 Updating file: system.ncd with current fully routed design.\r\r
3548 \r\r
3549 Phase  5  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
3550 \r\r
3551 Phase  6  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
3552 \r\r
3553 Phase  7  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
3554 \r\r
3555 Phase  8  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs \r\r
3556 \r\r
3557 Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 25 secs \r\r
3558 \r\r
3559 Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 57 secs \r\r
3560 Total REAL time to Router completion: 7 mins 57 secs \r\r
3561 Total CPU time to Router completion: 7 mins 31 secs \r\r
3562 \r\r
3563 Partition Implementation Status\r\r
3564 -------------------------------\r\r
3565 \r\r
3566   No Partitions were found in this design.\r\r
3567 \r\r
3568 -------------------------------\r\r
3569 \r\r
3570 Generating "PAR" statistics.\r\r
3571 \r\r
3572 **************************\r\r
3573 Generating Clock Report\r\r
3574 **************************\r\r
3575 \r\r
3576 +---------------------+--------------+------+------+------------+-------------+\r\r
3577 |        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
3578 +---------------------+--------------+------+------+------------+-------------+\r\r
3579 |clk_125_0000MHzPLL0_ |              |      |      |            |             |\r\r
3580 |              ADJUST | BUFGCTRL_X0Y2| No   | 3176 |  0.533     |  2.076      |\r\r
3581 +---------------------+--------------+------+------+------------+-------------+\r\r
3582 |PCIe_Bridge/Bridge_C |              |      |      |            |             |\r\r
3583 |                  lk |BUFGCTRL_X0Y28| No   | 1481 |  0.519     |  2.085      |\r\r
3584 +---------------------+--------------+------+------+------------+-------------+\r\r
3585 |clk_62_5000MHzPLL0_A |              |      |      |            |             |\r\r
3586 |               DJUST | BUFGCTRL_X0Y6| No   |  501 |  0.313     |  2.062      |\r\r
3587 +---------------------+--------------+------+------+------------+-------------+\r\r
3588 |clk_125_0000MHz90PLL |              |      |      |            |             |\r\r
3589 |            0_ADJUST | BUFGCTRL_X0Y5| No   |  165 |  0.262     |  2.028      |\r\r
3590 +---------------------+--------------+------+------+------------+-------------+\r\r
3591 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3592 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3593 |comp_endpoint/core_c |              |      |      |            |             |\r\r
3594 |                  lk |BUFGCTRL_X0Y27| No   |   92 |  0.338     |  2.085      |\r\r
3595 +---------------------+--------------+------+------+------------+-------------+\r\r
3596 |fpga_0_SysACE_Compac |              |      |      |            |             |\r\r
3597 |tFlash_SysACE_CLK_pi |              |      |      |            |             |\r\r
3598 |             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.171     |  1.797      |\r\r
3599 +---------------------+--------------+------+------+------------+-------------+\r\r
3600 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3601 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3602 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3603 |        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.065     |  1.886      |\r\r
3604 +---------------------+--------------+------+------+------------+-------------+\r\r
3605 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3606 |PHY_rx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3607 |                     |BUFGCTRL_X0Y30| No   |   12 |  0.086     |  1.874      |\r\r
3608 +---------------------+--------------+------+------+------------+-------------+\r\r
3609 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3610 |PHY_tx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3611 |                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |\r\r
3612 +---------------------+--------------+------+------+------------+-------------+\r\r
3613 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3614 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3615 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3616 | y_io/delayed_dqs<0> |        IO Clk| No   |   18 |  0.095     |  0.419      |\r\r
3617 +---------------------+--------------+------+------+------------+-------------+\r\r
3618 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3619 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3620 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3621 | y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |\r\r
3622 +---------------------+--------------+------+------+------------+-------------+\r\r
3623 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3624 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3625 |f_top/u_phy_top/u_ph |              |      |\r
3626       |            |             |\r\r
3627 | y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3628 +---------------------+--------------+------+------+------------+-------------+\r\r
3629 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3630 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3631 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3632 | y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |\r\r
3633 +---------------------+--------------+------+------+------------+-------------+\r\r
3634 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3635 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3636 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3637 | y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3638 +---------------------+--------------+------+------+------------+-------------+\r\r
3639 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3640 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3641 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3642 | y_io/delayed_dqs<4> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3643 +---------------------+--------------+------+------+------------+-------------+\r\r
3644 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3645 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3646 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3647 | y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |\r\r
3648 +---------------------+--------------+------+------+------------+-------------+\r\r
3649 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3650 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3651 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3652 | y_io/delayed_dqs<7> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3653 +---------------------+--------------+------+------+------------+-------------+\r\r
3654 | clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No   |    2 |  0.000     |  1.739      |\r\r
3655 +---------------------+--------------+------+------+------------+-------------+\r\r
3656 |     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.100     |  1.879      |\r\r
3657 +---------------------+--------------+------+------+------------+-------------+\r\r
3658 |RS232_Uart_1_Interru |              |      |      |            |             |\r\r
3659 |                  pt |         Local|      |    1 |  0.000     |  0.625      |\r\r
3660 +---------------------+--------------+------+------+------------+-------------+\r\r
3661 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3662 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3663 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3664 |lk/SIO/.pcie_gt_wrap |              |      |      |            |             |\r\r
3665 |  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.590      |\r\r
3666 +---------------------+--------------+------+------+------------+-------------+\r\r
3667 |Ethernet_MAC/Etherne |              |      |      |            |             |\r\r
3668 |  t_MAC/phy_tx_clk_i |         Local|      |    9 |  3.273     |  3.994      |\r\r
3669 +---------------------+--------------+------+------+------------+-------------+\r\r
3670 |ppc440_0_jtagppc_bus |              |      |      |            |             |\r\r
3671 |         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.699      |\r\r
3672 +---------------------+--------------+------+------+------------+-------------+\r\r
3673 \r\r
3674 * Net Skew is the difference between the minimum and maximum routing\r\r
3675 only delays for the net. Note this is different from Clock Skew which\r\r
3676 is reported in TRCE timing report. Clock Skew is the difference between\r\r
3677 the minimum and maximum path delays which includes logic delays.\r\r
3678 \r\r
3679 Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
3680 \r\r
3681 Number of Timing Constraints that were not applied: 5\r\r
3682 \r\r
3683 Asterisk (*) preceding a constraint indicates it was not met.\r\r
3684    This may be due to a setup or hold violation.\r\r
3685 \r\r
3686 ----------------------------------------------------------------------------------------------------------\r\r
3687   Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   \r\r
3688                                             |             |    Slack   | Achievable | Errors |    Score   \r\r
3689 ----------------------------------------------------------------------------------------------------------\r\r
3690   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.026ns|     7.974ns|       0|           0\r\r
3691   s HIGH 50%                                | HOLD        |     0.030ns|            |       0|           0\r\r
3692                                             | MINPERIOD   |     0.000ns|     8.000ns|       0|           0\r\r
3693 ------------------------------------------------------------------------------------------------------\r\r
3694   NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.026ns|     3.974ns|       0|           0\r\r
3695   lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.315ns|            |       0|           0\r\r
3696       4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0\r\r
3697 ------------------------------------------------------------------------------------------------------\r\r
3698   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.012ns|     0.838ns|       0|           0\r\r
3699   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3700   dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3701   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3702 ------------------------------------------------------------------------------------------------------\r\r
3703   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.015ns|     0.835ns|       0|           0\r\r
3704   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3705   dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3706   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3707 ------------------------------------------------------------------------------------------------------\r\r
3708   TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP       |     0.021ns|     1.879ns|       0|           0\r\r
3709   CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0\r\r
3710      1.9 ns                                 |             |            |            |        |            \r\r
3711 ------------------------------------------------------------------------------------------------------\r\r
3712   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     0.027ns|     7.973ns|       0|           0\r\r
3713   L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0\r\r
3714   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3715   LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3716   HIGH 50%                                  |             |            |            |        |            \r\r
3717 ------------------------------------------------------------------------------------------------------\r\r
3718   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3719   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3720   dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3721   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3722 ------------------------------------------------------------------------------------------------------\r\r
3723   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3724   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3725   dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3726   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3727 ------------------------------------------------------------------------------------------------------\r\r
3728   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3729   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3730   dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3731   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3732 ------------------------------------------------------------------------------------------------------\r\r
3733   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3734   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3735   dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3736   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3737 ------------------------------------------------------------------------------------------------------\r\r
3738   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3739   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3740   dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3741   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3742 ------------------------------------------------------------------------------------------------------\r\r
3743   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3744   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3745   dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3746   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3747 ------------------------------------------------------------------------------------------------------\r\r
3748   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.068ns|     0.532ns|       0|           0\r\r
3749   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3750   qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3751 ------------------------------------------------------------------------------------------------------\r\r
3752   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3753   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3754   qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3755 ------------------------------------------------------------------------------------------------------\r\r
3756   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3757   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3758   qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3759 ------------------------------------------------------------------------------------------------------\r\r
3760   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3761   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3762   qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3763 ------------------------------------------------------------------------------------------------------\r\r
3764   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3765   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3766   qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3767 ------------------------------------------------------------------------------------------------------\r\r
3768   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3769   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3770   qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3771 ------------------------------------------------------------------------------------------------------\r\r
3772   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3773   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3774   qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3775 ------------------------------------------------------------------------------------------------------\r\r
3776   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3777   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3778   qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3779 ------------------------------------------------------------------------------------------------------\r\r
3780   TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.188ns|     7.812ns|       0|           0\r\r
3781   ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.516ns|            |       0|           0\r\r
3782     DATAPATHONLY                            |             |            |            |        |            \r\r
3783 ------------------------------------------------------------------------------------------------------\r\r
3784   TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0\r\r
3785   HIGH 50%                                  |             |            |            |        |            \r\r
3786 ------------------------------------------------------------------------------------------------------\r\r
3787   TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     1.252ns|     6.748ns|       0|           0\r\r
3788   _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.451ns|            |       0|           0\r\r
3789     DATAPATHONLY                            |             |            |            |        |            \r\r
3790 ------------------------------------------------------------------------------------------------------\r\r
3791   TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.700ns|     4.300ns|       0|           0\r\r
3792   RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0\r\r
3793   thernet_MAC" 6 ns                         |             |            |            |        |            \r\r
3794 ------------------------------------------------------------------------------------------------------\r\r
3795   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.073ns|     5.466ns|       0|           0\r\r
3796   L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.307ns|            |       0|           0\r\r
3797   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3798   LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3799   PHASE 2 ns HIGH 50%                       |             |            |            |        |            \r\r
3800 ------------------------------------------------------------------------------------------------------\r\r
3801   TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0\r\r
3802   pin" 100 MHz HIGH 50%                     |             |            |            |        |            \r\r
3803 ------------------------------------------------------------------------------------------------------\r\r
3804   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.700ns|     8.600ns|       0|           0\r\r
3805   L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.153ns|            |       0|           0\r\r
3806   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3807   LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |            \r\r
3808    HIGH 50%                                 |             |            |            |        |            \r\r
3809 ------------------------------------------------------------------------------------------------------\r\r
3810   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.950ns|     1.050ns|       0|           0\r\r
3811   L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0\r\r
3812   lock_generator_0_clock_generator_0_PLL0_C | MINLOWPULSE |     3.946ns|     1.054ns|       0|           0\r\r
3813   LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |            \r\r
3814   H 50%                                     |             |            |            |        |            \r\r
3815 ------------------------------------------------------------------------------------------------------\r\r
3816   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.392ns|     0.608ns|       0|           0\r\r
3817   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3818 ------------------------------------------------------------------------------------------------------\r\r
3819   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.789ns|     0.211ns|       0|           0\r\r
3820   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3821 ------------------------------------------------------------------------------------------------------\r\r
3822   TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0\r\r
3823   L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |            \r\r
3824   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3825   LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3826   HIGH 50%                                  |             |            |            |        |            \r\r
3827 ------------------------------------------------------------------------------------------------------\r\r
3828   TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0\r\r
3829   GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |            \r\r
3830   IMEGRP "PADS" 10 ns                       |             |            |            |        |            \r\r
3831 ------------------------------------------------------------------------------------------------------\r\r
3832   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |    10.092ns|    11.165ns|       0|           0\r\r
3833   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.473ns|            |       0|           0\r\r
3834 ------------------------------------------------------------------------------------------------------\r\r
3835   TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    13.832ns|     6.168ns|       0|           0\r\r
3836   M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.471ns|            |       0|           0\r\r
3837       TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |            \r\r
3838 ------------------------------------------------------------------------------------------------------\r\r
3839   TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    16.202ns|     3.798ns|       0|           0\r\r
3840    TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.049ns|            |       0|           0\r\r
3841      TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |            \r\r
3842 ------------------------------------------------------------------------------------------------------\r\r
3843   TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.943ns|     2.057ns|       0|           0\r\r
3844   NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.295ns|            |       0|           0\r\r
3845     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3846 ------------------------------------------------------------------------------------------------------\r\r
3847   TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.975ns|     2.025ns|       0|           0\r\r
3848   NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.030ns|            |       0|           0\r\r
3849     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3850 ------------------------------------------------------------------------------------------------------\r\r
3851   TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.085ns|     1.915ns|       0|           0\r\r
3852   P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.096ns|            |       0|           0\r\r
3853   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3854 ------------------------------------------------------------------------------------------------------\r\r
3855   NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.710ns|     3.290ns|       0|           0\r\r
3856   K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.465ns|            |       0|           0\r\r
3857    HIGH 50%                                 |             |            |            |        |            \r\r
3858 ------------------------------------------------------------------------------------------------------\r\r
3859   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.431ns|     7.569ns|       0|           0\r\r
3860   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.351ns|            |       0|           0\r\r
3861 ------------------------------------------------------------------------------------------------------\r\r
3862   Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0\r\r
3863 ------------------------------------------------------------------------------------------------------\r\r
3864   TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3865   P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |            \r\r
3866   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3867 ------------------------------------------------------------------------------------------------------\r\r
3868   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3869   s HIGH 50%                                |             |            |            |        |            \r\r
3870 ------------------------------------------------------------------------------------------------------\r\r
3871 \r\r
3872 \r\r
3873 Derived Constraint Report\r\r
3874 Derived Constraints for TS_MC_CLK\r\r
3875 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3876 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3877 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3878 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3879 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3880 |TS_MC_CLK                      |      5.000ns|      3.990ns|      1.542ns|            0|            0|            0|          345|\r\r
3881 | TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      3.798ns|          N/A|            0|            0|           21|            0|\r\r
3882 | TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      6.168ns|          N/A|            0|            0|          274|            0|\r\r
3883 | TS_MC_GATE_DLY                |     20.000ns|      2.025ns|          N/A|            0|            0|           40|            0|\r\r
3884 | TS_MC_RDEN_DLY                |     20.000ns|      2.057ns|          N/A|            0|            0|            5|            0|\r\r
3885 | TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.915ns|          N/A|            0|            0|            5|            0|\r\r
3886 | TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|\r\r
3887 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3888 \r\r
3889 Derived Constraints for TS_sys_clk_pin\r\r
3890 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3891 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3892 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3893 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3894 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3895 |TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.966ns|            0|            0|            0|       636358|\r\r
3896 | TS_clock_generator_0_clock_gen|      8.000ns|      5.466ns|          N/A|            0|            0|          626|            0|\r\r
3897 | erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |\r\r
3898 | TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|\r\r
3899 | erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |\r\r
3900 | TS_clock_generator_0_clock_gen|      8.000ns|      7.973ns|          N/A|            0|            0|       624688|            0|\r\r
3901 | erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |\r\r
3902 | TS_clock_generator_0_clock_gen|      5.000ns|      1.054ns|          N/A|            0|            0|            2|            0|\r\r
3903 | erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |\r\r
3904 | TS_clock_generator_0_clock_gen|     16.000ns|      8.600ns|          N/A|            0|            0|        11042|            0|\r\r
3905 | erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |\r\r
3906 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3907 \r\r
3908 All constraints were met.\r\r
3909 INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
3910    constraint does not cover any paths or that it has no requested value.\r\r
3911 \r\r
3912 \r\r
3913 Generating Pad Report.\r\r
3914 \r\r
3915 All signals are completely routed.\r\r
3916 \r\r
3917 WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
3918 \r\r
3919 Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
3920 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3921 INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
3922 INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
3923    found: 128, number successful: 128\r\r
3924 Total REAL time to PAR completion: 9 mins 1 secs \r\r
3925 Total CPU time to PAR completion: 8 mins 19 secs \r\r
3926 \r\r
3927 Peak Memory Usage:  653 MB\r\r
3928 \r\r
3929 Placer: Placement generated during map.\r\r
3930 Routing: Completed - No errors found.\r\r
3931 Timing: Completed - No errors found.\r\r
3932 \r\r
3933 Number of error messages: 0\r\r
3934 Number of warning messages: 9\r\r
3935 Number of info messages: 4\r\r
3936 \r\r
3937 Writing design to file system.ncd\r\r
3938 \r\r
3939 \r\r
3940 \r\r
3941 PAR done!\r\r
3942 \r\r
3943 \r\r
3944 \r\r
3945 #----------------------------------------------#\r\r
3946 # Starting program post_par_trce\r\r
3947 # trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
3948 #----------------------------------------------#\r\r
3949 Release 11.2 - Trace  (nt)\r\r
3950 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3951 \r\r
3952 \r\r
3953 PMSPEC -- Overriding Xilinx file\r\r
3954 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
3955 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
3956 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3957 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3958    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3959 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
3960    8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET\r\r
3961    "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].\r\r
3962 \r\r
3963 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
3964    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;\r\r
3965    ignored during timing analysis.\r\r
3966 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more\r\r
3967    information, see the TSI report.  Please consult the Xilinx Command Line\r\r
3968    Tools User Guide for information on generating a TSI report.\r\r
3969 --------------------------------------------------------------------------------\r\r
3970 Release 11.2 Trace  (nt)\r\r
3971 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3972 \r\r
3973 trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
3974 \r\r
3975 \r\r
3976 Design file:              system.ncd\r\r
3977 Physical constraint file: system.pcf\r\r
3978 Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
3979 level 0)\r\r
3980 Report level:             error report\r\r
3981 --------------------------------------------------------------------------------\r\r
3982 \r\r
3983 INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
3984    option. All paths that are not constrained will be reported in the\r\r
3985    unconstrained paths section(s) of the report.\r\r
3986 INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
3987    50 Ohm transmission line loading model.  For the details of this model, and\r\r
3988    for more information on accounting for different loading conditions, please\r\r
3989    see the device datasheet.\r\r
3990 \r\r
3991 \r\r
3992 Timing summary:\r\r
3993 ---------------\r\r
3994 \r\r
3995 Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)\r\r
3996 \r\r
3997 Constraints cover 826342 paths, 18 nets, and 74598 connections\r\r
3998 \r\r
3999 Design statistics:\r\r
4000    Minimum period:  11.165ns (Maximum frequency:  89.566MHz)\r\r
4001    Maximum path delay from/to any node:   7.812ns\r\r
4002    Maximum net delay:   0.838ns\r\r
4003    Maximum net skew:   0.608ns\r\r
4004 \r\r
4005 \r\r
4006 Analysis completed Tue Jun 30 21:57:31 2009\r\r
4007 --------------------------------------------------------------------------------\r\r
4008 \r\r
4009 Generating Report ...\r\r
4010 \r\r
4011 Number of warnings: 2\r\r
4012 Number of info messages: 3\r\r
4013 Total time: 1 mins 36 secs \r\r
4014 \r\r
4015 \r\r
4016 xflow done!\r\r
4017 touch __xps/system_routed\r
4018 xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
4019 Analyzing implementation/system.par\r\r
4020 *********************************************\r
4021 Running Bitgen..\r
4022 *********************************************\r
4023 cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
4024 Release 11.2 - Bitgen L.46 (nt)\r\r
4025 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4026 PMSPEC -- Overriding Xilinx file\r\r
4027 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
4028 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
4029 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
4030 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
4031    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
4032 Opened constraints file system.pcf.\r\r
4033 \r\r
4034 Tue Jun 30 21:58:01 2009\r\r
4035 \r\r
4036 Running DRC.\r\r
4037 WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
4038    Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
4039    Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
4040    guidelines to minimize the impact on GTX performance. \r\r
4041 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
4042    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
4043    rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
4044    design practice. Use the CE pin to control the loading of data into the\r\r
4045    flip-flop.\r\r
4046 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
4047    Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
4048    This is not good design practice. Use the CE pin to control the loading of\r\r
4049    data into the flip-flop.\r\r
4050 WARNING:PhysDesignRules:367 - The signal\r\r
4051    <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
4052    not drive any load pins in the design.\r\r
4053 WARNING:PhysDesignRules:367 - The signal\r\r
4054    <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
4055    drive any load pins in the design.\r\r
4056 WARNING:PhysDesignRules:367 - The signal\r\r
4057    <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
4058    drive any load pins in the design.\r\r
4059 WARNING:PhysDesignRules:367 - The signal\r\r
4060    <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
4061    drive any load pins in the design.\r\r
4062 WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
4063    is incomplete. The signal does not drive any load pins in the design.\r\r
4064 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4065    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4066    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4067    used.\r\r
4068 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4069    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4070    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4071    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4072 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4073    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4074    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4075    used.\r\r
4076 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4077    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4078    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4079    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4080 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4081    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4082    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4083    used.\r\r
4084 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4085    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4086    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4087    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4088 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4089    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4090    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4091    used.\r\r
4092 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4093    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4094    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4095    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4096 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4097    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4098    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4099    used.\r\r
4100 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4101    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4102    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4103    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4104 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4105    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4106    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4107    used.\r\r
4108 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4109    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4110    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4111    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4112 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4113    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4114    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4115    used.\r\r
4116 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4117    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4118    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4119    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4120 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
4121    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4122    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
4123    used.\r\r
4124 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
4125    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
4126    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
4127    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
4128 DRC detected 0 errors and 24 warnings.  Please see the previously displayed\r\r
4129 individual error or warning messages for more details.\r\r
4130 Creating bit map...\r\r
4131 Saving bit stream in "system.bit".\r\r
4132 Bitstream generation is complete.\r\r
4133 \r
4134 \r
4135 Done!
4136 \r
4137 Writing filter settings....
4138 \r
4139 Done writing filter settings to:
4140         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
4141 \r
4142 Done writing Tab View settings to:
4143         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
4144 \r
4145 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
4146 \r
4147 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
4148 \r
4149 Generating Block Diagram to Buffer
4150 \r
4151 Generated Block Diagram SVG
4152 \r
4153 At Local date and time: Sat Jul 04 20:43:06 2009
4154  make -f system.make download started...
4155 \r
4156 cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
4157 *********************************************\r
4158 Initializing BRAM contents of the bitstream\r
4159 *********************************************\r
4160 bitinit -p xc5vfx70tff1136-1 system.mhs  -pe ppc440_0  bootloops/ppc440_0.elf  \\r
4161 -bt implementation/system.bit -o implementation/download.bit\r
4162 \r\r
4163 bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
4164 Copyright (c) Xilinx Inc. 2002.\r\r
4165 \r\r
4166 Parsing MHS File system.mhs...\r\r
4167 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4168    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
4169    251 - deprecated core for architecture 'virtex5fx'!\r\r
4170 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4171    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line\r\r
4172    296 - deprecated core for architecture 'virtex5fx'!\r\r
4173 \r\r
4174 Overriding IP level properties ...\r\r
4175 \r\r
4176 Performing IP level DRCs on properties...\r\r
4177 \r\r
4178 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
4179 Address Map for Processor ppc440_0\r\r
4180   (0b0000000000-0b0011111111) ppc440_0  \r\r
4181   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
4182   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
4183   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
4184   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
4185   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
4186   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
4187   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
4188   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
4189   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
4190   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
4191   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
4192   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
4193   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
4194   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
4195   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
4196 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
4197    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
4198    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
4199    C_SPLB0_P2P value to 0\r\r
4200 \r\r
4201 Computing clock values...\r\r
4202 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
4203    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
4204    performed for IPs connected to that clock port, unless they are connected\r\r
4205    through the clock generator IP. \r\r
4206 \r\r
4207 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
4208    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
4209    performed for IPs connected to that clock port, unless they are connected\r\r
4210    through the clock generator IP. \r\r
4211 \r\r
4212 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4213    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4214    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4215    C_PLBV46_NUM_MASTERS value to 1\r\r
4216 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4217    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4218    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
4219    C_PLBV46_NUM_SLAVES value to 12\r\r
4220 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4221    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4222    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4223    C_PLBV46_MID_WIDTH value to 1\r\r
4224 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4225    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4226    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4227    value to 128\r\r
4228 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4229    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4230    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
4231    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4232 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4233    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4234    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
4235    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
4236 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4237    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4238    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
4239    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
4240 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4241    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4242    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
4243    value to 0x2000\r\r
4244 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4245    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4246    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4247    C_PORT_DWIDTH value to 64\r\r
4248 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4249    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4250    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
4251    value to 8\r\r
4252 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
4253    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
4254    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
4255    C_SPLB_DWIDTH value to 128\r\r
4256 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
4257    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4258    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4259    value to 128\r\r
4260 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
4261    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4262    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4263    value to 128\r\r
4264 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
4265    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4266    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4267    value to 128\r\r
4268 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
4269    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4270    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4271    value to 128\r\r
4272 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
4273    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
4274    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4275    value to 128\r\r
4276 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4277    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4278    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
4279    C_SPLB_DWIDTH value to 128\r\r
4280 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4281    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4282    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
4283    C_SPLB_SMALLEST_MASTER value to 128\r\r
4284 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4285    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4286    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
4287    C_MPLB_DWIDTH value to 128\r\r
4288 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4289    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4290    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
4291    C_MPLB_SMALLEST_SLAVE value to 128\r\r
4292 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4293    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4294    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
4295    C_SPLB_MID_WIDTH value to 1\r\r
4296 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4297    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4298    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
4299    C_SPLB_NUM_MASTERS value to 1\r\r
4300 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4301    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4302    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
4303    C_SPLB_SMALLEST_MASTER value to 128\r\r
4304 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4305    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4306    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
4307    C_SPLB_DWIDTH value to 128\r\r
4308 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4309    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4310    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4311    C_PLBV46_NUM_MASTERS value to 1\r\r
4312 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4313    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4314    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
4315    C_PLBV46_NUM_SLAVES value to 1\r\r
4316 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4317    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4318    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4319    C_PLBV46_MID_WIDTH value to 1\r\r
4320 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4321    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4322    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4323    value to 128\r\r
4324 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4325    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
4326    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
4327    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4328 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4329    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4330    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4331    C_SPLB_DWIDTH value to 128\r\r
4332 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4333    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4334    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
4335    C_SPLB_MID_WIDTH value to 1\r\r
4336 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4337    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4338    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
4339    C_SPLB_NUM_MASTERS value to 1\r\r
4340 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
4341    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
4342    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4343    value to 128\r\r
4344 \r\r
4345 Checking platform address map ...\r\r
4346 \r\r
4347 Initializing Memory...\r\r
4348 Running Data2Mem with the following command:\r\r
4349 data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd\r\r
4350 "bootloops/ppc440_0.elf" tag ppc440_0  -o b implementation/download.bit \r\r
4351 Memory Initialization completed successfully.\r\r
4352 \r\r
4353 *********************************************\r
4354 Downloading Bitstream onto the target board\r
4355 *********************************************\r
4356 impact -batch etc/download.cmd\r
4357 Release 11.2 - iMPACT L.46 (nt)\r\r
4358 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4359 Preference Table\r\r
4360 Name                 Setting             \r\r
4361 StartupClock         Auto_Correction     \r\r
4362 AutoSignature        False               \r\r
4363 KeepSVF              False               \r\r
4364 ConcurrentMode       False               \r\r
4365 UseHighz             False               \r\r
4366 ConfigOnFailure      Stop                \r\r
4367 UserLevel            Novice              \r\r
4368 MessageLevel         Detailed            \r\r
4369 svfUseTime           false               \r\r
4370 SpiByteSwap          Auto_Correction     \r\r
4371 AutoDetecting cable. Please wait.\r\r
4372 Connecting to cable (Usb Port - USB21).\r\r
4373 Checking cable driver.\r\r
4374  Driver file xusb_xp2.sys found.\r\r
4375  Driver version: src=2301, dest=2301.\r\r
4376  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4377 13:58:07, version = 900.\r\r
4378  Cable PID = 0008.\r\r
4379  Max current requested during enumeration is 300 mA.\r\r
4380 Type = 0x0005.\r\r
4381  Cable Type = 3, Revision = 0.\r\r
4382  Setting cable speed to 6 MHz.\r\r
4383 Cable connection established.\r\r
4384 Firmware version = 2401.\r\r
4385 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4386 Firmware hex file version = 2401.\r\r
4387 PLD file version = 200Dh.\r\r
4388  PLD version = 200Dh.\r\r
4389 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4390 INFO:iMPACT:1777 - \r
4391    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4392 \r
4393 ----------------------------------------------------------------------\r\r
4394 ----------------------------------------------------------------------\r\r
4395 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4396 ----------------------------------------------------------------------\r\r
4397 ----------------------------------------------------------------------\r\r
4398 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4399 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4400 INFO:iMPACT:1777 - \r
4401    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4402 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4403 \r
4404 ----------------------------------------------------------------------\r\r
4405 ----------------------------------------------------------------------\r\r
4406 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4407 INFO:iMPACT:1777 - \r
4408    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4409 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4410 \r
4411 ----------------------------------------------------------------------\r\r
4412 ----------------------------------------------------------------------\r\r
4413 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4414 ----------------------------------------------------------------------\r\r
4415 ----------------------------------------------------------------------\r\r
4416 done.\r\r
4417 Elapsed time =      0 sec.\r\r
4418 Elapsed time =      0 sec.\r\r
4419 '5': Loading file 'implementation/download.bit' ...\r\r
4420 INFO:iMPACT:1777 - \r
4421    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4422 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4423 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4424 \r
4425 done.\r\r
4426 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4427 ----------------------------------------------------------------------\r\r
4428 ----------------------------------------------------------------------\r\r
4429 ----------------------------------------------------------------------\r\r
4430 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4431 Validating chain...\r\r
4432 Boundary-scan chain validated successfully.\r\r
4433 5: Device Temperature: Current Reading:   72.52 C, Min. Reading:   30.69 C, Max.\r\r
4434 Reading:   74.49 C\r\r
4435 5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.\r\r
4436 Reading:   1.002 V\r\r
4437 5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
4438 Reading:   2.508 V\r\r
4439 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
4440 \r
4441 '5': Programming device...\r\r
4442  Match_cycle = 2.\r\r
4443 done.\r\r
4444 '5': Reading status register contents...\r\r
4445 CRC error                                         :         0\r\r
4446 Decryptor security set                            :         0\r\r
4447 DCM locked                                        :         1\r\r
4448 DCI matched                                       :         1\r\r
4449 End of startup signal from Startup block          :         1\r\r
4450 status of GTS_CFG_B                               :         1\r\r
4451 status of GWE                                     :         1\r\r
4452 status of GHIGH                                   :         1\r\r
4453 value of MODE pin M0                              :         1\r\r
4454 value of MODE pin M1                              :         0\r\r
4455 Value of MODE pin M2                              :         1\r\r
4456 Internal signal indicates when housecleaning is completed:         1\r\r
4457 Value driver in from INIT pad                     :         1\r\r
4458 Internal signal indicates that chip is configured :         1\r\r
4459 Value of DONE pin                                 :         1\r\r
4460 Indicates when ID value written does not match chip ID:         0\r\r
4461 Decryptor error Signal                            :         0\r\r
4462 System Monitor Over-Temperature Alarm             :         0\r\r
4463 startup_state[18] CFG startup state machine       :         0\r\r
4464 startup_state[19] CFG startup state machine       :         0\r\r
4465 startup_state[20] CFG startup state machine       :         1\r\r
4466 E-fuse program voltage available                  :         0\r\r
4467 SPI Flash Type[22] Select                         :         1\r\r
4468 SPI Flash Type[23] Select                         :         1\r\r
4469 SPI Flash Type[24] Select                         :         1\r\r
4470 CFG bus width auto detection result               :         0\r\r
4471 CFG bus width auto detection result               :         0\r\r
4472 Reserved                                          :         0\r\r
4473 BPI address wrap around error                     :         0\r\r
4474 IPROG pulsed                                      :         0\r\r
4475 read back crc error                               :         0\r\r
4476 Indicates that efuse logic is busy                :         0\r\r
4477  Match_cycle = 2.\r\r
4478 '5': Programmed successfully.\r\r
4479 Elapsed time =     11 sec.\r\r
4480 ----------------------------------------------------------------------\r\r
4481 ----------------------------------------------------------------------\r\r
4482 ----------------------------------------------------------------------\r\r
4483 ----------------------------------------------------------------------\r\r
4484 ----------------------------------------------------------------------\r\r
4485 ----------------------------------------------------------------------\r\r
4486 ----------------------------------------------------------------------\r\r
4487 ----------------------------------------------------------------------\r\r
4488 INFO:iMPACT:2219 - Status register values:\r
4489 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
4490 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
4491 INFO:iMPACT - '5': Programing completed successfully.\r
4492 INFO:iMPACT - '5': Checking done pin....done.\r
4493 \r
4494 \r
4495 \r
4496 Done!
4497 \r
4498 At Local date and time: Sat Jul 04 20:43:42 2009
4499  make -f system.make program started...
4500 \r
4501 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
4502     -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
4503 -D GCC_PPC440 -mregnames  \r
4504 powerpc-eabi-size RTOSDemo/executable.elf \r
4505    text    data     bss     dec     hex filename\r
4506   53174     372   86528  140074   2232a RTOSDemo/executable.elf\r
4507 \r
4508 \r
4509 Done!
4510 \r
4511 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
4512 \r
4513 Writing filter settings....
4514 \r
4515 Done writing filter settings to:
4516         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
4517 \r
4518 Done writing Tab View settings to:
4519         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
4520 \r
4521 Xilinx Platform Studio (XPS)\r
4522 Xilinx EDK 11.2 Build EDK_LS3.47
4523 \r
4524 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4525 \r
4526 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
4527 \r
4528 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
4529 \r
4530 Generating Block Diagram to Buffer
4531 \r
4532 Generated Block Diagram SVG
4533 \r
4534 At Local date and time: Sun Jul 05 09:35:22 2009
4535  make -f system.make hwclean started...
4536 \r
4537 rm -f implementation/system.ngc\r
4538 rm -f platgen.log\r
4539 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
4540 rm -f implementation/system.bmm\r
4541 rm -f implementation/system.bit\r
4542 rm -f implementation/system.ncd\r
4543 rm -f implementation/system_bd.bmm \r
4544 rm -f implementation/system_map.ncd \r
4545 rm -f __xps/system_routed\r
4546 rm -rf implementation synthesis xst hdl\r
4547 rm -rf xst.srp system.srp\r
4548 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
4549 \r
4550 \r
4551 Done!
4552 \r
4553 At Local date and time: Sun Jul 05 09:35:36 2009
4554  make -f system.make swclean started...
4555 \r
4556 rm -rf ppc440_0/\r
4557 rm -f libgen.log\r
4558 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
4559 rm -f RTOSDemo/executable.elf \r
4560 \r
4561 \r
4562 Done!
4563 \r
4564 Writing filter settings....
4565 \r
4566 Done writing filter settings to:
4567         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
4568 \r
4569 Done writing Tab View settings to:
4570         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
4571 \r