1 /*******************************************************************************
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2 * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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5 * @author Microsemi SoC Products Group
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6 * @brief Hardware Abstraction Layer functions for Mi-V soft processors
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8 * SVN $Revision: 9835 $
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9 * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $
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15 #include "riscv_plic.h"
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22 *Return value from External IRQ handler. This will be used to disable the External
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25 #define EXT_IRQ_KEEP_ENABLED 0U
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26 #define EXT_IRQ_DISABLE 1U
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28 /*------------------------------------------------------------------------------
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29 * Interrupt enable/disable.
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31 void __disable_irq(void);
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32 void __enable_irq(void);
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34 /*------------------------------------------------------------------------------
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35 * System tick handler. This is generated from the RISC-V machine timer.
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37 void SysTick_Handler(void);
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39 /*------------------------------------------------------------------------------
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40 * System tick configuration.
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41 * Configures the machine timer to generate a system tick interrupt at regular
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43 * Takes the number of system clock ticks between interrupts.
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45 * Returns 0 if successful.
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46 * Returns 1 if the interrupt interval cannot be achieved.
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48 uint32_t SysTick_Config(uint32_t ticks);
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54 #endif /* RISCV_HAL_H */
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