2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
6 * SPDX-License-Identifier: BSD-3-Clause
9 #include "fsl_lpuart.h"
11 /*******************************************************************************
13 ******************************************************************************/
14 /* LPUART transfer state. */
15 enum _lpuart_transfer_states
17 kLPUART_TxIdle, /*!< TX idle. */
18 kLPUART_TxBusy, /*!< TX busy. */
19 kLPUART_RxIdle, /*!< RX idle. */
20 kLPUART_RxBusy /*!< RX busy. */
23 /* Typedef for interrupt handler. */
24 typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
26 /*******************************************************************************
28 ******************************************************************************/
30 * @brief Get the LPUART instance from peripheral base address.
32 * @param base LPUART peripheral base address.
33 * @return LPUART instance.
35 uint32_t LPUART_GetInstance(LPUART_Type *base);
38 * @brief Get the length of received data in RX ring buffer.
40 * @userData handle LPUART handle pointer.
41 * @return Length of received data in RX ring buffer.
43 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
46 * @brief Check whether the RX ring buffer is full.
48 * @userData handle LPUART handle pointer.
49 * @retval true RX ring buffer is full.
50 * @retval false RX ring buffer is not full.
52 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
55 * @brief Write to TX register using non-blocking method.
57 * This function writes data to the TX register directly, upper layer must make
58 * sure the TX register is empty or TX FIFO has empty room before calling this function.
60 * @note This function does not check whether all the data has been sent out to bus,
61 * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
64 * @param base LPUART peripheral base address.
65 * @param data Start addresss of the data to write.
66 * @param length Size of the buffer to be sent.
68 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
71 * @brief Read RX register using non-blocking method.
73 * This function reads data from the TX register directly, upper layer must make
74 * sure the RX register is full or TX FIFO has data before calling this function.
76 * @param base LPUART peripheral base address.
77 * @param data Start addresss of the buffer to store the received data.
78 * @param length Size of the buffer.
80 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
82 /*******************************************************************************
84 ******************************************************************************/
85 /* Array of LPUART handle. */
86 static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
87 /* Array of LPUART peripheral base address. */
88 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
89 /* Array of LPUART IRQ number. */
90 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
91 static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
92 static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
94 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
96 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
97 /* Array of LPUART clock name. */
98 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
100 #if defined(LPUART_PERIPH_CLOCKS)
101 /* Array of LPUART functional clock name. */
102 static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
105 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
107 /* LPUART ISR for transactional APIs. */
108 static lpuart_isr_t s_lpuartIsr;
110 /*******************************************************************************
112 ******************************************************************************/
113 uint32_t LPUART_GetInstance(LPUART_Type *base)
117 /* Find the instance index from base address mappings. */
118 for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++)
120 if (s_lpuartBases[instance] == base)
126 assert(instance < ARRAY_SIZE(s_lpuartBases));
131 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
137 if (handle->rxRingBufferTail > handle->rxRingBufferHead)
139 size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
143 size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
149 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
155 if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
166 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
172 /* The Non Blocking write data API assume user have ensured there is enough space in
173 peripheral to write. */
174 for (i = 0; i < length; i++)
176 base->DATA = data[i];
180 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
185 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
186 uint32_t ctrl = base->CTRL;
187 bool isSevenDataBits =
188 ((ctrl & LPUART_CTRL_M7_MASK) ||
189 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
192 /* The Non Blocking read data API assume user have ensured there is enough space in
193 peripheral to write. */
194 for (i = 0; i < length; i++)
196 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
199 data[i] = (base->DATA & 0x7F);
203 data[i] = base->DATA;
206 data[i] = base->DATA;
211 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
214 assert(config->baudRate_Bps);
215 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
216 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
217 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
221 uint16_t sbr, sbrTemp;
222 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
224 /* This LPUART instantiation uses a slightly different baud rate calculation
225 * The idea is to use the best OSR (over-sampling rate) possible
226 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
227 * loop to find the best OSR value possible, one that generates minimum baudDiff
228 * iterate through the rest of the supported values of OSR */
230 baudDiff = config->baudRate_Bps;
233 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
235 /* calculate the temporary sbr value */
236 sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
237 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
242 /* Calculate the baud rate based on the temporary OSR and SBR values */
243 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
245 tempDiff = calculatedBaud - config->baudRate_Bps;
247 /* Select the better value between srb and (sbr + 1) */
248 if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
250 tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
254 if (tempDiff <= baudDiff)
257 osr = osrTemp; /* update and store the best OSR value calculated */
258 sbr = sbrTemp; /* update store the best SBR value calculated */
262 /* Check to see if actual baud rate is within 3% of desired baud rate
263 * based on the best calculate OSR value */
264 if (baudDiff > ((config->baudRate_Bps / 100) * 3))
266 /* Unacceptable baud rate difference of more than 3%*/
267 return kStatus_LPUART_BaudrateNotSupport;
270 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
272 uint32_t instance = LPUART_GetInstance(base);
274 /* Enable lpuart clock */
275 CLOCK_EnableClock(s_lpuartClock[instance]);
276 #if defined(LPUART_PERIPH_CLOCKS)
277 CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
280 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
282 #if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
283 /*Reset all internal logic and registers, except the Global Register */
284 LPUART_SoftwareReset(base);
286 /* Disable LPUART TX RX before setting. */
287 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
292 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
293 * If so, then "BOTHEDGE" sampling must be turned on */
294 if ((osr > 3) && (osr < 8))
296 temp |= LPUART_BAUD_BOTHEDGE_MASK;
299 /* program the osr value (bit value is one less than actual value) */
300 temp &= ~LPUART_BAUD_OSR_MASK;
301 temp |= LPUART_BAUD_OSR(osr - 1);
303 /* write the sbr value to the BAUD registers */
304 temp &= ~LPUART_BAUD_SBR_MASK;
305 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
307 /* Set bit count and parity mode. */
308 base->BAUD &= ~LPUART_BAUD_M10_MASK;
311 ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
312 LPUART_CTRL_IDLECFG_MASK);
315 (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType);
317 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
318 if (kLPUART_SevenDataBits == config->dataBitsCount)
320 if (kLPUART_ParityDisabled != config->parityMode)
322 temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
326 temp |= LPUART_CTRL_M7_MASK;
332 if (kLPUART_ParityDisabled != config->parityMode)
334 temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
340 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
341 /* set stop bit per char */
342 temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
343 base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
346 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
347 /* Set tx/rx WATER watermark
349 Take care of the RX FIFO, RX interrupt request only assert when received bytes
350 equal or more than RX water mark, there is potential issue if RX water
352 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
353 5 bytes are received. the last byte will be saved in FIFO but not trigger
354 RX interrupt because the water mark is 2.
356 base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
358 /* Enable tx/rx FIFO */
359 base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
362 base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
365 /* Clear all status flags */
366 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
367 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
369 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
370 temp |= LPUART_STAT_LBKDIF_MASK;
373 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
374 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
377 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
378 /* Set the CTS configuration/TX CTS source. */
379 base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
380 if (config->enableRxRTS)
382 /* Enable the receiver RTS(request-to-send) function. */
383 base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
385 if (config->enableTxCTS)
387 /* Enable the CTS(clear-to-send) function. */
388 base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
392 /* Set data bits order. */
395 temp |= LPUART_STAT_MSBF_MASK;
399 temp &= ~LPUART_STAT_MSBF_MASK;
404 /* Enable TX/RX base on configure structure. */
406 if (config->enableTx)
408 temp |= LPUART_CTRL_TE_MASK;
411 if (config->enableRx)
413 temp |= LPUART_CTRL_RE_MASK;
418 return kStatus_Success;
420 void LPUART_Deinit(LPUART_Type *base)
424 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
425 /* Wait tx FIFO send out*/
426 while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
430 /* Wait last char shoft out */
431 while (0 == (base->STAT & LPUART_STAT_TC_MASK))
435 /* Clear all status flags */
436 temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
437 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
439 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
440 temp |= LPUART_STAT_LBKDIF_MASK;
443 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
444 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
449 /* Disable the module. */
452 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
453 uint32_t instance = LPUART_GetInstance(base);
455 /* Disable lpuart clock */
456 CLOCK_DisableClock(s_lpuartClock[instance]);
458 #if defined(LPUART_PERIPH_CLOCKS)
459 CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
462 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
465 void LPUART_GetDefaultConfig(lpuart_config_t *config)
469 config->baudRate_Bps = 115200U;
470 config->parityMode = kLPUART_ParityDisabled;
471 config->dataBitsCount = kLPUART_EightDataBits;
472 config->isMsb = false;
473 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
474 config->stopBitCount = kLPUART_OneStopBit;
476 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
477 config->txFifoWatermark = 0;
478 config->rxFifoWatermark = 0;
480 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
481 config->enableRxRTS = false;
482 config->enableTxCTS = false;
483 config->txCtsConfig = kLPUART_CtsSampleAtStart;
484 config->txCtsSource = kLPUART_CtsSourcePin;
486 config->rxIdleType = kLPUART_IdleTypeStartBit;
487 config->rxIdleConfig = kLPUART_IdleCharacter1;
488 config->enableTx = false;
489 config->enableRx = false;
492 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
494 assert(baudRate_Bps);
496 uint32_t temp, oldCtrl;
497 uint16_t sbr, sbrTemp;
498 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
500 /* This LPUART instantiation uses a slightly different baud rate calculation
501 * The idea is to use the best OSR (over-sampling rate) possible
502 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
503 * loop to find the best OSR value possible, one that generates minimum baudDiff
504 * iterate through the rest of the supported values of OSR */
506 baudDiff = baudRate_Bps;
509 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
511 /* calculate the temporary sbr value */
512 sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
513 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
518 /* Calculate the baud rate based on the temporary OSR and SBR values */
519 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
521 tempDiff = calculatedBaud - baudRate_Bps;
523 /* Select the better value between srb and (sbr + 1) */
524 if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
526 tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
530 if (tempDiff <= baudDiff)
533 osr = osrTemp; /* update and store the best OSR value calculated */
534 sbr = sbrTemp; /* update store the best SBR value calculated */
538 /* Check to see if actual baud rate is within 3% of desired baud rate
539 * based on the best calculate OSR value */
540 if (baudDiff < ((baudRate_Bps / 100) * 3))
542 /* Store CTRL before disable Tx and Rx */
543 oldCtrl = base->CTRL;
545 /* Disable LPUART TX RX before setting. */
546 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
550 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
551 * If so, then "BOTHEDGE" sampling must be turned on */
552 if ((osr > 3) && (osr < 8))
554 temp |= LPUART_BAUD_BOTHEDGE_MASK;
557 /* program the osr value (bit value is one less than actual value) */
558 temp &= ~LPUART_BAUD_OSR_MASK;
559 temp |= LPUART_BAUD_OSR(osr - 1);
561 /* write the sbr value to the BAUD registers */
562 temp &= ~LPUART_BAUD_SBR_MASK;
563 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
566 base->CTRL = oldCtrl;
568 return kStatus_Success;
572 /* Unacceptable baud rate difference of more than 3%*/
573 return kStatus_LPUART_BaudrateNotSupport;
577 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
579 base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
580 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
581 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
582 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
588 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
590 base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
591 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
592 base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
593 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
599 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
602 temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
603 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
604 temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
606 temp |= (base->CTRL & 0xFF0C000);
611 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
615 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
616 temp |= (base->FIFO &
617 (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
623 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
627 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
628 temp = (uint32_t)base->FIFO;
629 temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
630 temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
633 temp = (uint32_t)base->STAT;
634 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
635 temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
636 temp |= mask & LPUART_STAT_LBKDIF_MASK;
638 temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
639 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
640 temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
641 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
642 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
643 temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
644 temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
647 /* If some flags still pending. */
648 if (mask & LPUART_GetStatusFlags(base))
650 /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
651 kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
652 kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
653 kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
654 status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
658 status = kStatus_Success;
664 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
668 /* This API can only ensure that the data is written into the data buffer but can't
669 ensure all data in the data buffer are sent into the transmit shift buffer. */
672 while (!(base->STAT & LPUART_STAT_TDRE_MASK))
675 base->DATA = *(data++);
679 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
684 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
685 uint32_t ctrl = base->CTRL;
686 bool isSevenDataBits =
687 ((ctrl & LPUART_CTRL_M7_MASK) ||
688 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
693 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
694 while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
696 while (!(base->STAT & LPUART_STAT_RDRF_MASK))
699 statusFlag = LPUART_GetStatusFlags(base);
701 if (statusFlag & kLPUART_RxOverrunFlag)
703 LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
704 return kStatus_LPUART_RxHardwareOverrun;
707 if (statusFlag & kLPUART_NoiseErrorFlag)
709 LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
710 return kStatus_LPUART_NoiseError;
713 if (statusFlag & kLPUART_FramingErrorFlag)
715 LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
716 return kStatus_LPUART_FramingError;
719 if (statusFlag & kLPUART_ParityErrorFlag)
721 LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
722 return kStatus_LPUART_ParityError;
725 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
728 *(data++) = (base->DATA & 0x7F);
732 *(data++) = base->DATA;
735 *(data++) = base->DATA;
739 return kStatus_Success;
742 void LPUART_TransferCreateHandle(LPUART_Type *base,
743 lpuart_handle_t *handle,
744 lpuart_transfer_callback_t callback,
750 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
751 uint32_t ctrl = base->CTRL;
752 bool isSevenDataBits =
753 ((ctrl & LPUART_CTRL_M7_MASK) ||
754 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
757 /* Zero the handle. */
758 memset(handle, 0, sizeof(lpuart_handle_t));
760 /* Set the TX/RX state. */
761 handle->rxState = kLPUART_RxIdle;
762 handle->txState = kLPUART_TxIdle;
764 /* Set the callback and user data. */
765 handle->callback = callback;
766 handle->userData = userData;
768 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
769 /* Initial seven data bits flag */
770 handle->isSevenDataBits = isSevenDataBits;
773 /* Get instance from peripheral base address. */
774 instance = LPUART_GetInstance(base);
776 /* Save the handle in global variables to support the double weak mechanism. */
777 s_lpuartHandle[instance] = handle;
779 s_lpuartIsr = LPUART_TransferHandleIRQ;
781 /* Enable interrupt in NVIC. */
782 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
783 EnableIRQ(s_lpuartRxIRQ[instance]);
784 EnableIRQ(s_lpuartTxIRQ[instance]);
786 EnableIRQ(s_lpuartIRQ[instance]);
790 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
791 lpuart_handle_t *handle,
793 size_t ringBufferSize)
798 /* Setup the ring buffer address */
799 handle->rxRingBuffer = ringBuffer;
800 handle->rxRingBufferSize = ringBufferSize;
801 handle->rxRingBufferHead = 0U;
802 handle->rxRingBufferTail = 0U;
804 /* Enable the interrupt to accept the data when user need the ring buffer. */
805 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
808 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
812 if (handle->rxState == kLPUART_RxIdle)
814 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
817 handle->rxRingBuffer = NULL;
818 handle->rxRingBufferSize = 0U;
819 handle->rxRingBufferHead = 0U;
820 handle->rxRingBufferTail = 0U;
823 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
828 assert(xfer->dataSize);
832 /* Return error if current TX busy. */
833 if (kLPUART_TxBusy == handle->txState)
835 status = kStatus_LPUART_TxBusy;
839 handle->txData = xfer->data;
840 handle->txDataSize = xfer->dataSize;
841 handle->txDataSizeAll = xfer->dataSize;
842 handle->txState = kLPUART_TxBusy;
844 /* Enable transmiter interrupt. */
845 LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
847 status = kStatus_Success;
853 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
857 LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
859 handle->txDataSize = 0;
860 handle->txState = kLPUART_TxIdle;
863 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
868 if (kLPUART_TxIdle == handle->txState)
870 return kStatus_NoTransferInProgress;
873 *count = handle->txDataSizeAll - handle->txDataSize;
875 return kStatus_Success;
878 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
879 lpuart_handle_t *handle,
880 lpuart_transfer_t *xfer,
881 size_t *receivedBytes)
886 assert(xfer->dataSize);
890 /* How many bytes to copy from ring buffer to user memory. */
891 size_t bytesToCopy = 0U;
892 /* How many bytes to receive. */
893 size_t bytesToReceive;
894 /* How many bytes currently have received. */
895 size_t bytesCurrentReceived;
898 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
899 to lpuart handle, enable interrupt to store received data to xfer->data. When
900 all data received, trigger callback.
901 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
902 If there are enough data in ring buffer, copy them to xfer->data and return.
903 If there are not enough data in ring buffer, copy all of them to xfer->data,
904 save the xfer->data remained empty space to lpuart handle, receive data
905 to this empty space and trigger callback when finished. */
907 if (kLPUART_RxBusy == handle->rxState)
909 status = kStatus_LPUART_RxBusy;
913 bytesToReceive = xfer->dataSize;
914 bytesCurrentReceived = 0;
916 /* If RX ring buffer is used. */
917 if (handle->rxRingBuffer)
919 /* Disable LPUART RX IRQ, protect ring buffer. */
920 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
922 /* How many bytes in RX ring buffer currently. */
923 bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
927 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
929 bytesToReceive -= bytesToCopy;
931 /* Copy data from ring buffer to user memory. */
932 for (i = 0U; i < bytesToCopy; i++)
934 xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
936 /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
937 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
939 handle->rxRingBufferTail = 0U;
943 handle->rxRingBufferTail++;
948 /* If ring buffer does not have enough data, still need to read more data. */
951 /* No data in ring buffer, save the request to LPUART handle. */
952 handle->rxData = xfer->data + bytesCurrentReceived;
953 handle->rxDataSize = bytesToReceive;
954 handle->rxDataSizeAll = bytesToReceive;
955 handle->rxState = kLPUART_RxBusy;
957 /* Enable LPUART RX IRQ if previously enabled. */
958 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
960 /* Call user callback since all data are received. */
961 if (0 == bytesToReceive)
963 if (handle->callback)
965 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
969 /* Ring buffer not used. */
972 handle->rxData = xfer->data + bytesCurrentReceived;
973 handle->rxDataSize = bytesToReceive;
974 handle->rxDataSizeAll = bytesToReceive;
975 handle->rxState = kLPUART_RxBusy;
977 /* Enable RX interrupt. */
978 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
979 kLPUART_IdleLineInterruptEnable);
982 /* Return the how many bytes have read. */
985 *receivedBytes = bytesCurrentReceived;
988 status = kStatus_Success;
994 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
998 /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
999 if (!handle->rxRingBuffer)
1001 /* Disable RX interrupt. */
1002 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
1003 kLPUART_IdleLineInterruptEnable);
1006 handle->rxDataSize = 0U;
1007 handle->rxState = kLPUART_RxIdle;
1010 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
1015 if (kLPUART_RxIdle == handle->rxState)
1017 return kStatus_NoTransferInProgress;
1020 *count = handle->rxDataSizeAll - handle->rxDataSize;
1022 return kStatus_Success;
1025 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
1032 /* If RX overrun. */
1033 if (LPUART_STAT_OR_MASK & base->STAT)
1035 /* Clear overrun flag, otherwise the RX does not work. */
1036 base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
1038 /* Trigger callback. */
1039 if (handle->callback)
1041 handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
1045 /* If IDLE flag is set and the IDLE interrupt is enabled. */
1046 if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL))
1048 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1049 count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
1051 while ((count) && (handle->rxDataSize))
1053 tempCount = MIN(handle->rxDataSize, count);
1055 /* Using non block API to read the data from the registers. */
1056 LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
1057 handle->rxData += tempCount;
1058 handle->rxDataSize -= tempCount;
1061 /* If rxDataSize is 0, disable idle line interrupt.*/
1062 if (!(handle->rxDataSize))
1064 handle->rxState = kLPUART_RxIdle;
1066 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
1067 if (handle->callback)
1069 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
1074 /* Clear IDLE flag.*/
1075 base->STAT |= LPUART_STAT_IDLE_MASK;
1077 /* If rxDataSize is 0, disable idle line interrupt.*/
1078 if (!(handle->rxDataSize))
1080 LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable);
1082 /* If callback is not NULL and rxDataSize is not 0. */
1083 if ((handle->callback) && (handle->rxDataSize))
1085 handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
1088 /* Receive data register full */
1089 if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
1091 /* Get the size that can be stored into buffer for this interrupt. */
1092 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1093 count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
1098 /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
1099 while ((count) && (handle->rxDataSize))
1101 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1102 tempCount = MIN(handle->rxDataSize, count);
1107 /* Using non block API to read the data from the registers. */
1108 LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
1109 handle->rxData += tempCount;
1110 handle->rxDataSize -= tempCount;
1113 /* If all the data required for upper layer is ready, trigger callback. */
1114 if (!handle->rxDataSize)
1116 handle->rxState = kLPUART_RxIdle;
1118 if (handle->callback)
1120 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
1125 /* If use RX ring buffer, receive data to ring buffer. */
1126 if (handle->rxRingBuffer)
1130 /* If RX ring buffer is full, trigger callback to notify over run. */
1131 if (LPUART_TransferIsRxRingBufferFull(base, handle))
1133 if (handle->callback)
1135 handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
1139 /* If ring buffer is still full after callback function, the oldest data is overrided. */
1140 if (LPUART_TransferIsRxRingBufferFull(base, handle))
1142 /* Increase handle->rxRingBufferTail to make room for new data. */
1143 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
1145 handle->rxRingBufferTail = 0U;
1149 handle->rxRingBufferTail++;
1154 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1155 if (handle->isSevenDataBits)
1157 handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
1161 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
1164 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
1167 /* Increase handle->rxRingBufferHead. */
1168 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
1170 handle->rxRingBufferHead = 0U;
1174 handle->rxRingBufferHead++;
1178 /* If no receive requst pending, stop RX interrupt. */
1179 else if (!handle->rxDataSize)
1181 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
1188 /* Send data register empty and the interrupt is enabled. */
1189 if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
1191 /* Get the bytes that available at this moment. */
1192 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1193 count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
1194 ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
1199 while ((count) && (handle->txDataSize))
1201 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1202 tempCount = MIN(handle->txDataSize, count);
1207 /* Using non block API to write the data to the registers. */
1208 LPUART_WriteNonBlocking(base, handle->txData, tempCount);
1209 handle->txData += tempCount;
1210 handle->txDataSize -= tempCount;
1213 /* If all the data are written to data register, notify user with the callback, then TX finished. */
1214 if (!handle->txDataSize)
1216 handle->txState = kLPUART_TxIdle;
1218 /* Disable TX register empty interrupt. */
1219 base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
1221 /* Trigger callback. */
1222 if (handle->callback)
1224 handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
1231 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
1233 /* To be implemented by User. */
1235 #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
1236 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1237 void LPUART0_LPUART1_RX_DriverIRQHandler(void)
1239 if (CLOCK_isEnabledClock(s_lpuartClock[0]))
1241 if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
1242 ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)))
1244 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1247 if (CLOCK_isEnabledClock(s_lpuartClock[1]))
1249 if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
1250 ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)))
1252 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1256 void LPUART0_LPUART1_TX_DriverIRQHandler(void)
1258 if (CLOCK_isEnabledClock(s_lpuartClock[0]))
1260 if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
1261 ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
1263 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1266 if (CLOCK_isEnabledClock(s_lpuartClock[1]))
1268 if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
1269 ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
1271 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1276 void LPUART0_LPUART1_DriverIRQHandler(void)
1278 if (CLOCK_isEnabledClock(s_lpuartClock[0]))
1280 if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
1281 ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) ||
1282 ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
1284 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1287 if (CLOCK_isEnabledClock(s_lpuartClock[1]))
1289 if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
1290 ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) ||
1291 ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
1293 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1300 #if defined(LPUART0)
1301 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1302 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1303 void LPUART0_TX_DriverIRQHandler(void)
1305 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1307 void LPUART0_RX_DriverIRQHandler(void)
1309 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1312 void LPUART0_DriverIRQHandler(void)
1314 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
1320 #if defined(LPUART1)
1321 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1322 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1323 void LPUART1_TX_DriverIRQHandler(void)
1325 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1327 void LPUART1_RX_DriverIRQHandler(void)
1329 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1332 void LPUART1_DriverIRQHandler(void)
1334 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
1340 #if defined(LPUART2)
1341 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1342 void LPUART2_TX_DriverIRQHandler(void)
1344 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
1346 void LPUART2_RX_DriverIRQHandler(void)
1348 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
1351 void LPUART2_DriverIRQHandler(void)
1353 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
1358 #if defined(LPUART3)
1359 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1360 void LPUART3_TX_DriverIRQHandler(void)
1362 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
1364 void LPUART3_RX_DriverIRQHandler(void)
1366 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
1369 void LPUART3_DriverIRQHandler(void)
1371 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
1376 #if defined(LPUART4)
1377 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1378 void LPUART4_TX_DriverIRQHandler(void)
1380 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
1382 void LPUART4_RX_DriverIRQHandler(void)
1384 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
1387 void LPUART4_DriverIRQHandler(void)
1389 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
1394 #if defined(LPUART5)
1395 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1396 void LPUART5_TX_DriverIRQHandler(void)
1398 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
1400 void LPUART5_RX_DriverIRQHandler(void)
1402 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
1405 void LPUART5_DriverIRQHandler(void)
1407 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
1412 #if defined(CM4_0_LPUART)
1413 void M4_0_LPUART_DriverIRQHandler(void)
1415 s_lpuartIsr(CM4_0_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0_LPUART)]);
1419 #if defined(CM4_1_LPUART)
1420 void M4_1_LPUART_DriverIRQHandler(void)
1422 s_lpuartIsr(CM4_1_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1_LPUART)]);
1426 #if defined(DMA_LPUART0)
1427 void DMA_UART0_INT_IRQHandler(void)
1429 s_lpuartIsr(DMA_LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART0)]);
1433 #if defined(DMA_LPUART1)
1434 void DMA_UART1_INT_IRQHandler(void)
1436 s_lpuartIsr(DMA_LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART1)]);
1440 #if defined(DMA_LPUART2)
1441 void DMA_UART2_INT_IRQHandler(void)
1443 s_lpuartIsr(DMA_LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART2)]);
1447 #if defined(DMA_LPUART3)
1448 void DMA_UART3_INT_IRQHandler(void)
1450 s_lpuartIsr(DMA_LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART3)]);
1454 #if defined(DMA_LPUART4)
1455 void DMA_UART4_INT_IRQHandler(void)
1457 s_lpuartIsr(DMA_LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART4)]);