1 /* Copyright 2018 SiFive, Inc */
2 /* SPDX-License-Identifier: Apache-2.0 */
10 * @brief API for configuring caches
16 struct __metal_cache_vtable {
17 void (*init)(struct metal_cache *cache, int ways);
18 int (*get_enabled_ways)(struct metal_cache *cache);
19 int (*set_enabled_ways)(struct metal_cache *cache, int ways);
23 * @brief a handle for a cache
26 const struct __metal_cache_vtable *vtable;
30 * @brief Initialize a cache
31 * @param cache The handle for the cache to initialize
32 * @param ways The number of ways to enable
34 * Initializes a cache with the requested number of ways enabled.
36 __inline__ void metal_cache_init(struct metal_cache *cache, int ways) {
37 cache->vtable->init(cache, ways);
41 * @brief Get the current number of enabled cache ways
42 * @param cache The handle for the cache
43 * @return The current number of enabled cache ways
45 __inline__ int metal_cache_get_enabled_ways(struct metal_cache *cache) {
46 return cache->vtable->get_enabled_ways(cache);
50 * @brief Enable the requested number of cache ways
51 * @param cache The handle for the cache
52 * @param ways The number of ways to enabled
53 * @return 0 if the ways are successfully enabled
55 __inline__ int metal_cache_set_enabled_ways(struct metal_cache *cache, int ways) {
56 return cache->vtable->set_enabled_ways(cache, ways);
60 * @brief Check if dcache is supported on the core
61 * @param hartid The core to check
62 * @return 1 if dcache is present
64 int metal_dcache_l1_available(int hartid);
67 * @brief Flush dcache for L1 on the requested core with write back
68 * @param hartid The core to flush
69 * @param address The virtual address of cacheline to invalidate
72 void metal_dcache_l1_flush(int hartid, uintptr_t address);
75 * @brief Discard dcache for L1 on the requested core with no write back
76 * @param hartid The core to discard
77 * @param address The virtual address of cacheline to invalidate
80 void metal_dcache_l1_discard(int hartid, uintptr_t address);
83 * @brief Check if icache is supported on the core
84 * @param hartid The core to check
85 * @return 1 if icache is present
87 int metal_icache_l1_available(int hartid);
90 * @brief Flush icache for L1 on the requested core
91 * @param hartid The core to flush
94 void metal_icache_l1_flush(int hartid);