1 /***********************************************************************************************************************
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3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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4 * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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5 * applicable laws, including copyright laws.
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6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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7 * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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8 * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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9 * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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10 * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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11 * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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13 * of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15 * http://www.renesas.com/disclaimer
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17 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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18 ***********************************************************************************************************************/
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20 /***********************************************************************************************************************
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21 * File Name : r_cg_sci.h
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22 * Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]
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23 * Device(s) : R5F51138AxFP
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25 * Description : This file implements device driver for SCI module.
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26 * Creation Date: 21/09/2015
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27 ***********************************************************************************************************************/
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31 /***********************************************************************************************************************
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32 Macro definitions (Register bit)
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33 ***********************************************************************************************************************/
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36 Serial mode register (SMR)
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38 /* Clock select (CKS) */
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39 #define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */
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40 #define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */
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41 #define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */
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42 #define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */
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43 /* Multi-processor Mode (MP) */
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44 #define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */
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45 #define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */
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46 /* Stop bit length (STOP) */
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47 #define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */
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48 #define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */
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49 /* Parity mode (PM) */
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50 #define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */
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51 #define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */
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52 /* Parity enable (PE) */
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53 #define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */
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54 #define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */
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55 /* Character length (CHR) */
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56 #define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */
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57 #define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */
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58 /* Communications mode (CM) */
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59 #define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */
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60 #define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */
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61 /* Base clock pulse (BCP) */
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62 #define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */
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63 #define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */
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64 #define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */
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65 #define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */
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66 /* Block transfer mode (BLK) */
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67 #define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */
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68 #define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */
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69 /* GSM mode (GSM) */
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70 #define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */
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71 #define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */
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74 Serial control register (SCR)
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76 /* Clock enable (CKE) */
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77 #define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */
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78 #define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */
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79 #define _02_SCI_EXTERNAL (0x02U) /* External clock selected */
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80 #define _03_SCI_EXTERNAL (0x03U) /* External clock selected */
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81 /* Transmit end interrupt enable (TEIE) */
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82 #define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */
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83 #define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */
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84 /* Multi-processor interrupt enable (MPIE) */
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85 #define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */
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86 #define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */
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87 /* Receive enable (RE) */
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88 #define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */
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89 #define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */
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90 /* Transmit enable (TE) */
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91 #define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */
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92 #define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */
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93 /* Receive interrupt enable (RIE) */
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94 #define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */
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95 #define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */
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96 /* Transmit interrupt enable (TIE) */
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97 #define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */
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98 #define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */
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101 Serial status register (SSR)
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103 /* Multi-Processor bit transfer (MPBT) */
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104 #define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */
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105 #define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */
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106 /* Multi-Processor (MPB) */
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107 #define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */
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108 #define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */
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109 /* Transmit end flag (TEND) */
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110 #define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */
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111 #define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */
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112 /* Parity error flag (PER) */
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113 #define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */
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114 /* Framing error flag (FER) */
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115 #define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */
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116 /* Overrun error flag (ORER) */
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117 #define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */
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120 Smart card mode register (SCMR)
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122 /* Smart card interface mode select (SMIF) */
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123 #define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */
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124 #define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */
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125 /* Transmitted / received data invert (SINV) */
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126 #define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */
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127 #define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */
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128 /* Transmitted / received data transfer direction (SDIR) */
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129 #define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */
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130 #define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */
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131 /* Base clock pulse 2 (BCP2) */
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132 #define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */
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133 #define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */
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134 #define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */
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137 Serial extended mode register (SEMR)
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139 /* Asynchronous Mode Clock Source Select (ACS0) */
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140 #define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */
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141 #define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */
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142 /* Asynchronous mode base clock select (ABCS) */
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143 #define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */
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144 #define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */
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145 /* Digital noise filter function enable (NFEN) */
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146 #define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */
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147 #define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */
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148 /* Asynchronous start bit edge detections select (RXDESEL) */
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149 #define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */
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150 #define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */
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153 Noise filter setting register (SNFR)
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155 /* Noise filter clock select (NFCS) */
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156 #define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */
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157 #define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */
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158 #define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */
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159 #define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */
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160 #define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */
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163 I2C mode register 1 (SIMR1)
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165 /* Simple IIC mode select (IICM) */
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166 #define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */
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167 #define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */
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170 I2C mode register 2 (SIMR2)
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172 /* IIC interrupt mode select (IICINTM) */
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173 #define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */
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174 #define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */
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175 /* Clock synchronization (IICCSC) */
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176 #define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */
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177 #define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */
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178 /* ACK transmission data (IICACKT) */
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179 #define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */
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180 #define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */
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183 I2C mode register 3 (SIMR3)
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185 /* Start condition generation (IICSTAREQ) */
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186 #define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */
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187 #define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */
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188 /* Restart condition generation (IICRSTAREQ) */
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189 #define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */
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190 #define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */
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191 /* Stop condition generation (IICSTPREQ) */
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192 #define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */
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193 #define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */
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194 /* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */
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195 #define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */
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196 #define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */
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197 /* SSDA output select (IICSDAS) */
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198 #define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */
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199 #define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */
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200 #define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */
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201 #define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */
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202 /* SSCL output select (IICSCLS) */
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203 #define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */
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204 #define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */
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205 #define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */
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206 #define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */
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209 I2C status register (SISR)
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211 /* ACK reception data flag (IICACKR) */
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212 #define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */
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213 #define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */
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216 SPI mode register (SPMR)
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218 /* SS pin function enable (SSE) */
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219 #define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */
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220 #define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */
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221 /* CTS enable (CTSE) */
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222 #define _00_SCI_RTS (0x00U) /* RTS function is enabled */
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223 #define _02_SCI_CTS (0x02U) /* CTS function is disabled */
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224 /* Master slave select (MSS) */
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225 #define _00_SCI_SPI_MASTER (0x00U) /* Master mode */
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226 #define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */
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227 /* Mode fault flag (MFF) */
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228 #define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */
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229 #define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */
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230 /* Clock polarity select (CKPOL) */
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231 #define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */
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232 #define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */
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233 /* Clock phase select (CKPH) */
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234 #define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */
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235 #define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */
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238 Interrupt Source Priority Register n (IPRn)
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240 /* Interrupt Priority Level Select (IPR[3:0]) */
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241 #define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */
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242 #define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */
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243 #define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */
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244 #define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */
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245 #define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */
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246 #define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */
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247 #define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */
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248 #define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */
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249 #define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */
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250 #define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */
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251 #define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */
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252 #define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */
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253 #define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */
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254 #define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */
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255 #define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */
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256 #define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */
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259 Transfer status control value
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261 /* Simple IIC Transmit Receive Flag */
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262 #define _80_SCI_IIC_TRANSMISSION (0x80U)
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263 #define _00_SCI_IIC_RECEPTION (0x00U)
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264 /* Simple IIC Start Stop Flag */
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265 #define _80_SCI_IIC_START_CYCLE (0x80U)
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266 #define _00_SCI_IIC_STOP_CYCLE (0x00U)
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267 /* Multiprocessor Asynchronous Communication Flag */
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268 #define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)
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269 #define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)
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272 /***********************************************************************************************************************
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274 ***********************************************************************************************************************/
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276 /***********************************************************************************************************************
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277 Typedef definitions
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278 ***********************************************************************************************************************/
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280 /***********************************************************************************************************************
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282 ***********************************************************************************************************************/
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283 void R_SCI1_Create(void);
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284 void R_SCI1_Start(void);
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285 void R_SCI1_Stop(void);
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286 MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);
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287 MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);
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288 static void r_sci1_callback_transmitend(void);
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289 static void r_sci1_callback_receiveend(void);
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290 static void r_sci1_callback_receiveerror(void);
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292 /* Start user code for function. Do not edit comment generated here */
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294 /* Some of the code in this file is generated using "Code Generator" for e2 studio.
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295 * Warnings exist in this module. */
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297 /* Exported functions used to transmit a number of bytes and wait for completion */
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298 MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num);
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300 /* Character is used to receive key presses from PC terminal */
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301 extern uint8_t g_rx_char;
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303 /* Flag used to control transmission to PC terminal */
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304 extern volatile uint8_t g_tx_flag;
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306 /* End user code. Do not edit comment generated here */
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