1 /***********************************************************************************************************************
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3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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4 * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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5 * applicable laws, including copyright laws.
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6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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7 * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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8 * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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9 * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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10 * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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11 * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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13 * of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15 * http://www.renesas.com/disclaimer
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17 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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18 ***********************************************************************************************************************/
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20 /***********************************************************************************************************************
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21 * File Name : r_cg_cgc.h
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22 * Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]
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23 * Device(s) : R5F51138AxFP
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25 * Description : This file implements device driver for CGC module.
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26 * Creation Date: 21/09/2015
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27 ***********************************************************************************************************************/
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31 /***********************************************************************************************************************
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32 Macro definitions (Register bit)
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33 ***********************************************************************************************************************/
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35 System Clock Control Register (SCKCR)
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37 /* Peripheral Module Clock D (PCLKD) */
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38 #define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */
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39 #define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */
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40 #define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */
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41 #define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */
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42 #define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */
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43 #define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */
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44 #define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */
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45 /* Peripheral Module Clock B (PCLKB) */
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46 #define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */
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47 #define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */
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48 #define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */
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49 #define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */
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50 #define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */
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51 #define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */
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52 #define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */
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53 /* System Clock (ICLK) */
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54 #define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */
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55 #define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */
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56 #define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */
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57 #define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */
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58 #define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */
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59 #define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */
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60 #define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */
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61 /* System Clock (FCLK) */
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62 #define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */
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63 #define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */
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64 #define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */
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65 #define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */
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66 #define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */
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67 #define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */
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68 #define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */
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71 System Clock Control Register 3 (SCKCR3)
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73 #define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */
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74 #define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */
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75 #define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */
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76 #define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */
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77 #define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */
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80 PLL Control Register (PLLCR)
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82 /* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */
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83 #define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */
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84 #define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */
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85 #define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */
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86 /* Frequency Multiplication Factor Select (STC[5:0]) */
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87 #define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */
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88 #define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */
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91 USB-dedicated PLL Control Register (UPLLCR)
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93 /* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */
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94 #define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */
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95 #define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */
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96 #define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */
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97 /* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */
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98 #define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */
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99 #define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */
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100 /* Frequency Multiplication Factor Select (USTC[5:0]) */
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101 #define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */
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102 #define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */
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105 Oscillation Stop Detection Control Register (OSTDCR)
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107 /* Oscillation Stop Detection Interrupt Enable (OSTDIE) */
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108 #define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */
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109 #define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */
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110 /* Oscillation Stop Detection Function Enable (OSTDE) */
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111 #define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */
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112 #define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */
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115 Main Clock Oscillator Wait Control Register (MOSCWTCR)
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117 /* Main Clock Oscillator Wait Time (MSTS[4:0]) */
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118 #define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */
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119 #define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */
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120 #define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */
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121 #define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */
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122 #define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */
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123 #define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */
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124 #define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */
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125 #define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */
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128 HOCO Wait Control Register (HOCOWTCR)
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130 /* HOCO Wait Time (HOCOWTCR) */
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131 #define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */
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132 #define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */
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135 Clock Output Control Register (CKOCR)
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137 /* Clock Output Source Select (CKOSEL[2:0]) */
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138 #define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */
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139 #define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */
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140 #define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */
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141 #define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */
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142 /* Clock Output Division Ratio Select (CKODIV[2:0]) */
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143 #define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */
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144 #define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */
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145 #define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */
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146 #define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */
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147 #define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */
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148 /* Clock Output Control (CKOSTP) */
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149 #define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */
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150 #define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */
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153 Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
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155 /* Main Oscillator Drive Capability Switch (MODRV21) */
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156 #define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */
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157 #define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */
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158 /* Main Clock Oscillator Switch (MOSEL) */
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159 #define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */
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160 #define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */
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163 LCD Source Clock Control Register (LCDSCLKCR)
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165 /* LCD Source Clock Select (LCDSCLKSEL[2:0]) */
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166 #define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */
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167 #define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */
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168 #define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */
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169 #define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */
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170 #define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */
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173 /***********************************************************************************************************************
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175 ***********************************************************************************************************************/
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176 #define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */
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177 #define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */
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179 /***********************************************************************************************************************
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180 Typedef definitions
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181 ***********************************************************************************************************************/
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183 /***********************************************************************************************************************
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185 ***********************************************************************************************************************/
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186 void R_CGC_Create(void);
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188 /* Start user code for function. Do not edit comment generated here */
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189 /* End user code. Do not edit comment generated here */
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