1 /***********************************************************************************************************************
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3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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4 * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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5 * applicable laws, including copyright laws.
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6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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7 * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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8 * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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9 * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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10 * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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11 * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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13 * of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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15 * http://www.renesas.com/disclaimer
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17 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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18 ***********************************************************************************************************************/
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20 /***********************************************************************************************************************
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21 * File Name : r_cg_port.h
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22 * Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]
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23 * Device(s) : R5F51138AxFP
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25 * Description : This file implements device driver for Port module.
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26 * Creation Date: 21/09/2015
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27 ***********************************************************************************************************************/
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31 /***********************************************************************************************************************
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32 Macro definitions (Register bit)
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33 ***********************************************************************************************************************/
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35 Port Direction Register (PDR)
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37 /* Pmn Direction Control (B7 - B0) */
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38 #define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */
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39 #define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */
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40 #define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */
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41 #define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */
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42 #define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */
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43 #define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */
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44 #define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */
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45 #define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */
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46 #define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */
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47 #define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */
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48 #define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */
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49 #define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */
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50 #define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */
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51 #define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */
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52 #define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */
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53 #define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */
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54 #define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */
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55 #define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */
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56 #define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */
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57 #define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */
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58 #define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */
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59 #define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */
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60 #define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */
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61 #define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */
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64 Port Output Data Register (PODR)
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66 /* Pmn Output Data Store (B7 - B0) */
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67 #define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */
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68 #define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */
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69 #define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */
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70 #define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */
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71 #define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */
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72 #define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */
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73 #define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */
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74 #define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */
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75 #define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */
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76 #define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */
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77 #define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */
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78 #define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */
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79 #define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */
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80 #define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */
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81 #define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */
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82 #define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */
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85 Open Drain Control Register 0 (ODR0)
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87 /* Pmn Output Type Select (Pm0 to Pm3) */
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88 #define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */
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89 #define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */
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90 #define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */
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91 #define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */
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92 #define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */
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93 #define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */
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94 #define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */
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95 #define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */
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96 #define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */
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97 #define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */
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98 #define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */
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99 #define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */
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102 Open Drain Control Register 1 (ODR1)
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104 /* Pmn Output Type Select (Pm4 to Pm7) */
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105 #define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */
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106 #define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */
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107 #define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */
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108 #define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */
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109 #define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */
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110 #define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */
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111 #define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */
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112 #define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */
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113 #define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */
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114 #define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */
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115 #define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */
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116 #define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */
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119 Pull-Up Control Register (PCR)
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121 /* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */
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122 #define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */
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123 #define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */
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124 #define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */
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125 #define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */
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126 #define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */
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127 #define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */
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128 #define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */
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129 #define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */
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130 #define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */
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131 #define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */
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132 #define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */
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133 #define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */
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134 #define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */
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135 #define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */
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136 #define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */
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137 #define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */
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140 Port Switching Register A (PSRA)
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142 /* PB6/PC0 Switching (PSEL6) */
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143 #define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */
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144 #define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */
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145 /* PB7/PC1 Switching (PSEL7) */
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146 #define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */
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147 #define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */
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150 /***********************************************************************************************************************
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152 ***********************************************************************************************************************/
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153 #define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */
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154 #define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */
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155 #define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */
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156 #define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */
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157 #define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */
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158 #define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */
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159 #define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */
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160 #define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */
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163 /***********************************************************************************************************************
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164 Typedef definitions
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165 ***********************************************************************************************************************/
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167 /***********************************************************************************************************************
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169 ***********************************************************************************************************************/
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170 void R_PORT_Create(void);
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172 /* Start user code for function. Do not edit comment generated here */
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173 /* End user code. Do not edit comment generated here */
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