2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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30 * This file contains the non-portable and therefore RX62N specific parts of
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31 * the IntQueue standard demo task - namely the configuration of the timers
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32 * that generate the interrupts and the interrupt entry points.
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35 /* Scheduler includes. */
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36 #include "FreeRTOS.h"
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39 /* Demo includes. */
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40 #include "IntQueueTimer.h"
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41 #include "IntQueue.h"
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43 /* Hardware specifics. */
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44 #include "iodefine.h"
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46 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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47 #define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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49 void vInitialiseTimerForIntQueueTest( void )
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51 /* Ensure interrupts do not start until full configuration is complete. */
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52 portENTER_CRITICAL();
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54 /* Cascade two 8bit timer channels to generate the interrupts.
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55 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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56 utilised for this test. */
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58 /* Enable the timers. */
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59 SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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60 SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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62 /* Enable compare match A interrupt request. */
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63 TMR0.TCR.BIT.CMIEA = 1;
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64 TMR2.TCR.BIT.CMIEA = 1;
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66 /* Clear the timer on compare match A. */
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67 TMR0.TCR.BIT.CCLR = 1;
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68 TMR2.TCR.BIT.CCLR = 1;
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70 /* Set the compare match value. */
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71 TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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72 TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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74 /* 16 bit operation ( count from timer 1,2 ). */
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75 TMR0.TCCR.BIT.CSS = 3;
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76 TMR2.TCCR.BIT.CSS = 3;
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78 /* Use PCLK as the input. */
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79 TMR1.TCCR.BIT.CSS = 1;
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80 TMR3.TCCR.BIT.CSS = 1;
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82 /* Divide PCLK by 8. */
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83 TMR1.TCCR.BIT.CKS = 2;
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84 TMR3.TCCR.BIT.CKS = 2;
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86 /* Enable TMR 0, 2 interrupts. */
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87 IEN( TMR0, CMIA0 ) = 1;
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88 IEN( TMR2, CMIA2 ) = 1;
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90 /* Set the timer interrupts to be above the kernel. The interrupts are
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91 assigned different priorities so they nest with each other. */
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92 IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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93 IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
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95 portEXIT_CRITICAL();
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97 /* Ensure the interrupts are clear as they are edge detected. */
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98 IR( TMR0, CMIA0 ) = 0;
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99 IR( TMR2, CMIA2 ) = 0;
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101 /*-----------------------------------------------------------*/
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103 #pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )
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104 void vT0_1InterruptHandler( void )
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106 portYIELD_FROM_ISR( xFirstTimerHandler() );
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108 /*-----------------------------------------------------------*/
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110 #pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )
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111 void vT2_3InterruptHandler( void )
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113 portYIELD_FROM_ISR( xSecondTimerHandler() );
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