git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RX200_RX210-RSK_Renesas/RTOSDemo/include/rskrx210def.h

   1 \r
   2 /******************************************************************************\r
   3 * DISCLAIMER\r
   4 * Please refer to http://www.renesas.com/disclaimer\r
   5 ******************************************************************************\r
   6   Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
   7 *******************************************************************************\r
   8 * File Name    : rsksh7216.h\r
   9 * Version      : 1.00\r
  10 * Description  : RSK 7216 board specific settings\r
  11 ******************************************************************************\r
  12 * History : DD.MM.YYYY Version Description\r
  13 *         : 06.10.2009 1.00    First Release\r
  14 ******************************************************************************/\r
  15 \r
  16 #ifndef RSKRX62N_H\r
  17 #define RSKRX62N_H\r
  18 \r
  19 /******************************************************************************\r
  20 Includes   <System Includes> , "Project Includes"\r
  21 ******************************************************************************/\r
  22 \r
  23 /******************************************************************************\r
  24 Typedef definitions\r
  25 ******************************************************************************/\r
  26 \r
  27 /******************************************************************************\r
  28 Macro definitions\r
  29 ******************************************************************************/\r
  30 \r
  31 /* System Clock Settings */\r
  32 #define         CLK_SRC_HOCO    0\r
  33 \r
  34 /* DETAIL THIS LATER !!!! */\r
  35 #if (CLK_SRC_HOCO == 0)\r
  36 /* External xtal and PLL circuit */\r
  37 #define     XTAL_FREQUENCY  (20000000L) \r
  38 #define     PLL_MUL         (8)\r
  39 #define     PLL_INPUT_FREQ_DIV         (2)\r
  40 #define     ICLK_DIV        (2)\r
  41 #define     PCLK_DIV        (8)\r
  42 #define     BCLK_DIV        (8)\r
  43 #define     PLL_FREQUENCY   (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))   \r
  44 #define     ICLK_FREQUENCY  (PLL_FREQUENCY / ICLK_DIV)\r
  45 #define     PCLK_FREQUENCY  (PLL_FREQUENCY / PCLK_DIV)\r
  46 #define     BCLK_FREQUENCY  (PLL_FREQUENCY / BCLK_DIV)\r
  47 #else\r
  48 /* Internal high speed on-chip oscillator (HOCO) */\r
  49 #define     XTAL_FREQUENCY  (50000000L) \r
  50 #define     PLL_MUL         (1)\r
  51 #define     PLL_INPUT_FREQ_DIV         (1)\r
  52 #define     ICLK_DIV        (2)\r
  53 #define     PCLK_DIV        (8)\r
  54 #define     BCLK_DIV        (8)\r
  55 #define     PLL_FREQUENCY   (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))   \r
  56 #define     ICLK_FREQUENCY  (PLL_FREQUENCY / ICLK_DIV)\r
  57 #define     PCLK_FREQUENCY  (PLL_FREQUENCY / PCLK_DIV)\r
  58 #define     BCLK_FREQUENCY  (PLL_FREQUENCY / BCLK_DIV)\r
  59 #endif\r
  60 \r
  61 #define     CMT0_CLK_SELECT (512)\r
  62 \r
  63 /* General Values */\r
  64 #define         LED_ON          (0)\r
  65 #define         LED_OFF                 (1)\r
  66 #define         SET_BIT_HIGH    (1)\r
  67 #define         SET_BIT_LOW             (0)\r
  68 #define         SET_BYTE_HIGH   (0xFF)\r
  69 #define         SET_BYTE_LOW    (0x00)\r
  70 \r
  71 /* Define switches to be polled if not available as interrupts */\r
  72 #define         SW_ACTIVE               FALSE\r
  73 #define         SW1                     PORT0.DR.BIT.B0\r
  74 #define         SW2                     PORT0.DR.BIT.B1\r
  75 #define     SW3             PORT0.DR.BIT.B7\r
  76 #define         SW1_DDR                 PORT0.DDR.BIT.B0\r
  77 #define         SW2_DDR                 PORT0.DDR.BIT.B1\r
  78 #define     SW3_DDR         PORT0.DDR.BIT.B7\r
  79 #define         SW1_ICR                 PORT0.ICR.BIT.B0\r
  80 #define         SW2_ICR                 PORT0.ICR.BIT.B1\r
  81 #define     SW3_ICR         PORT0.ICR.BIT.B7\r
  82 \r
  83 /* LEDs */\r
  84 #define         LED0                    PORT1.PODR.BIT.B4\r
  85 #define         LED1                    PORT1.PODR.BIT.B5\r
  86 #define         LED2                    PORT1.PODR.BIT.B6\r
  87 #define         LED3                    PORT1.PODR.BIT.B7\r
  88 //#define           LED4                        PORT6.DR.BIT.B0\r
  89 //#define           LED5                        PORT7.DR.BIT.B3\r
  90 #define         LED0_DDR        PORT1.PDR.BIT.B4\r
  91 #define         LED1_DDR        PORT1.PDR.BIT.B5\r
  92 #define         LED2_DDR        PORT1.PDR.BIT.B6\r
  93 #define         LED3_DDR        PORT1.PDR.BIT.B7\r
  94 //#define           LED4_DDR        PORT6.DDR.BIT.B0\r
  95 //#define           LED5_DDR        PORT7.DDR.BIT.B3\r
  96 \r
  97 /* 2x8 segment LCD */\r
  98 #define         INCLUDE_LCD             1\r
  99 #define     LCD_RS          PORTJ.PODR.BIT.B1\r
 100 #define     LCD_EN          PORTJ.PODR.BIT.B3\r
 101 #define     LCD_DATA        PORTH.PODR.BYTE\r
 102 \r
 103 #define     LCD_RS_DDR      PORTJ.PDR.BIT.B1\r
 104 #define     LCD_EN_DDR      PORTJ.PDR.BIT.B3\r
 105 #define     LCD_DATA_DDR    PORTH.PDR.BYTE\r
 106 \r
 107 \r
 108 \r
 109 /******************************************************************************\r
 110 Variable Externs\r
 111 ******************************************************************************/\r
 112 \r
 113 /******************************************************************************\r
 114 Functions Prototypes\r
 115 ******************************************************************************/\r
 116 \r
 117 \r
 118 \r
 119 /* RSKRX62N_H */\r
 120 #endif          \r
 121 \r