git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/IAR_Support/defaults.s

   1 /*---------------------------------------------------------------------------*/\r
   2 /*                            - defaults.s -                                 */\r
   3 /*                                                                           */\r
   4 /*       This module contains default values for the following symbols       */\r
   5 /*                                                                           */\r
   6 /*       For RxV1 core:                                                      */\r
   7 /*        __MDES            @ 0xFFFFFF80 to 0xFFFFFF83                       */\r
   8 /*        __OFS1            @ 0xFFFFFF88 to 0xFFFFFF8B                       */\r
   9 /*        __OFS0            @ 0xFFFFFF8C to 0xFFFFFF8F                       */\r
  10 /*        __ROM_CODE        @ 0xFFFFFF9C                                     */\r
  11 /*        __ID_BYTES_1_4    @ 0xFFFFFFA0 to 0xFFFFFFA3                       */\r
  12 /*        __ID_BYTES_5_8    @ 0xFFFFFFA4 to 0xFFFFFFA7                       */\r
  13 /*        __ID_BYTES_9_12   @ 0xFFFFFFA8 to 0xFFFFFFAB                       */\r
  14 /*        __ID_BYTES_13_16  @ 0xFFFFFFAC to 0xFFFFFFAF                       */\r
  15 /*                                                                           */\r
  16 /*       For RxV1 core:                                                      */\r
  17 /*        __MDES            @ 0xFFFFFF80 to 0xFFFFFF83                       */\r
  18 /*        __OFS1            @ 0xFFFFFF88 to 0xFFFFFF8B                       */\r
  19 /*        __OFS0            @ 0xFFFFFF8C to 0xFFFFFF8F                       */\r
  20 /*        __ROM_CODE        @ 0xFFFFFF9C to 0xFFFFFF9F                       */\r
  21 /*        __OSIS_1          @ 0xFFFFFFA0 to 0xFFFFFFA3                       */\r
  22 /*        __OSIS_2          @ 0xFFFFFFA4 to 0xFFFFFFA7                       */\r
  23 /*        __OSIS_3          @ 0xFFFFFFA8 to 0xFFFFFFAB                       */\r
  24 /*        __OSIS_4          @ 0xFFFFFFAC to 0xFFFFFFAF                       */\r
  25 /*                                                                           */\r
  26 /*       For RxV2 core (RX64M):                                              */\r
  27 /*        __SPCC            @ 0x00120040 to 0x00120043                       */\r
  28 /*        __TMEF            @ 0x00120048 to 0x0012004B                       */\r
  29 /*        __OSIS_1          @ 0x00120050 to 0x00120053                       */\r
  30 /*        __OSIS_2          @ 0x00120054 to 0x00120057                       */\r
  31 /*        __OSIS_3          @ 0x00120058 to 0x0012005D                       */\r
  32 /*        __OSIS_4          @ 0x0012005C to 0x0012005F                       */\r
  33 /*        __TMINF           @ 0x00120060 to 0x00120063                       */\r
  34 /*        __MDE             @ 0x00120064 to 0x00120067                       */\r
  35 /*        __OFS0            @ 0x00120068 to 0x0012006B                       */\r
  36 /*        __OFS1            @ 0x0012006C to 0x0012006F                       */\r
  37 /*                                                                           */\r
  38 /*       To override default values in library add this file to your         */\r
  39 /*       project and change the values.                                      */\r
  40 /*                                                                           */\r
  41 /*       Copyright 2014 IAR Systems AB.                                      */\r
  42 /*                                                                           */\r
  43 /*       $Revision: 6046 $                                                   */\r
  44 /*                                                                           */\r
  45 /*---------------------------------------------------------------------------*/\r
  46 \r
  47         MODULE  DEFAULTS\r
  48         SECTION .text:CONST:NOROOT\r
  49 \r
  50 #if __CORE__ == __CORE_V1__\r
  51         PUBWEAK  __MDES\r
  52         PUBWEAK  __OFS1\r
  53         PUBWEAK  __OFS0\r
  54         PUBWEAK  __ROM_CODE\r
  55         PUBWEAK  __ID_BYTES_1_4\r
  56         PUBWEAK  __ID_BYTES_5_8\r
  57         PUBWEAK  __ID_BYTES_9_12\r
  58         PUBWEAK  __ID_BYTES_13_16\r
  59 #if __LITTLE_ENDIAN__\r
  60 __MDES           equ 0xffffffff\r
  61 #else\r
  62 __MDES           equ 0xfffffff8\r
  63 #endif\r
  64 __OFS0           equ 0xffffffff\r
  65 __OFS1           equ 0xffffffff\r
  66 __ROM_CODE       equ 0xffffffff\r
  67 __ID_BYTES_1_4   equ 0xffffffff\r
  68 __ID_BYTES_5_8   equ 0xffffffff\r
  69 __ID_BYTES_9_12  equ 0xffffffff\r
  70 __ID_BYTES_13_16 equ 0xffffffff\r
  71 \r
  72 #else /* __CORE__ == __CORE_V2__ */\r
  73         PUBWEAK  __ROM_CODE\r
  74         PUBWEAK  __MDE\r
  75         PUBWEAK  __OFS1\r
  76         PUBWEAK  __OFS0\r
  77         PUBWEAK  __OSIS_1\r
  78         PUBWEAK  __OSIS_2\r
  79         PUBWEAK  __OSIS_3\r
  80         PUBWEAK  __OSIS_4\r
  81         PUBWEAK  __SPCC\r
  82         PUBWEAK  __TMEF\r
  83         PUBWEAK  __TMINF\r
  84 \r
  85 __ROM_CODE       equ 0xffffffff\r
  86 \r
  87 // 0x00120040 SPCC register\r
  88 __SPCC           equ 0xffffffff\r
  89 \r
  90 // 0x00120048 TMEF register\r
  91 __TMEF           equ 0xffffffff\r
  92 \r
  93 // 0x00120050 OSIC register (ID codes)\r
  94 __OSIS_1         equ 0xffffffff\r
  95 __OSIS_2         equ 0xffffffff\r
  96 __OSIS_3         equ 0xffffffff\r
  97 __OSIS_4         equ 0xffffffff\r
  98 \r
  99 // 0x00120060 TMINF register\r
 100 __TMINF          equ 0xffffffff\r
 101 \r
 102 // 0x00120064 MDE register (Single Chip Mode)\r
 103 #if __LITTLE_ENDIAN__\r
 104 __MDE            equ 0xffffffff // little\r
 105 #else\r
 106 __MDE            equ 0xfffffff8 // big\r
 107 #endif\r
 108 \r
 109 // 0x00120068 OFS0 register\r
 110 __OFS0           equ 0xffffffff\r
 111 \r
 112 // 0x0012006c OFS1 register\r
 113 __OFS1           equ 0xffffffff\r
 114 \r
 115 #endif\r
 116         END\r