2 FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
6 ***************************************************************************
\r
8 * FreeRTOS provides completely free yet professionally developed, *
\r
9 * robust, strictly quality controlled, supported, and cross *
\r
10 * platform software that has become a de facto standard. *
\r
12 * Help yourself get started quickly and support the FreeRTOS *
\r
13 * project by purchasing a FreeRTOS tutorial book, reference *
\r
14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
18 ***************************************************************************
\r
20 This file is part of the FreeRTOS distribution.
\r
22 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
23 the terms of the GNU General Public License (version 2) as published by the
\r
24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
26 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
27 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
28 >>! the source code for proprietary components outside of the FreeRTOS
\r
31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
34 link: http://www.freertos.org/a00114.html
\r
38 ***************************************************************************
\r
40 * Having a problem? Start by reading the FAQ "My application does *
\r
41 * not run, what could be wrong?" *
\r
43 * http://www.FreeRTOS.org/FAQHelp.html *
\r
45 ***************************************************************************
\r
47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
48 license and Real Time Engineers Ltd. contact details.
\r
50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
56 licenses offer ticketed support, indemnification and middleware.
\r
58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
59 engineered and independently SIL3 certified version for use in safety and
\r
60 mission critical applications that require provable dependability.
\r
65 /* Hardware specific includes. */
\r
66 #include "iodefine.h"
\r
67 #include "typedefine.h"
\r
68 #include "r_ether.h"
\r
71 /* FreeRTOS includes. */
\r
72 #include "FreeRTOS.h"
\r
77 #include "net/uip.h"
\r
79 /* The time to wait between attempts to obtain a free buffer. */
\r
80 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
\r
82 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
\r
83 up on attempting to obtain a free buffer all together. */
\r
84 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
86 /* The number of Rx descriptors. */
\r
87 #define emacNUM_RX_DESCRIPTORS 8
\r
89 /* The number of Tx descriptors. When using uIP there is not point in having
\r
91 #define emacNUM_TX_BUFFERS 2
\r
93 /* The total number of EMAC buffers to allocate. */
\r
94 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
\r
96 /* The time to wait for the Tx descriptor to become free. */
\r
97 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
\r
99 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
\r
101 #define emacTX_WAIT_ATTEMPTS ( 50 )
\r
103 /* Only Rx end and Tx end interrupts are used by this driver. */
\r
104 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
\r
105 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
\r
107 /*-----------------------------------------------------------*/
\r
109 /* The buffers and descriptors themselves. */
\r
110 static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16)));
\r
111 static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16)));
\r
112 static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16)));
\r
114 /* Used to indicate which buffers are free and which are in use. If an index
\r
115 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
\r
116 the buffer is in use or about to be used. */
\r
117 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
\r
119 /*-----------------------------------------------------------*/
\r
122 * Initialise both the Rx and Tx descriptors.
\r
124 static void prvInitialiseDescriptors( void );
\r
127 * Return a pointer to a free buffer within xEthernetBuffers.
\r
129 static unsigned char *prvGetNextBuffer( void );
\r
132 * Return a buffer to the list of free buffers.
\r
134 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
137 * Examine the status of the next Rx FIFO to see if it contains new data.
\r
139 static unsigned long prvCheckRxFifoStatus( void );
\r
142 * Setup the microcontroller for communication with the PHY.
\r
144 static void prvResetMAC( void );
\r
147 * Configure the Ethernet interface peripherals.
\r
149 static void prvConfigureEtherCAndEDMAC( void );
\r
152 * Something has gone wrong with the descriptor usage. Reset all the buffers
\r
155 static void prvResetEverything( void );
\r
158 * Handler for the EMAC peripheral. See the documentation for this
\r
159 * port on http://www.FreeRTOS.org for more information on defining interrupt
\r
162 void vEMAC_ISR_Handler( void ) __attribute__((interrupt));
\r
164 /*-----------------------------------------------------------*/
\r
166 /* Points to the Rx descriptor currently in use. */
\r
167 static ethfifo *pxCurrentRxDesc = NULL;
\r
169 /* The buffer used by the uIP stack to both receive and send. This points to
\r
170 one of the Ethernet buffers when its actually in use. */
\r
171 unsigned char *uip_buf = NULL;
\r
173 /*-----------------------------------------------------------*/
\r
175 void vInitEmac( void )
\r
177 /* Software reset. */
\r
180 /* Set the Rx and Tx descriptors into their initial state. */
\r
181 prvInitialiseDescriptors();
\r
183 /* Set the MAC address into the ETHERC */
\r
184 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
\r
185 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
\r
186 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
\r
187 ( unsigned long ) configMAC_ADDR3;
\r
189 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
\r
190 ( unsigned long ) configMAC_ADDR5;
\r
192 /* Perform rest of interface hardware configuration. */
\r
193 prvConfigureEtherCAndEDMAC();
\r
195 /* Nothing received yet, so uip_buf points nowhere. */
\r
198 /* Initialize the PHY */
\r
201 /*-----------------------------------------------------------*/
\r
203 void vEMACWrite( void )
\r
207 /* Wait until the second transmission of the last packet has completed. */
\r
208 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
\r
210 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
212 /* Descriptor is still active. */
\r
213 vTaskDelay( emacTX_WAIT_DELAY_ms );
\r
221 /* Is the descriptor free after waiting for it? */
\r
222 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
224 /* Something has gone wrong. */
\r
225 prvResetEverything();
\r
228 /* Setup both descriptors to transmit the frame. */
\r
229 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
\r
230 xTxDescriptors[ 0 ].bufsize = uip_len;
\r
231 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
\r
232 xTxDescriptors[ 1 ].bufsize = uip_len;
\r
234 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
\r
235 for use by the stack. */
\r
236 uip_buf = prvGetNextBuffer();
\r
238 /* Clear previous settings and go. */
\r
239 xTxDescriptors[0].status &= ~( FP1 | FP0 );
\r
240 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
\r
241 xTxDescriptors[1].status &= ~( FP1 | FP0 );
\r
242 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
\r
244 EDMAC.EDTRR.LONG = 0x00000001;
\r
246 /*-----------------------------------------------------------*/
\r
248 unsigned long ulEMACRead( void )
\r
250 unsigned long ulBytesReceived;
\r
252 ulBytesReceived = prvCheckRxFifoStatus();
\r
254 if( ulBytesReceived > 0 )
\r
256 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
\r
257 the buffer that contains the received data. */
\r
258 prvReturnBuffer( uip_buf );
\r
260 /* Point uip_buf to the data about ot be processed. */
\r
261 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
\r
263 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
\r
265 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
\r
267 /* Prepare the descriptor to go again. */
\r
268 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
\r
269 pxCurrentRxDesc->status |= ACT;
\r
271 /* Move onto the next buffer in the ring. */
\r
272 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
274 if( EDMAC.EDRRR.LONG == 0x00000000L )
\r
276 /* Restart Ethernet if it has stopped */
\r
277 EDMAC.EDRRR.LONG = 0x00000001L;
\r
281 return ulBytesReceived;
\r
283 /*-----------------------------------------------------------*/
\r
285 long lEMACWaitForLink( void )
\r
289 /* Set the link status. */
\r
290 switch( phy_set_autonegotiate() )
\r
292 /* Half duplex link */
\r
293 case PHY_LINK_100H:
\r
294 ETHERC.ECMR.BIT.DM = 0;
\r
295 ETHERC.ECMR.BIT.RTM = 1;
\r
300 ETHERC.ECMR.BIT.DM = 0;
\r
301 ETHERC.ECMR.BIT.RTM = 0;
\r
306 /* Full duplex link */
\r
307 case PHY_LINK_100F:
\r
308 ETHERC.ECMR.BIT.DM = 1;
\r
309 ETHERC.ECMR.BIT.RTM = 1;
\r
314 ETHERC.ECMR.BIT.DM = 1;
\r
315 ETHERC.ECMR.BIT.RTM = 0;
\r
324 if( lReturn == pdPASS )
\r
326 /* Enable receive and transmit. */
\r
327 ETHERC.ECMR.BIT.RE = 1;
\r
328 ETHERC.ECMR.BIT.TE = 1;
\r
330 /* Enable EDMAC receive */
\r
331 EDMAC.EDRRR.LONG = 0x1;
\r
336 /*-----------------------------------------------------------*/
\r
338 static void prvInitialiseDescriptors( void )
\r
340 volatile ethfifo *pxDescriptor;
\r
343 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
345 /* Ensure none of the buffers are shown as in use at the start. */
\r
346 ucBufferInUse[ x ] = pdFALSE;
\r
349 /* Initialise the Rx descriptors. */
\r
350 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
\r
352 pxDescriptor = &( xRxDescriptors[ x ] );
\r
353 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
\r
355 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
356 pxDescriptor->size = 0;
\r
357 pxDescriptor->status = ACT;
\r
358 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ];
\r
360 /* Mark this buffer as in use. */
\r
361 ucBufferInUse[ x ] = pdTRUE;
\r
364 /* The last descriptor points back to the start. */
\r
365 pxDescriptor->status |= DL;
\r
366 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ];
\r
368 /* Initialise the Tx descriptors. */
\r
369 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
\r
371 pxDescriptor = &( xTxDescriptors[ x ] );
\r
373 /* A buffer is not allocated to the Tx descriptor until a send is
\r
374 actually required. */
\r
375 pxDescriptor->buf_p = NULL;
\r
377 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
378 pxDescriptor->size = 0;
\r
379 pxDescriptor->status = 0;
\r
380 pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ];
\r
383 /* The last descriptor points back to the start. */
\r
384 pxDescriptor->status |= DL;
\r
385 pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] );
\r
387 /* Use the first Rx descriptor to start with. */
\r
388 pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] );
\r
390 /*-----------------------------------------------------------*/
\r
392 static unsigned char *prvGetNextBuffer( void )
\r
395 unsigned char *pucReturn = NULL;
\r
396 unsigned long ulAttempts = 0;
\r
398 while( pucReturn == NULL )
\r
400 /* Look through the buffers to find one that is not in use by
\r
402 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
404 if( ucBufferInUse[ x ] == pdFALSE )
\r
406 ucBufferInUse[ x ] = pdTRUE;
\r
407 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
\r
412 /* Was a buffer found? */
\r
413 if( pucReturn == NULL )
\r
417 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
422 /* Wait then look again. */
\r
423 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
\r
429 /*-----------------------------------------------------------*/
\r
431 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
435 /* Return a buffer to the pool of free buffers. */
\r
436 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
\r
438 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
\r
440 ucBufferInUse[ ul ] = pdFALSE;
\r
445 /*-----------------------------------------------------------*/
\r
447 static void prvResetEverything( void )
\r
449 /* Temporary code just to see if this gets called. This function has not
\r
450 been implemented. */
\r
451 portDISABLE_INTERRUPTS();
\r
454 /*-----------------------------------------------------------*/
\r
456 static unsigned long prvCheckRxFifoStatus( void )
\r
458 unsigned long ulReturn = 0;
\r
460 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
\r
462 /* Current descriptor is still active. */
\r
464 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
\r
466 /* Frame error. Clear the error. */
\r
467 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
\r
468 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
\r
469 pxCurrentRxDesc->status |= ACT;
\r
470 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
472 if( EDMAC.EDRRR.LONG == 0x00000000UL )
\r
474 /* Restart Ethernet if it has stopped. */
\r
475 EDMAC.EDRRR.LONG = 0x00000001UL;
\r
480 /* The descriptor contains a frame. Because of the size of the buffers
\r
481 the frame should always be complete. */
\r
482 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
\r
484 ulReturn = pxCurrentRxDesc->size;
\r
488 /* Do not expect to get here. */
\r
489 prvResetEverything();
\r
495 /*-----------------------------------------------------------*/
\r
497 static void prvResetMAC( void )
\r
499 /* Ensure the EtherC and EDMAC are enabled. */
\r
500 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
\r
501 vTaskDelay( 100 / portTICK_RATE_MS );
\r
503 EDMAC.EDMR.BIT.SWR = 1;
\r
505 /* Crude wait for reset to complete. */
\r
506 vTaskDelay( 500 / portTICK_RATE_MS );
\r
508 /*-----------------------------------------------------------*/
\r
510 static void prvConfigureEtherCAndEDMAC( void )
\r
512 /* Initialisation code taken from Renesas example project. */
\r
514 /* TODO: Check bit 5 */
\r
515 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
\r
517 /* Set the EDMAC interrupt priority. */
\r
518 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
520 /* TODO: Check bit 5 */
\r
521 /* Enable interrupts of interest only. */
\r
522 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
\r
523 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
\r
524 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
\r
527 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
\r
528 #ifdef __RX_LITTLE_ENDIAN__
\r
529 EDMAC.EDMR.BIT.DE = 1;
\r
531 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
\r
532 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
\r
533 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
\r
534 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
\r
535 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
\r
536 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
\r
537 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
\r
539 /* Enable the interrupt... */
\r
540 _IEN( _ETHER_EINT ) = 1;
\r
542 /*-----------------------------------------------------------*/
\r
544 void vEMAC_ISR_Handler( void )
\r
546 unsigned long ul = EDMAC.EESR.LONG;
\r
547 long lHigherPriorityTaskWoken = pdFALSE;
\r
548 extern xQueueHandle xEMACEventQueue;
\r
549 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
\r
551 /* Re-enabled interrupts. */
\r
552 __asm volatile( "SETPSW I" );
\r
554 /* Has a Tx end occurred? */
\r
555 if( ul & emacTX_END_INTERRUPT )
\r
557 /* Only return the buffer to the pool once both Txes have completed. */
\r
558 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
\r
559 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
\r
562 /* Has an Rx end occurred? */
\r
563 if( ul & emacRX_END_INTERRUPT )
\r
565 /* Make sure the Ethernet task is not blocked waiting for a packet. */
\r
566 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
\r
567 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
\r
568 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
\r