2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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76 * This file contains the non-portable and therefore RX62N specific parts of
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77 * the IntQueue standard demo task - namely the configuration of the timers
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78 * that generate the interrupts and the interrupt entry points.
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81 /* Scheduler includes. */
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82 #include "FreeRTOS.h"
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85 /* Demo includes. */
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86 #include "IntQueueTimer.h"
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87 #include "IntQueue.h"
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89 /* Hardware specifics. */
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90 #include <iorx62n.h>
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92 #define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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93 #define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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95 /* Handlers for the two timers used. */
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96 __interrupt void vT0_1InterruptHandler( void );
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97 __interrupt void vT2_3InterruptHandler( void );
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99 void vInitialiseTimerForIntQueueTest( void )
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101 /* Ensure interrupts do not start until full configuration is complete. */
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102 portENTER_CRITICAL();
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104 /* Cascade two 8bit timer channels to generate the interrupts.
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105 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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106 utilised for this test. */
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108 /* Enable the timers. */
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109 SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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110 SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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112 /* Enable compare match A interrupt request. */
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113 TMR0.TCR.BIT.CMIEA = 1;
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114 TMR2.TCR.BIT.CMIEA = 1;
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116 /* Clear the timer on compare match A. */
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117 TMR0.TCR.BIT.CCLR = 1;
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118 TMR2.TCR.BIT.CCLR = 1;
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120 /* Set the compare match value. */
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121 TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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122 TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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124 /* 16 bit operation ( count from timer 1,2 ). */
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125 TMR0.TCCR.BIT.CSS = 3;
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126 TMR2.TCCR.BIT.CSS = 3;
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128 /* Use PCLK as the input. */
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129 TMR1.TCCR.BIT.CSS = 1;
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130 TMR3.TCCR.BIT.CSS = 1;
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132 /* Divide PCLK by 8. */
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133 TMR1.TCCR.BIT.CKS = 2;
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134 TMR3.TCCR.BIT.CKS = 2;
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136 /* Enable TMR 0, 2 interrupts. */
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137 IEN( TMR0, CMIA0 ) = 1;
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138 IEN( TMR2, CMIA2 ) = 1;
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140 /* Set the timer interrupts to be above the kernel. The interrupts are
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141 assigned different priorities so they nest with each other. */
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142 IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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143 IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
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145 portEXIT_CRITICAL();
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147 /* Ensure the interrupts are clear as they are edge detected. */
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148 IR( TMR0, CMIA0 ) = 0;
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149 IR( TMR2, CMIA2 ) = 0;
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151 /*-----------------------------------------------------------*/
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153 #pragma vector = VECT_TMR0_CMIA0
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154 __interrupt void vT0_1InterruptHandler( void )
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156 __enable_interrupt();
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157 portYIELD_FROM_ISR( xFirstTimerHandler() );
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159 /*-----------------------------------------------------------*/
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161 #pragma vector = VECT_TMR2_CMIA2
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162 __interrupt void vT2_3InterruptHandler( void )
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164 __enable_interrupt();
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165 portYIELD_FROM_ISR( xSecondTimerHandler() );
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